TMK325BJ226MM- [INTERSIL]

Dual 15A/Single 30A Step-Down Power Module; 双路15A / 30A单降压型电源模块
TMK325BJ226MM-
型号: TMK325BJ226MM-
厂家: Intersil    Intersil
描述:

Dual 15A/Single 30A Step-Down Power Module
双路15A / 30A单降压型电源模块

电源电路
文件: 总28页 (文件大小:1136K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Dual 15A/Single 30A Step-Down Power Module  
ISL8225M  
Features  
• Fully-encapsulated dual step-down switching power supply  
• Up to 100W output from a 17mm square PCB footprint  
• Dual 15A or single 30A output  
The ISL8225M is a fully-encapsulated step-down switching  
power supply that can deliver up to 100W output power from a  
small 17mm square PCB footprint. The two 15A outputs may  
be used independently or combined to deliver a single 30A  
output. Designing a high-performance board-mounted power  
supply has never been simpler -- only a few external  
components are needed to create a very dense and reliable  
power solution.  
• Up to 95% conversion efficiency  
• 4.5V to 20V input voltage range  
• 0.6V to 6V output voltage range  
Automatic current sharing and phase interleaving allow up to  
six modules to be paralleled for 180A output capability. 1.5%  
output voltage accuracy, differential remote voltage sensing  
and fast transient response create a very high-performance  
power system. Built-in output over-voltage, over-current and  
over-temperature protection enhance system reliability.  
• 1.5% output voltage accuracy with differential remote  
sensing  
• Up to six modules may be paralleled to support 180A output  
current  
• Output over-voltage, over-current and over-temperature  
protection  
The ISL8225M is available in a thermally-enhanced QFN  
package. Excellent efficiency and low thermal resistance  
permit full power operation without heat sinks or fans. In  
addition, the QFN package with external leads permits easy  
probing and visual solder inspection.  
• Full power operation without heat sinks or fans  
• QFN package with exposed leads permits easy probing and  
visual solder inspection  
Related Resources  
• See AN1789 “ISL8225MEVAL2Z 6-Phase, 90A Evaluation  
Board Setup Procedure”  
Applications  
• Computing, networking and telecom infrastructure  
equipment  
• See AN1790 “ISL8225MEVAL3Z 30A, Single Output  
Evaluation Board Setup Procedure”  
• Industrial and medical equipment  
• General purpose point-of-load (POL) power  
• See AN1793, “ISL8225MEVAL4Z Dual 15A/Optional 30A  
Cascadable Evaluation Board”  
• See ISL8225M 110A Thermal Performance Video  
4.5V TO 20V  
4x22µF  
1.2V@30A  
V
V
VIN1  
VIN2  
VOUT1  
VOUT2  
IN  
OUT  
1k  
VSEN1+  
R
SET  
1kΩ  
EN/FF1  
EN/FF2  
VSEN2-  
5x100µF  
7.5mm  
OFF ON  
VSEN1-  
VMON1  
VMON2  
COMP1  
COMP2  
ISL8225M  
VCC  
4.7µF  
470pF  
NOTE: ALL PINS NOT SHOWN ARE FLOATING.  
FIGURE 1. COMPLETE 30A STEP-DOWN POWER SUPPLY  
FIGURE 2. SMALL FOOTPRINT WITH HIGH POWER DENSITY  
January 31, 2013  
FN7822.1  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
1
ISL8225M  
Pinout Internal Circuit  
VCC  
7
FILTER  
2.2µF  
VIN1  
14  
15  
LDO  
SOFT-START  
AND FAULT  
LOGIC  
EN/FF1  
Q1  
Q2  
12 PHASE1  
UGATE1  
24  
PGOOD  
L1  
GATE  
DRIVER  
23  
VOUT1  
LGATE1  
0.32µH  
17  
19  
CLKOUT  
ISHARE  
ISEN1B  
ISEN1A  
CURRENT  
SENSING/  
SHARING  
13  
PGND  
10kΩ  
VSEN1+  
VSEN1-  
22  
21  
+
DIFF  
AMP1  
MODE  
SYNC  
3
5
-
18 VMON1  
ZCOMP1  
ZCOMP2  
-
ERROR  
AMP1  
20  
COMP1  
+
INTERNAL  
REFERENCE  
8
VIN2  
SOFT-START  
AND FAULT  
LOGIC  
16  
EN/FF2  
Q3  
10 PHASE2  
25 VOUT2  
UGATE2  
LGATE2  
L2  
GATE  
DRIVER  
0.32µH  
Q4  
ISEN2B  
ISEN2A  
CURRENT  
SENSING/  
SHARING  
9
PGND  
26  
1
VSEN2+  
VSEN2-  
VMON2  
+
DIFF  
SGND  
6
AMP2  
-
4
ZCOMP3  
7.5kΩ  
MODE  
ZCOMP4  
-
ERROR  
COMP2  
2
AMP2  
+
INTERNAL  
REFERENCE  
FN7822.1  
January 31, 2013  
2
ISL8225M  
Ordering Information  
PART NUMBER  
(Notes 2, 3)  
PART  
MARKING  
TEMP. RANGE (°C)  
PACKAGE  
(Pb-Free)  
PKG.  
DWG. #  
(Note 4)  
ISL8225MIRZ  
ISL8225M  
ISL8225M  
-40 to +125  
-40 to +125  
26 Ld QFN  
L26.17x17  
L26.17x17  
ISL8225MIRZ-T  
(Note 1)  
26 Ld QFN  
(Tape & Reel)  
NOTES:  
1. Please refer to TB347 for details on reel specifications.  
2. These products do contain Pb but they are RoHs compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic components, and  
fluorescent tubes).  
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8225M. For more information on MSL, please see tech brief TB363  
4. The ISL8225M is guaranteed over the full -40°C to +125°C internal junction temperature range. Note that the allowed ambient temperature  
consistent with these specifications is determined by specific operating conditions, including board layout, cooling scheme and other environmental  
factors.  
FN7822.1  
January 31, 2013  
3
ISL8225M  
Pin Configuration  
ISL8225M  
(26 LD QFN)  
TOP VIEW  
PIN 1  
9
8
7
6
5
4
3
2
1
VSEN2-  
26  
VSEN2+  
PHASE2  
10  
25  
VOUT2  
24  
23  
N/C  
PGOOD  
VOUT1  
11  
12  
PHASE1  
22  
21  
VSEN1+  
VSEN1-  
13  
14  
15 16 17 18  
19 20  
FN7822.1  
January 31, 2013  
4
ISL8225M  
Pin Descriptions  
PIN  
PIN  
NUMBER  
NAME  
TYPE  
I
PIN DESCRIPTION  
21, 1 VSEN1-, VSEN2-  
Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the  
negative rail or ground of the load/processor, as shown in Figure 19. The negative feedback pins can be used to  
program the module operation conditions. See Table 3 and Table 5 for details.  
20, 2 COMP1, COMP2 I/O Error amplifier outputs. Typically floating for dual-output use. For parallel use, a 470pF~1nF capacitor is recommended  
on the COMP pins of each SLAVE phase to eliminate the coupling noise. All COMP pins of SLAVE phases need to tie to  
MASTER phase COMP1 pin (first phase). Internal compensation networks are implemented for working in the full range  
of I/O conditions.  
3
MODE  
I
Mode setting. Typically floating for dual-output use; tie to SGND for parallel use. See Table 3 and Table 5 for details.  
When VSEN2- is pulled within 700mV of VCC, the 2nd channel’s remote sensing amplifier is disabled. The MODE pin,  
as well as the VSEN2+ pin, determine relative phase-shift between the two channels and the CLKOUT signal output.  
18, 4 VMON1, VMON2 I/O Remote sensing amplifier outputs. These pins are connected internally to OV/UV/PGOOD comparators, so they can’t  
be floated when the module works in multi-phase operation. When VSEN1-, VSEN2- are pulled within 700mV of VCC,  
the corresponding remote sensing amplifier is disabled; the output (VMON pin) is in high impedance. In this event, the  
VMON pins can be used as an additional monitor of the output voltage, with a resistor divider to protect the system  
against single point of failure. The default setting voltage is 0.6V. See Table 3 for details.  
5
SYNC  
I
Signal synchronization. An optional external resistor (R  
) connected from this pin to SGND increases oscillator  
SYNC  
switching frequency (Figure 31 and Table 1). The internal default frequency is 500kHz with this pin floating. Also, the  
internal oscillator can lock to an external frequency source or the CLKOUT signal from another ISL8225M. Input voltage  
range for external source: 3V to 5V square wave. No capacitor is recommended on this pin.  
6
7
SGND  
VCC  
PWR Control signal ground. Connect to PGND under the module in the quiet inner layer. Make sure to have the single location  
for the connection between SGND and PGND to avoid noise coupling. See “Layout Guide” on page 23.  
PWR 5V internal linear regulator output. Voltage range: 3V to 5.6V. The decoupling ceramic capacitor for the VCC pin is  
recommended to be 4.7µF.  
14, 8  
VIN1, VIN2  
PGND  
PWR Power inputs. Input voltage range: 4.5V to 20V. Tie directly to the input rail. VIN1 provides power to the internal linear  
drive circuitry. When the input is 4.5V to 5.5V, VIN should be tied directly to VCC.  
9, 13  
PWR Power ground. Power ground pins for both input and output returns.  
12, 10  
PHASE1,  
PHASE2  
PWR Phase node. Use for monitoring switching frequency. Phase pins should be floating or used for snubber connections.To  
achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected  
to large inner layers. See “Layout Guide” on page 23.  
11  
NC  
-
Non-connection pin. This pin is floating with no connection inside.  
15, 16  
EN/FF1,  
EN/FF2  
I/O Enable and feed-forward control. Tie a resistor divider to VIN or use the system enable signal for this pin. The voltage  
turn-on threshold is 0.8V. With a voltage lower than the threshold, the corresponding channel can be disabled  
independently. By connecting to VIN with a resistor divider, the input voltage can be monitored for UVLO (under-voltage  
lockout) function. The voltage on each EN/FF pin is also used to adjust the internal control loop gain independently to  
realize the feed-forward function. Please set the EN/FF between 1.25V to 5V. A 1nF capacitor is recommended on each  
EN/FF pin. Please see Table 1 to select resistor divider and application details in “EN/FF Turn ON/OFF” on page 19.  
17  
19  
CLKOUT  
ISHARE  
I/O Clock out. Provide the clock signal for the input synchronization signal of other ISL8225Ms. Typically tied to VCC for  
dual-output use with 180° phase-shift. See Table 3 and Table 5 when using more than one ISL8225M. When the  
module is in dual-output mode, the clock-out signal is disabled. By programming the voltage level of this CLKOUT pin,  
the module can work for DDR/tracking or as two independent outputs with selectable phase-shift. See Table 6.  
O
Current sharing control. Tie all ISHARE pins together when multiple modules are configured for current sharing and  
share a common current output. The ISHARE voltage represents the average current of all active and connected  
channels. A 470pF capacitor is recommended for each ISHARE pin for multiple phase applications. Typically, the  
ISHARE pin should be floating for dual-output or single module application.  
22, 26  
VSEN1+,  
VSEN2+  
I
Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. A resistor divider can  
be connected to this pin to program the output voltage. It is recommended to put the resistor divider close to the  
module and connect the kelvin sensing traces of VOUT and VSEN- to the sensing points of the load/processor; see  
Figure 19. The VSEN2+ pin can be used to program the module operation conditions. See Table 3 and Table 5 for  
details.  
23, 25 VOUT1, VOUT2 PWR Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 6V.  
24  
PGOOD  
O
Power good. Provide open-drain power-good signal when the output is within 9% of the nominal output regulation point  
with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON) of the internal differential  
amplifiers.  
FN7822.1  
January 31, 2013  
5
ISL8225M  
Absolute Maximum Ratings  
Thermal Information  
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +25V  
Driver Bias Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V  
CC  
Thermal Resistance (Typical)  
QFN Package (Notes 5, 6) . . . . . . . . . . . . . .  
θ
(°C/W)  
10.0  
θ
(°C/W)  
0.9  
IN  
JA  
JC  
Phase Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V  
Maximum Storage Temperature Range . . . . . . . . . . . . . .-55°C to +150°C  
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to Figure 41  
PHASE  
Input, Output or I/O Control Voltage . . . . . . . . . . . . . . . -0.3V to V + 0.3V  
CC  
ESD Rating  
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV  
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V  
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV  
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA  
Recommended Operating Conditions  
Input Voltage, V  
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 20.0V  
IN1  
IN2  
Output Voltage, V  
and V  
. . . . . . . . . . . . . . . . . . . . . . . 0.6V to 6.0V  
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C  
OUT1  
OUT2  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product  
reliability and result in failures not covered by warranty.  
NOTES:  
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech  
JA  
Brief TB379.  
6. For θ , the “case temp” location is the center of the phase exposed metal pad on the package underside.  
JC  
Electrical Specifications  
T
= +25°C, V = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature  
IN  
A
range, -40°C to +125°C (Note 4).  
MIN  
TYP  
MAX  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
(Note 7) (Note 8) (Note 7) UNITS  
VCC SUPPLY CURRENT  
Nominal Supply V Current  
IN  
I
V
V
V
V
V
V
V
= 20V; No Load; EN1 = EN2 = high  
131  
72  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Q_VIN  
IN  
= 20V; No Load; EN1 = high, EN2 = low  
= 20V; No Load; EN1 = 0, EN2 = high  
= 12V; No Load; EN1 = high, EN2 = high  
IN1  
IN2  
IN1  
71  
134  
136  
73  
= 4.5V; No Load; EN1 = EN2 = high  
IN  
= 4.5V; No Load; EN1 = high, EN2 = low  
= 4.5V; No Load; EN1 = 0, EN2 = high  
IN1  
IN2  
70  
INTERNAL LINEAR REGULATOR (Note 9)  
Maximum Current  
I
V
= 4V to 5.6V  
250  
1
mA  
PVCC  
CC  
Saturated Equivalent Impedance  
VCC Voltage Level  
R
P-Channel MOSFET (V = 5V)  
IN  
LDO  
VCC  
I
= 0mA  
5.15  
5.4  
5.95  
V
VCC  
POWER-ON RESET (Note 9)  
Rising VCC Threshold  
0°C to +75°C  
2.85  
2.85  
2.65  
384  
2.97  
3.05  
2.75  
V
-40°C to +85°C  
V
V
Falling VCC Threshold  
System Soft-start Delay  
t
After PLL and V PORs, and EN above their  
CC  
Cycles  
SS_DLY  
thresholds  
ENABLE (Note 9)  
Turn-On Threshold Voltage  
Hysteresis Sink Current  
Under-voltage Lockout Hysteresis  
0.75  
23  
0.8  
30  
0.86  
35  
V
µA  
V
I
EN_HYS  
V
V
= 10.6V; V = 9V, R = 53.6k,  
EN_FTH UP  
1.6  
EN_HYS  
EN_RTH  
R
= 5.23kΩ  
DOWN  
Sink Current  
I
V
= 1V  
15.4  
mA  
EN_SINK  
ENFF  
Sink Impedance  
OSCILLATOR  
R
I
= 5mA, V = 1V  
ENFF  
64  
EN_SINK  
EN_SINK  
Oscillator Frequency  
f
SYNC pin is open  
510  
kHz  
OSC  
FN7822.1  
January 31, 2013  
6
ISL8225M  
Electrical Specifications  
T
= +25°C, V = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature  
IN  
A
range, -40°C to +125°C (Note 4). (Continued)  
MIN  
TYP  
MAX  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= 5V; -40°C < T < +85°C  
(Note 7) (Note 8) (Note 7) UNITS  
Total Variation (Note 9)  
V
-9  
+9  
1500  
90  
%
CC  
A
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 9)  
Synchronization Frequency  
PLL Locking Time  
V
= 5V  
150  
10  
kHz  
µs  
%
CC  
CC  
V
= 5.4V, f  
= 500kHz  
130  
SW  
Input Signal Duty Cycle Range  
PWM (Note 9)  
Minimum PWM OFF Time  
Current Sampling Blanking Time  
OUTPUT CHARACTERISTICS  
Output Continuous Current Range  
t
310  
345  
175  
410  
ns  
ns  
MIN_OFF  
t
BLANKING  
I
V
V
V
= 12V, V  
= 12V, V  
= 12V, V  
= 1.5V  
= 1.5V  
0
0
0
15  
15  
30  
A
A
A
OUT(DC)  
IN  
IN  
IN  
OUT1  
OUT2  
= 1.5V, in Parallel mode  
OUT  
Line Regulation Accuracy  
ΔV  
/ΔV  
V
= 4.5V to 20V  
OUT  
IN IN  
V
= 1.5V, I  
= 1.5V, I  
= 0A  
= 0A  
0.0065  
0.0065  
%
%
OUT1  
OUT2  
OUT1  
OUT2  
V
V
= 4.5V to 20V  
IN  
V
= 1.5V, I  
= 1.5V, I  
= 15A  
= 15A  
0.01  
0.01  
%
%
OUT1  
OUT2  
OUT1  
OUT2  
V
Load Regulation Accuracy  
Output Ripple Voltage  
ΔV  
/V  
V
= 12V, 5x22µF, 2x4.7µF ceramic capacitor and  
OUT OUT IN  
1x330µF POSCAP  
I
I
= 0A to 15A, V  
= 0A to 15A, V  
= 1.5V  
= 1.5V  
1
1
%
%
OUT1  
OUT2  
OUT1  
OUT2  
ΔV  
OUT  
V
= 12V, 3x100µF ceramic capacitor and  
IN  
1x330µF POSCAP  
I
I
I
I
= 0A, V  
= 0A, V  
= 1.5V  
= 1.5V  
11  
11  
14  
14  
mV  
OUT1  
OUT2  
OUT1  
OUT2  
OUT1  
P-P  
P-P  
P-P  
P-P  
mV  
mV  
mV  
OUT2  
= 15A, V  
= 1.5V  
= 1.5V  
OUT1  
OUT2  
= 15A, V  
DYNAMIC CHARACTERISTICS  
Voltage Change for Positive Load Step  
ΔV  
Current slew rate = 2.5A/µs  
= 12V, V = 1.5V, 2x47µF ceramic capacitor  
OUT-DP  
V
IN  
OUT  
and 1x330µF POSCAP  
I
I
= 0A to 7.5A  
= 0A to 7.5A  
75  
75  
mV  
mV  
OUT1  
OUT2  
P-P  
P-P  
Voltage Change for Negative Load Step  
ΔV  
Current slew rate = 2.5A/µs  
= 12V, V = 1.5V, 2x47µF ceramic capacitor  
OUT-DN  
V
IN  
OUT  
and 1x330µF POSCAP  
I
I
= 7.5A to 0A  
= 7.5A to 0A  
70  
70  
mV  
mV  
OUT1  
OUT2  
P-P  
P-P  
REFERENCE (Note 9)  
Reference Voltage (Include Error and  
Differential Amplifier Offsets)  
V
T
= -40°C to +85°C  
0.6  
V
REF1  
A
-0.7  
0.7  
%
FN7822.1  
January 31, 2013  
7
ISL8225M  
Electrical Specifications  
T
= +25°C, V = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature  
IN  
A
range, -40°C to +125°C (Note 4). (Continued)  
MIN  
TYP  
MAX  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= -40°C to +85°C  
A
(Note 7) (Note 8) (Note 7) UNITS  
Reference Voltage (Include Error and  
Differential Amplifier Offsets)  
V
T
0.6  
V
REF2  
-0.75  
0.2  
0.95  
2.5  
%
DIFFERENTIAL AMPLIFIER (Note 9)  
DC Gain  
UG_DA  
Unity gain amplifier  
0
5
dB  
MHz  
µA  
Unity Gain Bandwidth  
VSEN+ Pin Sourcing Current  
UGBW_DA  
I
1
VSEN+  
I
VSEN1- Source Current for Current Sharing when  
parallel multiple modules, each of which has its  
own voltage loop  
350  
µA  
VSEN1-  
Maximum Source Current for Current Sharing  
Input Impedance  
R
V
/I  
, V  
= 0.6V  
-600  
kΩ  
VSEN+_to  
_VSEN-  
VSEN+ VSEN+ VSEN+  
Output Voltage Swing  
0
V
V
- 1.8  
V
V
V
CC  
Input Common Mode Range  
Disable Threshold  
-0.2  
- 1.8  
CC  
V
V
= tri-state  
V
- 0.4  
VSEN-  
MON1,2  
IN  
CC  
OVER-CURRENT PROTECTION (Note 9)  
Channel Over-current Limit  
I
I
V
V
V
= 12V, V  
= 1.5V, R  
= Open  
= Open  
20  
20  
A
A
V
limit1  
limit2  
OUT1  
SYNC  
= 12V, V  
= 1.5V, R  
IN  
OUT2  
SYNC  
Share Pin OC Threshold  
V
= 5V  
1.16  
1.20  
1.22  
OC_SET  
CC  
(comparator offset included)  
CURRENT SHARE  
Current Share Accuracy  
ΔI/IOUT  
V
= 12V, V  
= 1.5V  
= 30A, VSEN2- = high  
±10  
%
IN  
OUT  
I
OUT  
POWER-GOOD MONITOR (Note 9)  
Under-voltage Falling Trip Point  
Under-voltage Rising Hysteresis  
Over-voltage Rising Trip Point  
Over-voltage Falling Hysteresis  
PGOOD Low Output Voltage  
V
Percentage below reference point  
Percentage above UV trip point  
Percentage above reference point  
Percentage below OV trip point  
-15  
11  
-13  
4
-11  
15  
%
%
UVF  
V
V
UVR_HYS  
V
13  
4
%
OVR  
%
OVF_HYS  
I
I
= 2mA  
= 2mA  
< 0.8V  
0.35  
70  
V
PGOOD  
Sinking Impedance  
PGOOD  
Maximum Sinking Current  
V
10  
mA  
PGOOD  
OVER-VOLTAGE PROTECTION (Note 9)  
OV Latching-up Trip Point  
EN/FF = UGATE = LATCH Low, LGATE = High  
EN = Low, UGATE = Low, LGATE = High  
EN = Low/HIGH, UGATE = Low, LGATE = Low  
118  
120  
113  
87  
122  
%
%
%
OV Non-Latching-up Trip Point  
LGATE Release Trip Point  
OVER-TEMPERATURE PROTECTION (Note 9)  
Over-Temperature Trip (Controller Junction  
Temperature)  
150  
125  
°C  
°C  
Over-Temperature Release Threshold  
(Controller Junction Temperature)  
NOTES:  
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.  
8. Parameters with TYP limits are not production tested, unless otherwise specified.  
9. Parameters are 100% tested for internal IC prior to module assembly.  
FN7822.1  
January 31, 2013  
8
ISL8225M  
Typical Performance Characteristics  
Efficiency Performance  
T = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled. The efficiency equation is  
A
as follows:  
P
(V  
xI  
)
Output Power  
Input Power  
OUT  
OUT OUT  
-----------------------------------------  
---------------  
--------------------------------------  
=
Efficiency =  
=
P
(V xI  
)
IN  
IN IN  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
100  
95  
3.3V  
1.8V  
2.5V AT 500kHz  
3.3V AT 650kHz  
1.2V AT 500kHz  
2.5V  
1.5V  
5V AT 850kHz  
90  
85  
1V  
1.2V  
80  
1.5V AT 500kHz  
1.8V AT 500kHz  
75  
70  
65  
60  
55  
50  
1V AT 500kHz  
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
FIGURE 3. EFFICIENCY vs LOAD CURRENT (5V AT 500kHz)  
IN  
FIGURE 4. EFFICIENCY vs LOAD CURRENT (12V )  
IN  
100  
100  
95  
90  
85  
80  
75  
70  
2.5V  
OUT  
1.8V  
2.5V AT 500kHz  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
OUT  
3.3V AT 650kHz  
5V AT 900kHz  
1.5V  
OUT  
1.2V  
OUT  
1.8V AT 500kHz  
1V  
OUT  
1.5V AT 500kHz  
1.2V AT 500kHz  
1V AT 500kHz  
0
2
4
6
8
10  
12  
14  
16  
0
5
10  
15  
20  
25  
30  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
FIGURE 5. EFFICIENCY vs LOAD CURRENT (20V  
)
FIGURE 6. EFFICIENCY vs LOAD CURRENT (PARALLEL SINGLE  
OUTPUT, AS SHOWN IN FIGURE 19 AT 5V /500kHz)  
IN  
IN  
95  
1.8V  
1.5V  
OUT  
2.5V  
OUT  
90  
85  
80  
75  
70  
65  
60  
OUT  
1.2V  
OUT  
1V  
OUT  
0
5
10  
15  
20  
25  
30  
LOAD CURRENT (A)  
FIGURE 7. EFFICIENCY vs LOAD CURRENT (PARALLEL SINGLE OUTPUT, AS SHOWN IN FIGURE 19 AT 12V /500kHz  
IN  
FN7822.1  
January 31, 2013  
9
ISL8225M  
Typical Performance Characteristics(Continued)  
Transient Response Performance  
V
= 12V, COUT = 1x10µF and 3x100µF ceramic capacitors, I  
= 0A to 7.5A, current  
OUT  
IN  
slew rate = 2.5A/µs. T = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled.  
A
50mV/DIV  
50mV/DIV  
2A/DIV  
2A/DIV  
200µs/DIV  
200µs/DIV  
FIGURE 8. 1V  
FIGURE 10. 1.5V  
FIGURE 12. 2.5V  
TRANSIENT RESPONSE  
FIGURE 9. 1.2V  
TRANSIENT RESPONSE  
OUT  
OUT  
50mV/DIV  
50mV/DIV  
2A/DIV  
2A/DIV  
200µs/DIV  
200µs/DIV  
TRANSIENT RESPONSE  
FIGURE 11. 1.8V  
OUT  
TRANSIENT RESPONSE  
OUT  
50mV/DIV  
100mV/DIV  
2A/DIV  
2A/DIV  
200µs/DIV  
200µs/DIV  
200uS/DIV  
TRANSIENT RESPONSE  
FIGURE 13. 3.3V TRANSIENT RESPONSE  
OUT  
OUT  
FN7822.1  
January 31, 2013  
10  
ISL8225M  
Typical Performance Characteristics(Continued)  
Start-up and Short Circuit Performance  
V
= 12V, V  
= 1.5V, CIN = 1x 180µF, 2x10µF/Ceramic, COUT = 2x47µF and  
IN  
OUT  
1x330µF POSCAP. T = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled.  
A
V
OUT  
V
out  
OUT  
0.5V/DIV
0.5V/DIV  
I
in  
IN  
I
N
0.1A/DIV  
0.1A/DIV  
1ms/DIV  
1ms/DIV  
FIGURE 14. START-UP AT 0A  
FIGURE 15. START-UP AT 15A  
V
OUT  
V
out  
OUT  
0.5V/DIV
0.5V/DIV  
I
I
IN  
in  
IN  
0.2A/DIV  
V  
I
0.5A/DIV  
100µs/DIV
100µs/DIV  
FIGURE 16. SHORT CIRCUIT AT 0A  
FIGURE 17. SHORT CIRCUIT AT 15A  
FN7822.1  
January 31, 2013  
11  
ISL8225M  
Typical Application Circuits  
4.5V TO 20V  
14  
1.2V@15A  
VOUT1  
23  
22  
21  
25  
26  
1
VIN  
VIN1  
VOUT1  
CFF  
+
(OPTIONAL)  
+
CIN1  
330µF  
CIN2  
4x22µF  
COUT2  
330µF  
8
15  
16  
7
VIN2  
VSEN1+  
VSEN1-  
VOUT2  
VSEN2+  
VSEN2-  
VMON1  
R2*  
1kΩ  
COUT1  
2x47µF  
R1*  
1kΩ  
EN/FF1  
EN/FF2  
VCC  
R5*  
1.5V@15A  
VOUT2  
CFF  
(OPTIONAL)  
+
COUT4  
330µF  
COUT3  
2x47µF  
R4*  
665Ω  
R3*  
1kΩ  
R6*  
17  
3
CLKOUT  
MODE  
ISHARE  
SYNC  
C1  
4.7µF  
ISL8225M  
18  
4
*SEE TABLE 4 ON PAGE 19, RESISTORS  
SET ON VSEN+ AND VSEN- PINS.  
19  
5
*SEE TABLE 1 ON PAGE 17 FOR R5/R6  
VALUES.  
VMON2  
12  
10  
24  
PHASE1  
20  
2
COMP1  
COMP2  
PHASE2  
PGOOD  
6
9
SEE “LAYOUT GUIDE” ON PAGE 23 FOR SHORTING SGND TO PGND  
FIGURE 18. DUAL OUTPUTS FOR 1.2V/15A AND 1.5V/15A  
4.5V TO 20V  
+
1.5V@30A  
14  
8
23  
22  
21  
25  
26  
1
VIN  
VOUT  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
R1  
CIN1  
330µF  
CIN2  
VIN2  
4x22µF  
1kΩ  
COUT  
5x100µF  
R2  
LOAD  
665Ω  
15  
16  
7
EN/FF1  
EN/FF2  
VCC  
R3*  
KELVIN REMOTE SENSING LINES  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
VCC  
17  
3
R4*  
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
C1  
4.7µF  
18  
4
19  
5
*SEE TABLE 1 ON PAGE 17 FOR R3/R4  
VALUES.  
2200pF  
2Ω  
12  
SIZE:1210  
2Ω  
20  
2
10  
24  
COMP1  
COMP2  
SIZE:1210  
2200pF  
C2  
OPTIONAL SNUBBER FOR NOISE  
ATTENUATION. SEE FIGURE 32,  
470pF  
6
9
“RECOMMENDED LAYOUT,” ON PAGE 23.  
SEE “LAYOUT GUIDE” ON PAGE 23 FOR SHORTING SGND TO PGND  
FIGURE 19. PARALLEL USE FOR SINGLE 1.5V/30A OUTPUT  
FN7822.1  
January 31, 2013  
12  
ISL8225M  
Typical Application Circuits(Continued)  
2.5V  
4.5V TO 20V  
14  
8
23  
22  
21  
25  
26  
1
VDDQ  
VIN  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
+
R1  
CIN2  
4x22µF  
CIN1  
330µF  
VIN2  
1kΩ  
R2  
COUT1  
3x100µF  
316Ω  
15  
16  
7
R5*  
EN/FF1  
EN/FF2  
VCC  
1.25V VDDQ/2  
VTT  
*SEE TABLE 1 ON PAGE 17 FOR  
R5/R6 VALUES.  
R3  
1kΩ  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
R6*  
R4  
931Ω  
COUT2  
3x100µF  
C1  
4.7µF  
17  
3
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
18  
4
VDDQ  
19  
5
R7  
12  
10  
24  
1kΩ  
20  
2
COMP1  
COMP2  
R8  
C2  
1nF  
324Ω  
6
9
*SET THE CLKOUT VOLTAGE CLOSE TO 0.61V.  
SEE DETAILS IN “FUNCTIONAL DESCRIPTION” ON PAGE 20  
FIGURE 20. DDR/TRACKING USE  
3.3V@10A  
VOUT1  
8V TO 20V  
+
14  
8
23  
22  
21  
25  
26  
1
VIN  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
R1  
1kΩ  
CIN1  
CIN2  
VIN2  
330µF  
4x22µF  
COUT1  
3x100µF  
R2  
221Ω  
R5  
15  
16  
7
EN/FF1  
EN/FF2  
VCC  
7.15kΩ  
5V@10A  
VOUT2  
R3  
1kΩ  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
R4  
137Ω  
COUT2  
3x100µF  
R6  
2.05kΩ  
17  
3
C1  
4.7µF  
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
18  
4
*SEE FIGURE 25, “RECOMMENDED  
FREQUENCY VS VIN AT VOUT,” ON  
PAGE 19 FOR THE FREQUENCY SETTING  
FOR I/O CONDITIONS.  
19  
5
12  
10  
24  
20  
2
COMP1  
COMP2  
R7  
88.7kΩ  
6
9
*SEE FIGURE 31, “R  
VS SWITCHING  
SYNC  
FREQUENCY,” ON PAGE 22 TO SELECT R7 FOR THE  
DESIRED FREQUENCY OPERATION.  
FIGURE 21. HIGH OUTPUT VOLTAGE APPLICATION WITH THE FREQUENCY SET AT 900kHz  
FN7822.1  
January 31, 2013  
13  
ISL8225M  
Typical Application Circuits(Continued)  
1.5V/60A  
4.5V TO 20V  
MASTER PHASE  
VIN  
VOUT1  
VIN1  
VIN2  
VOUT1  
R1  
+
CIN1  
2x470µF  
CIN2  
VSEN1+  
4x22µF  
R2  
665Ω  
1kΩ  
COUT1  
4x100µF  
R4*  
EN/FF1  
VSEN1-  
VOUT2  
SLAVE  
VCC1  
EN/FF2  
VCC  
VCC1  
*SEE TABLE 1 ON  
PAGE 17 FOR R3/R4  
VALUES.  
R3*  
VSEN2+  
C1  
4.7µF  
CLKOUT  
VSEN2-  
ISL8225M  
MODE  
VMON1  
VMON2  
VCC  
ISHARE  
R8  
1kΩ  
SYNC  
PHASE1  
R5  
3.3kΩ  
COMP1  
COMP2  
PHASE2  
PGOOD  
PGOOD  
C3  
470pF  
SLAVE  
VIN1  
VOUT1  
VIN2  
VSEN1+  
CIN2  
4x22µF  
COUT2  
4x100µF  
VCC2  
EN/FF1  
EN/FF2  
VSEN1-  
VOUT2  
SLAVE  
VCC2  
VCC  
VSEN2+  
CLKOUT  
MODE  
VSEN2-  
VMON1  
C2  
4.7µF  
ISL8225M  
R6  
1kΩ  
R7  
665Ω  
ISHARE  
VMON2  
R9  
1kΩ  
SYNC  
PHASE1  
PHASE2  
COMP1  
COMP2  
PGOOD  
C4  
470pF  
C5  
470pF  
FIGURE 22. 4-PHASE PARALLELED AT 1.5V/60A WITH 90° INTERLEAVING  
FN7822.1  
January 31, 2013  
14  
ISL8225M  
Typical Application Circuits(Continued)  
4.5V TO 20V  
1.5V/40A  
14  
8
23 MASTER PHASE  
VOUT1  
VIN  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
+
R1  
22  
CIN1  
2x470µF  
VIN2  
4x22µF  
1kΩ  
316Ω  
R2  
COUT1  
4x100µF  
R4*  
15  
16  
7
21  
25  
26  
1
EN/FF1  
EN/FF2  
VCC  
*SEE TABLE 1  
ON PAGE 17  
FOR R3/R4  
VALUES.  
SLAVE  
VCC1  
VCC1  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
R3*  
C1  
4.7µF  
17  
3
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
VCC  
18  
4
VCC1  
19  
5
12  
10  
24  
R6  
1kΩ  
R5  
3.3kΩ  
20  
2
COMP1  
COMP2  
R7  
100kΩ  
PGOOD  
6
9
C2  
470pF  
14  
23  
22  
21  
25  
26  
1
SLAVE  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
COUT2  
2x100µF  
8
15  
16  
VIN2  
VCC2  
CIN2  
EN/FF1  
EN/FF2  
VCC  
4x22µF  
5V/10A  
VOUT2  
VCC2  
7
R8  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
1kΩ  
137Ω  
R9  
COUT3  
3x100µF  
17  
3
C3  
4.7µF  
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
R10  
1kΩ  
18  
4
19  
5
R11  
316Ω  
12  
10  
24  
20  
2
COMP1  
COMP2  
C4  
470pF  
6
9
FIGURE 23. 3-PHASE PARALLELED AT 1.5V/40A AND 1-PHASE AT 5V/10A OUTPUT WITH 90° INTERLEAVING  
FN7822.1  
January 31, 2013  
15  
ISL8225M  
Typical Application Circuits(Continued)  
4.5V TO 20V  
1.2V/90A  
MASTER PHASE  
R1  
14  
8
23  
22  
VIN  
VIN1  
VOUT1  
VOUT  
+
CIN1  
2x470µF  
VSEN1+  
VIN2  
4x22µF  
1kΩ  
R2  
1kΩ  
COUT1  
4x100µF  
15  
16  
7
21  
25  
R4*  
EN/FF1  
EN/FF2  
VCC  
VSEN1-  
VOUT2  
*SEE TABLE 1 ON PAGE 17  
FOR R3/R4 VALUES.  
SLAVE  
VCC1  
26  
1
VCC1  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
R3*  
C1  
4.7µF  
17  
3
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
18  
4
VCC1  
19  
5
12  
10  
24  
R5  
3.3kΩ  
20  
2
COMP1  
COMP2  
PGOOD  
6
9
C8  
470pF  
14  
8
23  
22  
21  
SLAVE  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
VIN2  
VCC2  
COUT2  
4x100µF  
15  
16  
7
EN/FF1  
EN/FF2  
VCC  
CIN2  
4x22µF  
25  
26  
1
SLAVE  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
VCC2  
17  
3
CLKOUT  
MODE  
ISL8225M  
C2  
4.7µF  
R6*  
500Ω  
18  
4
19  
5
R7*  
500Ω  
ISHARE  
SYNC  
12  
10  
24  
20  
2
*KEEP R6/R7 THE SAME  
RATIO AS R1/R2. EACH VMON  
PIN CAN HAVE SEPERATE  
RESISTOR DIVIDER TO  
MONITOR THE OUTPUT  
VOLTAGE.  
COMP1  
COMP2  
C3  
470pF  
6
9
C4  
470pF  
14  
23 SLAVE  
VIN1  
VOUT1  
VSEN1+  
VSEN1-  
VOUT2  
8
15  
16  
7
22  
VIN2  
VCC3  
COUT3  
4x100µF  
21  
EN/FF1  
EN/FF2  
VCC  
CIN3  
4x22µF  
25  
26  
1
SLAVE  
VCC3  
VSEN2+  
VSEN2-  
VMON1  
VMON2  
PHASE1  
PHASE2  
PGOOD  
17  
3
CLKOUT  
MODE  
ISHARE  
SYNC  
ISL8225M  
C5  
4.7µF  
18  
4
19  
5
12  
10  
24  
20  
2
COMP1  
COMP2  
C6  
470pF  
C7  
470pF  
6
9
FIGURE 24. SIX-PHASE 90A 1.2V OUTPUT CIRCUIT  
FN7822.1  
January 31, 2013  
16  
ISL8225M  
TABLE 1. ISL8225M DESIGN GUIDE MATRIX (REFER TO FIGURE 18)  
CIN1  
(BULK)  
(NOTE 10)  
EN/FF (k)  
R5/R6  
(NOTE 11)  
LOAD  
(A)  
(NOTE 12)  
V
V
R2 or R4  
CIN2  
(CERAMIC)  
COUT1  
(CERAMIC)  
COUT2  
(BULK)  
CFF  
(nF)  
FREQ.  
(kHz)  
R
SYNC  
IN OUT  
CASE (V) (V)  
()  
(k)  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
249  
1
2
3
4
5
6
7
8
9
5
5
1
1
1.5k  
1.5k  
1.5k  
1.5k  
1.0k  
1.0k  
1.0k  
1.0k  
1.0k  
1.0k  
665  
665  
665  
665  
665  
665  
316  
316  
316  
316  
316  
316  
221  
221  
221  
221  
221  
221  
137  
137  
137  
137  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x330µF  
1x100µF  
1x100µF  
2x22µF  
2x22µF  
1x100µF  
1x100µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
1x100µF  
1x100µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
1x100µF  
1x100µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
1x100µF  
1x100µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
2x22µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x100µF  
3x100µF  
1x330µF  
None  
None  
3.3  
6.04/3.01  
6.04/3.01  
6.04/1.50  
6.04/1.50  
6.04/3.01  
6.04/3.01  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/3.01  
6.04/3.01  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/3.01  
6.04/3.01  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/3.01  
6.04/3.01  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
6.04/1.50  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
650  
650  
750  
750  
500  
500  
800  
800  
850  
850  
950  
950  
950  
950  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
14  
14  
15  
15  
14  
14  
13  
13  
12  
12  
10  
10  
12  
12  
5
1
1x330µF  
None  
None  
3.3  
1
1.2  
1.2  
1x330µF  
None  
None  
3.3  
5
12 1.2  
12 1.2  
20 1.2  
1x330µF  
None  
None  
3.3  
1x330µF  
None  
3.3  
10 20 1.2  
4.7  
11  
12  
5
5
1.5  
1.5  
1x330µF  
None  
None  
3.3  
13 12 1.5  
14 12 1.5  
15 20 1.5  
16 20 1.5  
1x330µF  
None  
None  
3.3  
1x330µF  
None  
None  
3.3  
17  
18  
5
5
2.5  
2.5  
1x330µF  
None  
None  
3.3  
19 12 2.5  
20 12 2.5  
21 20 2.5  
22 20 2.5  
1x330µF  
None  
None  
3.3  
249  
1x330µF  
None  
None  
3.3  
147  
147  
23  
24  
5
5
3.3  
3.3  
1x330µF  
None  
None  
None  
None  
None  
None  
3.3  
None  
None  
124  
25 12 3.3  
26 12 3.3  
27 20 3.3  
28 20 3.3  
1x330µF  
None  
124  
1x330µF  
None  
107  
107  
29 12  
30 12  
31 20  
32 20  
5
5
5
5
1x330µF  
None  
None  
None  
None  
3.3  
82.5  
82.5  
82.5  
82.5  
1x330µF  
None  
NOTES:  
10. CIN bulk capacitor is optional only for decoupling noise due to the long input cable. CIN2 and COUT1 ceramic capacitors are listed for one phase only.  
Please double the capacitor quantity for dual-phase operations.  
11. EN/FF resistor divider is tied directly to VIN. The resistors listed here are for two channels' EN/FF pins tied together. If the separate resistor divider is  
used for each channel, the resistor value needs to be doubled.  
12. MAX load current listed in the table is for conditions at +25°C and no air flow on a typical Intersil 4-layer evaluation board.  
FN7822.1  
January 31, 2013  
17  
ISL8225M  
TABLE 2. RECOMMENDED I/O CAPACITOR IN TABLE 1  
VALUE  
VENDOR  
PART NUMBER  
C3225X5R0J107M  
GRM32ER60J107M  
12106D107MAT2A  
GRM32ER61E226KE15L  
TMK325BJ226MM-T  
12103D226KAT2A  
10TPB330M  
TDK, Input and Output Ceramic  
Murata, Input and Output Ceramic  
AVX, Input and Output Ceramic  
Murata, Input Ceramic  
100µF, 6.3V, 1210  
100µF, 6.3V, 1210  
100µF, 6.3V, 1210  
22µF, 25V, 1210  
Taiyo Yuden, Input Ceramic  
AVX, Input Ceramic  
22µF, 25V, 1210  
22µF, 25V, 1210  
Panasonic POSCAP, Output Bulk  
Panasonic SMT, Input Bulk  
330µF, 10V  
330µF, 25V  
EEVHA1E331UP  
TABLE 3. ISL8225M OPERATION MODES  
1ST MODULE (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BI-DIRECTION)  
MODES OF OPERATION  
OPERATION OPERATION  
VMON1  
ND  
OUTPUT  
(SEE  
ND  
CLKOUT/REFIN  
OF 2  
2
CHANNEL  
ST  
MODE  
OF 2ND  
MODULE  
MODE  
ST  
EN1/FF1 EN2/FF2 VSEN2- MODE VSEN2+  
WRT 1  
VMON2 MODULE WRT 1 (O)  
OF 3RD  
DESCRIPTION  
FOR DETAILS)  
MODE  
1
(I)  
(I)  
(I)  
(I)  
(I)  
(I OR O)  
(Note 14) (Note 14)  
(NOTE 13)  
MODULE  
-
0
0
-
-
-
-
-
-
-
-
-
-
-
-
Disabled  
2A  
0
1
Active Active Active  
Active  
VMON1 =  
VMON2toKeep  
PGOOD Valid  
Single Phase  
2B  
1
0
-
-
-
-
-
-
VMON1 =  
VMON2toKeep  
PGOOD Valid  
-
-
Single Phase  
3A  
3B  
1
1
1
1
<V -0.7V Active Active 29% to 45%  
CC  
Active  
Active  
-
-
0°  
-
-
-
-
Dual Regulator  
Dual Regulator  
of V (I)  
CC  
<V -0.7V Active Active 45% to 62%  
CC  
90°  
of V (I)  
CC  
3C  
4
1
1
1
1
1
1
<V -0.7V Active Active >62% of V (I) Active  
CC CC  
-
-
-
180°  
-60°  
-
-
-
-
-
-
Dual Regulator  
DDR Mode  
2-Phase  
<V -0.7V Active Active <29% of V (I) Active  
CC CC  
5A  
V
GND  
-
60°  
VMON1  
or  
180°  
CC  
Divider  
5B  
5C  
1
1
1
1
V
V
GND  
GND  
-
-
60°  
60°  
Divider Divider  
180°  
180°  
5B  
5C  
5B  
5C  
6-Phase  
CC  
VMON1 Active  
3 Outputs  
CC  
or  
Divider  
6
1
1
1
1
1
1
V
V
V
V
V
V
GND  
120°  
90°  
1kΩ  
1kΩ  
1kΩ  
Active  
Divider  
Active  
240°  
180°  
180°  
2B  
7A  
7B  
-
-
-
3-Phase  
4-Phase  
CC  
CC  
CC  
CC  
CC  
CC  
7A  
7B  
V
V
CC  
90°  
2 Outputs  
CC  
st  
(1 module in  
Mode 7A)  
7C  
1
1
V
V
V
90°  
1kΩ  
Active  
180°  
3, 4  
-
3 Outputs  
(1 module in  
CC  
CC  
CC  
st  
Mode 7A)  
8
9
Cascaded Module Operation MODEs 5B+5B+7A+5B+5B+5B/7A, No External Clock Required  
External Clock or External Logic Circuits Required for Equal Phase Interval  
12-Phase  
5, 7, 8, 9, 10, 11,  
or  
(PHASE >12)  
NOTE:  
ND  
13. “2 CHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this  
column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°.  
14. “VMON1” means that the pin is tied to the VMON1 pin of the same module.  
“Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 24.  
“1k” means that there is a 1kresistor connecting the pin to SGND; refer to Figure 22.  
FN7822.1  
January 31, 2013  
18  
ISL8225M  
recommended to increase the frequency to lower the inductor  
ripple. Please refer to Figure 25 for frequency selection at different  
Application Information  
Programming the Output Voltage  
operating conditions, then refer to Figure 31 to choose R  
.
SYNC  
The ISL8225M has an internal 0.6V ±0.7% reference voltage.  
Programming the output voltage requires a resistor divider (R1  
and R2) between the VOUT, VSEN+, and VSEN- pins, as shown in  
Figure 18. Please note that the output voltage accuracy is also  
dependent on the resistor accuracy of R1 and R2. The user needs  
to select a high accuracy resistor (i.e. 0.5%) in order to achieve  
the overall output accuracy. The output voltage can be calculated  
as shown in Equation 1:  
Selection of Input Capacitor  
Selection of the input filter capacitor is based on how much  
ripple the supply can tolerate on the DC input line. The larger the  
capacitor, the less ripple expected, however, consideration  
should be given to the higher surge current during power-up. The  
ISL8225M provides a soft-start function that controls and limits  
the current surge. The value of the input capacitor can be  
calculated as shown in Equation 2:  
R1  
R2  
(EQ. 1)  
-------  
V
= 0.6 × 1 +  
I
D(1 D)  
OUT  
O
V
(EQ. 2)  
----------------------------------  
=
C
IN(MIN)  
f  
P-P SW  
Note: It is recommended to use a 1kvalue for the top resistor,  
R1. The value of the bottom resistor for different output voltages  
is shown in Table 4.  
where:  
• C  
is the minimum required input capacitance (µF)  
IN(MIN)  
TABLE 4. VALUE OF BOTTOM RESISTOR FOR DIFFERENT OUTPUT  
• I is the output current (A)  
O
VOLTAGES (V  
vs R2)  
OUT  
• D is the duty cycle  
R1  
V
R2  
OUT  
• V  
is the allowable peak-to-peak voltage (V)  
is the switching frequency (Hz)  
P-P  
()  
(V)  
()  
• f  
1k  
1k  
1k  
1k  
1k  
1k  
1k  
1k  
1k  
1k  
1k  
0.6  
0.8  
1.0  
1.2  
1.5  
1.8  
2.0  
2.5  
3.3  
5.0  
6.0  
Open  
3.01k  
1.50k  
1.00k  
665  
SW  
In addition to the bulk capacitance, some low Equivalent Series  
Resistance (ESR) ceramic capacitance is recommended to  
decouple between the VIN and PGND of each channel. See Table 2  
for some recommended capacitors. This capacitance reduces  
voltage ringing created by the switching current across parasitic  
circuit elements. All these ceramic capacitors should be placed as  
closely as possible to the module pins. The estimated RMS current  
should be considered in choosing ceramic capacitors.  
Io D(1 D)  
491  
422  
316  
--------------------------------  
=
(EQ. 3)  
I
IN(RMS)  
221  
η
137  
Each 10µF X5R or X7R ceramic capacitor is typically good for 2A  
to 3A of RMS ripple current. Refer to the capacitor vendor to  
check the RMS current ratings. In a typical 15A output  
application for one channel, if the duty cycle is 0.5, it needs at  
least three 10µF X5R or X7R ceramic input capacitors.  
110  
Due to the minimum off-time limit of 410ns, the module has a  
maximum output voltage, depending on input voltage. Refer to  
Figure 25 for the 5V input voltage limitation.  
Selection of Output Capacitors  
1100  
20V  
IN  
The ISL8225M is designed for low-output voltage ripple. The  
output voltage ripple and transient requirements can be met with  
bulk output capacitors (COUT) that have adequately low ESR.  
COUT can be a low ESR tantalum capacitor, a low ESR polymer  
capacitor, or a ceramic capacitor. The typical capacitance is  
330µF, and decoupled ceramic output capacitors are used for  
each phase. See Table 1 and Table 2 for more capacitor  
information. Internally optimized loop compensation provides  
sufficient stability margins for all ceramic capacitor applications,  
with a recommended total value of 300µF per phase. Additional  
output filtering may be needed if further reduction of output  
ripple or dynamic transient spike is required.  
1000  
15V  
IN  
900  
800  
700  
600  
500  
12V  
IN  
10V  
IN  
8V  
IN  
5V  
IN  
0
1
2
3
4
5
EN/FF Turn ON/OFF  
V
(V)  
OUT  
Each output of the ISL8225M can be turned on/off independently  
through the EN/FF pins. For parallel use, tie all EN/FF pins together.  
Since this pin has the feed-forward function, the voltage on this pin  
can actively adjust the loop gain to be constant for variable input  
voltage. Please refer to Table 1 to select the resistor divider for  
FIGURE 25. RECOMMENDED FREQUENCY vs V AT V  
IN OUT  
At higher output voltage, the inductor ripple increases, which makes  
both output ripple and inductor power loss higher. Therefore, it is  
FN7822.1  
January 31, 2013  
19  
ISL8225M  
commonly used conditions. Otherwise, use the following procedures  
to finish the EN/FF design:  
Functional Description  
Initialization  
1. A resistor divider from V to GND is recommended to set the  
IN  
EN/FF voltage between 1.25V to 5.0V. The resistor divider  
ratio is recommended to be between 3/1 to 4/1 (as shown in  
Figure 21) with a resistor divider at 7.15k/2.05k.  
Initially, the Power-On Reset (POR) circuits continuously monitor  
bias voltages (V ) and voltage at the EN/FF pin. The POR  
CC  
function initiates soft-start operation 384 clock cycles  
after: (1) the EN pin voltage is pulled above 0.8V, (2) all input  
supplies exceed their POR thresholds, and (3) the PLL locking  
time expires. The Enable pin can be used as a voltage monitor  
and to set the desired hysteresis, with an internal 30µA sinking  
current going through an external resistor divider. The sinking  
current is disengaged after the system is enabled. This feature is  
specially designed for applications that require higher input rail  
POR for better under-voltage protection. For example, in 12V  
2. Check EN turn-on hysteresis (Recommend V  
> 0.3V) :  
(EQ. 4)  
EN_HYS  
5  
V
= N R 3x10  
UP  
EN HYS  
where:  
• R is the top resistor of the resistor divider  
UP  
• N is the total number of the EN/FF pins tied to the resistor divider  
3. Set the maximum current flowing through the top pull-up  
applications, R = 53.6kand R  
turn-on threshold (V  
EN_RTH  
= 5.23ksets the  
UP  
DOWN  
) to 10.6V and the turn-off threshold  
).  
resistor R to below 7mA (considering EN/FF is pulled to  
UP  
ground (V  
= 0)). Refer to Figure 23; a 3.01k/1kΩ  
EN/FF  
(V  
) to 9V, with 1.6V hysteresis (V  
EN_FTH EN_HYS  
resistor is used to allow for the input voltage from 5V to 20V  
operation. In addition, the maximum current flowing through  
R5 is 6.6mA (<7mA).  
During shutdown or fault conditions, soft-start is quickly reset,  
and the gate driver immediately changes state (<100ns) when  
input drops below POR.  
4. If the EN/FF is controlled by system EN signal instead of the  
input voltage, we recommend setting the fixed EN/FF voltage  
to about 1/3.5 of the input voltage. If the input voltage is 12V,  
a 3.3V system EN signal can be tied to EN/FF pin directly.  
Enable and Voltage Feed-forward  
Voltage applied to the EN/FF pin is fed to adjust the sawtooth  
amplitude of the channel. Sawtooth amplitude is set to 1.25 times  
the corresponding FF voltage when the module is enabled. This  
configuration helps maintain a constant gain. This configuration  
also helps maintain input voltage to achieve optimum loop response  
over a wide input voltage range.  
5. If the input voltage is below 5.5V, it is recommended to have  
EN/FF voltage >1.5V to have better stability. The input voltage  
can be directly tied to the VCC pin to disable the internal LDO.  
6. A 1nF capacitor is recommended on the EN/FF pin to avoid  
the noise injecting into the feed-forward loop.  
A 384-cycle delay is added after the system reaches its rising  
POR and prior to soft-start. The RC timing at the FF pin should be  
small enough to ensure that the input bus reaches its static state  
and that the internal ramp circuitry stabilizes before soft-start. A  
large RC could cause the internal ramp amplitude not to  
synchronize with the input bus voltage during output start-up or  
when recovering from faults. A 1nF capacitor is recommended as  
a starting value for typical applications.  
Thermal Considerations  
The ISL8225M QFN package offers typical junction to ambient  
thermal resistance θ of approximately 10°C/W at natural  
JA  
convection (~5.8°C/W at 400LFM) with a typical 4-layer PCB.  
Therefore, use Equation 5 to estimate the module junction  
temperature:  
(EQ. 5)  
T
= P × Θ + T  
junction  
jA ambient  
In a multi-module system, with the EN pins are wired together, all  
modules can immediately turn off, at one time, when a fault  
condition occurs in one or more modules. A fault pulls the EN pin  
low, disabling all modules, and does not create current bounce;  
thus, no single channel is overstressed when a fault occurs.  
where:  
• T  
is the module internal maximum temperature (°C)  
is the system ambient temperature (°C)  
junction  
• T  
ambient  
• P is the total power loss of the module package (W)  
Because the EN pins are pulled down under fault conditions, the  
θ is the thermal resistance of module junction to ambient  
JA  
pull-up resistor (R ) should be scaled to sink no more than 7mA  
UP  
current from the EN pin. Essentially, the EN pins cannot be  
directly connected to VCC.  
If the calculated temperature, T  
design target, the extra cooling scheme is required. Please refer  
to “Current Derating” on page 24 for adding air flow.  
, is over the required  
junction  
VIN  
R
² V  
V
EN_HYS  
UP  
= --------------------------------------------------------------  
EN_REF  
V  
R
V
= ----------------------------  
R
UP  
DOWN  
I
V
R
EN_HYS  
UP  
EN_FTH  
EN_REF  
384  
0.8V  
CLOCK  
EN  
SOFT-START  
= V  
V  
CYCLES  
EN_FTH  
EN_RTH  
EN_HYS  
ON/OFF  
R
DOWN  
I
= 30µA  
EN_HYS  
OV, OT, OC, AND PLL LOCKING FAULTS  
FIGURE 26. SIMPLIFIED ENABLE AND VOLTAGE FEED-FORWARD CIRCUIT  
FN7822.1  
January 31, 2013  
20  
ISL8225M  
Soft-Start  
Power-Good  
The ISL8225M has an internal, digital, pre-charged soft-start  
circuitry (Figures 27 to 29). The circuitry has a rise time inversely  
proportional to the switching frequency. Rise time is determined  
by a digital counter that increments with every pulse of the phase  
clock. The full soft-start time from 0V to 0.6V can be estimated  
as shown in Equation 6. The typical soft-start time is ~2.5ms.  
1280  
Power-good comparators monitor voltage on the VMON pin. Trip  
points are shown in Figure 30. PGOOD is not asserted until the  
soft-start cycle is complete. PGOOD pulls low upon both ENs  
disabling it or when the VMON voltage is out of the threshold  
window. PGOOD does not pull low until the fault presents for  
three consecutive clock cycles.  
------------  
t
=
(EQ. 6)  
UV indication is not enabled until the end of soft-start. In a UV  
event, if the output drops below -13% of the target level due to a  
reason other than OV, OC, OT, or PLL faults (cases when EN is not  
pulled low), PGOOD is pulled low.  
SS  
f
SW  
The ISL8225M is able to work under a pre-charged output. The  
PWM outputs do not feed to the drivers until the first PWM pulse  
is seen. The low-side MOSFET is on for the first clock cycle, to  
provide charge for the bootstrap capacitor. If the pre-charged  
output voltage is greater than the final target level but less than  
the 113% set point, switching does not start until the output  
voltage is reduced to the target voltage and the first PWM pulse  
is generated. The maximum allowable pre-charged level is 113%.  
If the pre-charged level is above 113% but below 120%, the  
output hiccups between 113% (LGATE turns on) and 87% (LGATE  
turns off), while EN is pulled low. If the pre-charged load voltage  
is above 120% of the targeted output voltage, then the controller  
is latched off and cannot power up.  
CHANNEL 1 UV/OV  
CHANNEL 2 UV/OV  
PGOOD  
AND  
END OF SS1  
END OF SS2  
OR  
SS1_PERIOD  
SS2_PERIOD  
AND  
+20%  
SS SETTLING AT VREF + 100mV  
FIRST PWM PULSE  
+13%  
+9%  
VMON1, 2  
V
TARGET VOLTAGE  
OUT  
0.0V  
-100mV  
V
REF  
1280  
t
= ------------  
SS  
f
SW  
-9%  
-13%  
384  
-----------  
t
=
SS_DLY  
f
SW  
PGOOD LATCH OFF  
AFTER 120% OV  
PGOOD  
FIGURE 27. SOFT-START WITH V  
OUT  
= 0V  
FIGURE 30. POWER-GOOD THRESHOLD WINDOW  
Current Share  
In parallel operations, the share bus voltages (I  
SS SETTLING AT VREF + 100mV  
VOUT TARGET VOLTAGE  
FIRST PWM PULSE  
) of  
SHARE  
different modules must tie together. The ISHARE pin voltage is  
set by an internal resistor and represents the average current of  
all active modules. The average current signal is compared with  
the local module current, and the current share error signal is fed  
into the current correction block to adjust each module’s PWM  
pulse accordingly. The current share function provides at least  
10% overall accuracy between modules. The current share bus  
works for up to 12 phases without requiring an external clock. A  
470pF ~1nF capacitor is recommended for each ISHARE pin.  
INIT. V  
OUT  
-100mV  
FIGURE 28. SOFT-START WITH V  
< TARGET VOLTAGE  
OUT  
In current sharing scheme, all slave channels have the feedback  
loops disabled with the VSEN- pin tied to VCC. The master  
channel can control all modules with COMP and ISHARE pins tied  
together. For phase-shift setting, all VMON pins of slave channels  
are needed to set 0.6V for monitoring use only. Typically, the  
slaved VMON pins can be tied together with a resistor divider to  
VOUT. However, if the MODE pin is tied to VCC for mode setting,  
the related VMON2 pin is needed to tie to SGND with a 1.0kΩ  
resistor, as shown in Figure 23 on page 15. If there are multiple  
OV = 113%  
FIRST PWM PULSE  
V
TARGET VOLTAGE  
OUT  
FIGURE 29. SOFT-START WITH V  
TARGET VOLTAGE  
BELOW 113% BUT ABOVE FINAL  
OUT  
FN7822.1  
January 31, 2013  
21  
ISL8225M  
modules paralleled with the MODE pins tied to VCC, each VMON2  
disturbance. After the delay time, the controller initiates a  
soft-start interval. If the output voltage comes up and returns to  
regulation, PGOOD transitions high. If the OC trip is exceeded  
during the soft-start interval, the controller pulls EN low again.  
The PGOOD signal remains low, and the soft-start interval is  
allowed to expire. Another soft-start interval is initiated after the  
delay interval. If an over-current trip occurs again, this same cycle  
repeats until the fault is removed. Since the output voltage may  
trigger the OVP if the output current changes too fast, the module  
can go into latch-off mode. In this case, the module needs to be  
restarted.  
pin of the slave module needs to have a 1.0kresistor to GND  
while all VMON1 pins of the slave modules can be tied together  
with a resistor divider from VOUT to GND, as shown in Figure 24  
on page 16. Also see Table 3 for VMON settings.  
Over-voltage Protection (OVP)  
The over-voltage (OV) protection indication circuitry monitors  
voltage on the VMON pin. OV protection is active from the  
beginning of soft-start. An OV condition (>120%) would latch the  
IC off. In this condition, the high-side MOSFET (Q1 or Q3) latches  
off permanently. The low-side MOSFET (Q2 or Q4) turns on  
immediately at the time of OV trip and then turns off  
Frequency Synchronization and Phase Lock  
Loop  
The SYNC pin has two primary capabilities: fixed frequency  
operation and synchronized frequency operation. ISL8225M has  
an internally set fixed frequency of 500kHz. By tying a resistor  
permanently after the output voltage drops below 87%. EN and  
PGOOD are also latched low in an OV event. The latch condition  
can be reset only by recycling V  
.
CC  
There is another non-latch OV protection (113% of target level).  
When EN is low and output is over 113% OV, the low-side  
MOSFET turns on until output drops below 87%. This action  
protects the power trains when even a single channel of a  
multi-module system detects OV. The low-side MOSFET always  
turns on when EN = LOW and the output voltage rises above  
113% (all EN pins are tied together) and turns off after the output  
drops below 87%. Thus, in a high phase count application  
(multi-module mode), all cascaded modules can latch off  
simultaneously via the EN pins (EN pins are tied together in  
multi-phase mode). Each channel shares the same sink current  
to reduce stress and eliminate bouncing among phases.  
(R  
) to SGND from the SYNC pin, the switching frequency can  
SYNC  
be set to be more than 500kHz. To increase the switching  
frequency, select an externally connected resistor, R , from  
SYNC  
SYNC to SGND according to the frequency setting curve shown in  
Figure 31. See Table 1 for R  
at commonly used frequency.  
SYNC  
800  
700  
600  
500  
400  
300  
200  
100  
0
Over-Temperature Protection (OTP)  
When the junction temperature of the internal controller is  
greater than +150°C (typically), the EN pin is pulled low to inform  
other cascaded channels via their EN pins. All connected ENs  
stay low and then release after the module’s junction  
temperature drops below +125°C (typically), a +25°C hysteresis  
(typically).  
500  
600 700 800 900 1000 1100 1200 1300 1400 1500  
FREQUENCY (kHz)  
FIGURE 31. R  
vs SWITCHING FREQUENCY  
SYNC  
Over-current Protection (OCP)  
The OCP peak level is set to about 20A for each channel, but the OC  
Connecting the SYNC pin to an external square-pulse waveform  
(such as the CLKOUT signal, typically 50% duty cycle from  
another ISL8225M) synchronizes the ISL8225M switching  
frequency to the fundamental frequency of the input waveform.  
The synchronized frequency can be from 150kHz to 1500kHz.  
The applied square-pulse recommended high level voltage range  
trip point can vary, due mainly to MOSFET r  
variations (over  
DS(ON)  
process, current, and temperature). The OCP can be increased by  
increasing the switching frequency since the inductor ripple is  
reduced. However, the module efficiency drops accordingly with  
more switching loss. When OCP is triggered, the controller pulls  
EN low immediately to turn off all switches. The OCP function is  
enabled at start-up and has a 7-cycle delay before it triggers.  
is 3V to V +0.3V. The frequency synchronization feature  
CC  
synchronizes the leading edge of the CLKOUT signal with the  
falling edge of Channel 1’s PWM signal. CLKOUT is not available  
until PLL locks. No capacitor is recommended on the SYNC pin.  
In multi-module operation, ISHARE pins can be connected to  
create V  
, which represents the average current of all  
ISHARE  
Locking time is typically 130µs. EN is not released for a soft-start  
cycle until SYNC is stabilized and PLL is locking. Connecting all  
EN pins together in a multi-phase configuration is recommended.  
active channels. Total system currents are compared with a  
precision threshold to determine the over-current condition. Each  
channel also has an additional over-current set point with a  
7-cycle delay. This scheme helps protect modules from damage  
in multi-module mode by having each module carry less current  
than the set point.  
Loss of a synchronization signal for 13 clock cycles causes the  
module to be disabled until PLL returns locking, at which point, a  
soft-start cycle is initiated and normal operation resumes.  
Holding SYNC low disables the module. Please note that the  
quick change of the synchronization signal can cause module  
shutdown.  
For overload and hard short conditions, over-current protection  
reduces the regulator RMS output current to much less than full  
load by putting the controller into hiccup mode. A delay equal to  
three soft-start intervals is entered to allow time to clear the  
FN7822.1  
January 31, 2013  
22  
ISL8225M  
Tracking Function  
Layout Guide  
If CLKOUT is less than 800mV, an external soft-start ramp (0.6V)  
can be in parallel with the Channel 2 internal soft-start ramp for  
tracking applications. Therefore, the Channel 2’s output voltage  
can track the output voltage of Channel 1.  
To achieve stable operation, low losses, and good thermal  
performance, some layout considerations are necessary  
(Figure 32).  
• VOUT1, VOUT2, PHASE1, PHASE2, PGND, VIN1 and VIN2  
should have large, solid planes. Place enough thermal vias to  
connect the power planes in different layers under or around  
the module.  
The tracking function can be applied to a typical Double Data  
Rate (DDR) memory application, as shown in Figure 20 on  
page 13. The output voltage (typical VTT output) of Channel 2  
tracks with the input voltage [typical VDDQ*(1+k) from  
Channel 1] at the CLKOUT pin. As for the external input signal  
and the internal reference signal (ramp and 0.6V), the one with  
the lowest voltage is used as the reference for comparing with  
the FB signal. In DDR configuration, VTT channel should start up  
later, after its internal soft-start ramp, such that VTT tracks the  
voltage on the CLKOUT pin derived from VDDQ. This configuration  
can be achieved by adding more filtering at EN/FF1 than at  
EN/FF2.  
• Place high-frequency ceramic capacitors between VIN, VOUT,  
and PGND, as closely to the module as possible in order to  
minimize high-frequency noise.  
• Use remote sensed traces to the regulation point to achieve  
tight output voltage regulation, and keep the sensing traces  
close to each other in parallel.  
• PHASE1 and PHASE2 pads are switching nodes that generate  
switching noise. Keep these pads under the module. For  
noise-sensitive applications, it is recommended to keep phase  
pads only on the top and inner layers of the PCB. Also, do not  
place phase pads exposed to the outside on the bottom layer  
of the PCB.  
The resistor divider ratio (k) of R7/R8 in Figure 20 is calculated  
as shown in Equation 7:  
V
TT  
(EQ. 7)  
------------  
k =  
1  
0.6V  
• Avoid routing any noise-sensitive signal traces, such as the  
VSEN+, VSEN-, ISHARE, COMP and VMON sensing points, near  
the PHASE pins.  
Mode Programming  
ISL8225M can be programmed for dual-output, paralleled  
single-output or mixed outputs (Channel 1 in parallel and  
Channel 2 in dual-output). With multiple ISL8225Ms, up to 6  
modules using its internal cascaded clock signal control, the  
modules can supply large current up to 180A. For complete  
operation, please refer to Table 3 on page 18. Commonly used  
settings are listed in Table 5.  
• Use a separated SGND ground copper area for components  
connected to signal ground pins. Connect SGND to PGND with  
multiple vias underneath the unit in one location to avoid the  
noise coupling, as shown in Figure 32. Don't ground vias  
surrounded by the noisy planes of VIN, PHASE and VOUT. For  
dual output applications, the SGND to PGND vias are preferred  
to be as close as possible to SGND pin.  
TABLE 5. PHASE-SHIFT SETTING  
• Optional snubbers can be put on the bottom side of the board  
layout, connecting the PHASE to PGND planes, as shown in  
Figure 32.  
PHASE-SHIFT  
OPERATION  
BETWEEN PHASES VSEN2- VSEN2+ CLKOUT MODE  
Dual Output  
(Figure 18)  
180°  
180°  
90°  
N/C  
VCC  
VCC  
VCC  
N/C  
N/C  
VCC  
N/C  
VCC  
N/C  
N/C  
N/C  
N/C  
SGND  
VCC  
COUT2  
COUT1  
PGND  
R3  
PGND  
R1  
30A  
(Figure 19)  
VOUT2  
VOUT1  
+
-
+
-
TO LOAD  
R4  
TO LOAD  
R2  
60A  
(Figure 22)  
KELVIN CONNECTIONS  
FOR THE VSENS LINES  
KELVIN CONNECTIONS  
FOR THE VSENS LINES  
PIN 1  
90A  
60°  
SGND  
(Figure 24)  
SGND  
VIN2  
VIN1  
When the module is in the dual-output condition, depending  
upon the voltage level at CLKOUT (which is set by the VCC resistor  
divider output), ISL8225M operates with phase shifted as the  
CLKOUT voltage shown in Table 6. The phase shift is latched as  
CIN2  
CIN1  
PHASE2  
PHASE1  
V
rises above POR; it cannot be changed on the fly.  
CC  
OPTIONAL SNUBBER  
OPTIONAL SNUBBER  
TABLE 6. CLKOUT TO PROGRAM PHASE SHIFT AT DUAL-OUTPUT  
CLKOUT  
VOLTAGE SETTING  
PHASE FOR CLKOUT WRT RECOMMENDED  
PGND  
CHANNEL 1  
CLKOUT VOLTAGE  
<29% of V  
CC  
-60°  
15% V  
37% V  
53% V  
CC  
CC  
CC  
FIGURE 32. RECOMMENDED LAYOUT  
29% to 45% of V  
90°  
CC  
CC  
45% to 62% of V  
120°  
62% of V  
CC  
180°  
V
CC  
FN7822.1  
January 31, 2013  
23  
ISL8225M  
pad and the I/O termination dimensions, except that the PCB  
Current Derating  
Experimental power loss curves (Figures 33 and 34), along with  
lands are slightly longer than the QFN terminations by about  
0.2mm (0.4mm max). This extension allows for solder filleting  
around the package periphery and ensures a more complete and  
inspectable solder joint. The thermal lands on the PCB layout  
should match 1:1 with the package exposed die pads.  
θ
from thermal modeling analysis, can be used to evaluate the  
JA  
thermal consideration for the module. Derating curves are  
derived from the maximum power allowed while maintaining  
temperature below the maximum junction temperature of  
+120°C (Figures 35 through 40). The maximum +120°C  
junction temperature is considered for the module to load the  
current consistently and it provides the 5°C margin of safety  
from the rated junction temperature of +125°C. If necessary,  
customers can adjust the margin of safety according to the real  
applications. All derating curves are obtained from the tests on  
the ISL8225MEVAL4Z evaluation board. In the actual  
application, other heat sources and design margins should be  
considered.  
Thermal Vias  
A grid of 1.0mm to 1.2mm pitched thermal vias, which drops  
down and connects to buried copper planes, should be placed  
under the thermal land. The vias should be about 0.3mm to  
0.33mm in diameter, with the barrel plated to about 2.0 ounce  
copper. Although adding more vias (by decreasing pitch)  
improves thermal performance, it also diminishes results as  
more vias are added. Use only as many vias as are needed for  
the thermal land size and as your board design rules allow.  
Package Description  
Stencil Pattern Design  
The ISL8225M is integrated into a quad flat-pack no-lead  
package (QFN). This package has such advantages as good  
thermal and electrical conductivity, low weight, and small size.  
The QFN package is applicable for surface mounting technology  
and is becoming more common in the industry. The ISL8225M  
contains several types of devices, including resistors, capacitors,  
inductors, and control ICs. The ISL8225M is a copper lead-frame  
based package with exposed copper thermal pads, which have  
good electrical and thermal conductivity. The copper lead frame  
and multi-component assembly are over-molded with polymer  
mold compound to protect these devices.  
Reflowed solder joints on the perimeter I/O lands should have  
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder  
paste stencil design is the first step in developing optimized,  
reliable solder joins. The stencil aperture size to land size ratio  
should typically be 1:1. Aperture width may be reduced slightly to  
help prevent solder bridging between adjacent I/O lands.  
To reduce solder paste volume on the larger thermal lands, an  
array of smaller apertures instead of one large aperture is  
recommended. The stencil printing area should cover 50% to  
80% of the PCB layout pattern. A typical solder stencil pattern is  
shown in the L26.17x17 package outline drawing on page 28.  
The gap width between pads is 0.6mm. Consider the symmetry  
of the whole stencil pattern when designing the pads.  
The package outline, typical PCB layout pattern, and typical  
stencil pattern design are shown in the L26.17x17 package  
outline drawing on page 27. Figure 41 shows typical reflow  
profile parameters. These guidelines are general design rules.  
Users can modify parameters according to specific applications.  
A laser-cut, stainless-steel stencil with electropolished  
trapezoidal walls is recommended. Electropolishing smooths the  
aperture walls, resulting in reduced surface friction and better  
paste release, which reduces voids. Using a trapezoidal section  
aperture (TSA) also promotes paste release and forms a  
brick-like paste deposit, which assists in firm component  
placement. A 0.1mm to 0.15mm stencil thickness is  
recommended for this large-pitch (1.0mm) QFN.  
PCB Layout Pattern Design  
The bottom of ISL8225M is a lead-frame footprint, which is  
attached to the PCB by surface mounting. The PCB layout pattern  
is shown in the L26.17x17 package outline drawing on page 28.  
The PCB layout pattern is essentially 1:1 with the QFN exposed  
7
6
5
4
3
8
7
6
5
12V TO 2.5V  
IN  
OUT  
4
3
2
1
0
5V TO 2.5V  
IN  
OUT  
2
1
0
5V TO 1V  
IN  
OUT  
12V TO 1V  
IN  
OUT  
20  
12V TO 1.5V  
IN  
OUT  
5V TO 1.5V  
IN  
OUT  
0
5
10  
15  
20  
25  
30  
0
5
10  
15  
25  
30  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
FIGURE 33. POWER LOSS CURVES OF 5V  
FIGURE 34. POWER LOSS CURVES OF 12V  
IN  
IN  
FN7822.1  
January 31, 2013  
24  
ISL8225M  
Derating Curves All of the following curves were plotted at T = +120°C.  
J
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
400LFM  
200LFM  
200LFM  
400LFM  
0LFM  
0LFM  
0
25  
0
45  
65  
85  
105  
125  
25  
45  
65  
85  
105  
125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 35. DERATING CURVE 5V TO 1V  
IN  
FIGURE 36. DERATING CURVE 12V TO 1V  
IN  
OUT  
OUT  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
400LFM  
200LFM  
0LFM  
400LFM  
200LFM  
0LFM  
0
25  
0
25  
45  
65  
85  
105  
125  
45  
65  
85  
105  
125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 37. DERATING CURVE 5V TO 1.5V  
IN  
FIGURE 38. DERATING CURVE 12V TO 1.5V  
IN  
OUT  
OUT  
30  
30  
25  
20  
15  
10  
5
400LFM  
25  
20  
15  
10  
5
400LFM  
200LFM  
0LFM  
0LFM  
200LFM  
0
25  
0
25  
45  
65  
85  
105  
125  
45  
65  
85  
105  
125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 39. DERATING CURVE 5V TO 2.5V  
IN  
FIGURE 40. DERATING CURVE 12V TO 2.5V  
IN OUT  
OUT  
FN7822.1  
January 31, 2013  
25  
ISL8225M  
Reflow Parameters  
300  
250  
200  
150  
100  
50  
PEAK TEMPERATURE +230°C~+245°C;  
TYPICALLY 60s-70s ABOVE +220°C  
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.  
Due to the low mount height of the QFN, "No Clean" Type 3 solder  
paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is  
also recommended during reflow. A system board reflow profile  
depends on the thermal mass of the entire populated board, so it  
is not practical to define a specific soldering profile just for the  
QFN. The profile given in Figure 41 is provided as a guideline to  
customize for varying manufacturing practices and applications.  
SLOW RAMP (3°C/s MAX)  
AND SOAK FROM +100°C  
TO +180°C FOR 90s~120s  
RAMP RATE 1.5°C FROM +70°C TO +90°C  
0
0
100  
150  
200  
250  
300  
350  
DURATION (s)  
FIGURE 41. TYPICAL REFLOW PROFILE  
Revision History  
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you  
have the latest revision.  
DATE  
REVISION  
FN7822.1  
CHANGE  
January 4, 2013  
“Thermal Information” on page 6:  
Changed “Maximum Storage Temperature Range” from "-40°C to +150°C" to "-55°C to +150°C"  
“Selection of Input Capacitor” on page 19:  
Added "f " to Equation 2. Added "f  
SW  
is the switching frequency (Hz)"  
SW  
December 3, 2012  
FN7822.0  
Initial Release  
About Intersil  
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management  
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,  
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of  
our winning team, visit our website and career page at www.intersil.com.  
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.  
Also, please check the product information page to ensure that you have the most updated datasheet: ISL8225M  
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff  
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php  
For additional products, see www.intersil.com/en/products.html  
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted  
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time  
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be  
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third  
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN7822.1  
January 31, 2013  
26  
ISL8225M  
Package Outline Drawing  
L26.17x17  
26 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)  
Rev 4, 10/12  
17.8±0.2  
17.0±0.2  
9
8
7 6 5 4 3 2  
9
8
7 6 5 4 3 2  
1
26  
1
26  
10  
11  
12  
10  
11  
12  
25  
24  
23  
25  
24  
23  
22  
21  
22  
21  
13  
14  
1516171819 20  
13  
14  
151617181920  
PIN NO. DEFINITION (TOP VIEW)  
TOP VIEW  
X4  
0.2 S AB  
16X 0.70 (FULL LEAD)  
3.66  
4.00  
3.50  
A A A A A A A A A A A A A  
3.50  
0.80  
8.95  
12  
10  
12  
B
8.95  
10  
1
1
A:1.0±0.1  
3.35  
14x 0.75  
3.35  
2.97  
A A A A A A A A A A A A A  
16x 1.75±0.05 (FULL LEAD)  
PIN-TO-PIN DISTANCE (BOTTOM VIEW)  
0.05 S AB  
A
BOTTOM VIEW  
S 0.2  
SIDE VIEW  
S
FN7822.1  
January 31, 2013  
27  
ISL8225M  
9.30  
7.83  
6.53  
6.50  
6.13  
5.73  
5.33  
0.75  
0.65  
0.40  
0.25  
9.30  
7.15  
6.35  
5.65  
5.35  
4.65  
4.35  
1
10  
12  
0.75  
0.35  
0
0.35  
0.75  
0.25  
0.40  
0.65  
0.75  
4.35  
4.65  
5.35  
5.65  
6.35  
7.15  
9.30  
5.33  
5.73  
6.13  
6.50  
6.53  
7.83  
9.30  
TYPICAL RECOMMENDED LAND PATTERN (TOP VIEW)  
7.25  
6.25  
5.75  
5.25  
4.75  
9.20  
7.93  
5.25  
4.75  
4.25  
3.75  
3.25  
2.75  
2.25  
1.75  
1.25  
0.85  
0.15  
4.25  
3.75  
7.38  
6.83  
3.25 6.43  
2.75 5.43  
2.25 5.03  
1.75 3.36  
1.25 2.76  
0.95 0.95  
7.38  
6.60  
4.05  
2.70  
2.40  
0.25  
1.05  
0.00  
1.05  
0.70  
0
0.15  
0.85  
1.25  
1.75  
0
0
0.70  
0.95  
0.25  
0.95  
2.40  
2.70  
4.05  
1.25  
1.75  
3.36  
2.25  
2.75  
3.25  
3.75  
4.25  
4.75  
2.25  
2.75  
3.25  
3.75  
4.25  
4.75  
5.25  
5.75  
6.25  
7.25  
5.03  
5.43  
6.43  
6.83  
7.38  
6.60  
7.38  
5.25  
7.93  
SOLDER STENCIL PATTERN WITH SQUARE PADS 2 OF 2 (TOP VIEW)  
SOLDER STENCIL PATTERN WITH SQUARE PADS 1 OF 2 (TOP VIEW)  
FN7822.1  
January 31, 2013  
28  

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TAIYO YUDEN

TMK325BJ335MN-T

Capacitor, Ceramic, Chip, General Purpose, 3.3uF, 25V, ±20%, X5R, 1210 (3225 mm), 0.075"T, -55º ~ +85ºC, 7" Reel/4mm pitch
TAIYO YUDEN

TMK325BJ475KN-B

Ceramic Capacitor, Multilayer, Ceramic, 25V, 10% +Tol, 10% -Tol, X5R, 15% TC, 4.7uF, Surface Mount, 1210, CHIP
TAIYO YUDEN

TMK325BJ475KN-T

Capacitor, Ceramic, Chip, General Purpose, 4.7uF, 25V, ±10%, X5R, 1210 (3225 mm), 0.075"T, -55º ~ +85ºC, 7" Reel/4mm pitch
TAIYO YUDEN

TMK325BJ475KNHT

Multilayer Ceramic Capacitors (High dielectric type) for Automotive
TAIYO YUDEN

TMK325BJ475MN-T

Capacitor, Ceramic, Chip, General Purpose, 4.7uF, 25V, ±20%, X5R, 1210 (3225 mm), 0.075"T, -55º ~ +85ºC, 7" Reel/4mm pitch
TAIYO YUDEN

TMK325BJ475MNHT

CAP CER 4.7UF 25V X5R 1210
TAIYO YUDEN

TMK325C7226MM-T

CAP CER 22UF 25V X7S 1210
TAIYO YUDEN

TMK325F106ZH-T

Ceramic Capacitor, Multilayer, Ceramic, 25V, 80% +Tol, 20% -Tol, Y5V, -82/+22% TC, 10uF, Surface Mount, 1210, CHIP
TAIYO YUDEN

TMK325F225ZH-T

CAP CER 2.2UF 25V Y5V 1210
TAIYO YUDEN