概述
数据手册SP601 概述
Half Bridge 500VDC Driver 半桥驱动器500VDC
SP601 数据手册
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PDF下载SP601
®
July 1998
File Number 2429.5
Features
Half Bridge 500VDC Driver
• Maximum Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
The SP601 is a smart power high voltage integrated circuit
(HVIC) optimized to drive MOS gated power devices in half-
bridge topologies. It provides the necessary control and
management for PWM motor drive, power supply, and UPS
applications.
• Ability to Interface and Drive Standard and Current
Sensing N-Channel Power MOSFET/IGBT Devices
• Creation and Management of a Floating Power Supply
for Upper Rail Drive
• Simultaneous Conduction Lockout
• Overcurrent Protection
Ordering Information
• Single Low Current Bias Supply Operation
• Latch Immune CMOS Logic
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
• Peak Drive in Excess of 0.5A
o
o
SP601
-40 C to +85 C
22 Lead Plastic DIP
Pinout
Functional Block Diagram
V
BS
SP601 (PDIP)
12
TOP VIEW
D1U
19
G1U
V
10Ω R
ND
UP/
BIAS
22
21
20
19
1
2
3
4
5
6
7
8
9
FAULT
DOWN
EN-
3
I
18
I
ONT
TRIPSEL
V
ABLE
NC
DD
4
S
I
LEVEL
SHIFT
OFFT
G2U
V
Q
BIAS
R
17
V
D1U
DD
3.5Ω R
V
BS
DF
TRIP
15
U
V
18 G1U
17 G2U
SS
UV
+
-
11
LOCK
OUT
TRIP
L
CL2
16
CL2
CL1
G2L
G1L
D1L
16
15 TRIP
U
PHASE
14
14 PHASE
S
R
I
UP/DN
22
TRIPSEL
Q
V
13
10
11
3.5Ω R
OUT
O
V
OUT
V
12 V
BS
DF
13
D1L
10
I
ONB
G1L
S
R
ENABLE
21
Q
9
G2L
I
OFFB
CMOS
TIMING
AND
V
OUT
SENSE
AND
8
CONTROL
FILTER
UV
LOCK
OUT
TRIP
FAULT
L
750Ω R
FAULT
1
F
+
-
6
S
CL1
Q
R
7
I
TRIPSEL
FILTER
S
R
Q
I
V
TRIPSEL
SS
2
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
SP601
Absolute Maximum Ratings Full Temperature Range, All
Voltage Referenced to V Unless Otherwise Noted. Note 1, Note 2.
Thermal Information
SS
Low Voltage Power Supply, V
(Note 1). . . . . . . . . . . . . . 18V
Thermal Resistance, Junction-to-Ambient
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at T = +85 C, P
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Operating Ambient Temperature Range, T . . . . . . .-40 C to +85 C
Storage Temperature Range, T . . . . . . . . . . . . . .-40 C to +150 C
S
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265 C
θ
JA
75 C/W
BIAS
Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18V
DC
DC
o
o
Power Supply to Phase, V
Low Voltage Signal Pins
BS
A O
o
o
o
o
Fault, I
, V , TRIP , CL1, G2L . . .-0.5V
to V
+0.5
TRIPSEL DD
L
DC
DD
A
o
G1L, D1L, V , TOP, BOT
DF
CL2, TRIP , G1U, G2U, D1U to Phase . . . .-0.5
U
to V +0.5
BS
VDC
High Voltage Pins
Phase, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
DC
PHASE
(V , V , TRIP , CL2, G2U and D1U: 0V-18V Higher Than
BS OUT
Phase)
Dynamic High Voltage Rating Phase,. . . . . . . . . . . . . 10,000V/µs
U
DV
PHASE/DT
NOTES:
1. Care must be taken in the application of V
as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (R ).
ND
BIAS
Prolonged high peak currents may result if +15V
is applied abruptly and/or if the local bypass capacitor C
is large. It is suggested that C
be ≤ 10MFD.
DC
DD
is larger, additional series impedance may be required.
DD
DD
If it is desirable to switch the 15V
source or if a C
DC
2. Consult factory for additional package offerings.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications (V
= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V Except TRIP ,
SS U
BIAS
CL2, G1U, D1U, and V
Referenced to PHASE. D : V to V , C : V to PHASE
BS
F
DF BS BS
F
PARAMETER
DC CHARACTERISTICS
Input Current (5V < V
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
o
, V
, V
< 15V)
I
+25 C
-
20
30
1.7
1.7
1.7
1.7
875
900
8
30
33
µA
µA
mA
mA
mA
mA
µA
µA
V
TOP BOT TRIPSEL
IN
o
o
-40 C to +85 C
-
o
I
I
Quiescent Current (All Inputs Low)
I
+25 C
-
-
2.05
2.1
2.05
2.1
1000
1060
9
BIAS
BIAS
L
o
o
-40 C to +85 C
o
Quiescent Current
I
+25 C
-
BIAS
BIAS
H
(V
≥ V , and All Inputs Low)
BIAS
OUT
o
o
-40 C to +85 C
-
o
I
Quiescent Current Bootstrap Supply
I
+25 C
-
BS
BS
o
o
-40 C to +85 C
-
o
ENABLE Threshold Level
V
+25 C
7
TOP
BOT
o
o
-40 C to +85 C
6.95
7
8
9.1
9
V
o
UP/DN Threshold Level
V
+25 C
8
V
o
o
-40 C to +85 C
6.95
7
8
9.1
9
V
o
Current Trip Select Threshold Level
V
+25 C
8
V
TRIPSEL
o
o
-40 C to +85 C
6.95
90
90
110
109
8
9.1
125
127
150
152
V
o
Trip Lower and Upper Comparator Threshold
Level - Normal (I = V
V
+25 C
105
105
130
130
mV
mV
%
TRIP L/U
N
)
TRIPSEL SS
o
o
-40 C to +85 C
o
Trip Lower and Upper Comparator Threshold
Level - Boost (I = V ) % of Measured
V
+25 C
TRIP L/U
B
TRIPSEL DD
o
o
-40 C to +85 C
%
V
TRIP L/U
N
o
Under Voltage Lockout Thresholds (V
DD
and V
)
V
V
+25 C
9
10
10.5
7
11.5
11.8
9
V
V
V
V
Ω
Ω
BS
LOCK
o
o
-40 C to +85 C
9.7
5
o
Phase Out of Status Voltage Threshold (PHASE)
+25 C
OSVT
o
o
-40 C to +85 C
4.7
500
450
7
9.6
o
Faultbar Impedance at I
FBAR
= 1mA
RF
+25 C
760
760
1000
1100
o
o
-40 C to +85 C
2
SP601
Electrical Specifications (V
= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V Except TRIP ,
BIAS
SS
U
CL2, G1U, D1U, and V
Referenced to PHASE. D : V to V , C : V to PHASE (Continued)
BS
F
DF BS BS
F
PARAMETER
Upper/Lower Source Impedances (I
SYMBOL
R
TEMP
MIN
TYP
17
17
12
12
3.5
3.5
10
10
1
MAX
23
29
16
20
5
UNITS
o
= 10mA)
+25 C
12
7
Ω
Ω
SOURCE
SO L/U
o
o
-40 C to +85 C
o
Upper/Lower Sink Impedances (I
SINK
= 10mA)
R
+25 C
8
Ω
SI L/U
o
o
-40 C to +85 C
5
Ω
o
Bootstrap Supply Current Limiting Impedance
Noise Dropping Resistor Impedance
R
+25 C
2
Ω
BS
ND
LK
o
o
-40 C to +85 C
1.4
6
5.6
14
14.6
3
Ω
o
R
+25 C
Ω
o
o
-40 C to +85 C
5.4
-
Ω
o
High Voltage Leakage (500V V , V
BS OUT
, PHASE,
I
+25 C
µA
TRIP , CL2, G1U, G2U, and D1U to V
.
U
SS
All other Pins at V
)
SS
o
Miller Clamp Diodes; D1U and D1L (I = 10mA)
V
+25 C
0.4
6.35
6.15
7.0
0.9
6.61
6.61
8.5
1.4
6.85
7.15
8.0
V
V
V
V
D
D1U/L
o
Noise Clamping Zeners; CL2 and CL1 (I = 10mA)
V
+25 C
Z
CL2/1-LOW
o
o
-40 C to +85 C
o
Noise Clamping Zeners; CL2 and CL1 (I = 50mA)
V
+25 C
Z
CL2/1-
HIGH
o
V
Limiting Resistance
R
+25 C
2
3.5
3.5
5
Ω
Ω
OUT
O
o
o
-40 C to +85 C
1.4
5.6
NOTE: Maximum Steady State ÷ 15V
Supply Current = I ÷ I
BIAS BS
L
DC
Switching Specifications (All Referenced to V , Except: TRIP , Cl2, G1U, G2U, and D1U Referenced to PHASE.
SS
U
D : V to V , C : V to PHASE)
F
DF BS BS
F
PARAMETER
Refresh One Shot Timer
SYMBOL
TEMP
MIN
200
180
2
TYP
350
350
3
MAX
500
540
4
UNITS
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
o
t
+25 C
REF
o
o
-40 C to +85 C
o
Delay Time of Trip I/U Voltage (I
G2U/G2L Low (50% Overdrive
low) to
t
+25 C
TRIPSEL
OFF
TN
o
o
-40 C to +85 C
1.85
2
3
4.35
4
o
Delay Time of Trip I Voltage (I
Faultbar Low
low) to
t
+25 C
3
TRIPSEL
FN
o
o
-40 C to +85 C
1.85
500
400
300
275
1.6
3
4.35
900
1050
600
660
3.1
o
Delay Time of Phase Out of Status to Faultbar
Low (TOP High)
t
+25 C
700
700
430
430
2.3
2.4
2.0
2.1
3.2
3.3
3.2
3.3
1.0
1.1
OSVF
o
o
-40 C to +85 C
o
Minimum Logic Input Pulse Width: TOP and
BOTTOM
t
+25 C
MINIW
o
o
-40 C to +85 C
o
Minimum G1U/G1L On Time
t
+25 C
ON
o
o
-40 C to +85 C
1.5
3.4
o
Minimum Pulsed Off Time, G2U/G2L
Turn On Delay Time of G1U (BISTATE MODE)
Turn On Delay Time of G1L (BISTATE MODE)
t
+25 C
1.3
3.4
OFF
o
o
-40 C to +85 C
1.05
2.5
3.9
o
t
+25 C
4.5
ON
D
o
o
-40 C to +85 C
2.1
5.2
o
t
+25 C
2.5
4.5
ON
D
D
o
o
-40 C to +85 C
2.1
5.2
o
Turn On Delay Time of G1U
(THREE-STATE MODE)
t
+25 C
0.75
0.60
1.5
ON
o
o
-40 C to +85 C
1.75
3
SP601
Switching Specifications (All Referenced to V , Except: TRIP , Cl2, G1U, G2U, and D1U Referenced to PHASE.
SS
U
D : V to V , C : V to PHASE) (Continued)
F
DF
BS
F
BS
PARAMETER
Turn On Delay Time of G1L
SYMBOL
TEMP
MIN
0.75
0.60
0.75
0.60
1.5
TYP
1.0
1.1
1.0
1.1
2.5
2.6
4.5
4.8
50
MAX
1.5
UNITS
µs
o
t
+25 C
ON
D
(THREE-STATE MODE)
o
o
-40 C to +85 C
1.75
1.45
1.75
3.5
µs
o
Turn Off Delay Time of G2U and G2L
t
+25 C
µs
OFF
D
o
o
-40 C to +85 C
µs
o
Minimum Dead Time: G1U OFF to G1L ON, or
G1L off to G1U on (BISTATE MODE)
t
+25 C
µs
D.T.
o
o
-40 C to +85 C
1.2
4
µs
o
Fault Reset Delay to Clear Faultbar
t
+25 C
3.4
6.6
µs
R.T.
o
o
-40 C to +85 C
3.15
25
7.4
µs
o
Rise Time of Upper and Lower Driver
(Load = 2000pF)
t
+25 C
100
115
100
115
ns
R U/L
o
o
-40 C to +85 C
15
50
ns
o
Fall Time of Upper and Lower Driver
(Load = 2000pF)
t
+25 C
25
50
ns
F U/L
o
o
-40 C to +85 C
15
50
ns
Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to V , Unless
SS
Otherwise Noted. See Figure 1)
PARAMETER
CONDITION
FAULTBAR
Open Drain Fault Indicator Output
Digital Input Command to Increase TRIP and TRIP Threshold by 30%
I
TRIPSELECT
L
U
V
14.5V to 16.5V with 15V nominal, ≅ 1.5mA DC BIAS Current
C to V
DD
BIAS
V
DD
SS
V
COMMON
SS
TRIP I
CL1
100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output
Lower Noise Clamp Zener
G2L and G1L
Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER)
Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply
V
V
DF
Bootstrap Supply, Normally a Diode Drop Below V
Load Connection Node
Voltage with Respect to the Floating PHASE Reference
BS
DD
V
OUT
PHASE
TRIP
Floating Reference Point for High Side Control Circuitry: V , TRIP , CL2, G1U, G2U and D1U
BS
U
100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive
U
CL2
G2U and G1U
ENABLE
UP/DN
Upper Noise Clamp Zener
Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER)
Digital Input to ENABLE the UP/DN Command to Turn on Top/Bottom Devices
Digital Input to Top/Bottom Device (If ENABLE is High)
D1U
Miller Clamp UPPER to V
BS
D1L
Miller Clamp LOWER to V
DD
4
SP601
Timing Diagram
ENABLE
1
0
ENABLE
1
0
1
0
1
1
0
UP/DOWN
UP/DOWN
1
REFRESH
ONE SHOT
REFRESH
ONE SHOT
0
1
0
1
I
B
I
B
ON
ON
0
1
0
1
VALID BOT
ON
VALID BOT
ON
0
1
0
1
I
T
T
OFF
I
T
OFF
0
1
0
1
0
1
I
ON
I
T
ON
0
1
0
1
I
B
I
B
OFF
OFF
0
1
UPPER
LOWER
UPPER
LOWER
0
1
0
1
0
0
V
DC
V
DC
V
OUT
V
OUT
COM
COM
THREE-STATE MODE SLOWER THAN REFRESH ONE SHOT TIMER
BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER
NOTE: BOT switching not relevant.
Typical Circuit Configuration
TRUTH TABLE
Applicable to Typical Circuit Configuration (Figure 1)
INPUTS
OUTPUTS
UP/DN
ENABLE
TRIP
TRIP
X
PHASE
V
UPPER
LOWER
FAULT BAR
L
U
BIAS
0
1
1
1
X
0
1
X
0
1
1
1
X
1
0
X
0
0
0
0
1
0
0
X
X
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
X
0
X
X
X
X
X
X
X
X
NOTE: 0 = False, 1 = True, X = Don’t Care
5
SP601
25V
≤ V
LINK
≤ 500V
DC
DC
R
R
CU
DU
17
R
U
PU
19 18
14
15
13
D1U G1U G2U TRIP
PHASE
V
OUT
C
F
12
11
10
9
21
22
1
V
BS
BOT
TOP
D
V
F
OUT
I
BS
V
DF
SP601
HVIC
LOAD
D1L
G1L
R
CL
DL
FAULT
R
2
8
6
I
TRIPSELECT
G2L
V
V
V
TRIP
BIAS
DD
SS
L
R
PL
COM
3
4
5
15V
C
DD
I
BIAS
FIGURE 1. TYPICAL CIRCUIT CONFIGURATION
LEGEND
Application Specific
Application Specific
Application Specific
Application Specific
Application Specific
Application Specific
3µF at ≥ 15DC
R
R
R
Upper Gate Charging Resistor
Upper Gate Discharge Resistor
Upper Current Pilot Resistor
Lower Gate Charging Resistor
Lower Gate Discharging Resistor
Lower Current Pilot Resistor
Local LV Filter Capacitor
CU
DU
PU
R
R
R
CL
DL
PL
C
DD
0.22µF Ceramic X7R at ≥ 15V
C
Flying Capacitor for Bootstrap Supply
Flying Diode for Bootstrap Supply
DC
F
F
Intersil P/N A114M or Equiv PRV ≥ V
D
LINK
NOTE: Refer to ‘Additional Product Offerings’ for information concerning power output devices.
6
SP601
The SP601 provides a flexible, digitally controlled power
function which is intended to be used as PWM drivers of
N-Channel MOSFETs and/or IGBTs for up to 240VAC line
rectified totem-pole applications. The CMOS driveable
inputs are filtered and captured by the control logic to deter-
mine the output state. The logic includes fixed timing to pro-
hibit simultaneous conduction of the external power switches
Each application can be individually optimized by the selec-
tion of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (R ) and discharge
C
and, thru the V
sense detector, verifies the output volt-
(R ) impedance chosen per the load capacitance, frequency
OUT
age state is in agreement with the controlled inputs. The
> 11V floating power supply required to drive the upper
D
of operation, and D /D dependent recovery characteristics
I
T
of the associated FBDs. R should also be sized to prevent
DC
D
rail external power device is created and managed by the
HVIC through C and D . This capacitor is refreshed from
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (t
).
F
F
OFF MIN
the V
supply each time V
goes low. If the upper chan-
DD
nel is commanded on for a long period of time, the bootstrap
capacitor C is automatically refreshed by bringing V
OUT
The selection of over current detection resistors (R ), com-
P
patible with current sense MOSFETs/IGBTs or shunt(s) may
be used.
F
OUT
low. This is accomplished by turning off the upper rail MOS-
FET/IGBT, momentarily turning on the lower rail output
device, followed by returning control back to the upper
For the floating bootstrap supply D and C must be deter-
F
F
mined. D must support the worse case system bus voltage
F
switch. Otherwise, C would gradually deplete its charge
and handle the charging currents of C . Proper selection
F
F
allowing the upper switch to come out of saturation. The
upper and lower gate drivers allow for controlled charge and
discharge rates as well as facilitate the use of nearly lossless
current sensing power MOS devices. The over current trip
level can be boosted 30% on a pulse by pulse basis by logic
should take into consideration T
and T
per the desired
RR
operating frequency. Proper selection of C is a trade off
FR
F
between the minimum t
time of the lower rail to charge up
ON
the capacitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350µs TYP (or even sooner if the UP/DN
input switches at a faster repetition rate).
level ‘1’ applied to I
. A FAULT output signal is
TRIPSELECT
generated when any of the following occurs:
V bias is low
Over current is detected
V phase doesn’t agree with the input signal
The local filter capacitor (C ) should be sized sufficiently
DD
large enough to transfer the charge to C without causing a
F
significant droop in V . As a rule of thumb it should be at
DD
least 10 times larger than C and be located adjacent to the
F
Reset of FAULT is provided by externally removing power or
by holding the ENABLE input low for the required reset time
V
and V pins to minimize series resistance and
DD
inductance.
SS
(trt
).
MAX
Refer to Application Note AN8829 for more details about module operation and selection of external components.
7
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| SP6013A | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
| SP6013AS8RG | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
| SP6013AS8RGB | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
| SP6013AS8TG | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
| SP6013AS8TGB | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
| SP6013A_12 | SYNC-POWER | Synchronous Rectifier Driver | 获取价格 |
|
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