SP431 [INTERSIL]
Serial I/O Filter; 串行I / O过滤器
| 型号： | SP431 |
| 厂家： | 
Intersil |
| 描述： | Serial I/O Filter |
| 文件： | 总17页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP43124
Data Sheet
May 1999
File Number 3555.6
Serial I/O Filter
Features
The Serial I/O Filter is a high performance filter engine that is
ideal for off loading the burden of filter processing from a
DSP microprocessor. It supports a variety of multistage filter
configurations based on a user programmable filter and fixed
coefficient halfband filters. These configurations include a
programmable FIR filter of up to 256 taps, a cascade of from
one to five halfband filters, or a cascade of halfband filters
followed by a programmable FIR. The half band filters each
decimate by a factor of two, and the FIR filter decimates from
one to eight. When all six filters are selected, a maximum
decimation of 256 is provided.
• 45MHz Clock Rate
• 256 Tap Programmable FIR Filter
• 24-Bit Data, 32-Bit Coefficients
• Cascade of up to 5 Half Band Filters
• Decimation from 1 to 256
• Two Pin Interface for Down Conversion by F /4
S
• Multiplier for Mixing or Scaling Input with an External
Source
• Serial I/O Compatible with Most DSP Microprocessors
For digital tuning applications, a separate multiplier is
provided which allows the incoming data stream to be
multiplied, or mixed, by a user supplied mix factor. A two pin
interface is provided for serially loading the mix factor from
an external source or selecting the mix factor from an on-
board ROM. The on-board ROM contains samples of a
sinusoid capable of spectrally shifting the input data by one
Applications
• Low Cost FIR Filter
• Filter Co-Processor
• Digital Tuner
quarter of the sample rate, F /4. This allows the chip to
function as a digital down converter when the filter stages
are configured as a low-pass filter.
S
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER
HSP43124PC-45
HSP43124PC-33
HSP43124SC-45
HSP43124SC-33
HSP43124SI-40
RANGE ( C)
PACKAGE
28 Ld PDIP
The serial interface for3- input and output data is compatible
with the serial ports of common DSP microprocessors.
Coefficients and configuration data are loaded over a
bidirectional eight bit interface.
0 to 70
E28.6
0 to 70
28 Ld PDIP
28 Ld SOIC
28 Ld SOIC
28 Ld SOIC
E28.6
M28.3
M28.3
M28.3
0 to 70
0 to 70
-40 to 85
Block Diagram
DIN
DOUT
SCLK
HALF
BAND
FILTER
#1
HALF
BAND
FILTER
#2
HALF
BAND
FILTER
#5
SYNCOUT
CLKOUT
SYNCIN
MXIN
SYNCMX
CONTROL
INTERFACE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HSP43124
Pinout
28 LEAD PDIP, SOIC
TOP VIEW
SCLK
SYNCIN
GND
1
2
3
4
5
6
7
8
9
28 DIN
27 DOUT
26 SYNCOUT
25 CLKOUT
MXIN
SYNCMX
FSYNC
24
V
CC
23 C7
22 C6
21 C5
V
CC
FCLK
WR
20
C4
RD 10
A0 11
A1 12
A2 13
19 GND
18 C3
17 C2
16 C1
15 C0
V
14
CC
2
HSP43124
Pin Description
NAME
TYPE
DESCRIPTION
V
-
-
I
+5V Power Supply
Ground
CC
GND
DIN
Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input
represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con-
tained in the Data Input Section.
SYNCIN
I
Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYN-
CIN “HIGH” one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a “HIGH” state
for longer than one SCLK cycle.
SCLK
MXIN
I
I
Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are
synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX.
Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on
this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM
output as a part of the two pin F 4 down conversion interface. Details on word format and operation are contained
S/
in the Mix Factor Section.
SYNCMX
I
Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples
SYNCMX “HIGH” one SCLK before the first bit of the new mix factor. NOTE: SYNCMX should only pulse “HIGH” for
one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin F /4 down con-
S
version interface.
FCLK
I
I
Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require-
ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock
may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock.
FSYNC
Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the
data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is
currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until
the next SYNCIN cycle occurs.
WR
RD
I
I
I
Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by
the address on A0-2. The WR signal is asynchronous to all other clocks. NOTE: WR should not be low when
RD is low.
Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places
the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus.
The RD pin is asynchronous to all other clocks. NOTE: RD should not be low when WR is low.
A0-2
Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address
map for the control registers.
C0-7
I/O
O
Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM.
CLKOUT
Output Clock. Programmable bit clock for serial output. NOTE: Assertion of FSYNC initializes CLKOUT to a
high state.
SYNCOUT
DOUT
O
O
Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample
is available on DOUT.
Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter
section for additional details.)
3
HSP43124
INPUT FORMATTER
FILTER COMPUTE ENGINE
OUTPUT
FORMATTER
# BITS†
VARIABLE LENGTH
SHIFT REGISTER
(8-24-BITS)
MSB F/2†
FORMAT†
DIN
MULTIPLY/
ACCUMULATOR
57
MSB F/L†
FCLK†
CLKOUT
# BITS†
SYNCIN
SYNCIN
INPUT
HOLDING
REG
SYNCOUT
24
25
M
U
X
R
E
G
SERIAL
MULTIPLIER
REGISTER
FILE
ROUND/
SATURATE
ROUND/
SATURATE
CLKOUT
DOUT
+
+
MIX FACTOR
HOLDING
REG
48
SYNCMX
ROUND†
FORMAT†
GAIN COR†
32
MUX
MIX
SEL†
CONTROL
DECIMATION
MXIN
†
†
PARAMETERS
RATE†
SYNCMX
MUX
FILT EN†
# HBs†
WEAVER
MODULATOR
ROM
FIR SYM†
CONTROL
RD EN†
FILTER LENGTH†
RAM ACCESS†
HALFBAND
COEFFICIENT
ROM
COEFFICIENT
RAM
# BITS†
FORMAT†
VARIABLE LENGTH
SHIFT REGISTER
(8 TO 24 BITS)
MXIN
A0-2
C0-7
WR
RD
FSYNC
FCLK
†Indicates configuration control word data parameter.
SCLK
FIGURE 1. SERIAL FILTER BLOCK DIAGRAM
Data is written to the configuration control registers on the
Functional Descriptions
falling edge of the WR input. This requires that the address,
A0-2, and data, C0-7, be stable and valid on the falling edge
of the WR, as shown in Figure 2. NOTE: WR should not be
active low when RD is active low.
The HSP43124 is a high performance digital filter designed to
process a serial input data stream. A second serial interface is
provided for mix factor inputs, which are multiplied by the input
samples as shown in Figure 1. The multiplier result is passed
to the Filter Compute Engine for processing.
Data is read from the configuration control registers on the
falling edge of the RD input. The contents of a particular
register are accessed by setting up an address, A0-2, to the
falling edge of RD as shown in Figure 2. The data is output on
C0-7. The data on C0-7 remains valid until RD returns HIGH,
at which point the C0-7 bus is Three-Stated and functions as
an input. For proper operation, the address on A0-2 must be
held until RD returns “high” as shown in Figure 2. NOTE: RD
should not be active low when WR is active low.
WRITE TIMING
The Filter Compute Engine centers around a single
multiply/accumulator (MAC). The MAC performs the sum-of-
products required by a particular filter configuration. The
processing rate of the MAC is determined by the filter clock,
FCLK. Increasing FCLK relative to the input sample rate
increases the length of filter that can be realized.
The filtered results are passed to the Output Formatter where
they are rounded or truncated to a user defined bit width. The
Output Formatter then generates the timing and
synchronization signals required to serially transmit the data
to an external device.
WR
A0-2
C0-7
Filter Configuration
The HSP43124 is configured for operation by loading a set of
eight control registers. These registers are written through a
bidirectional interface which is also used for reading the
control registers. The interface consists of an 8-bit data bus,
C0-7, a 3-bit address bus, A0-2, and read/write lines, RD and
WR. The address map for the control registers is shown in
Table 1.
READ TIMING
RD
A0-2
C0-7
FIGURE 2. READ/WRITE TIMING
4
HSP43124
TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION
BIT
ADDRESS
REGISTER DESCRIPTION
POSITIONS
BIT FUNCTION
000
Filter Configuration
2-0
Specifies the number of halfbands to use. Number ranges from 0 to 5. Other
values are invalid.
3
4
Filter Enable bit. 1 = Enable. 0 = Minimum filter bypass (either the FIR or
HBF must be enabled to get an output).
Coefficient read enable. When set to 1, enables reading and disables writing
of coefficient RAM. NOTE: This bit must be set to 0 prior to writing the
Coefficient RAM.
7-5
7-0
FIR Decimation Rate. Range is 1-8 (8 = 000).
001
Programmable FIR Filter Length
Number of Taps in the Programmable FIR Filter. For even or odd symmetric
filters, values range from 4- 256, 1 to 3 are invalid, and 0000000 = 256. For
asymmetric filters, the value loaded in this register must be two times the ac-
tual number of coefficients.
010
011
Coefficient RAM Access
Input Format
7-0
4-0
Coefficient RAM is loaded by multiple writes to this address. (See Writing
Coefficients section for additional details.)
Number of bits in input data word, from 8 (01000) to 24 (11000). Values out-
side the range of 8 - 24 are invalid.
5
6
Number System. 0 = Two’s Complement, 1 = Offset Binary.
Serial Format. 1 = MSB First, 0 = LSB First.
7
Unused
100
101
Output Timing
Output Format
4-0
5
Number of FCLKS per CLKOUT. Range 1 to 32. (00000 = 32 FCLKS)
1 = MSB First, 0 = LSB First.
Unused
6-7
4-0
Number of bits in output data word, from 8 to 32. A value of 32 is represented
by 00000, and values from 1 to 7 are invalid.
5
6
Round Select. 1 = Round to Selected Number of Bits, 0 = Truncate.
Number System. 0 = Two’s Complement, 1 = Offset Binary.
Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling.
7
110
111
Filter Symmetry
1-0
00 = Even Symmetric FIR Coefficients
01 = Non-Symmetric Coefficients
10 = Odd Symmetric FIR
7-2
4-0
Reserved: Must be 0.
Mix Factor Format
Number of bits in mix factor, from 8 (01000) to 24 (11000). Values outside
the range of 8 - 24 are invalid.
5
6
7
Serial Format. 1 = MSB First, 0 = LSB First.
Mix Factor Select. 1 = Serial Input, 0 = Weaver modulator look-up-table.
Unused
The coefficient registers are loaded by first setting the
coefficient read enable bit to “0” (bit 4 of the Filter
Writing Coefficients
The HSP43124 provides a register bank to store filter
coefficients for configurations which use the programmable
filter. The register bank consists of 128 thirty-two-bit
registers. Each register is loaded by 4 one byte writes to the
bidirectional interface used for loading the configuration
registers. The coefficients are loaded in order from least
significant byte (LSB) to most significant byte (MSB).
Configuration Register). Next, coefficients are loaded by
setting the A2-0 address to 010 (binary) and writing one byte
at a time as shown in Figure 3. The down loaded bytes are
stored in a holding register until the 4th write cycle. On
completion of the fourth write cycle, the contents of the
holding register are loaded into the Coefficient RAM, and the
write pointer is incremented to the next register. If the user
attempts to write more than 128 coefficients, the pointer
5
HSP43124
halts at the 128th register location, and writing is disabled.
The coefficient address pointer is reset when any other
configuration register is written or read. NOTE: A new
coefficient set may be loaded during a filter calculation
at the risk of corrupting output data until the load is
complete.
and ending with the center tap. The coefficient associated
with the first tap is the first to be multiplied by an incoming
data sample as shown in Figure 5. For even/odd symmetric
filters of length N, N/2 coefficients must be loaded if the filter
length is even, and (N+1)/2 coefficients must be loaded if the
filter length is odd. For example, a 17 tap symmetric filter
would require the loading of 9 coefficients. Enough storage
is provided for a 256 tap symmetric filter.
WR
A0-2 = 010 (BINARY)
MSB LSB
A0-2
C0-7
X
X
X
0
2
1
-1
-1
X(n) INPUT
C0
Z
Z
LSB
MSB
C1
C2
LAST
FILTER TAP
FIRST COEFFICIENT
SECOND COEFFICIENT
FIRST
FILTER TAP
+
FIGURE 3. COEFFICIENT LOADING
Y(n) OUTPUT
Y(n) = C X + C X + C X
2 0
0
2
1
1
The number of coefficients that must be loaded is dependent
on whether the coefficient set exhibits even symmetry, odd
symmetry, or asymmetry (see Figure 4).
FIGURE 5. THREE TAP TRANSVERSAL FILTER
ARCHITECTURE
For asymmetric filters the entire coefficient set must be
loaded. The coefficients are loaded in order starting with the
first tap and ending with the final filter tap (see Figure 5 for
tap/coefficient association). Enough storage is provided for a
128 tap asymmetric filter. For asymmetric filters the value
loaded into the Programmable Filter Length Register
addressed must be twice the actual number of coefficients.
EVEN SYMMETRIC
POINT
OF
SYMMETRY
ODD LENGTH
EVEN LENGTH
Reading Coefficients
NOTE: Filters with even symmetric coefficients exhibit symme-
try about the center of the coefficient set. Most FIR filters have
coefficients which are symmetric in nature.
The coefficients are read from the storage registers one byte
at a time via C0-7 as shown in Figure 6. To read the
coefficients, the user first sets the Coefficient Read Enable
bit to 1 (bit 4 of Filter Configuration Control Register). Setting
this bit resets the RAM read pointer and disables the RAM
from being written. Next, with A2-0 = 010, multiple “high” to
“low” transitions of RD, output the coefficients on C0-7, one
byte at a time, in the order they were written. NOTE: RD
should not be “low” when WR is “low”.
ODD SYMMETRIC
CENTER OF
COEFFICIENT SET
0.5
0.25
0.1
-0.1
-0.25
-0.5
NOTE: Odd symmetric coefficients have a coefficient envelope
which has the characteristics of an odd function (i.e. coeffi-
cients which are equidistant from the center of the coefficient
set are equal in magnitude but opposite in sign). Coefficients
designed to function as a differentiator or Hilbert Transform ex-
hibit these characteristics.
RD
A0-2
C0-7
A0-2 = 010 (BINARY)
MSB LSB
MSB
SECOND COEFFICIENT
LSB
ASYMMETRIC
FIRST COEFFICIENT
FIGURE 6. COEFFICIENT READING
NOTE: Asymmetric Coefficient sets exhibit no symmetry.
FIGURE 4. COEFFICIENT CHARACTERISTICS
Data Input
Data is serially input to the HSP43124 through the DIN input.
On the rising edge of SCLK, the bit value present at DIN is
clocked into the Variable Length Shift Register. The
beginning of a serial data word is designated by asserting
SYNCIN “high” one SCLK prior to the first data bit as shown
For filters that exhibit either even or odd symmetry, only the
unique half of the coefficient set must be loaded. The
coefficients are loaded in order starting with the first filter tap
6
HSP43124
in Figure 7. On the following SCLK, the first data bit is
multiplier. The mix factor data word is programmable in
length from 8 to 24 bits and may be input MSB or LSB first
as specified in the Mix Factor Format Register. If a data word
is specified to be less than 24 bits, the least significant bits of
the Mix Factor Holding Register are zeroed.
clocked into the Variable Length Shift Register. Data bits are
clocked into the shift register until the data word, of user
programmable length (8 to 24 bits), is complete. At this point,
the shifting of data into the register is disabled and its
contents are held until SYNCIN is asserted on the rising
edge of SCLK. When this occurs, the contents of the
Variable Length Shift Register are transferred to the Input
Holding Register, and the shift register is enabled to accept
serial data on the following SCLK. The serial data word may
be two’s complement or offset binary and may be input most
significant bit (MSB) first or least significant bit (LSB) first as
defined in the Input Format Register (see Table 1). If a data
word is specified to be less than 24 bits, the least significant
bits of the Input Holding Register are zeroed.
The MXIN and SYNCMX inputs can function as two pin
interfaces to Weaver Modulator ROM addresses. Used in
proper sequence, down conversion by F /4 can be achieved.
S
These inputs are latched on the rising edge of SCLK when
SYNCIN is high as shown in Figure 9. The mapping of
SYNCIN and MXIN to ROM outputs is given in Table 2.
When SYNCIN is high on the rising edge of SCLK, the
output of the ROM is transferred to the Mix Factor holding
register, and the SYNCMX and MXIN inputs are decoded to
produce a new ROM output. As a result, there is a latency of
one SYNCIN cycle between when the SYNCMX and MXIN
inputs are decoded and when the ROM output is loaded into
the Mix Factor Holding register.
NOTE: SYNCIN should not be “high” for longer than
one SCLK cycle.
SCLK
TABLE 2. WEAVER MODULATOR ROM DECODING
SYNCIN/
SYCNMX
SYNCMX
MXIN
MIX FACTOR
0
0
1
1
0
1
0
1
0
-1
0
DIN/
MXIN
LSB
LSB
SYNC LEADS DATA
NOTE: Assumes data is being loaded LSB first.
1
FIGURE 7. SERIAL INPUT TIMING FOR EITHER DIN OR MXIN
INPUTS
Serial Multiplier
The Serial Multiplier multiplies the Mix Factor Holding
register by the contents of the Input Holding register. The
multiplication cycle is initiated when SYNCIN is sampled
high by the rising edge of SCLK. This transfers the contents
of the Variable Length Shift register to the Input Holding
Register, and loads the output of the Mix Factor Holding
Register into the Serial Multiplier. On subsequent SCLKs,
the contents of the Input Holding Register are shifted into the
Serial Multiplier for processing. When the last data bit is
shifted into the multiplier, the multiplication cycle is complete
and the result is written to the Register File on the next rising
edge of FCLK.
Mix Factor
The HSP43124 provides a second serial interface for
loading values which are multiplied by the input samples in
the serial multiplier. These values, or mix factors, are input
using the MXIN and SYNCMX pins. Aside from being used
as a serial input, this interface can also be used to select mix
factors from the Weaver Modulator ROM. The mix factor
source is specified in the Mix Factor Format Register (see
Table 1). NOTE: Data is passed unmodified through the
serial multiplier by selecting the Weaver Modulation ROM
as the mix factor source and tying both SYNCMX and
MXIN “high”.
The synchronization between a data sample and the mix
factor it is to be multiplied by is dependent on which mix
factor source is specified. For mix factors which are input
serially, the mix factor is loaded concurrently with the data
sample to be multiplied (see Figure 8).
The procedure for loading serial mix factors is similar to that
for the loading of data via the DIN input. The bit value
present on MXIN is clocked into the Variable Length Shift
register by the rising edge of SCLK. The beginning of the
serial word is designated by the assertion of SYNCMX one
SCLK prior to the first bit of the serial word as shown in
Figure 7. After the serial word has been clocked into the shift
register, the shifting of bits into the register is disabled and
its contents are held until the next assertion of SYNCMX.
When SYNCMX is asserted on the rising edge of SCLK, the
contents of the Variable Length Shift register are transferred
into the Mix Factor Holding Register. The parallel output of
the Mix Factor Holding Register feeds directly into the serial
7
HSP43124
The cascade of up to five halfband filters is an efficient
SCLK
SYNCIN
DIN
decimating filter structure. Each fixed coefficient filter in the
chain introduces a decimation of two, and the aggregate
decimation rate of the entire halfband filtering stage is given
by:
MSB
MSB
LSB
LSB
(EQ. 1)
(NUMBER OF HALFBAND FILTERS SELECTED)
DEC = 2
HB
X0
Thus, a cascade of 3 halfband filters would decimate the
input sample stream by a factor of 8.
SYNCMX
MXIN
LSB
LSB
Figure 10A is a block diagram of the halfband filter section.
The normalized frequencies for each halfband stage is
labeled. Figure 10B is an illustration of a cascaded filter
composed of five halfband filters. The final stage filter output
is clocked at FCLK/32. Since the output of each filter is at
half the rate of the input, the five halfband filter passband
characteristics can be viewed on a single plot whose X axis
is normalized to the filter output clock rate. Notice that all
halfband filters, by design, have 120dB passbands that are
less than the output rate divided by 2. Since the alias profile
is well below -120dB in the filter passband, alias concerns
are eliminated. The frequency responses of the five filters
are presented graphically in Figure 10C and in tabular form
in Table 3. Notice that the 6dB passband bandwidth (F =
0.25) is identical for all five halfband filters. The width of the
transition band, however, is different for each filter. The
transition band for the fifth halfband filter, HB5, is the
narrowest while that for the first halfband filter, HB1, is the
widest. The cascade of the halfband filters always
M0
SYNC LEADS DATA
FIGURE 8. DATA/MIX FACTOR SYNCHRONIZATION FOR
SERIALLY INPUT MIX FACTORS
NOTE: Figure 8 shows the loading of a data sample, X0, such
that it will be multiplied by a mix factor designated by M0. For
mix factor bit widths which are less than the input bit width,
SYNCMX may be asserted before SYNCIN if desired.
If the mix factor is generated by the Weaver Modulator ROM,
the mix factor must be specified on MXIN and SYNCMX one
SYNCIN before that which precedes the target data word
(see Figure 9).
SCLK
SYNCIN
terminates with HB5 and is preceded by filters in order of
increasing transition bandwidth. For example, if the
HSP43124 is configured to operate with three halfbands, the
chain of filters would consist of HB3 followed by HB4 and
terminated with HB5. If only one halfband is selected, HB5 is
used.
LSB
MSB LSB
DIN
X0
SYCNMX/
MXIN
SYNC LEADS DATA
M0
FIGURE 9. DATA/MIX FACTOR SYNCHRONIZATION WEAVER
MODULATOR MIX FACTORS
Filter Compute Engine
The Filter Compute Engine centers around a multiply
accumulator which is used to perform the sum-of-products
required for a variety of filtering configurations. These
configurations include a cascade of up to 5 halfband filters, a
single symmetric filter of up to 256 taps, a single asymmetric
filter of up to 128 taps, or a cascade of halfband filters
followed by a programmable filter. The filter configuration is
specified by programming the Filter Configuration Register
(see Table 1).
8
HSP43124
INPUT TO
HALFBAND
SECTION
STAGE 1
F
s
FCLK
4
FCLK
2
3FCLK
4
FCLK
FCLK
F
= F
s
NORMALIZED
35 TAP
HB5
STAGE 2
STAGE 3
F /2
s
FCLK
2
MUX5
= F
FCLK FCLK
0
1
8
4
F
F
= F or F /2
NORMALIZED
HB1
HB1
s
s
23 TAP
/2
HB4
F
FCLK
HB1
= F
FCLK
2
FCLK FCLK FCLK
16
MUX4
= F
0
1
8
4
F
F
or F
/2
HB1
NORMALIZED
HB2
HB2
HB1
STAGE 4
19 TAP
HB3
1
FCLK FCLK FCLK
F
FCLK
FCLK
S
F
/2
HB2
32
8
4
MUX3
= F
2
0
FCLK
16
F
NORMALIZED
HB3
F
= F
or F
/2
HB2
HB3
HB2
STAGE 5
11 TAP
HB2
FCLK
64
FCLK FCLK FCLK
F
S
F
/2
32
8
4
HB3
2
MUX2
= F
0
1
F
COM-
POSITE
FILTER
F
NORMALIZED
HB4
= F
or F
/2
HB3
HB4
HB3
7 TAP
HB1
1
FCLK
64
FCLK
F
/2
HB4
0
MUX1
FIGURE 10B. SPECTRAL COMPOSITION OF FIVE CASCADED
HALFBANDS
OUTPUT OF
HALFBAND SECTION
0
-20
6dB BANDWIDTH
MULTIPLEXERS’ DECODER TABLE AND EQUATIONS
BITS2-0 MUX1 MUX2 MUX3 MUX4 MUX5
-40
-60
-80
000
001
010
011
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
1
HB1 TRANSITION BW
-100
-120
-140
-160
HB2
HB3
HB4
HB5
100
101
0
1
1
1
1
1
1
1
1
1
-180
-200
MUX1 = (BIT2 AND BIT0) AND BIT1
MUX2 = BIT2
0.125
0.25
0.375
0.5
NORMALIZED FREQUENCY
MUX3 = (BIT1 AND BIT0) OR BIT2
MUX4 = BIT1 OR BIT2
(NORMALIZED TO OUTPUT FREQUENCY)
FIGURE 10C. COMPOSITE RESPONSE OF FIXED COEFFI-
MUX5 = BIT0 OR BIT1 OR BIT2
INVALID = BIT2 AND BIT1
CIENT HALFBAND FILTERS WITH RESPECT TO
THE NORMALIZED FREQUENCY SHOWN IN FIG-
URE 10A
FIGURE 10A. BLOCK DIAGRAM OF FIXED COEFFICIENT
HALFBAND FILTERS
9
HSP43124
The coefficient set for each of the halfband filters is given in
Table 4. These values are the 32-bit, two’s complement,
integer representation of the filter coefficients. Scaling these
values by 2-31 yields the fractional two’s complement
and DEC is the aggregate decimation rate for the
HB
cascade of halfband filters (see Table 5). For example, if the
input sample rate is 800kHz, a 128 tap FIR filter with no
decimation is selected, and a cascade of 2 halfband filters is
used, calculate the minimum FCLK rate as follows:
coefficients used to achieve unity gain in the Filter Processor.
If a specific frequency response is desired, a programmable
FIR filter may be activated. The filter compute engine takes
advantage of symmetry in FIR coefficients is by summing
data samples sharing a common coefficient prior to
multiplication. In this manner, two filter taps are calculated
per multiply accumulate cycle. If an asymmetric filter is
specified, only one tap per multiply accumulate cycle is
calculated.
800kHz 128
--------------------- ---------
+ 33 + 1
1
4
2
Min FCLK =
(EQ. 3)
(200kHz)[64 + 33 + 1] = 19.6MHz
or at least 14 (800kHz) = 11.2MHz
Thus, the Min FCLK is 19.6MHz.
NOTE: For configurations in which the halfband filters are used,
the FCLK rate must exceed 14F .
S
The processing rate of the Filter Compute Engine is
proportional to FCLK. As a result, the frequency of FCLK
must exceed a minimum value to insure that a filter
calculation is complete before the result is required for
output. In configurations which do not use decimation, one
input sample period is available for filter calculation before
an output is required. For configurations which employ
decimation, up to 256 input sample periods may be available
for filter calculation. The following equation specifies the
minimum FCLK rate required for configurations which use
the programmable filter as an FIR filter.
The longest length FIR filter realizable for a particular
configuration is determined by solving the above equation for
TAPS. The resulting expression is given below.
Max TAPS = 2DEC
FIR
((FCLK/F )DEC
HB
- HB
CLKS
- 1)
(EQ. 4)
S
The maximum throughput sample rate may be specified by
solving the above equation for F . The resulting equation is
S
Max F = FCLK*DEC /(TAPS/(2*DEC ) + HB
HB FIR CLKS
+ 1). (EQ. 5)
S
NOTE: For configurations using filters with asymmetric coeffi-
cients, the term TAPS in the above equations should be multi-
plied by two in order to determine the correct FCLK.
F
S
DEC
HB
-------------------
(TAPS/(2*DEC
) + HB
+ 1)
CLKS
FIR
Min FCLK =
(EQ. 2)
The Filter Compute Engine is synchronized with an incoming
data stream by asserting the FSYNC input. When this input
is sampled low by the rising edge of FCLK, the Compute
Engine is reset, and the data word following the next
assertion of SYNCIN is recognized as the first data sample
input to the filter structure.
or at least14F when Halfbands are used
S
In this equation F is the input sample rate (SCLK/# Bits in
S
SER word), TAPS is the number of taps in the FIR filter (0 to
256), DEC
is the decimation rate of the programmable
is a compute clock factor based on the
number of halfband filters in the configuration (see Table 5),
FIR
FIR (1 to 8), HB
CLKS
TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS
HALFBAND HALFBAND HALFBAND HALFBAND
#2 #3
NORMALIZED
FREQUENCY
HALFBAND
#5
#1
#4
0.000000
0.007812
0.015625
0.023438
0.031250
0.039062
0.046875
0.054688
0.062500
0.070312
0.078125
0.085938
0.093750
-0.000000
0.000000
-0.000113
-0.000677
-0.002243
-0.005569
-0.011596
-0.021433
-0.036333
-0.057670
-0.086916
-0.125619
-0.175382
0.000000
-0.000000
-0.000000
-0.000006
-0.000052
-0.000227
-0.000719
-0.001859
-0.004165
-0.008391
-0.015557
-0.026983
-0.044301
0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000001
-0.000009
-0.000041
-0.000149
-0.000448
-0.001175
-0.002767
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
0.000000
-0.000000
-0.000000
-0.000001
-0.000012
-0.000066
-0.000258
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
10
HSP43124
TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)
NORMALIZED
FREQUENCY
HALFBAND
#1
HALFBAND
#2
HALFBAND
#3
HALFBAND
#4
HALFBAND
#5
0.101562
0.109375
0.117188
0.125000
0.132812
0.140625
0.148438
0.156250
0.164062
0.171875
0.179688
0.187500
0.195312
0.203125
0.210938
0.218750
0.226562
0.234375
0.242188
0.250000
0.257812
0.265625
0.273438
0.281250
0.289062
0.296875
0.304688
0.312500
0.320312
0.328125
0.335938
0.343750
0.351562
0.359375
0.367188
0.375000
0.382812
0.390625
0.398438
0.406250
0.414062
0.421875
-0.237843
-0.314663
-0.407509
-0.518045
-0.647925
-0.798791
-0.972266
-1.169959
-1.393465
-1.644372
-1.924262
-2.234728
-2.577375
-2.953834
-3.365774
-3.814917
-4.303048
-4.832037
-5.403856
-6.020599
-6.684504
-7.397981
-8.163642
-8.984339
-9.863195
-10.803663
-11.809574
-12.885208
-14.035372
-15.265501
-16.581776
-17.991278
-19.502172
-21.123947
-22.867725
-24.746664
-26.776485
-28.976198
-31.369083
-33.984089
-36.857830
-40.037594
-0.069457
-0.104701
-0.152566
-0.215834
-0.297499
-0.400727
-0.528809
-0.685131
-0.873129
-1.096269
-1.358019
-1.661842
-2.011181
-2.409468
-2.860128
-3.366593
-3.932319
-4.560817
-5.255675
-6.020600
-6.859450
-7.776287
-8.775419
-9.861469
-11.039433
-12.314765
-13.693460
-15.182171
-16.788332
-18.520315
-20.387625
-22.401131
-24.573368
-26.918915
-29.454887
-32.201569
-35.183285
-38.429543
-41.976673
-45.870125
-50.167850
-54.945438
-0.005963
-0.011924
-0.022368
-0.039695
-0.067100
-0.108640
-0.169262
-0.254777
-0.371785
-0.527552
-0.729872
-0.986908
-1.307047
-1.698769
-2.170548
-2.730783
-3.387764
-4.149669
-5.024594
-6.020600
-7.145791
-8.408404
-9.816921
-11.380193
-13.107586
-15.009147
-17.095793
-19.379534
-21.873730
-24.593418
-27.555685
-30.780161
-34.289623
-38.110786
-42.275345
-46.821358
-51.795181
-57.254162
-63.270584
-69.937607
-77.378593
-85.762718
-0.000815
-0.002208
-0.005313
-0.011613
-0.023435
-0.044186
-0.078552
-0.132639
-0.214009
-0.331613
-0.495620
-0.717181
-1.008144
-1.380771
-1.847495
-2.420719
-3.112694
-3.935463
-4.900864
-6.020600
-7.306352
-8.769932
-10.423476
-12.279667
-14.352002
-16.655094
-19.205034
-22.019831
-25.119940
-28.528942
-32.274414
-36.389088
-40.912403
-45.892738
-51.390583
-57.483341
-64.272881
-71.898048
-80.556969
-90.550629
-102.379677
-117.007339
-0.000000
-0.000000
-0.000000
-0.000000
-0.000031
-0.000287
-0.001468
-0.005427
-0.016180
-0.041152
-0.092409
-0.187497
-0.349593
-0.606862
-0.991193
-1.536664
-2.278126
-3.250174
-4.486639
-6.020600
-7.884833
-10.112627
-12.738912
-15.801714
-19.344007
-23.416153
-28.079247
-33.409992
-39.508194
-46.509052
-54.604954
-64.087959
-75.444221
-89.610390
-108.973686
-152.503693
-153.443375
-158.914017
-156.960175
-153.317627
-161.115540
-153.504684
11
HSP43124
TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)
NORMALIZED
FREQUENCY
HALFBAND
#1
HALFBAND
#2
HALFBAND
#3
HALFBAND
#4
HALFBAND
#5
0.429688
0.437500
0.445312
0.453125
0.460938
0.468750
0.476562
0.484375
0.492188
-43.585945
-47.588165
-52.164894
-57.495132
-63.861992
-71.755898
-82.156616
-97.627930
-139.751450
-60.304272
-66.385063
-73.392075
-81.640152
-91.658478
-104.468010
-122.641861
-166.537369
-165.699081
-95.332924
-106.462181
-119.793030
-136.802948
-175.030167
-158.939362
-157.095886
-155.613434
-154.708450
-136.890198
-185.130432
-187.297241
-182.300125
-203.460876
-174.691895
-174.737076
-175.108841
-169.966568
-158.650345
-154.637756
-153.870453
-161.882385
-152.278915
-164.329758
-153.535690
-153.507477
-167.665482
TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED)
HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4
-67230275 12724188 624169 -197705
COEFFICIENT
C0
HALFBAND #5
23964
C1
0
604101076
1073741823
604101076
0
0
-105279784
0
0
0
0
C2
-6983862
2303514
-242570
C3
0
0
0
C4
629426509
1073741827
629426509
0
38140187
-13225905
1306852
C5
0
-145867861
0
0
0
C6
-67230275
51077176
-4942818
C7
0
0
C8
-105279784
0
650958284
1073741793
650958284
0
-161054660
14717750
C9
0
657968488
1073741825
657968488
0
0
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
12724188
-37027884
0
-145867861
0
84032070
0
38140187
0
-161054660
0
-191585682
0
-6983862
0
51077176
0
670589251
1073741824
624169
-13225905
0
670589251
0
2303514
0
-191585682
0
-197705
84032070
0
-37027884
0
14717750
0
-4942818
0
12
HSP43124
TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED) (Continued)
COEFFICIENT
HALFBAND #1
HALFBAND #2
HALFBAND #3
HALFBAND #4
HALFBAND #5
1306852
C30
C31
C32
C33
C34
0
-242570
0
23964
The duty cycle of CLKOUT is 50% for rates that have an
even number of FCLKs per CLKOUT. For rates that have and
odd number of FCLKs per CLKOUT the high portion of the
CLKOUT waveform spans (n+1)/2 FCLKs and the low
portion spans (n-1)/2 FCLKs where n is the number of
FCLKs.
TABLE 5. PERFORMANCE ENVELOPE PARAMETERS
NUMBER OF
HALFBANDS
HB
DEC
CLKS
HB
0
1
2
3
4
5
0
1
2
4
8
13
33
69
External devices synchronize to the beginning of an output
data word by monitoring SYNCOUT. This output is asserted
“high” one CLKOUT prior to the first bit of the next data word
as shown in Figure 11.
125
221
16
32
CLKOUT
Serial Output Formatter
SYNCOUT
The Output Formatter serializes the parallel output of the
filter compute engine and generates the timing and
synchronization signals required to support a serial
interface. The Formatter produces serial data words with
programmable lengths from 8 to 32 bits. The data words may
be organized with either most or least significant bit first.
Also, the data word may be rounded or truncated to the
desired length and the format of the output data may be
specified as either two's complement or offset binary. To
simplify applications where the Serial I/O Filter is used as a
down converter, the output formatter can be configured to
scale the output by a factor of 2. The above options are
programmed via the Output Format and Output Timing
Registers detailed in Table 1.
MSB LSB
MSB LSB
DOUT
SYNC LEADS DATA
NOTE: Assumes data is being output LSB first.
FIGURE 11. SERIAL OUTPUT TIMING
Input and Output Data Formats
The data formats for the input, output and coefficients are
fractional two’s complement. The bit weightings in the data
words are given in Figure 12. Input or output data words
programmed to have less than 24 bits, map to the most
significant bit positions of the 24-bit word. For example, an
input word defined to be 8 bits wide would map to the bit
positions with weightings from -20 to 2-7.
The HSP43124 outputs a bit stream through DOUT which is
synchronous to a programmable clock signal output on
CLKOUT. The output clock, CLKOUT, is derived from FCLK
1
and has a programmable rate from 1 to / times FCLK.
32
FRACTIONAL TWO’S COMPLEMENT FORMAT FOR 24-BIT INPUT AND OUTPUT
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23
-2
.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
FRACTIONAL TWO’S COMPLEMENT FORMAT FOR 32-BIT COEFFICIENTS
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31
-2
.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
NOTE: The negative sign on the MSB implies 2’s complement formt.
FIGURE 12. DATA FORMATS
13
HSP43124
The SYNCOUT jitter demonstrated by the 3/2 frequency
example can be generalized to other asynchronous
/F ratios. Setting the frequencies for FCLK and
SCLK at integer multiples of one another eliminates timing
jitter in the output sample rate.
FCLK/SCLK Uncertainty Region
Figure 13 shows a clocking relationship for the HSP43124
Serial I/O filter that could result in an uncertainty at the
output. For simplicity, the frequency of FCLK and SCLK are
assumed to be equal to each other, and CLKOUT is
assumed to be equal to FLCK. When the rising edge of
FCLK lags behind the rising edge of SCLK by a small
F
FCLK SCLK
1
2
SCLK
amount of time (T
), then the FCLK edge on which
SCFC
SYNCIN
DIN
samples are read into the filter compute engine is
determined by a race condition. In order to insure proper
MSB
LSB
1
MSB
function for the HSP43124, T
3.8ns.
must be greater than
SCFC
2
CLKOUT
If exact timing (a particular clock edge for a specific data bit)
then make SCLK and FCLK synchronous. If FCLK and
SCLK are asynchronous, there will be jitter (a specific data
bit will be output as 1 of 2 possible clock edges depending
on the FCLK to SCLK phasing). For multiple part
applications, use synchronous clocks or use separate syncs
on what receives each data, as the outputs may vary by a
clock cycle.
SYNCOUT
MSB
NULL
DOUT
LSB
MSB
FIGURE 14A. NUMBER OF CLKOUT = NUMBER OF BITS + 1
FOR THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F = 3/2
/F
FCLK SCLK
1
2
SCLK
SCLK
SYNCIN
DIN
SYNCIN
LSB
MSB
MSB
2
LSB
MSB
DIN
MSB
1
CLKOUT
FCLK
SYNCOUT
DOUT
SYNCOUT
DOUT
MSB
LSB
MSB
MSB
LSB
MSB
T
SCFC
FIGURE 14B. NUMBER OF CLKOUT = NUMBER OF BITS FOR
THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F = 3/2
/F
FCLK SCLK
FIGURE 13. FCLK/SCLK UNCERTAINTY REGION
Asynchronous FCLK and SCLK
If FCLK and SCLK are asynchronous clocks, then the output
sample rate (tracked by SYNCOUT) of the HSP43124 might
jitter in a real time system. This jitter will be demonstrated
using an SCLK with a period that is 3/2 times the period of
FCLK (i.e., F
/F = 3/2), as shown in Figure 14A
FCLK SCLK
and Figure 14B. If the LSB occurs when there are two FCLK
edges in one SCLK period (see Figure 14A), then a null data
bit will occur in the DOUT data stream. If the LSB occurs
when there is one FCLK edge in one SCLK period for the
LSB (see Figure 14B), then no null data bit will occur. Given
the 3/2 period relationship between FCLK and SCLK, the
user can see that the SYNCOUT jitters by one clock. For
example, if the output data is represent by 16 bits, then the
number of CLKOUT rising edges between SYNCOUT pulses
should jitter between 15 and 16.
14
HSP43124
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to V +0.5V
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
55
o
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
Operating Conditions
o
Voltage Range (Commercial). . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
Voltage Range (Industrial) . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
(SOIC - Lead Tips Only)
o
o
Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0 C to 70 C
o
o
Die Characteristics
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40 C to 85 C
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40,304
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
o
o
DC Electrical Specifications
PARAMETER
V
= 5.0V +5%, T = 0 to 70 C Commercial, T = -40 to 85 C Industrial
CC
A
A
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Power Supply Current
I
V
= Max, FCLK = SCLK = 45MHz
CC
-
203
mA
CCOP
Notes 2, 3
Standby Power Supply Current
Input Leakage Current
Output Leakage Current
Clock Input High
I
V
V
V
V
V
V
V
= Max, Outputs Not Loaded
-
-10
-10
3.0
-
500
10
10
-
µA
µA
µA
V
CCSB
CC
CC
CC
CC
CC
CC
CC
I
= Max, Input = 0V or V
= Max, Input = 0V or V
I
CC
I
O
CC
V
= Max, FCLK and SCLK
= Min, FCLK and SCLK
= Max
IHC
Clock Input Low
V
0.8
-
V
ILC
Logical One Input Voltage
Logical Zero Input Voltage
Logical One Output Voltage
Logical Zero Output Voltage
Input Capacitance
V
2.0
-
V
IH
V
= Min
0.8
-
V
IL
V
I
I
= -5mA, V
= Min
= Min
2.6
-
V
OH
OH
OL
CC
V
= 5mA, V
CC
0.4
10
10
V
OL
C
FCLK = SCLK = 1MHz
All Measurements Referenced to GND.
-
pF
pF
IN
Output Capacitance
C
-
o
OUT
T
= 25 C, Note 4
A
NOTES:
2. Power supply current is proportional to frequency. Typical rating is 4.5mA/MHz.
3. Output load per test circuit and C = 40pF.
L
4. Not tested, but characterized at initial design and at major process/design changes.
15
HSP43124
o
o
AC Electrical Specifications (Note 5) V = +4.75V to +5.25V, T = 0 C to 70 C (Commercial)
CC
A
o
o
V
= +4.75V to +5.25V, T = -40 C to 85 C (Industrial)
CC
A
45MHz
40MHz
33MHz
PARAMETER
FCLK, SCLK Period
SYMBOL
NOTES
MIN
22
8
MAX
MIN
MAX
MIN
MAX
UNITS
ns
t
-
-
-
-
25
10
10
8
-
-
-
-
30
12
12
9
-
-
-
-
CP
FCLK, SCLK High
FCLK, SCLK Low
t
ns
CH
t
8
ns
CL
Setup Time DIN, MXIN, SYNCIN, SYNCMX to
SCLK
t
8
ns
DS
Hold Time DIN, MXIN, SYNCIN, SYNCMX from
SCLK
t
0
-
0
-
0
-
ns
DH
Setup Time FSYNC to FCLK
Hold Time FSYNC from FCLK
Setup Time C0-7, A0-2 to Falling Edge of WR
Hold Time C0-7, A0-2 from Falling Edge of WR
Setup Time A0-2 to Falling Edge of RD
Hold Time A0-2 from Rising Edge of RD
WR High
t
8
0
-
-
8
0
-
-
8
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS
t
SH
t
10
3
-
10
3
-
10
3
-
WS
t
-
-
-
WH
t
10
0
-
10
0
-
10
0
-
RS
t
-
-
-
RH
t
10
10
10
-
-
10
10
10
-
-
12
12
10
-
-
WRH
WR Low
t
-
-
-
WRL
RD High
t
-
-
-
RDH
RDO
RD Low to Data Valid
t
25
6
12
8
3
25
6
13
9
3
25
6
14
10
3
RD High to Output Disable
FCLK to CLKOUT
t
-
-
-
OD
t
-
-
-
FOC
CLKOUT to SYNCOUT, DOUT
Output Rise, Fall Time
t
-
-
-
DO
t
Note 6
-
-
-
RF
NOTES:
5. AC tests performed with C = 40pF, I = 5mA, and I
OL OH
= -5mA. Input reference level for FCLK and SCLK is 2.0V, all other inputs 1.5V. Test
L
V
= 3.0V, V
= 4.0V, V = 0V.
IH
IHC IL
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
AC Test Load Circuit
S
DUT
1
C
(NOTE)
L
±
I
1.5V
I
OL
OH
SWITCH S1 OPEN FOR I
AND I
CCOP
CCSB
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
16
HSP43124
Waveforms
t
t
WRL
WRH
WR
t
t
WH
WS
t
t
RF
RF
C0-7,
A0-2
2.0V
0.8V
FIGURE 16. OUTPUT RISE AND FALL TIMES
FIGURE 15. TIMING RELATIVE TO WR
t
RDH
RD
t
CP
t
RS
t
CH
t
RH
t
CL
A0-2
C0-7
SCLK
t
t
DH
DS
DIN, MXIN,
SYNCIN,
SYNCMX
t
RDO
t
OD
FIGURE 17. INPUT DATA TIMING
FIGURE 18. TIMING RELATIVE TO READ
t
CP
t
FOC
t
t
CH
CL
FCLK
CLKOUT
SYNCOUT
DOUT
t
SS
t
t
DO
SH
FSYNC
FIGURE 19. TIMING RELATIVE TO FLCK AND CLKOUT
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
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17
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