RFV10N50BE [INTERSIL]
10A, 500V, Fast Switching N-Channel Enhancement-Mode Power MOSFETs; 10A ， 500V ，快速开关N沟道增强型功率MOSFET
| 型号： | RFV10N50BE |
| 厂家： | 
Intersil |
| 描述： | 10A, 500V, Fast Switching N-Channel Enhancement-Mode Power MOSFETs |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S E M I C O N D U C T O R
RFV10N50BE
10A, 500V, Fast Switching N-Channel
Enhancement-Mode Power MOSFETs
August 1995
Features
Package
• 10A, 500V
JEDEC STYLE 5 LEAD TO-247
• rDS(ON) = 0.480Ω
• Very Fast Turn-Off Characteristics
• Nanosecond Switching Speeds
• Electrostatic Discharge Protected
• UIS Rating Curve
• SOA is Power Dissipation Limited
• High Input Impedance
Description
The RFV10N50BE is an N-Channel fast switching MOSFET transis-
tor that is designed for switching regulators, inverters and motor driv-
ers. The RFV10N50BE is a monolithic structure incorporating a high
voltage, high current MOSFET, a control MOSFET and ESD protec-
tion diodes. As indicated in the symbol to the right, the turn-on of the
main MOSFET is controlled by Gate 1 (G1). The control MOSFET,
controlled by Gate 2 (G2), is distributed throughout the structure. Gate
2 provides a very low impedance and inductive path to rapidly dis-
charge the gate of the main MOSFET. Gate 2 affords very fast turn-off
(typically less than 25ns) when desired. A separate return connection,
Source Kelvin (SK), is supplied for the gate drive circuit to avoid volt-
age induced transients from the output circuit during switching. The
RFV10N50BE can be operated directly from integrated circuits.
Terminal Diagram
D
G1
G2
SK
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
BRAND
V10N50BE
S
RFV10N50BE
TO-247
NOTE: When ordering use the entire part number.
Formerly developmental type TA9881.
o
Absolute Maximum Ratings T = +25 C
C
UNITS
Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
500
+14, -0.3
+14, -0.3
2
V
V
DSS
Gate Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Control FET Gate Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
V
GS
Electrostatic Discharge Rating, MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . . . . . ESD
Drain Current
KV
RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
10
25
A
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Control FET Avalanche Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Control FET Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Refer to UIS Curve
AS
AS
AS
1.5
50
A
mJ
Power Dissipation
o
T
= +25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
156
W
C
D
o
o
Derate Above +25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.25
W/ C
Control FET Power Dissipation
o
T
= +25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
21
0.17
W
C
D
o
o
Derate Above +25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
, T
-55 to +150
C
STG
J
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
File Number 3377.1
Copyright © Harris Corporation 1995
1
Specifications RFV10N50BE
o
Electrical Specifications Case Temperature (T ) = +25 C, Unless Otherwise Specified
C
LIMITS
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 0.25mA, V = 0V
MIN
TYP
MAX
UNITS
V
Drain-Source Breakdown Voltage
Gate Threshold Voltage
I
500
-
-
DSS
D
GS
V
V
= V , I = 0.25mA
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
V
GS(TH)
GS
DS
D
o
Zero Gate Voltage Drain Current
I
V
V
= 500V,
= 0V
T
T
= +25 C
1
250
±500
0.480
75
-
µA
µA
nA
Ω
DSS
GSS
DS
GS
C
o
= +125 C
-
C
Gate-Source Leakage Current
On Resistance
I
V
= +12V, V = -0.3V
-
GS
GS
r
I
= 10A, V = 10V
-
DS(ON)
D
GS
Turn-On Time
t
V
V
R
= 250V, I = 10A, R = 25Ω,
-
ns
ON
DD
D
L
= V
= +10V, R
= 6.25Ω,
GS1
GS2
GS1
Turn-On Delay Time
Rise Time
t
20
30
21
5
ns
D(ON)
= 20Ω
GS2
t
-
ns
R
Turn-Off Delay Time
Fall Time
t
-
ns
D(OFF)
t
-
ns
F
Turn-Off Time
t
-
50
190
22
74
-
ns
OFF
Total Gate Charge
Gate Source Charge
Gate Drain (“Miller”) Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance
Thermal Resistance
Q
V
V
= 0V to 10V
V = 400V,
DD
145
17
57
3800
290
75
-
nC
nC
nC
pF
pF
pF
G10
GS
DS
I
= 10A,
D
Q
Q
GS
GD
ISS
R = 40Ω
L
C
= 25V, V = 0V, f = 1MHz
GS
C
C
-
OSS
RSS
-
o
R
R
Junction to Case
0.8
40
C/W
θJC
θJA
o
Junction to Ambient
-
C/W
Control FET Specifications
LIMITS
PARAMETER
Static Drain to Source
SYMBOL
TEST CONDITIONS
= 10V, I = 1.0A
MIN
TYP
1.6
15
-
MAX
UNITS
r
V
-
14
2
-
-
Ω
V
DS(ON)
GS
D
Drain Source Breakdown Voltage
Gate Threshold Voltage
Total Gate Charge
BV
I = 1.0mA, V = 0V
D GS
DSS
V
V
= V , I = 0.25mA
4
5
V
GS(TH)
DS
GS
D
Q
I
= 1.0A, V = 10V
-
-
nC
G10
D
GS
Source-Drain Diode Ratings and Specifications
LIMITS
PARAMETER
Continuous Source Current
Pulsed Source Current
Forward Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
10
UNITS
I
-
-
-
-
-
-
-
-
A
A
S
I
25
SM
V
I
I
= 10A, V = 0V
1.4
750
V
SD
RR
SD
GS
Reverse Recovery Time
t
= 10A, V = 0V, dI /dt = 100A/µs
ns
SD
GS
SD
2
RFV10N50BE
Typical Performance Curves
CASE TEMPERATURE (TC) = +25oC
50.0
30
100µs
STARTING TJ = +25oC
STARTING TJ = +150oC
IDM
10
1ms
IF R = 0
tAV = (L)(IAS)/
(1.3 RATED BVDSS-VDD
10.0
)
IF R ≠ 0
tAV = (L/R) In[(IAS x R)/
(1.3 RATED BVDSS-VDD)+1]
OPERATION IN THIS AREA
MAY BE LIMITED BY rDS(ON)
100ms
DC
10ms
1000
5.0
0.01
1
0.10
1.00
2.00
1
10
100
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
tAV, TIME IN AVALANCHE (ms)
FIGURE 1. SAFE OPERATING AREA CURVE
FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING
1.2
12
1.0
0.8
0.6
10
8
6
4
0.4
0.2
0
2
0
25 35 45 55 65 75 85 95 105 115 125 135 145
TC, CASE TEMPERATURE (oC)
0
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. NORMALIZED POWER DISSIPATION vs TEMPER-
TURE DERATING CURVE
VDD = 30V
PULSE DURATION = 250µs, TC = +25oC
25
25
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 6.0V
VGS = 10V
20
15
10
5
20
V
GS = 5.5V
15
10
+150oC
VGS = 5V
+25oC
-40oC
5
0
VGS = 4.5V
12.5 15.0
0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, GATE-TO-SOURCE VOLTAGE (V)
0
2.5
5.0
7.5
10.0
V
DS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS
FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
3
RFV10N50BE
Typical Performance Curves (Continued)
PULSE DURATION = 250µs, VGS = 10V, ID = 10A
VGS = VDS, ID = 250µA
3.0
2.0
1.5
1.0
2.5
2.0
1.5
1.0
0.5
0
0.5
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED r
vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
TEMPERATURE
DS(ON)
ID = 250µA
VGS = 0V, FREQUENCY (f) = 1MHz
5000
2.0
1.5
1.0
0.5
0
4000
CISS
3000
2000
COSS
1000
CRSS
0
-50
-25
0
25
50
75
100
125
150
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (oC)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN
VOLTAGE vs TEMPERATURE
FIGURE 10. TYPICAL CAPACITANCE vs VOLTAGE
10
500
10
400
300
200
8
6
4
VDD = BVDSS
1
VDD = BVDSS
0.1
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
PD
t1
10-2
10-3
t2
RL = 50Ω
IG(REF) = 3.25mA
VGS = 10V
100
0
2
0
DUTY CYCLE, D = t1/t2
TJ = PD x ZθJC + TC
10-5
10-4
10-3
10-2
IG(REF)
IG(REF)
0.1
t, RECTANGULAR PULSE WIDTH (s)
1
10
20
80
t, TIME (µs)
IG(ACT)
IG(ACT)
FIGURE 11. TYPICAL SWITCHING WAVEFORMS FOR CON-
FIGURE 12. MAXIMUM NORMALIZED TRANSIENT THERMAL
IMPEDANCE
STANT GATE CURRENT. REFER TO APPLICATION
NOTES AN7254 AND AN7260
4
RFV10N50BE
Test Circuits and Waveforms
+10V
90%
10%
RL
50%
VGS1
D
0V
+
<20ns
VGS1
VDD
G1
-
0V
+10V
VGS2
90%
50%
10%
t(ON)
VGS2
tD(ON)
G2
tR
0V
0
t(OFF)
tD(OFF)
tF
90%
RGS1
RGS2
VGS1
VGS2
10%
S
0V
SK
VDS
90%
10%
0V
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUITS
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
VDS
DUT
L
RG
+
VDD
-
BVDSS
tP
IAS
VDS
IL
VDD
0.01Ω
VGS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tAV
tP
0V
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
5
RFV10N50BE
TO-247
Packaging
E
A
TERM. 6
ØP
5 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
ØS
Q
SYMBOL
MAX
0.190
0.051
0.070
0.105
0.026
0.820
0.625
MIN
4.58
MAX
4.82
NOTES
ØR
D
A
b
0.180
0.046
0.060
0.095
0.020
0.800
0.605
-
1.17
1.29
2, 3
b
b
1.53
1.77
1, 2
1
2
2.42
2.66
1, 2
c
0.51
0.66
1, 2, 3
L1
b1
D
E
e
20.32
15.37
20.82
15.87
-
-
b2
b
L
c
0.110 TYP
0.438 BSC
0.090
2.79 TYP
11.12 BSC
4
4
5
-
e
1
1
5
4
3
2
1
1
2
3
4
5
J1
J
0.105
0.640
0.155
0.144
0.220
0.205
0.270
2.29
2.66
16.25
3.93
3.65
5.58
5.20
6.85
BACK VIEW
e
e1
L
0.620
0.145
0.138
0.210
0.195
0.260
15.75
3.69
3.51
5.34
4.96
6.61
L
1
-
1
ØP
Q
-
TERMINAL CONNECTIONS
ØR
-
Lead No. 1
Lead No. 2
- Gate 1 (G )
1
ØS
-
- Gate 2 (G )
2
NOTES:
Lead No. 3 and - Drain (D)
Mounting Flange
1. Lead dimension and finish uncontrolled in L .
1
2. Lead dimension (without solder).
Lead No. 4
Lead No. 5
- Source Kelvin (S )
K
3. Add typically 0.002 inches (0.05mm) for solder coating.
- Source (S)
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom
of dimension D.
5. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of dimension D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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6
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