KAD2710L [INTERSIL]
10-Bit, 275/210/170/105MSPS A/D Converter; 10位，二百一分之二百七十五/ 170 / 105MSPS A / D转换器
| 型号： | KAD2710L |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 275/210/170/105MSPS A/D Converter |
| 文件： | 总16页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAD2710L
®
Data Sheet
December 5, 2008
FN6818.0
10-Bit, 275/210/170/105MSPS A/D
Converter
Features
• On-Chip Reference
The KAD2710L is the industry’s lowest power, 10-bit,
275MSPS, high performance Analog-to-Digital converter. It
is designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process. The KAD2710L
offers high dynamic performance (55.6dBFS SNR @
• Internal Sample and Hold
• 1.5V
P-P
Differential Input Voltage
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
f
= 138MHz) while consuming less than 280mW. Features
IN
include an over-range indicator and a selectable divide-by-2
input clock divider. The KAD2710L is one member of a
pin-compatible family offering 8 and 10-bit ADCs with
sample rates from 105MSPS to 350MSPS and
• Selectable ÷2 Clock Input
• LVDS Compatible Outputs
LVDS-compatible or LVCMOS outputs (Table 1). This family
of products is available in 68-pin RoHS-compliant QFN
packages with exposed paddle. Performance is specified
over the full industrial temperature range (-40°c to +85°C).
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
• Medical Imaging
• Cable Head Ends
• Power-Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
CLK_P
CLK_N
CLKOUTP
CLKOUTN
Clock
Generation
• Point-to-Point Microwave Systems
• Communications Test Equipment
• Pb-Free (RoHS Compliant)
D9P – D0P
D9N – D0N
ORP
ORN
INP
10-bit
275MSPS
ADC
10
LVDS
Drivers
S/H
INN
Key Specs
• SNR = 55.6dBFS at f = 275MSPS, f = 138MHz
IN
VREF
2SC
1.21V
+
S
VREFSEL
VCM
–
• SFDR = 68.5dBc at f = 275MSPS, f = 138MHz
IN
S
• Power Consumption <280mW at f = 275MSPS
S
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
8 Bits 350MSPS
8 Bits 275MSPS
8 Bits 210MSPS
8 Bits 170MSPS
8 Bits 105MSPS
10 Bits 275MSPS
10 Bits 210MSPS
10 Bits 170MSPS
10 Bits 105MSPS
KAD2708L-35
KAD2708L-27
KAD2708L-21
KAD2708L-17
KAD2708L-10
KAD2710L-27
KAD2710L-21
KAD2710L-17
KAD2710L-10
KAD2708C-27
KAD2708C-21
KAD2708C-17
KAD2708C-10
KAD2710C-27
KAD2710C-21
KAD2710C-17
KAD2710C-10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
KAD2710L
Ordering Information
PART NUMBER
(Note)
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
L68.10x10B
KAD2710L-27Q68
KAD2710L-21Q68
KAD2710L-17Q68
KAD2710L-10Q68
275
210
170
105
-40 to +85
-40 to +85
-40 to +85
-40 to +85
68 Ld QFN
68 Ld QFN
68 Ld QFN
68 Ld QFN
L68.10x10B
L68.10x10B
L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6818.0
December 5, 2008
2
KAD2710L
Table of Contents
Absolute Maximum Ratings ......................................... 3
Thermal Information...................................................... 3
Electrical Specifications............................................... 3
Digital Specifications.................................................... 4
Timing Diagram ............................................................. 5
Timing Specifications ................................................... 5
Thermal Impedance....................................................... 5
ESD................................................................................. 5
Pin Descriptions............................................................ 6
Pinout............................................................................. 7
Typical Performance Curves........................................ 8
Functional Description ................................................. 11
Reset .......................................................................... 11
Voltage Reference...................................................... 11
Analog Input ............................................................... 11
Clock Input ................................................................. 12
Jitter............................................................................ 12
Digital Outputs............................................................ 13
Equivalent Circuits........................................................ 13
Layout Considerations ................................................. 14
Split Ground and Power Planes ................................. 14
Clock Input Considerations......................................... 14
Bypass and Filtering................................................... 14
LVDS Outputs ............................................................ 14
Unused Inputs ............................................................ 14
Definitions...................................................................... 14
Package Outline Drawing ............................................. 15
L68.10x10B ................................................................ 15
FN6818.0
December 5, 2008
3
KAD2710L
Absolute Maximum Ratings
Thermal Information
AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V
Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V
Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V
VREF to AVSS. . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
LVDS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), f
= 275MSPS, 210MSPS,
SAMPLE
A
170MSPS and 105MSPS, f = Nyquist at -0.5dBFS.
IN
KAD2710L-27
KAD2710L-21
KAD2710L-17
KAD2710L-10
PARAMETER
DC SPECIFICATIONS
Analog Input
SYMBOL
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Full-Scale Analog Input
Range
V
1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6
V
P-P
FS
Full Scale Range Temp.
Drift
A
Full Temp
230
860
210
860
198
860
178
860
ppm/°C
mV
VTC
Common-Mode Output
Voltage
V
CM
Power Requirements
1.8V Analog Supply
Voltage
AVDD2
AVDD3
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
V
3.3V Analog Supply
Voltage
1.8V Digital Supply Voltage OVDD
V
1.8V Analog Supply
Current
I
44
41
36
51
45
41
38
33
35
42
37
39
35
28
34
39
32
38
29
21
31
33
24
35
mA
AVDD2
3.3V Analog Supply
Current
I
mA
AVDD3
I
1.8V Digital Supply Current
Power Dissipation
mA
OVDD
P
278 314
240 268
217 244
178 202
mW
D
AC SPECIFICATIONS
Maximum Conversion
Rate
f
MAX
MIN
275
210
170
105
MSPS
S
Minimum Conversion Rate
Differential Nonlinearity
Integral Nonlinearity
f
50
50
50
50 MSPS
S
DNL
INL
-1.0 ±0.8 1.5 -1.0 ±0.8 1.5 -1.0 ±0.8 1.5 -1.0 ±0.8 1.5
-2.5 ±1.0 2.0 -2.5 ±1.0 1.5 -2.5 ±1.0 1.5 -2.5 ±1.0 1.5
LSB
LSB
Signal-to-Noise Ratio
SNR
f
f
f
f
f
f
= 10MHz
= Nyquist
= 430MHz
= 10MHz
= Nyquist
= 430MHz
55.7
53.5 55.6
55.2
56.4
53.5 56.2
54.8
56.6
53.5 56.5
54.6
56.6
53.5 56.5
54.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
IN
IN
IN
IN
IN
IN
Signal-to-Noise and
Distortion
SINAD
55.3
56.1
56.3
56.3
52.5 55.2
54.4
52.5 56.0
53.7
52.5 56.2
53.4
52.5 56.2
53.2
FN6818.0
December 5, 2008
4
KAD2710L
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, T = -40°C to +85°C (typical specifications at +25°C), f
= 275MSPS, 210MSPS,
SAMPLE
A
170MSPS and 105MSPS, f = Nyquist at -0.5dBFS. (Continued)
IN
KAD2710L-27
KAD2710L-21
KAD2710L-17
KAD2710L-10
PARAMETER
SYMBOL
CONDITIONS
= 10MHz
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Effective Number of Bits
ENOB
f
f
f
f
f
f
8.9
8.4 8.9
8.7
9.0
8.4 9.0
8.6
9.1
8.4 9.0
8.6
9.1
8.4 9.0
8.5
Bits
Bits
Bits
dBc
dBc
dBc
dBc
IN
IN
IN
IN
IN
IN
= Nyquist
= 430MHz
= 10MHz
Spurious-Free Dynamic
Range
SFDR
68.5
70
71
71
= Nyquist
62 68.5
63.8
62 71.1
62.6
62
71
60.1
70
62
72
60.9
71
= 430MHz
Two-Tone SFDR
2TSFDR f = 133MHz, 135MHz
IN
68
70
-12
10
-12
10
-12
10
-12
10
Word Error Rate
WER
Full Power Bandwidth
FPBW
600
600
600
600
MHz
Digital Specifications
PARAMETER
INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage High (VREFSEL)
Input Voltage Low (VREFSEL)
Input Current High (VREFSEL)
Input Current Low (VREFSEL)
Input Voltage High (CLKDIV)
Input Voltage Low (CLKDIV)
Input Current High (CLKDIV)
Input Current Low (CLKDIV)
Input Voltage High (RST,2SC)
Input Voltage Low (RST,2SC)
Input Current High (RST,2SC)
Input Current Low (RST,2SC)
Input Capacitance
V
0.8*AVDD3
V
V
IH
V
0.2*AVDD3
IL
I
V
V
= AVDD3
= AVSS
0
10
µA
µA
V
IH
IN
IN
I
-90
-65
-30
IL
V
0.8*AVDD3
IH
V
0.2*AVDD3
V
IL
I
V
V
= AVDD3
= AVSS
100
65
0
10
µA
µA
V
IH
IN
IN
I
-10
IL
V
0.8*OVDD2
IH
V
0.2*OVDD2
V
IL
I
VIN = OVDD
VIN = OVSS
0
-30
3
10
-5
µA
µA
pF
IH
I
-50
0.5
IL
C
DI
CLKP, CLKN P-P Differential Input Voltage
CLKP, CLKN Differential Input Resistance
CLKP, CLKN Common-Mode Input Voltage
LVCMOS OUTPUTS
V
R
V
3.6
V
P-P
CDI
CDI
CCI
10
MΩ
0.9
V
Differential Output Voltage
Output Offset Voltage
V
210
1.15
500
500
mV
V
T
V
OS
Output Rise Time
t
ps
ps
R
Output Fall Time
t
F
FN6818.0
December 5, 2008
5
KAD2710L
Timing Diagram
Sample N
INP
INN
tA
CLKN
CLKP
L
tPID
CLKOUTN
CLKOUTP
tPCD
tPH
D[9:0]P
D[9:0]N
Data N-L
invalid
Data N-L+1
Data N
FIGURE 1. LVDS TIMING DIAGRAM
Timing Specifications
PARAMETER
SYMBOL
MIN
TYP
1.7
MAX
UNITS
ns
Aperture Delay
t
A
RMS Aperture Jitter
j
200
5.0
fs
A
Input Clock to Data Propagation Delay
Data Hold Time
t
3.5
6.5
3.7
ns
PID
t
-300
ps
PH
Output Clock to Data Propagation Delay
Latency (Pipeline Delay)
Overvoltage Recovery
t
2.8
28
1
ns
PCD
L
cycles
cycle
t
OVR
Thermal Impedance
PARAMETER
Junction to Paddle (Note 1)
NOTE:
SYMBOL
TYP
UNIT
θ
30
°C/W
JP
1. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable
care must be taken in the storage and handling of ESD
sensitive products. Contact Intersil for the specific ESD
sensitivity rating of this product.
FN6818.0
December 5, 2008
6
KAD2710L
Pin Descriptions
PIN NUMBER
NAME
AVDD2
FUNCTION
1, 14, 18, 20
1.8V Analog Supply
2, 7, 10, 19, 21, 24
AVSS
Analog Supply Return
3
VREF
Reference Voltage Out/In
4
5
VREFSEL
VCM
Reference Voltage Select (0:Int 1:Ext)
Common-Mode Voltage Output
3.3V Analog Supply
6, 15, 16, 25
8, 9
AVDD3
INP, INN
DNC
Analog Input Positive, Negative
Do Not Connect
11-13, 29-32, 62, 63, 67
17
CLKDIV
CLKN, CLKP
OVSS
Clock Divide by Two (Active Low)
Clock Input Complement, True
Output Supply Return
22, 23
26, 45, 61
27, 41, 44, 60
28
OVDD2
RST
1.8V LVDS Supply
Power On Reset (Active Low)
LVDS Bit 0 (LSB) Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 3 Output Complement, True
33, 34
D0N, D0P
D1N, D1P
D2N, D2P
D3N, D3P
35, 36
37, 38
39, 40
42, 43
CLKOUTN, CLKOUTP LVDS Clock Output Complement, True
46, 47
D4N, D4P
D5N, D5P
D6N, D6P
D7N, D7P
D8N, D8P
D9N, D9P
ORN, ORP
LVDS Bit 4 Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bit 7 Output Complement, True
LVDS Bit 8 Output Complement, True
LVDS Bit 9 (MSB) Output Complement, True
Over-Range Complement, True
Connect to OVDD2
48, 49
50, 51
52, 53
54, 55
56, 57
58, 59
64-66
68
2SC
Two’s Complement Select (Active Low)
Analog Supply Return
Exposed Paddle
AVSS
FN6818.0
December 5, 2008
7
KAD2710L
Pinout
KAD2710C
(68 LD QFN)
TOP VIEW
AVDD2
AVSS
VREF
1
2
3
4
5
6
7
8
9
51 D6P
50 D6N
49 D5P
VREFSEL
VCM
AVDD3
AVSS
INP
48 D5N
47 D4P
46 D4N
45 OVSS
44 OVDD2
43 CLKOUTP
42 CLKOUTN
41 OVDD2
40 D3P
INN
AVSS 10
DNC 11
DNC 12
DNC 13
39 D3N
Top View
Not to Scale
AVDD2 14
AVDD3 15
AVDD3 16
CLKDIV 17
38 D2P
37 D2N
36 D1P
35 D1N
FIGURE 2. PIN CONFIGURATION
FN6818.0
December 5, 2008
8
KAD2710L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 275MSPS, f = 137MHz,
SAMPLE IN
A
A
= -0.5dBFS unless noted.
IN
80
75
70
65
60
55
50
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
SFDR
HD3
HD2
SNR
0
50 100 150 200 250 300 350 400 450 500 550
IN (MHz)
0
50 100 150 200 250 300 350 400 450 500 550
IN (MHz)
FIGURE 4. HD2 AND HD3 vs f
f
f
FIGURE 3. SNR AND SFDR vs f
IN
IN
75
70
65
60
55
50
45
40
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
HD3
HD2
SNR
SFDR
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
AIN (dBFS)
AIN (dBFS)
FIGURE 5. SNR AND SFDR vs A
FIGURE 6. HD2 AND HD3 vs A
IN
IN
80
75
70
65
60
55
50
-70
-75
SFDR
HD3
HD2
-80
-85
-90
SNR
-95
-100
50
100
150
200
250
300
50
100
150
200
250
300
fSAMPLE (fS) (MSPS)
fSAMPLE (fS) (MSPS)
FIGURE 7. SNR AND SFDR vs f
FIGURE 8. HD2 AND HD3 vs f
SAMPLE
SAMPLE
FN6818.0
December 5, 2008
9
KAD2710L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 275MSPS, f = 137MHz,
SAMPLE IN
A
A
= -0.5dBFS unless noted. (Continued)
IN
300
280
260
240
220
200
180
160
140
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
50
100
150
200
250
300
0
128
256
384
512
CODE
640
768
896 1023
fSAMPLE (fS) (MSPS)
FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE
FIGURE 9. POWER DISSIPATION vs f
SAMPLE
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
640
768
896
1023
CODE
FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE
FIGURE 12. NOISE HISTOGRAM
0
0
Ain = -0.49dBFS
Ain= -0.49dBFS
SNR = 56.5dBFS
-20
SNR = 56.5dBFS
SFDR = 70.0dBc
SINAD = 55.7dBc
HD2 = -94.3dBc
HD3 = -70.5dBc
-20
-40
SFDR = 71.0dBc
-40
-60
SINAD = 55.7dBc
HD2 = -84.8dBc
HD3 = -71.0dBc
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 13. OUTPUT SPECTRUM; f = 10MHz
IN
FIGURE 14. OUTPUT SPECTRUM; f = 134MHz
IN
FN6818.0
December 5, 2008
10
KAD2710L
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T = +25°C, f
= 275MSPS, f = 137MHz,
IN
A
SAMPLE
A
= -0.5dBFS unless noted. (Continued)
IN
0
-20
0
Ain = -0.50dBFS
SNR = 56.0dBFS
SFD R = 63.6dBc
SINAD = 55.1dBc
HD2 = -67.8dBc
HD3 = - 63.6dBc
Ain = -7dBFS
-20
-40
2TSFDR = 71dBc
IMD3 = -78dBFS
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. OUTPUT SPECTRUM; f = 300MHz
IN
FIGURE 16. TWO-TONE SPECTRUM; f = 69MHz, 70MHz
IN
0
-20
0
Ain = -7dBFS
Ain= -7dBFS
-20
2TSFDR = 74.7dBc
IMD3 = -84.5dBFS
2TSFDR = 63dBc
IMD3 =-75dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM; f = 140MHz, 141MHz
IN
FIGURE 18. TWO-TONE SPECTRUM; f = 300MHz, 305MHz
IN
75
800
700
600
500
400
300
200
70
65
60
55
50
SFDR
SNR
-40
-20
0
20
40
60
80
100
125
150
175
200
225
250
275
f
SAMPLE (fS) (MSPS)
Ambient Temperature deg.C
FIGURE 19. SNR vs TEMPERATURE
FIGURE 20. CALIBRATION TIME vs f
S
FN6818.0
December 5, 2008
11
KAD2710L
Voltage Reference
Functional Description
The VREF pin is the reference voltage which sets the
full-scale input voltage for the chip. This pin requires a
bypass capacitor of 0.1µF at a minimum. The internally
generated bandgap reference voltage is provided by an on-
chip voltage buffer. This buffer can sink or source up to 50µA
externally.
The KAD2710 is a ten bit, 275MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample and hold circuit and converted to a unit of charge.
Proprietary charge-domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage, or to match the full-scale reference for
multiple KAD2710L chips.One option in the latter
configuration is to use one KAD2710L's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
At power-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is held low internally at
power-up and will remain in that state until the calibration is
complete. The clock frequency should remain fixed during
this time.
To select whether the full-scale reference is internally
generated or externally provided, the digital input VREFSEL
is set low for internal, or high for external.This pin has
internal pull-up.use the internally generated reference
VREFSEL can be tied directly to AVSS, and to use an
external reference VREFSEL can be left unconnected.
Calibration accuracy is maintained for the sample rate at
which it is performed, and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Analog Input
Reset
The ADC core contains a fully differential input (INP/INN) to
the sample and hold circuit. The ideal full-scale input voltage
is 1.50V, centered at the VCM voltage of 0.86V as shown in
Figure 22.
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (ORP) is
set high once RST is pulled low, and remains in that state
until calibration is complete. The ORP output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an over-
range state the ORP pin will stay high and it will not be
possible to detect the end of the calibration cycle.
V
1.8
INN
INP
1.4
0.75V
VCM
1.0
0.86V
0.6
-0.75V
0.2
While RST is low, the output clock (CLKOUTP/CLKOUTN)
stops toggling and is set low. Normal operation of the output
clock resumes at the next input clock edge (CLKP/CLKN)
after RST is deasserted. At 275MSPS the nominal
calibration time is ~240ms.
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 23 and 24. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 23 and 24.
CLKN
CLKP
Calibration Time
RST
Calibration Begins
ORP
Calibration Complete
CLKOUTP
FIGURE 21. CALIBRATION TIMING
FN6818.0
December 5, 2008
12
KAD2710L
The recommended drive circuit is shown in Figure 26. The
clock can be driven single-ended, but this will reduce the
edge rate and may impact SNR performance.
0.01µF
Analog
In
KAD2710L
VCM
50Ω
1kΩ
1kΩ
ADT1-1WT
AVDD2
ADT1-1WT
0.1µF
CLKP
CLKN
1nF
1nF
Clock
Input
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
200Ω
TC4-1W
FIGURE 26. RECOMMENDED CLOCK DRIVE
25Ω
ADTL1-12
ADTL1-12
1000pF
1000pF
Analog
Input
KAD2710L
VCM
25Ω
Use of the clock divider is optional. The KAD2710L's ADC
requires a clock with 50% duty cycle for optimum
0.1µF
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate and use the
KAD2710L's divide-by-2 setting. This frequency divider uses
the rising edge of the clock, so 50% clock duty cycle is
assured. Table 2 describes the CLKDIV connection.
FIGURE 24. TRANSFORMER INPUT FOR HIGH IF
APPLICATIONS
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to V . The value of the shunt
CM
TABLE 2. CLKDIV PIN SETTINGS
resistor should be determined based on the desired load
impedance.
CLKDIV PIN
AVSS
DIVIDE RATIO
2
1
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
AVDD
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
recommended for optimal performance.
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
A differential amplifier can be used in applications that
require dc coupling. In this configuration the amplifier will
typically determine the achievable SNR and distortion. A
typical differential amplifier circuit is shown in Figure 25.
between clock jitter (t ) and SNR is shown in Equation 1 and
J
is illustrated in Figure 27.
1
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
IN J
348OΩ
Where t is the RMS uncertainty in the sampling instant.
J
69.8OΩ
25OΩ
100OΩ
10 0
95
Analog
Input
0.22µF
217ΩO
KAD2710
VCM
tj=0.1p s
CM
90
14 Bits
100OΩ
69.8OΩ
85
80
75
70
25OΩ
49.9OΩ
tj = 1 ps
12 Bits
10 Bits
0.1µF
348OΩ
tj = 1 0p s
65
60
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
tj=100p s
55
50
Clock Input
The sample clock input circuit is a differential pair (see
Figure 29). Driving these inputs with a high level (up to
1
10
100
1000
Input Frequency - MHz
1.8V on each input) sine or square wave will provide the
lowest jitter performance.
PP
FIGURE 27. SNR vs CLOCK JITTER
FN6818.0
December 5, 2008
13
KAD2710L
This relationship shows the SNR that would be achieved if
Digital Outputs
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1.
Data is output on a parallel bus with LVDS-compatible
drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS
Any internal aperture jitter combines with the input clock jitter
in a root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
2SC PIN
AVSS
MODE
Two’s Complement
Binary
AVDD (or unconnected)
Equivalent Circuits
AVDD2
AVDD3
To
INP
INN
Charge
Pipeline
AVDD2
2pF
2pF
To Clock
Generation
Csamp
0.3pF
Φ
2
Φ
1
CLKP
AVDD3
To
Charge
Pipeline
AVDD2
Csamp
0.3pF
Φ
2
Φ
F 1
CLKN
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
OVDD
OVDD
DATA
DATA
D[9:0]P,
ORP
OVDD
D[9:0]N,
ORN
DATA
DATA
FIGURE 30. LVDS OUTPUTS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6818.0
December 5, 2008
14
KAD2710L
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. If analog and digital
ground planes are separate, analog supply and ground
planes should be laid out under signal and clock inputs and
digital planes under outputs and logic pins. Grounds should
be joined under the chip.
Gain Error is the ratio of the difference between the voltages
that cause the lowest and highest code transitions to the
full-scale voltage (less 2 LSB). It is typically expressed in
percent.
Integral Non-Linearity (INL) is the deviation of each
individual code from a line drawn from negative full-scale
(1/2 LSB below the first code transition) through positive full-
scale (1/2 LSB above the last code transition). The deviation
of any given code from this line is measured from the center
of that code.
Clock Input Considerations
Use matched transmission lines to the inputs for the analog
input and clock signals. Locate transformers, drivers and
terminations as close to the chip as possible.
Bypass and Filtering
Least Significant Bit (LSB) is the bit that has the smallest
Bulk capacitors should have low equivalent series
resistance. Tantalum is recommended. Keep ceramic
bypass capacitors very close to device pins. Longer traces
will increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct, and low impedance.
value or weight in a digital word. Its value in terms of input
N
voltage is V /(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep trace
lengths equal, and minimize bends where possible. Avoid
crossing ground and power-plane breaks with signal traces.
Pipeline Delay, or latency, is the number of clock cycles
between the initiation of a conversion and the appearance at
the output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in input voltage necessary to correct a change in
output code that results from a change in power supply
voltage.
Unused Inputs
The RST and 2SC inputs are internally pulled up, and can be
left open-circuit if not used.
CLKDIV is internally pulled low, which divides the input clock
by two.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
VREFSEL is internally pulled up. It must be held low for
internal reference, but can be left open for external
reference.
Signal-to-Noise Ratio (SNR) (without Harmonics) is the
ratio of the RMS signal amplitude to the RMS sum of all
other spectral components below one-half the sampling
frequency, excluding harmonics and DC.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
SNR and SINAD are either given in units of dBc when the
power level of the fundamental is used as the reference, or
dBFS (dB to full scale) when the converter’s full-scale input
power is used as the reference.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the peak spurious
spectral component. The peak spurious spectral component
may or may not be a harmonic.
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Two-Tone SFDR is the ratio of the RMS value of the lowest
power input tone to the RMS value of the peak spurious
component, which may or may not be an IMD product.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
FN6818.0
December 5, 2008
15
KAD2710L
Package Outline Drawing
L68.10x10B
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/08
PIN 1
INDEX AREA
10.00
A
4X 8.00
PIN 1
6
INDEX AREA
B
52
68
6
1
51
64X 0.50
Exp. DAP
7.70 Sq.
10.00
17
35
(4X)
0.15
34
18
68X 0.55
BOTTOM VIEW
68X 0.25
4
0.10 M C A B
TOP VIEW
SEE DETAIL "X"
C
0.10
0.08 C
SEATING PLANE
0.90 Max
8.00 Sq
C
64X 0.50
68X 0.25
SIDE VIEW
9.65 Sq
5
0 . 2 REF
C
7.70 Sq
0 . 00 MIN.
0 . 05 MAX.
68X 0.75
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6818.0
December 5, 2008
16
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