ISLA222P13IRZ [INTERSIL]
Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC; 双通道12位， 250MSPS / 200MSPS / 130MSPS ADC
| 型号： | ISLA222P13IRZ |
| 厂家： | 
Intersil |
| 描述： | Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC |
| 文件： | 总33页 (文件大小：938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA222P
Features
The ISLA222P is a family of dual-channel 12-bit
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA222P is part of a pin-compatible portfolio
of 12-bit and 14-bit dual-channel A/Ds with maximum sample
rates ranging from 130MSPS to 250MSPS.
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA222P is available in a 72 lead QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Key Specifications
• SNR @ 250/200/130MSPS
Applications
• Radar Array Processing
70.3/71.0/71.3dBFS f = 30MHz
IN
68.5/68.8/68.4dBFS f = 363MHz
IN
• Software Defined Radios
• SFDR @ 250/200/130MSPS
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
85/87/86dBc f = 30MHz
IN
73/75/80dBc f = 363MHz
IN
• Total Power Consumption = 823mW @ 250MSPS
Pin-Compatible Family
SPEED
(MSPS)
MODEL
RESOLUTION
ISLA224P25
ISLA224P20
ISLA224P13
ISLA222P25
ISLA222P20
ISLA222P13
14
14
14
12
12
12
250
200
130
250
200
130
CLKP
CLKOUTP
CLKOUTN
CLOCK
MANAGEMENT
CLKN
12-BIT
250 MSPS
ADC
VINBP
VINBN
D[11:0]P
D[11:0]N
SHA
SHA
ORP
ORN
VREF
DIGITAL
ERROR
CORRECTION
VCM
OUTFMT
OUTMODE
VINAN
VINAP
12-BIT
250 MSPS
ADC
VREF
1.25V
SPI
CONTROL
+
-
–
June 17, 2011
FN7853.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISLA222P
Pin Configuration - LVDS Mode
ISLA222P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
DNC
DNC
1
2
54 D1P
D1N
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
D2P
4
D2N
5
AVSS
D3P
6
VINBP
VINBN
AVSS
D3N
7
CLKOUTP
CLKOUTN
RLVDS
OVSS
D4P
8
9
AVDD
AVDD
AVSS
10
11
12
13
14
VINAN
VINAP
AVSS
D4N
D5P
D5N
15
16
17
40
39
38
CLKDIV
IPTAT
DNC
D6P
D6N
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions
D7P
Connect Thermal Pad to AVSS
RESETN 18
37 D7N
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 17, 57, 58, 59, 60
DNC
Do Not Connect
1.8V Analog Supply
Analog Ground
9, 10, 19, 20, 21, 70, 71, 72
AVDD
5, 8, 11, 14
AVSS
27, 32, 62
OVDD
1.8V Output Supply
Output Ground
26, 45, 61, 65
OVSS
3
4
NAPSLP
VCM
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
6, 7
12, 13
VINBP, VINBN
VINAN, VINAP
Channel B Analog Input Positive, Negative
Channel A Analog Input Negative, Positive
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ISLA222P
Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
15
CLKDIV
Tri-Level Clock Divider Control
16
IPTAT
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
18
RESETN
22, 23
24, 25
28, 29
30, 31
33, 34
35, 36
37, 38
39, 40
41, 42
43, 44
46
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11N, D11P
D10N, D10P
D9N, D9P
D8N, D8P
D7N, D7P
D6N, D6P
D5N, D5P
D4N, D4P
RLVDS
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bit 11 (MSB) Output Complement, True
LVDS Bit 10 Output Complement, True
LVDS Bit 9 Output Complement, True
LVDS Bit 8 Output Complement, True
LVDS Bit 7 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 4 Output Complement, True
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
LVDS Clock Output Complement, True
LVDS Bit 3 Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Bit 0 (LSB) Output Complement, True
LVDS Over Range Complement, True
SPI Serial Data Output
47, 48
49, 50
51, 52
53, 54
55, 56
63, 64
66
CLKOUTN, CLKOUTP
D3N, D3P
D2N, D2P
D1N, D1P
D0N, D0P
ORN, ORP
SDO
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7853.1
June 17, 2011
3
ISLA222P
Pin Configuration - CMOS Mode
ISLA222P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
DNC
DNC
1
2
54 D1
DNC
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
D2
4
DNC
D3
5
AVSS
6
VINBP
VINBN
AVSS
DNC
CLKOUT
DNC
RLVDS
OVSS
D4
7
8
9
AVDD
AVDD
AVSS
10
11
12
13
14
VINAN
VINAP
AVSS
DNC
D5
DNC
D6
15
16
17
40
CLKDIV
IPTAT
DNC
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions
39 DNC
38
Connect Thermal Pad to AVSS
D7
37 DNC
RESETN 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
1, 2, 17, 28, 30, 33, 35, 37, 39,
41, 43, 47, 49, 51, 53, 55, 57,
58, 59, 60, 63
DNC
Do Not Connect
9, 10, 19, 20, 21, 70, 71, 72
AVDD
AVSS
1.8V Analog Supply
Analog Ground
5, 8, 11, 14
27, 32, 62
OVDD
OVSS
1.8V Output Supply
Output Ground
26, 45, 61, 65
3
4
NAPSLP
VCM
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
FN7853.1
June 17, 2011
4
ISLA222P
Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
6, 7
VINBP, VINBN
Channel B Analog Input Positive, Negative
12, 13
VINAN, VINAP
Channel A Analog Input Negative, Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
CMOS Bit 11 (MSB) Output
CMOS Bit 10 Output
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
29
D11
D10
D9
31
34
CMOS Bit 9 Output
36
D8
CMOS Bit 8 Output
38
D7
CMOS Bit 7 Output
40
D6
CMOS Bit 6 Output
42
D5
CMOS Bit 5 Output
44
D4
CMOS Bit 4 Output
46
RLVDS
CLKOUT
D3
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
CMOS Clock Output
48
50
CMOS Bit 3 Output
52
D2
CMOS Bit 2 Output
54
D1
CMOS Bit 1 Output
56
D0
CMOS Bit 0 (LSB) Output
CMOS Over Range
64
OR
66
SDO
CSB
SCLK
SDIO
AVSS
SPI Serial Data Output
67
SPI Chip Select (active low)
SPI Clock
68
69
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
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June 17, 2011
5
ISLA222P
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
PACKAGE
(Pb-free)
PKG.
DWG. #
(°C)
ISLA222P13IRZ
ISLA222P20IRZ
ISLA222P25IRZ
ISLA224IR72EV1Z
NOTES:
ISLA222P13 IRZ
ISLA222P20 IRZ
ISLA222P25 IRZ
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
72 Ld QFN
L72.10x10E
72 Ld QFN
72 Ld QFN
L72.10x10E
L72.10x10E
14 Bit ADC Evaluation Board - This board can be configured for 12-bit testing
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222P. For more information on MSL please see techbrief TB363.
FN7853.1
June 17, 2011
6
ISLA222P
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User Initiated Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Divider Synchronous Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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ISLA222P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latch Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
23
θ
(°C/W)
0.9
JA
JC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply over
A
IN
SAMPLE
the operating temperature range, -40°C to +85°C.
ISLA222P25
MIN MAX
ISLA222P20
MIN MAX
ISLA222P13
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
V
Differential
1.95
2.0
2.2
1.95
2.0
2.2
1.95
2.0
2.2
V
P-P
FS
Input Resistance
Input Capacitance
R
C
Differential
Differential
Full Temp
600
4.5
600
4.5
82
600
4.5
75
Ω
IN
pF
IN
Full-Scale Range Temp.
Drift
A
108
ppm/°C
VTC
Input Offset Voltage
V
-7.0
-1.7
7.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
V
OS
Common-Mode Output
Voltage
V
0.94
0.94
0.94
CM
Common-Mode Input
Current (per pin)
I
2.6
2.6
2.6
µA/MSPS
CM
Clock Inputs
Inputs Common Mode
Voltage
0.9
1.8
0.9
1.8
0.9
1.8
V
V
CLKP, CLKN Input Swing
Power Requirements
1.8V Analog Supply
Voltage
AVDD
OVDD
1.7
1.7
1.8
1.8
374
83
1.9
1.9
389
90
1.7
1.7
1.8
1.8
344
78
1.9
1.9
376
85
1.7
1.7
1.8
1.8
293
68
1.9
1.9
312
75
V
1.8V Digital Supply
Voltage
V
1.8V Analog Supply
Current
I
mA
mA
dB
AVDD
1.8V Digital Supply
Current (Note 6)
I
3mA LVDS
OVDD
Power Supply Rejection
Ratio
PSRR
30MHz, 50mV signal
P-P
on AVDD
-65
-65
-65
FN7853.1
June 17, 2011
8
ISLA222P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply over
A
IN
SAMPLE
the operating temperature range, -40°C to +85°C. (Continued)
ISLA222P25
MIN MAX
ISLA222P20
MIN MAX
ISLA222P13
MIN MAX
PARAMETER
Total Power Dissipation
Normal Mode
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
P
2mA LVDS
774
823
765
87
709
760
691
83
614
650
578
77
mW
mW
mW
mW
mW
µs
D
3mA LVDS
CMOS
862
830
697
Nap Mode
P
P
96
11
93
11
85
10
D
Sleep Mode
CSB at logic high
6
6
6
D
Nap/Sleep Mode
Wakeup Time
Sample Clock Running
200
400
630
AC SPECIFICATIONS
Differential Nonlinearity
DNL
INL
f
= 105MHz
-0.9 ±0.16
0.9
-0.5 ±0.12
0.5
-0.5 ±0.12
0.5
LSB
IN
No Missing Codes
Integral Nonlinearity
f
= 105MHz
-2.0
250
69.1
±0.8
2.0
40
-1.5
200
70.0
±0.6
1.5
40
-1.5
130
70.5
±0.6
1.5
40
LSB
IN
Minimum Conversion
Rate (Note 7)
f
MIN
MSPS
S
Maximum Conversion
Rate
f
MAX
MSPS
S
Signal-to-Noise Ratio
(Note 8)
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
70.3
70.2
69.7
68.5
67.8
66.6
70.0
69.3
68.5
66.7
65.6
63.2
11.34
71.0
70.8
70.2
68.8
67.7
66.5
70.8
70.3
69.4
67.8
65.8
61.6
11.47
71.3
71.1
70.3
68.4
67.3
65.7
71.1
70.3
69.3
68.0
65.5
60.0
11.52
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
Signal-to-Noise and
Distortion
(Note 8)
SINAD
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
67.7
68.6
68.7
Effective Number of Bits
(Note 8)
ENOB
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
10.95 11.22
11.09
11.10 11.39
11.24
11.12 11.39
11.22
Bits
Bits
10.79
10.97
11.00
Bits
10.60
10.64
10.59
Bits
10.21
9.94
9.67
Bits
FN7853.1
June 17, 2011
9
ISLA222P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -1dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply over
A
IN
SAMPLE
the operating temperature range, -40°C to +85°C. (Continued)
ISLA222P25
MIN MAX
ISLA222P20
MIN MAX
ISLA222P13
MIN MAX
PARAMETER
SYMBOL
SFDR
CONDITIONS
= 30MHz
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
Spurious-Free Dynamic
Range
(Note 8)
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
85
78
76
87
80
77
75
71
86
78
76
80
71
62
99
96
92
88
87
83
86
100
90
90
dBc
dBc
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
71
72
71
dBc
73
69
67
88
92
88
87
88
87
87
96
105
100
dBc
dBc
64
96
94
91
85
83
81
87
102
100
93
dBc
Spurious-Free Dynamic SFDRX23
Range Excluding H2, H3
(Note 8)
dBc
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 70MHz
dBc
dBc
dBc
dBc
dBc
Intermodulation
Distortion
IMD
dBFS
dBFS
dBFS
dBFS
= 170MHz
= 10MHz
Channel-to-Channel
Isolation
= 121MHz
-12
-12
-12
Word Error Rate
Full Power Bandwidth
NOTES:
WER
10
700
10
700
10
700
FPBW
MHz
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
specifications apply for 10pF load on each digital output.
OVDD
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5) UNITS
INPUTS
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (SDIO)
Input Current Low (SDIO)
I
V
V
V
V
= 1.8V
= 0V
0
1
-12
4
10
-7
µA
µA
µA
µA
V
IH
IN
IN
IN
IN
I
-25
IL
I
= 1.8V
= 0V
12
IH
I
-600
1.17
-415
-300
IL
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
Input Current High (CLKDIV) (Note 9)
Input Current Low (CLKDIV)
V
IH
V
0.63
34
V
IL
I
16
25
-25
3
µA
µA
pF
IH
I
-34
-16
IL
Input Capacitance
C
DI
FN7853.1
June 17, 2011
10
ISLA222P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak-to-peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5) UNITS
V
825
250
1575
450
mV
mV
kΩ
kΩ
ICM
V
ID
R
R
100
100
Ipd
Ipu
Differential Output Voltage (Note 10)
Output Offset Voltage
V
3mA Mode
3mA Mode
612
1150
240
mV
P-P
T
V
1120
1200
mV
ps
OS
Output Rise Time
t
R
Output Fall Time
t
240
ps
F
CMOS OUTPUTS
Voltage Output High
V
I
I
= -500µA
= 1mA
OVDD - 0.3 OVDD - 0.1
V
V
OH
OH
Voltage Output Low
V
0.1
1.8
1.4
0.3
OL
OL
Output Rise Time
t
ns
ns
R
Output Fall Time
t
F
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[11:0]N
A DATA
N-L
B DATA A DATA
N-L
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA B DATA
N
N
D[11:0]P
FIGURE 1. LVDS
FN7853.1
June 17, 2011
11
ISLA222P
Timing Diagrams(Continued)
INP
INN
t
A
CLKN
CLKP
LATENCY = L CYCLES
t
CPD
CLKOUT
D[11:0]
t
DC
t
PD
A DATA
N-L
B DATA
N-L
A DATA
N
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
B DATA
N
FIGURE 2. CMOS
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 5)
MAX
(Note 5)
PARAMETER
SYMBOL
CONDITION
TYP
UNITS
ADC OUTPUT
Aperture Delay
t
114
75
ps
fs
A
RMS Aperture Jitter
j
A
Input Clock to Output Clock Propagation
Delay
t
t
AVDD, OVDD = 1.7V to 1.9V,
1.65
2.4
3
ns
CPD
T
= -40°C to +85°C
A
AVDD, OVDD = 1.8V, T = +25°C
A
1.9
2.3
2.75
450
ns
ps
CPD
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
dt
AVDD, OVDD = 1.7V to 1.9V,
-450
CPD
T
= -40°C to +85°C
A
Input Clock to Data Propagation Delay
t
t
1.65
-0.1
2.4
3.5
0.5
ns
ns
PD
Output Clock to Data Propagation Delay,
LVDS Mode
Rising/Falling Edge
Rising/Falling Edge
0.16
DC
Output Clock to Data Propagation Delay,
CMOS Mode
t
-0.1
0.4
0.2
0.65
ns
ns
DC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
t
0.06
RSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
t
0.02
52
0.35
ns
µs
RSTH
Synchronous Clock Divider Reset Recovery
Time
t
DLL recovery time after
Synchronous Reset
RSTRT
L
Latency (Pipeline Delay)
Overvoltage Recovery
10
1
cycles
cycles
t
OVR
FN7853.1
June 17, 2011
12
ISLA222P
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SPI INTERFACE (Notes 11, 12)
SCLK Period
SYMBOL
CONDITION
(Note 5)
TYP
(Note 5)
UNITS
t
t
Write Operation
7
16
28
5
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
CLK
Read Operation
Read or Write
Write
CLK
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
CSB↑ after SCLK↓ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
NOTES:
t
S
t
H
t
Read
16
6
HR
t
Write
DS
DH
t
Read or Write
Read
4
5
t
DVR
11. SPI Interface timing is directly proportional to the ADC sample period (t ). Values in Switching Specifications table reflect multiples of a 4ns sample
S
period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Typical Performance Curves All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -dBFS, f = 105MHz, f
= 250MSPS.
A
IN
IN
SAMPLE
-65
90
85
80
75
70
65
60
HD2 AT 250MSPS
-70
-75
HD3 AT 250MSPS
SFDR AT 130MSPS
SFDR AT 250MSPS
-80
HD3 AT 130MSPS
-85
SNR AT 130MSPS
-90
-95
HD2 AT 130MSPS
-100
-105
SNR AT 250MSPS
100
0
100
200
300
400
500
600
0
200
300
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs f
FIGURE 4. HD2 AND HD3 vs f
IN
IN
100
90
80
70
60
50
40
30
20
10
-30
-40
HD2 (dBc)
SFDR (dBfs)
-50
-60
SNR (dBfs)
SFDR (dBc)
HD3 (dBc)
HD2 (dBFS)
-70
-80
HD3 (dBFS)
SNR (dBc)
-20
-90
-100
-110
-60
-50
-40
-30
-10
0
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs A
FIGURE 6. HD2 AND HD3 vs A
IN
IN
FN7853.1
June 17, 2011
13
ISLA222P
Typical Performance Curves All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -dBFS, f = 105MHz, f
= 250MSPS. (Continued)
A
IN
IN
SAMPLE
84
82
80
78
76
74
72
70
-75
SFDR A = -2dBFS
IN
H3
-80
-85
-90
SFDR A = -1dBFS
IN
-95
H2
-100
-105
SNR A = -1dBFS
IN
70
90
110 130 150 170 190 210 230 250
SAMPLE RATE (MSPS)
70
90
110 130 150 170 190 210 230 250
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs f
FIGURE 8. HD2 AND HD3 vs f
SAMPLE
SAMPLE
1.0
0.8
0.6
0.4
0.2
0
850
800
750
700
650
600
550
500
LVDS
-0.2
-0.4
-0.6
-0.8
-1.0
CMOS
450
400
40 60
80 100 120 140 160 180 200 220 240
SAMPLE RATE (MSPS)
0
500
1000 1500 2000 2500 3000 3500 4000
CODES
FIGURE 9. POWER vs f
IN 3mA LVDS AND CMOS MODES
FIGURE 10. DIFFERENTIAL NONLINEARITY
SAMPLE
1.0
0.8
0.6
0.4
0.2
0
80
78
76
74
72
70
68
66
64
62
60
SFDR
SNR
-0.2
-0.4
-0.6
-0.8
-1.0
0
500
1000 1500 2000 2500 3000 3500 4000
CODES
0.75
0.85
0.95
1.05
1.15
INPUT COMMON MODE (V)
FIGURE 11. INTEGRAL NONLINEARITY
FIGURE 12. SNR AND SFDR vs VCM
FN7853.1
June 17, 2011
14
ISLA222P
Typical Performance Curves All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -dBFS, f = 105MHz, f = 250MSPS. (Continued)
SAMPLE
A
IN
IN
140000
120000
100000
80000
60000
40000
20000
0
0
A
= -1.0dBFS
IN
126,227
SNR = 70.3dBFS
SFDR = 78.8dBc
SINAD = 69.5dBFS
-20
-40
73,478
-60
-80
-100
-120
0
0
0
294
1
0
0
0
2040 2041 2042 2043 2044 2045 2046 2047 2048 2049
CODE
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 13. NOISE HISTOGRAM
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
0
-20
0
-20
A
= -1.0dBFS
A
= -1.0dBFS
IN
IN
SNR = 68.9dBFS
SFDR = 75.0dBc
SINAD = 67.7dBFS
SNR = 69.9dBFS
SFDR = 76.8dBc
SINAD = 68.7dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
0
20
40
60
80
100
120
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
-40
-20
-40
-60
-60
IMD3 = 96dBFS
-80
-80
IMD3 = 87dBFS
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM
(F1 = 70MHz, F2 = 71MHz AT -7dBFS)
FIGURE 18. TWO-TONE SPECTRUM
(F1 = 170MHz, F2 = 171MHz AT -7dBFS)
FN7853.1
June 17, 2011
15
ISLA222P
After the power supply has stabilized, the internal POR releases
Theory of Operation
Functional Description
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The ISLA222P is based on a 12-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 20). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 19. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
CLKN
CLKP
CALIBRATION
TIME
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
RESETN
CALIBRATION
BEGINS
CAL_STATUS
• DNC pins must not be connected
BIT
• SDO has an internal pull-up and should not be driven externally
CALIBRATION
COMPLETE
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
CLKOUTP
• SPI communications must not be attempted
FIGURE 19. CALIBRATION TIMING
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
CLOCK
GENERATION
INP
2.5-BIT
2.5-BIT
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
SHA
FLASH
FLASH
INN
+
1.25V
–
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 20. A/D CORE BLOCK DIAGRAM
FN7853.1
June 17, 2011
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ISLA222P
In situations where the sample rate is not constant, best results
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a less than 0.5mA pull-up is
recommended, as RESETN has an internal pull-up to OVDD. As is
the case during power-on reset, RESETN and DNC pins must be in
the proper state for the calibration to successfully execute.
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
The performance of the ISLA222P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
Temperature Calibration
72.0
85
-2dBFS ANALOG INPUT
200MSPS
-1dBFS ANALOG INPUT
130MSPS
71.5
250MSPS
130MSPS
200MSPS
71.0
80
75
250MSPS
70.5
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
70.0
-40
-35
-30
-25
-20
-40
-35
-30
-25
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
FIGURE 22. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, f = 105MHz
DEVICE CALIBRATED AT -40°C, f = 105MHz
IN
IN
72.0
71.5
71.0
70.5
70.0
85
80
75
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
200MSPS
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
130MSPS
200MSPS
130MSPS
250MSPS
250MSPS
5
10
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
FIGURE 24. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, f = 105MHz
DEVICE CALIBRATED AT +25°C, f = 105MHz
IN
IN
FN7853.1
June 17, 2011
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ISLA222P
Temperature Calibration(Continued)
72
71
70
69
85
80
75
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
200MSPS
130MSPS
200MSPS
250MSPS
130MSPS
250MSPS
65
67
69
71
73
75
77
79
81
83
85
65
70
75
80
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
FIGURE 26. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
IN
IN
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V as shown in Figure 27.
ADTL1-12
TX-2-5-1
1000pF
A/D
VCM
1.8
1.4
1.0
0.6
0.2
VINN
1000pF
VINP
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH
IF APPLICATIONS
VCM
0.94V
1.0V
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA222P is 600Ω.
FIGURE 27. ANALOG INPUT RANGE
The SHA design uses a switched capacitor input stage (see
Figure 43), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 28 through
30. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 28 and 29.
A differential amplifier, as shown in the simplified block diagram
in Figure 30, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact sales support for more information:
http://www.intersil.com/contacts/.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
FN7853.1
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ISLA222P
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 23. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
A/D
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
Jitter
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8V on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t ) and SNR is shown in Equation 1 and is
J
P-P
illustrated in Figure 32.
1
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
IN J
100
95
90
85
80
75
70
65
60
55
t
= 0.1ps
J
14 BITS
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
t
= 1ps
J
12 BITS
t
= 10ps
J
10 BITS
t
= 100ps
J
1000pF
TC4-19G2+
50
CLKP
200
1M
10M
100M
1G
INPUT FREQUENCY (Hz)
FIGURE 32. SNR vs CLOCK JITTER
0.01µF
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instance shown in Figure 32. The internal aperture
jitter combines with the input clock jitter in a root-sum-square
fashion, since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
CLKN
1000pF
1000pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in the 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
Voltage Reference
A temperature compensated internal voltage reference provides the
reference charges used in the successive approximation operations.
The full-scale range of each A/D is proportional to the reference
voltage. The nominal value of the voltage reference is 1.25V.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
AVSS
DIVIDE RATIO
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1 and 2 on pages 11 and
12 show the timing relationships for LVDS and CMOS modes,
respectively.
2
1
4
Float
AVDD
FN7853.1
June 17, 2011
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ISLA222P
Additionally, the drive current for LVDS mode can be set to a
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
nominal 3mA (default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout; therefore the user should
experiment to determine if performance degradation is observed.
BINARY
11
10
9
1
0
• • • •
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 23.
• • • •
• • • •
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
GRAY CODE
11
10
9
1
0
The power dissipated by the ISLA222P is primarily dependent on
the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
11
10
9
1
0
• • • •
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
• • • •
• • • •
• • • •
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
AVSS
MODE
Normal
Sleep
Nap
BINARY
11
10
9
1
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
Float
Mapping of the input voltage to the various data formats is
shown in Table 3.
AVDD
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 23.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
TWO’S
VOLTAGE
OFFSET BINARY
COMPLEMENT
GRAY CODE
Data Format
–Full-Scale 0000 0000 0000 1000 0000 0000 0000 0000 0000
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 23.
–Full-Scale 0000 0000 0001 1000 0000 0001 0000 0000 0001
+1LSB
Mid–Scale 1000 0000 0000 0000 0000 0000 1100 0000 0000
+Full-Scale 1111 1111 1110 0111 1111 1110 1000 0000 0001
-1LSB
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
+Full-Scale 1111 1111 1111 0111 1111 1111 1000 0000 0000
FN7853.1
June 17, 2011
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ISLA222P
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. This clock is at half the frequency
of the sample clock, and the absolute phase of the output clocks
for multiple A/Ds is indeterminate. This feature allows the phase
of multiple A/Ds to be synchronized (refer to Figure 35), which
greatly simplifies data capture in systems employing multiple
A/Ds.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 12).
SAMPLE CLOCK
INPUT
s1
ANALOG INPUT
s2
L+td
(Note 13)
tRSTH
(Note 14)
CLKDIVRSTP
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
s0
s1
s2
s2
s3
s3
ADC1 CLKOUTP
ADC2 OUTPUT DATA
s1
ADC2 CLKOUTP
(Note 14)
(phase 1)
ADC2 CLKOUTP
(Note 15)
(phase 2)
NOTES:
13. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.
14. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
FIGURE 35. SYNCHRONOUS RESET OPERATION
FN7853.1
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ISLA222P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 36. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 37. LSB-FIRST ADDRESSING
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 38. SPI WRITE
tDSW
tCLK
tHR
tHI
tDVR
tS
CSB
tDHW
tLO
SCLK
WRITING A READ COMMAND
A9 A2 A1
READING DATA
)
(3 WIRE MODE
SDIO
SDO
A0
D7 D6
D2 D1 D0
D3
W1 W 0
A12 A11
A10
R/W
(4 WIRE MODE)
D3 D2 D1
D7
D0
SPI READ
FIGURE 39. SPI READ
FN7853.1
June 17, 2011
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ISLA222P
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the A/D sample rate (f
for write operations and f
SAMPLE
) divided by 32
divided by 132 for reads. At
SAMPLE
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 36 and 37 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
f
= 250MHz, maximum SCLK is 15.63MHz for writing and
SAMPLE
3.79MHz for read operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 38,
and timing values are given in “Switching Specifications” on
page 12.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA222P functioning as a slave. Multiple
slave devices can interface to a single master in three-wire mode
only, since the SDO output of an unaddressed device is asserted
in four wire mode.
FN7853.1
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ISLA222P
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0] BYTES TRANSFERRED
00
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
1
01
10
11
2
3
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
4 or more
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
Figures 40 and 41 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
TABLE 5. OFFSET ADJUSTMENTS
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
PARAMETER
Steps
Bit 7 SDO Active
Bit 6 LSB First
255
255
–Full-Scale (0x00)
Mid–Scale (0x80)
+Full-Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
+5LSB (+1.75mV)
0.04LSB (0.014mV)
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. In
3-wire SPI mode, the burst is ended by pulling the CSB pin high. If
the device is operated in 2-wire mode the CSB pin is not
available. In that case, setting the burst_end address determines
the end of the transfer. During a write operation, the user must
be cautious to transmit the correct number of bytes based on the
starting and ending addresses.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
TABLE 6. COARSE GAIN ADJUSTMENT
0x22[3:0] CORE 0
0x26[3:0] CORE 1
NOMINAL COARSE GAIN ADJUST
(%)
Device Information
Bit3
Bit2
Bit1
Bit0
+2.8
+1.4
-2.8
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
-1.4
FN7853.1
June 17, 2011
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ISLA222P
output data clock. This control is accomplished through the use of
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
the phase_slip SPI feature, which allows the rising edge of the
output data clock to be advanced by one input clock period, as
shown in the Figure 42. Execution of a phase_slip command is
accomplished by first writing a '0' to bit 0 at address 0x71,
followed by writing a '1' to bit 0 at address 0x71.
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
PARAMETER
Steps
256
-2%
256
–Full-Scale (0x00)
Mid–Scale (0x80)
+Full-Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
0.00%
+2%
ADC Input
Clock (500MHz)
+0.2%
2ns
4ns
0.016%
0.0016%
Output Data
Clock (250MHz)
No clock_slip
ADDRESS 0X25: MODES
2ns
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to “Nap/Sleep” on page 20). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
FIGURE 42. PHASE SLIP
TABLE 8. POWER-DOWN CONTROL
0x25[2:0]
ADDRESS 0X72: CLOCK_DIVIDE
VALUE
POWER DOWN MODE
The ISLA222P has a selectable clock divider that can be set to
divide by two or one (no division). By default, the tri-level CLKDIV
pin selects the divisor. This functionality can be overridden and
controlled through the SPI, as shown in Table 9. This register is
not changed by a Soft Reset.
000
Pin Control
001
Normal Operation
Nap Mode
010
100
Sleep Mode
TABLE 9. CLOCK DIVIDER SELECTION
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
0x72[2:0]
CLOCK DIVIDER
VALUE
000
Pin Control
The input offset of A/D core #1 can be adjusted in fine and
coarse steps in the same way that offset for core #0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
001
Divide by 1
010
Divide by 2
other
Not Allowed
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA222P can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
This register is not changed by a Soft Reset.
TABLE 10. OUTPUT MODE CONTROL
0x73[7:5]
VALUE
000
OUTPUT MODE
LVDS 3mA (Default)
LVDS 2mA
Global Device Configuration/Control
001
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily
latch the data from each A/D by controlling the phase of the
100
LVCMOS
FN7853.1
June 17, 2011
25
ISLA222P
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
TABLE 13. OUTPUT TEST MODES
0xC0[7:4]
VALUE
OUTPUT TEST MODE
WORD 1
WORD 2
VALUE
OUTPUT FORMAT
Two’s Complement (Default)
Gray Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Off
000
Midscale
0x8000
0xFFFF
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
010
Positive Full-Scale
Negative Full-Scale
Reserved
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
Reserved
N/A
This bit sets the DLL operating range to fast (default) or slow.
Reserved
N/A
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
Reserved
User Pattern
Reserved
user_patt1
N/A
user_patt2
N/A
TABLE 12. DLL RANGES
Ramp
N/A
N/A
DLL RANGE
Slow
MIN
40
MAX
100
250
UNIT
MSPS
MSPS
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
Fast
80
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete. This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
DEVICE TEST
The ISLA222P can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 28 for more detail. The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock; therefore several sample
clock cycles may elapse before the data is present on the output
bus.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These bits set the test mode according to Table 13. Other
values are reserved. User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See the “SPI Memory
Map” on page 28.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
Bits 2:0 User Test Mode
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
“SPI Memory Map” on page 28.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
FN7853.1
June 17, 2011
26
ISLA222P
Bit [0] Select sampler bit. Set to ‘0’.
Digital Temperature Sensor
This set of registers provides digital access to a PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
information that can be used to decide when to recalibrate the
A/D as needed.
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
The nominal transfer function of the temperature counter is
Codes (in decimal) = 0.56*T(°C) + 618. This corresponds to
approximately a 65 LSB increase from -40° to +85°C.
ADDRESS 0X4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
A typical temperature measurement can occur as follows:
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide=’101’
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power down, disable temp
counter-recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
Bit [5] Temperature counter power-down bit. Set to ‘1’ to
power-down temperature counter.
4. Read address 0x4B (MSBs)
5. Read address 0x4C (LSBs)
6. Record temp code value
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~ 66µs (for 250MSPS). Faster update rates result in lower
precision.
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter. Contact sales support for more information:
http://www.intersil.com/contacts/
FN7853.1
June 17, 2011
27
ISLA222P
SPI Memory Map
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
port_config
Reserved
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
00
SDO Active LSB First Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
burst_end
Burst end address [7:0]
Reserved
00h
03-07
Reserved
08
09
chip_id
chip_version
Chip ID #
Chip Version #
Reserved
Read only
Read only
0A-0F
10-1F
20
Reserved
Reserved
Reserved
offset_coarse_adc0
offset_fine_adc0
gain_coarse_adc0
gain_medium_adc0
gain_fine_adc0
modes_adc0
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
21
22
Reserved
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
26
27
28
29
2A
2B
offset_coarse_adc1
offset_fine_adc1
gain_coarse_adc1
gain_medium_adc1
gain_fine_adc1
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
Reserved
Reserved
Coarse Gain
Medium Gain
Fine Gain
modes_adc1
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
2C-2F
33-4A
4B
Reserved
Reserved
Reserved
Reserved
temp_counter_high
temp_counter_low
temp_counter_control
Reserved
Temp Counter [10:8]
Read only
Read only
00h
4C
Temp Counter [7:0]
Reset
4D
Enable
PD
Divider [2:0]
Select
4E-6F
70
Reserved
skew_diff
Differential Skew
Reserved
80h
00h
71
phase_slip
Next Clock
Edge
72
clock_divide
Clock Divide [2:0]
00h
000 = Pin Control
001 = divide by 1
NOT reset by
Soft Reset
010 = divide by 2
100 = divide by 4
Other codes = Reserved
FN7853.1
June 17, 2011
28
ISLA222P
SPI Memory Map (Continued)
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
output_mode_A
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
73
Output Mode [7:5]
Output Format [2:0]
00h
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
000 = Two’s Complement (Default) NOT reset by
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
Soft Reset
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
00h
NOT reset by
Soft Reset
Default=’0’
75-B5
B6
Reserved
cal_status
Reserved
Calibration
Done
Read Only
00h
B7-BF
C0
Reserved
test_io
Output Test Mode [7:4]
User Test Mode [2:0]
0 = user pattern 1 only
0 = Off (Note 14)
1 = Midscale Short
2 = +FS Short
1 = cycle pattern 1,3
2 = cycle pattern 1,3,5
3 = cycle pattern 1,3,5,7
4-7 = NA
3 = -FS Short
4 = Reserved (Note15)
5-6 = Reserved
7 = Reserved (Note16)
8 = User Pattern (1 to 4 deep)
9 = Reserved
10 = Ramp
11-15 = Reserved
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
user_patt3_lsb
user_patt3_msb
user_patt4_lsb
user_patt4_msb
user_patt5_lsb
user_patt5_msb
user_patt6_lsb
user_patt6_msb
user_patt7_lsb
user_patt7_msb
user_patt8_lsb
user_patt8_msb
Reserved
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
0x00
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CD
CE
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CF
D0
D1-FF
B15
B14
B13
B12
B11
B10
Reserved
NOTES:
14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to determine calibration state.
15. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs.
16. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs.
FN7853.1
June 17, 2011
29
ISLA222P
Equivalent Circuits
AVDD
AVDD
TO
CLOCK-PHASE
GENERATION
AVDD
CSAMP
4pF
TO
CHARGE
PIPELINE
CLKP
INP
AVDD
E2
11k
11k
E3
E3
E1
18k
600
CSAMP
4pF
AVDD
TO
CHARGE
PIPELINE
INN
18k
AVDD
E2
E1
CLKN
FIGURE 43. ANALOG INPUTS
FIGURE 44. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
75k
OVDD
AVDD
TO
SENSE
LOGIC
75k
280
OVDD
20k
INPUT
INPUT
TO
LOGIC
280
75k
75k
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[11:0]P
D[11:0]N
OVDD
DATA
D[11:0]
DATA
DATA
2mA OR
3mA
FIGURE 48. CMOS OUTPUTS
FIGURE 47. LVDS OUTPUTS
FN7853.1
June 17, 2011
30
ISLA222P
Equivalent Circuits(Continued)
AVDD
VCM
+
0.94V
–
FIGURE 49. VCM_OUT OUTPUT
LVDS Outputs
A/D Evaluation Platform
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Intersil offers an A/D Evaluation platform which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
http://www.intersil.com/converters/adc_eval_platform/
characteristic impedance.
Unused Inputs
Layout Considerations
Standard logic inputs (RESETN, CSB, SCLK, SDIO and SDO) which
will not be operated do not require connection to ensure optimal
A/D performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Bypass and Filtering
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
FN7853.1
June 17, 2011
31
ISLA222P
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
I2E the Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Least Significant Bit (LSB) is the bit that has the smallest value or
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to
full-scale) when the converter’s full-scale input power is used as
the reference.
weight in a digital word. Its value in terms of input voltage is
N
V
/(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7853.1
CHANGE
6/17/11
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISLA222P
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7853.1
June 17, 2011
32
ISLA222P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
10.00
A
Z
X
6
EXPOSED
PAD AREA
9.75
B
PIN #1
72
72
INDEX AREA
1
1
6
PIN 1
INDEX AREA
9.75
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
7.150 REF.
TOP VIEW
9.75 ±0.10
0.100 M C A B
BOTTOM VIEW
11°
Y
ALL AROUND
C0.400X45° (4X)
10.00 ±0.10
SIDE VIEW
(0.350)
R0.200
(7.15)
(4.15 REF)
1
0.500 ±0.100
R0.115 TYP.
72
(4X 9.70)
(4X 8.50)
(3.00 )
DETAIL "X"
DETAIL "Z"
(6.00)
R0.200 MAX.
ALL AROUND
( 72X 0 .23)
0.100 C
( 72X 0 .70)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
SEATING
PLANE
0.080C
0.190~0.245
0.23 ±0.050
2. Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
0.50
C
0.025 ±0.020
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
0.100M C A B
0.050M C
4. Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
DETAIL "Y"
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Package outline compliant to JESD-M0220.
7.
FN7853.1
June 17, 2011
33
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