ISLA216S25IR1Z [INTERSIL]
16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC; 16位250/200/130 MSPS JESD204B高速串行输出ADC
| 型号： | ISLA216S25IR1Z |
| 厂家： | 
Intersil |
| 描述： | 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC |
| 文件： | 总34页 (文件大小：1654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 250/200/130 MSPS JESD204B High Speed
Serial Output ADC
ISLA216S
Features
• JESD204A/B High Speed Data Interface
- JESD204A Compliant
The ISLA216S is a series of low-power, high-performance,
16-bit, analog-to-digital converters. Designed with
FemtoCharge™ technology on a standard CMOS process, the
series supports sampling rates of up to 250MSPS. The
ISLA216S is part of a pin-compatible family of 12-, 14-, and
16-bit A/Ds with maximum sample rates ranging from 130 to
500MSPS and shares the same analog core as Intersil's
proven ISLA216P series of ADCs. The family minimizes power
consumption while providing state-of-the art dynamic
performance, offering an optimal performance-vs-power
trade-off.
- JESD204B Device Subclass 0 Compliant
- JESD204B Device Subclass 2 Compatible
- JESD204 Output Lanes Run up to 4.375Gbps
- Highly Configurable JESD204 Transmitter
• Multiple Chip Time Alignment and Deterministic Latency
Support (JESD204B Device Subclass 2)
• SPI Programmable Debugging Features and Test Patterns
• 48-pin QFN 7mmx7mm Package
Differentiating the ISLA216S from the ISLA216P is its highly
configurable, JESD204B-compliant, high speed serial output
link. The link offers data rates up to 4.375Gbps per lane and
multiple packing modes. It uses two lanes to transmit the
conversion data. The SERDES transmitter also provides
deterministic latency and multi-chip time alignment support to
satisfy an application's complex synchronization requirements.
Key Specifications
• SNR @ 250/200/130MSPS
75.8/77.2/78.0 dBFS f = 30MHz
IN
74.6/75.2/74.8 dBFS f = 190MHz
IN
• SFDR @ 250/200/130MSPS
A serial peripheral interface (SPI) port allows for extensive
configurability of the JESD204B transmitter including access
to its built-in link and transport-layer test patterns. The SPI port
also provides control for numerous additional features
including the fine gain and offset adjustments of the two ADC
cores as well as the programmable clock divider, enabling 2x
and 4x harmonic clocking.
87/93/94 dBc f = 30MHz
IN
82/81/81 dBc f = 190MHz
IN
• Total Power Consumption: 887mW @ 250MSPS
Applications
• Radar and Satellite Antenna Array Processing
• Broadband Communications and Microwave Receivers
• High-Performance Data Acquisition
• Communications Test Equipment
• High-Speed Medical Imaging
The ISLA216S is available in a space-saving 7mmx7mm 48 Ld
QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C).
Pin-Compatible Family
SPEED
PRODUCT
MODEL
ISLA216S25
ISLA216S20
ISLA216S13
ISLA214S50
ISLA212S50
ISLA214S25
ISLA212S25
RESOLUTION
(MSPS)
AVAILABILITY
16
16
16
14
12
14
12
250
200
130
500
500
250
250
Now
Now
Now
Now
Soon
Soon
Soon
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
February 2, 2012
FN7996.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISLA216S
CLKP
CLKN
CLOCK
GENERATION
LANE[1:0]P
LANE[1:0]N
VINP
VINN
16-BIT
250MSPS
ADC
JESD204
TRANSMITTER
SHA
VREF
+
1.25V
–
VCM
SPI
CONTROL
FIGURE 2. BLOCK DIAGRAM
Pin Configuration
ISLA216S
(48 LD QFN)
TOP VIEW
48 47 46
45 44
43 42
41
40 39 38
37
VCM
OVDD
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
AVSS
AVSS
VINN
VINN
OVSS
DNC
3
DNC
4
OVSS
5
LANE1N
LANE1P
6
7
VINP
VINP
8
OVSS
LANE0N
AVSS
9
LANE0P
AVSS
AVDD
10
11
OVSS
OVDD
PAD – Exposed Paddle
DNC 12
13 14 15
16 17
18 19
20
21 22 23
24
FN7996.0
February 2, 2012
2
ISLA216S
Pin Descriptions
PIN NUMBER
NAME
AVDD
FUNCTION
2, 11, 14, 15, 46
1.8V Analog Supply
12, 20, 33, 34, 47, 48
DNC
Do Not Connect
3, 4, 9, 10
AVSS
Analog Ground
7, 8
VINP
Analog Input, Positive
Analog Input, Negative
Common Mode Output
Clock Divider Control
Clock Input True, Complement
5, 6
VINN
1
VCM
44
CLKDIV
CLKP, CLKN
NAPSLP
RESETN
OVSS
16, 17
45
Power Control (Nap, Sleep modes)
Power On Reset (Active Low)
Output Ground
13
26, 29, 32, 35, 37, 38
25, 36, 39
22, 24
21, 23
18, 19
27, 28
30, 31
40
OVDD
1.8V Digital Supply
OVDD (PLL)
OVSS (PLL)
SYNCP, SYNCN
LANE0P, LANE0N
LANE1P, LANE1N
SDO
1.8V Analog Supply for SERDES PLL
Analog Ground Supply for SERDES PLL
JESD204A SYNC Input
SERDES Lane 0
SERDES Lane 1
SPI Serial Data Output
41
CSB
SPI Chip Select (active low)
SPI Clock
42
SCLK
43
SDIO
SPI Serial Data Input/Output
Exposed Paddle. Analog Ground (connect to AVSS)
PAD
AVSS
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA216S25IR1Z
ISLA216S20IR1Z
ISLA216S13IR1Z
ISLA216S25 IR1Z
ISLA216S20 IR1Z
-40 to +85
-40 to +85
-40 to +85
48 Ld QFN
L48.7x7G
48 Ld QFN
48 Ld QFN
L48.7x7G
L48.7x7G
ISLA216S13 IR1Z
Coming Soon
ISLA216S25IR48EV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216S13, ISLA216S20, ISLA216S25. For more information on MSL
please see techbrief TB363.
FN7996.0
February 2, 2012
3
ISLA216S
Table of Contents
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JESD204A Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Initial Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ADDRESS 0xDF - 0xF3: JESD204 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address 0xDF-0xEE: JESD204A Parameter INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Bypass and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CML Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7996.0
February 2, 2012
4
ISLA216S
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
24
θ
(°C/W)
0.4
JA
JC
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C.
ISLA216S25
MAX
ISLA216S20
MIN MAX
ISLA216S13
MIN MAX
MIN
(Note 6) TYP (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS
PARAMETER
DC SPECIFICATIONS
Analog Input
SYMBOL
CONDITIONS
Full-Scale Analog Input
Range
V
Differential
1.95
2.14
2.22
1.95
2.08
2.22
1.95
2.03
2.22
V
P-P
FS
Input Resistance
Input Capacitance
R
Differential
Differential
Full Temp
300
10.7
145
300
10.7
124
300
10.7
68
Ω
IN
C
pF
IN
Full Scale Range Temp.
Drift
A
ppm/°C
VTC
Input Offset Voltage
Gain Error
V
-5.0
±1
1
5.0
-5.0
±1
1
5.0
-5.0
±1
1
5.0
mV
%
OS
E
G
Common-Mode Output
Voltage
V
0.94
0.94
0.94
V
CM
Common Mode Input
Current (per pin)
I
12.0
12.0
12.0
µA/MSPS
CM
Clock Inputs
Inputs Common Mode
Voltage
0.9
1.8
0.9
1.8
0.9
1.8
V
V
CLKP, CLKN Swing
Power Requirements
1.8V Analog Supply
Voltage
AVDD
OVDD
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
1.8
1.8
V
1.8V Digital Supply
Voltage
V
1.8V Analog Supply
Current
I
354
139
378
152
325
128
349
140
283
109
306
122
mA
mA
AVDD
1.8V Digital Supply
Current
I
OVDD
FN7996.0
February 2, 2012
5
ISLA216S
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216S25
MAX
ISLA216S20
MIN MAX
ISLA216S13
MIN MAX
MIN
(Note 6) TYP (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS
PARAMETER
SYMBOL
CONDITIONS
Power Supply Rejection
Ratio (Note 7)
PSRR
30MHz 200mV
38
44
38
44
38
44
dB
P-P
1MHz 200mV
dB
P-P
Total Power Dissipation
Normal Mode
P
P
P
887
323
6
954
367
14
815
300
6
880
342
14
706
267
6
770
310
14
mW
mW
mW
µs
D
D
D
Nap Mode
Sleep Mode
CSB at logic high
Nap Mode Wakeup
Time
Sample Clock
Running
5
5
5
Sleep Mode Wakeup
Time
Sample Clock
Running
1
1
1
ms
AC SPECIFICATIONS (Note 8)
Differential Nonlinearity
Integral Nonlinearity
DNL
INL
-0.99 ±0.24
±16.0
-0.99 ±0.17
±12.0
-0.99 ±0.14
±9.0
LSB
LSB
Minimum Conversion
Rate (Note 9)
f
MIN
100
100
100
MSPS
S
Maximum Conversion
Rate
f
MAX
250
200
130
MSPS
S
Signal-to-Noise Ratio
(Note 10)
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
75.8
77.2
78.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 495MHz
= 605MHz
= 30MHz
72.3
75.5
74.6
72.4
70.8
69.3
75.5
74.9
73.9
69.8
66.5
64.9
12.20
74.3
76.6
75.2
72.5
70.6
69.2
77.1
76.3
74.1
69.0
66.3
64.1
12.45
75.0
76.8
74.8
71.2
69.6
67.3
77.7
76.3
73.8
66.0
65.9
58.4
12.59
Signal-to-Noise and
Distortion (Note 10)
SINAD
= 105MHz
= 190MHz
= 363MHz
= 495MHz
= 605MHz
= 30MHz
71.1
73.6
74.2
Effective Number of Bits
(Note 10)
ENOB
= 105MHz
= 190MHz
= 363MHz
= 495MHz
= 605MHz
11.51 12.14
11.95
11.93 12.36
12.03
12.03 12.36
11.91
Bits
Bits
11.27
11.19
10.66
Bits
10.76
10.72
10.61
Bits
10.52
10.43
9.52
Bits
FN7996.0
February 2, 2012
6
ISLA216S
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216S25
MAX
ISLA216S20
MIN MAX
ISLA216S13
MIN MAX
MIN
(Note 6) TYP (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS
PARAMETER
SYMBOL
CONDITIONS
Spurious-Free Dynamic
Range (Note 10)
SFDR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
87
84
82
72
67
65
88
89
87
81
79
75
96
87
93
88
81
70
67
64
94
95
91
86
87
83
97
86
94
85
81
66
67
57
100
94
89
84
80
77
96
87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 495MHz
= 605MHz
= 30MHz
74
76
76
Spurious-Free Dynamic SFDRX23
Range Excluding H2, H3
(Note 10)
= 105MHz
= 190MHz
= 363MHz
= 495MHz
= 605MHz
= 70MHz
Intermodulation
Distortion
IMD
= 170MHz
-13
10
-13
-13
Word Error Rate
Full Power Bandwidth
NOTES:
WER
10
10
FPBW
620
620
620
MHz
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude
of the spur in the captured data at the frequency of the disturber sinusoid.
8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” on
page 14 and “User Initiated Reset” on page 15 for more detail.
9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates
below 100MSPS, as long as the lane data rate is greater than or equal to 1Gbps.
10. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
CMOS INPUTS
Input Current High (RESETN)
Input Current Low (RESETN)
I
V
V
V
V
V
V
= 1.8V
= 0V
1
-12
4
10
-7
µA
µA
µA
µA
µA
µA
V
IH
IN
IN
IN
IN
IN
IN
I
-25
IL
Input Current High (SDIO, SCL, SDA SCLK)
Input Current Low (SDIO, SCL, SDA SCLK)
Input Current High (CSB)
I
= 1.8V
= 0V
12
IH
I
-600
40
-400
52
1
-300
70
IL
I
= 1.8V
= 0V
IH
Input Current Low (CSB)
I
10
IL
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
Input Current High (NAPSLP, CLKDIV) (Note 11)
Input Current Low (NAPSLP, CLKDIV)
V
1.17
IH
V
0.63
30
V
IL
I
19
25
µA
µA
IH
I
--30
-25
-19
IL
FN7996.0
February 2, 2012
7
ISLA216S
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 6)
TYP
4
(Note 6) UNITS
Input Capacitance
C
DI
pF
LVDS INPUTS (SYNCP, SYNCN)
Input Common Mode Range
V
825
250
1575
450
mV
mV
kΩ
ICM
Input Differential Swing (peak-to-peak, single-ended)
Input Pull-up and Pull-down Resistance
CML OUTPUTS
V
ID
R
100
Ipu
Output Common Mode Voltage
1.14
V
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 6)
MAX
(Note 6)
PARAMETER
SYMBOL
CONDITION
TYP
UNITS
ADC OUTPUT
Aperture Delay
RMS Aperture Jitter
t
190
100
250
ps
fs
A
j
A
Synchronous Clock Divider Reset Recovery Time (Note 12)
t
DLL recovery
time after
Synchronous
Reset
µs
RSTRT
Latency (ADC Pipeline Delay)
Overvoltage Recovery
SERDES
L
10
1
cycles
cycles
t
OVR
PLL Lock Time
295
2.2
5
µs
PLL Bandwidth
MHz
Added Random Jitter
ps
RMS
Added Deterministic Jitter
7
5
ps P-P
ps rms
Maximum Input Sample Clock Total Jitter to Maintain SERDES
BER <1E-12
Integrated from
1kHz to 10MHz
offset from
carrier
LVDS Inputs
SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of
CLKP)
t
AVDD,
OVDD = 1.7V to
1.9V, T = -40°C
to +85°C
400
75
ps
ps
RSTS
A
SYNCP, SYNCN Hold Time (with respect to the positive edge of
CLKP)
t
AVDD,
OVDD = 1.7V to
150
350
RSTH
1.9V, T = -40°C
A
to +85°C
CML Outputs
Output Rise Time
t
165
145
50
ps
ps
%
R
Output Fall Time
t
F
Data Output Duty Cycle
Differential Output Resistance
100
Ω
FN7996.0
February 2, 2012
8
ISLA216S
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Differential Output Voltage (Note 13)
SPI INTERFACE (Notes 14, 15)
SCLK Period
SYMBOL
CONDITION
(Note 6)
TYP
760
(Note 6)
UNITS
mV
P-P
t
Write Operation
Read Operation
Read or Write
Read or Write
Read or Write
Read or Write
Read
7
16
2
cycles
cycles
cycles
cycles
cycles
cycles
cycles
CLK
t
CLK
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
NOTES:
t
S
t
5
H
t
6
DS
DH
t
4
t
4
DVR
11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input.
13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing.
14. The SPI interface timing is directly proportional to the ADC sample period (t ). Values above reflect multiples of a 4ns sample period, and must be
S
scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
15. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -2dBFS, f = 105MHz, f
= 250MSPS.
IN
IN
SAMPLE
95
-55
-60
HD2 AT 200 MSPS
SFDR AT 200 MSPS
HD2 AT 130 MSPS
90
85
80
75
70
65
60
55
50
SFDR AT 250 MSPS
SFDR AT 130 MSPS
-65
-70
-75
HD2 AT 250 MSPS
-80
SNR AT 250 MSPS
-85
-90
SNR AT 130 MSPS
SNR AT 200 MSPS
-95
HD3 AT 200 MSPS
HD3 AT 130 MSPS
HD3 AT 250 MSPS
-100
-105
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs f
FIGURE 4. HD2 AND HD3 vs f
IN
IN
FN7996.0
February 2, 2012
9
ISLA216S
Typical Performance Curves(Continued)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -2dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
-40
-50
100
HD3 (dBc)
SFDR (dBFS)
HD2 (dBc)
SNR (dBFS)
-60
80
SFDR (dBc)
60
-70
-80
-90
40
20
HD3 (dBFS)
-100
-110
-120
SNR (dBc)
HD2 (dBFS)
-30
0
-60
-60
-50
-40
-20
-10
0
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 6. HD2 AND HD3 vs A
IN
FIGURE 5. SNR AND SFDR vs A
IN
90
-75
-80
85
80
75
70
65
60
SFDR
SNR
HD3
HD2
-85
-90
-95
-100
-105
-110
100 120 140 160 180 200 220 240 260 280
100 120 140 160 180 200 220 240 260 280
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs f
SAMPLE
FIGURE 7. SNR AND SFDR vs f
SAMPLE
1000
1.0
0.8
0.6
0.4
0.2
0
900
800
700
600
500
400
300
200
100
0
-0.2
-0.4
-0.6
-0.8
-1.0
100 120 140 160 180 200 220 240 260
SAMPLE RATE (MSPS)
0
10000 20000 30000 40000 50000 60000
CODE
FIGURE 9. POWER vs f
FIGURE 10. DIFFERENTIAL NONLINEARITY
SAMPLE
FN7996.0
February 2, 2012
10
ISLA216S
Typical Performance Curves(Continued)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -2dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
15
10
5
90
85
80
75
70
65
60
SFDR
SNR
0
-5
-10
-15
-20
0
10000 20000 30000 40000 50000 60000
CODE
700
800
900 1000 1100 1200 1300 1400 1500
Vcm (mV)
FIGURE 11. INTEGRAL NONLINEARITY
FIGURE 12. SNR AND SFDR vs VCM
140000
120000
100000
80000
60000
40000
20000
0
0
-20
A
= -2.0 dBFS
IN
SNR = 75.1 dBFS
SFDR = 84 dBc
SINAD = 74.7 dBFS
-40
-60
-80
-100
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
ADC CODE
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
FIGURE 13. NOISE HISTOGRAM
0
-20
0
A
= -2.0 dBFS
IN
A
= -2.0 dBFS
IN
SNR = 74.1 dBFS
SFDR = 82 dBc
SINAD = 73.4 dBFS
SNR = 71.9 dBFS
SFDR = 75 dBc
SINAD = 70.5 dBFS
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
FN7996.0
February 2, 2012
11
ISLA216S
Typical Performance Curves(Continued)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -2dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
0
0
-20
IMD = -87 dBFS
IMD = -96 dBFS
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
FIGURE 20. SERDES DATA EYE at 3.0Gbps
FIGURE 19. SERDES DATA EYE at 1.0Gbps
FIGURE 21. SERDES DATA EYE at 4.375Gbps
FIGURE 22. SERDES BATHTUB at 1.0Gbps
FN7996.0
February 2, 2012
12
ISLA216S
Typical Performance Curves(Continued)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -2dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
FIGURE 23. SERDES BATHTUB at 3.0Gbps
FIGURE 24. SERDES BATHTUB at 4.375Gbps
FIGURE 26. SERDES HISTOGRAM at 3.0Gbps
FIGURE 25. SERDES HISTOGRAM at 1.0Gbps
FIGURE 27. SERDES HISTOGRAM at 4.375Gbps
FN7996.0
February 2, 2012
13
ISLA216S
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
Theory of Operation
Functional Description
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The ISLA216S is based upon a 16-bit, 250MSPS ADC converter
core that utilizes a pipelined successive approximation
architecture (see Figure 28). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 29. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. During calibration the JESD204 transmitter PLL is not
locked to the ADC sample clock, so the CML outputs will toggle at
an undetermined rate. Normal operation is resumed once
calibration is complete.
Power-On Calibration
The ADC core(s) perform a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
At 250MSPS the nominal calibration time is 280ms, while the
maximum calibration time is 550ms.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted during
calibration, with the only exception of performing read
operations on the cal_done register at address 0xB6.
CLOCK
GENERATION
INP
2.5-BIT
2.5-BIT
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
SHA
FLASH
FLASH
INN
+
1.25V
–
DIGITAL
ERROR
CORRECTION
FIGURE 28. ADC CORE BLOCK DIAGRAM
FN7996.0
February 2, 2012
14
ISLA216S
The performance of the ISLA216S changes with variations in
CLKN
CLKP
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the ADC under the environmental conditions at
which it will operate.
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc. In
situations where the sample rate is not constant, best results will
be obtained if the device is calibrated at the highest sample rate.
Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
CALIBRATION
COMPLETE
FIGURE 29. CALIBRATION TIMING
User Initiated Reset
Figures 30 through 32 show the affect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
Recalibration of the ADC can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
Temperature Calibration
90
90
SFDR, 200MSPS
SFDR, 200MSPS
85
85
SFDR, 250MSPS
SFDR, 130MSPS
80
SFDR, 250MSPS
SNR, 250MSPS
SFDR, 130MSPS
SNR, 130MSPS
80
75
70
65
60
75
SNR, 130MSPS
SNR, 250MSPS
SNR, 200MSPS
SNR, 200MSPS
70
65
60
-40
-35
-30
-25
-20
5
15
25
TEMPERATURE (°C)
35
45
TEMPERATURE (°C)
FIGURE 30. TYPICAL SNR AND SFDR PERFORMANCE vs
TEMPERATURE, DEVICE CALIBRATED AT -40°C,
= 105MHz
FIGURE 31. TYPICAL SNR AND SFDR PERFORMANCE vs
TEMPERATURE, DEVICE CALIBRATED AT +25°C,
= 105MHz
f
f
IN
IN
95
90
85
80
75
70
65
60
SFDR, 200MSPS
SFDR, 250MSPS
SNR, 250MSPS
SFDR, 130MSPS
SNR, 130MSPS
SNR, 200MSPS
65
70
75
80
85
TEMPERATURE (°C)
FIGURE 32. TYPICAL SNR AND SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +85°C, f = 105MHz
IN
FN7996.0
February 2, 2012
15
ISLA216S
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage as
shown in Figure 33.
ADC
1.8
1.4
1.0
0.6
0.2
VINN
VCM
VINP
1.0V
FIGURE 36. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram
in Figure 36, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
FIGURE 33. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 34 through
36. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 34 and 35.
When an over range occurs, the data sample output bits are held
at full scale (all 0’s or all 1’s), thus allowing the detection of this
condition in the receiver device.
Clock Input
The clock input circuit is a differential pair (see Figure 49).
ADT1-1WT
ADT1-1WT
Driving these inputs with a high level (up to 1.8V
on each
P-P
1000pF
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
ADC
VCM
0.1µF
FIGURE 34. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
The recommended drive circuit is shown in Figure 37. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
TX-2-5-1
ADTL1-12
AV /2 through a Thevenin equivalent of 10kΩ to facilitate AC
coupling.
DD
1000pF
ADC
1000pF
TC4-19G2+
VCM
CLKP
200
1000pF
FIGURE 35. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
0.01µF
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA216S is 300Ω.
CLKN
1000pF
1000pF
FIGURE 37. RECOMMENDED CLOCK DRIVE
The SHA design uses a switched capacitor input stage (see
Figure 48), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input, which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A selectable 2x or 4x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a sample
clock equal to twice the desired sample rate or in 4x mode with a
sample clock equal to four times the desired sample rate. Use of the
2x or 4x frequency divider enables the use of the Phase Slip feature,
which enables the system to be able to select the phase of the
divide by 2 or divide by 4 that causes the ADC to sample the
analog input.
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TABLE 1. CLKDIV PIN SETTINGS
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each ADC is proportional to
the reference voltage. The nominal value of the voltage reference
is 1.25V.
CLKDIV PIN
DIVIDE RATIO
AVSS
Float
AVDD
2
1
4
Digital Outputs
The digital outputs are in CML format, and feature analog and
digital characteristics compliant with the JESD204A standard
requirements.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 22. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
Power Dissipation
The power dissipated by the device is dependent on the ADC
sample rate and the number of active lanes in the link. There is a
fixed bias current drawn from the analog supply for the ADC,
along with a fixed bias current drawn from the digital supply for
each active lane. The remaining power dissipation is linearly
related to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for ADC core sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate. The lane data
rate is related to the ADC core sample rate by a relationship that
is defined by the JESD204 transmitter configuration, and has
additional frequency constraints; see“JESD204A Transmitter” on
page 18 for additional details.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation significantly while taking a very short time to return to
functionality. Sleep mode reduces power consumption drastically
while taking longer to return to functionality.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t ) and SNR is shown in Equation 1 and is
J
illustrated in Figure 38.
1
In Nap mode the JESD204 lanes will continue to produce valid
encoded data, allowing the link to remain active and thus return to
a functional state quickly. The data transmitted over the lanes in
nap mode is the last valid ADC sample, repeated until leaving nap
mode. The 8b/10b encoder’s running disparity will prevent the
potentially long time repetition of this last valid sample from
creating DC bias on the lane. In sleep mode the JESD204 lanes will
be deactivated to conserve power. Thus, sometime after wake up
code group alignment will be required to reestablish the link.
⎛
⎝
⎞
⎠
-------------------
SNR = 20 log
(EQ. 1)
10
2πf
t
IN J
100
95
90
85
80
75
70
65
60
55
tj = 0.1ps
14 BITS
tj = 1ps
12 BITS
The input clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. The JESD204 link
will only remain established during nap mode if the input clock
continues to remain stable during the nap period.
tj = 10ps
10 BITS
tj = 100ps
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2. Please note
that power on calibration occurs at power up time regardless of
the state of the NAPSLP pin; immediately following this power on
calibration routine the device will enter nap or sleep state if the
NAPSLP pin voltage dictates it is to do so.
50
1M
10M
100M
1G
INPUT FREQUENCY (Hz)
FIGURE 38. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise as well. Internal aperture jitter is the uncertainty in
the sampling instant. The internal aperture jitter combines with
the input clock jitter in a root-sum-square fashion, since they are
not statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
AVSS
MODE
Normal
Nap
Float
AVDD
Sleep
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 22.
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.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
TWO’S
Data Format
Output data can be presented in three formats: two’s
complement(default), Gray code and offset binary. The data
format can be controlled through the SPI port by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 22.
INPUT
VOLTAGE
OFFSET BINARY
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
–Full Scale 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
+ 1LSB
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
+Full Scale 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
– 1LSB
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 39 shows this
operation.
Clock Divider Synchronous Reset
The function of clock divider synchronous reset is available as a
SPI-programmable overloaded function on the SYNCP and
SYNCN pins. Given that the clock divider reset and SYNC features
have the same electrical and timing requirements, this
overloading allows the system to generate only a single well
timed signal with respect to the ADC sample clock and select the
ADC’s interpretation of the signal as a SPI-programmable option
(see SPI register 0x77 description for more information). By
default the SYNCP and SYNCN pins will function as the
JESD204A SYNC~.
BINARY
13
12
11
1
0
• • • •
• • • •
• • • •
GRAY CODE
13
12
11
1
0
The use of clock divider reset function is a requirement in a
system that uses the ISLA214S50, ISLA214S35, or CLKDIV = 2
or 4 and also requires time alignment or deterministic latency of
multiple devices. Please contact the factory for more details
about this feature and its usage.
FIGURE 39. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 40.
Soft Reset
GRAY CODE
13
12
11
1
0
• • • •
Soft reset is a function intended to be used when the power on
reset is to be re-run. An application may decide to issue a soft
calibration command after significant temperature change or
after a change in the sample rate frequency to optimize
performance under the new condition.
Soft reset is issued by writing the Soft Reset bit at SPI address
0x00. Soft reset is a self-resetting bit in that will automatically
return to 0 once the power on calibration has completed.
• • • •
• • • •
• • • •
JESD204A Transmitter
Overview
The conversion data is presented by a JESD204B-compliant
SERDES interface. The SERDES lane data rate supports typical
speeds up to 4.375Gbps, exceeding the 3.125Gbps maximum
specified by the JESD204 rev A standard. A SYNC input is
included, which is used for lane initialization as well as time
alignment of multiple converter devices. AC coupling of the
SERDES lane(s) on the board is required. A block diagram of this
SERDES transmitter is shown in Figure 41.
BINARY
13
12
11
1
0
FIGURE 40. GRAY CODE TO BINARY CONVERSION
For more information about the standardized characteristics and
features of a JESD204 interface, please see JESD204 rev A and rev
B standards. For application design support, including evaluation kit
schematics and layout, reference FPGA project(s), and simulation
models for functionality and signal integrity, please contact the
factory and/or view application notes at
Mapping of the input voltage to the various data formats is
shown in Table 3.
http://www.intersil.com/contacts/.
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SERDES Block
Link Layer
Analog
Input
Transport
Layer
Scrambler
1+x14+x15
Encoder
8/10
Lane 0
Sample Data
SER
Logic
PLL
Multiply
Clock
Management
Sample
Clock
- Code group Synchronization
- Alignment Characters
- Initial Lane Synchronization
- Etc
SYNC
Lane 1
Link Layer
FIGURE 41. SERDES TRANSMITTER BLOCK DIAGRAM
See Table 4 on page 20 for the full list of programmable
JESD204 parameters. Via SPI, the JESD204 transmitter is highly
configurable, supporting user configuration of the transmitter.
Please contact the factory for a full list of downgradeable
configurations that are supported.
the previous frame, is replaced with a different specific control
character. A more complete description of the link initialization
sequence, including finite state machine implementation, can be
found in the JESD204 rev A standard.
LANE DATA RATE
Signal integrity plots, including data eye, BER bathtub curves,
and edge histogram plots versus lane data rate can be found in
the typical operating curves section.
The lane data rate for this product family is constrained to be
greater than or equal to 1Gbps and less than or equal to
3.125Gbps for guaranteed operation, so as to be consistent with
the lane data rate limit of 3.125Gbps set by the JESD204 rev A
standard. The lane data rate can typically exceed 4.2Gbps for this
product family.
Initial Lane Alignment
The link initialization process is started by asserting the SYNC~
signal to the ADC device. This assertion causes the JESD204
transmitter to generate comma characters, which are used by the
receiver to accomplish code group synchronization (bit and octet
alignment, respectively). Once code group synchronization is
detected in the receiver, it de-asserts the SYNC~ signal, causing the
JESD204 transmitter to generate the initial lane alignment
sequence (ILA). The ILA is comprised of 4 multi-frames of data in a
standard format, with the length of each multi-frame determined by
the K parameter as programmed into the SPI JESD204A parameter
table. The ILA includes standard control character markers that can
be used to perform channel bonding in the receiving device if
desired. The 2nd multi-frame includes the full JESD204A parameter
data, allowing the receiver to auto-detect the lane configuration if
desired.
SCRAMBLER
The bypassable scrambler is compliant with the scrambler
defined in the JESD204 rev A standard.
This implementation seeds the scrambler with the initial lane
alignment sequence, such that the first two octets following the
sequence can be properly descrambled if the receiver also
passes the lane alignment sequence through its descrambler.
Even if the receiver does not implement this detail, the 3rd and
subsequent octets can be descrambled to yield ADC data due to
the self-synchronizing nature of the scrambler used.
MULTI-CHIP TIME ALIGNMENT
After completion of the ILA the JESD204 transmitter begins
transmitting ADC sample data. Continuous link and lane
alignment monitoring is accomplished via an octet substitution
scheme. The last octet in each frame, if identical to the last octet
in the previous frame, is replaced with a specific control
character. If both sides of the link support lane synchronization,
the last octet in each multi-frame, if identical to the last octet in
The JESD204 standard (in various revisions) provides the
capability to time align multiple JESD204 ADC devices to a single
logic device (FPGA or ASIC). This feature is critical in many
applications that cannot tolerate the variable latency of the
JESD204 link, and that must process pipeline depth correct data
from more than one ADC device.
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ISLA216S
Time alignment of multiple devices provides the capability to
Supported test patterns include both transport and link layer
patterns. Transport layer patterns are passed through the
transport layer of the JESD204 transmitter, following the same
sequence of being packed and sliced into octets as the ADC
sample data. Link layer test patterns bypass the transport layer
and are injected directly into the 8b/10b encoder, serialized, and
sent out of the physical media. Test pattern generation is
controlled through SPI register 0xC0.
align samples from multiple JESD204 ADC devices in the system
in a pipeline-depth correct manner, thus enabling the system to
analyze the ADC data from multiple devices while eliminating the
variable latency of the JESD204 link as a concern. This capability
enables configurations of JESD204 ADCs as IQ, interleave,
and/or simultaneously-sampled converters.
This ADC family uses the asserted to de-asserted SYNC~
transition as the absolute time event with which to generate a
known sequence of characters at the JESD204 transmitter of
equal pipeline depth between all ADC devices in the system to be
time aligned. This is consistent with the JESD204 rev B
subclass 2 device definition.
Link layer PRBS patterns are standard PRBS patterns that can be
used with built-in standard PRBS checkers in, for example, FPGA
SERDES-capable pins.
All transport layer test patterns re-initialize their phase when the
SYNC~ de-assertion occurs; consequently, a system that provides
a well-timed SYNC~ signal with respect to the ADC sample clock
can expect transport layer test patterns to have consistent phase
with respect to that de-assertion, which can be a significant aid
when debugging the system.
Test Patterns
The complexity of the JESD204 interface merits much more test
pattern capability than less complex parallel interfaces. This
device family consequently supports a much wider range of test
patterns than previous ADC families.
TABLE 4. JESD204A PARAMETERS
NUMBER
JESD204
PRODUCT
OF LANES PARAMETER ENCODED
JESD204A PARAMETERS AND FRAME MAP (Notes 16, 17, 18)
C0S0[7:0]
ISLA216S25
ISLA216S20
ISLA216S13
2
CF = 0
CS = 0
F = 2
0
0
C0S0[15:8]
C0S1[15:8]
1
HD = 0
L = 2
0
1
C0S1[8:0]
M = 1
N = 16
N' = 16
S = 2
0
15
15
1
K >= 9
>= 8
NOTES:
16. The JESD204A parameters are shown as their actual values, with the JESD204 encoded values (i.e., the values that are programmed into the SPI
registers) in the next column over. Typically values that must always be greater than 1 are encoded as value minus 1, and so on.
17. Frame map format decoder: "CxSy[a:b]" = Converter x, Sample y, bits a through b. For example, "C0S0[13:6]" = Converter 0, Sample 0, bits 13 through
6, etc. "T" = Tail bit (information-less bit packed in the transport layer mapping to form octets).
18. The topmost lane in the graphical frame map is Lane0, followed by Lane1.
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ISLA216S
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 42. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 43. LSB-FIRST ADDRESSING
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 44. SPI WRITE
tDSW
tCLK
tHI
tH
tDVR
tS
CSB
tDHW
tLO
SCLK
WRITING A READ COMMAND
A9 A2 A1
READING DATA
)
( 3 WIRE MODE
D2 D1 D0
SDIO
SDO
A0
D7
D6
D3
W1 W 0
A12 A11
A10
R/W
( 4 WIRE MODE)
D3 D2 D1
D7
D0
SPI READ
FIGURE 45. SPI READ
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CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 46. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 47. N-BYTE TRANSFER
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 42 and 43 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
SCLK rate is equal to the ADC sample rate (f
) divided by 7
divided by 16 for reads. There is
SAMPLE
for write operations and f
no minimum SCLK rate.
SAMPLE
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 5). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 44,
and timing values are given in “Switching Specifications” on
page 8.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
The SPI port operates in a half duplex master/slave
configuration, with the ADC functioning as a slave. Multiple slave
devices can interface to a single master in three-wire mode only,
since the SDO output of an unaddressed device is asserted in
four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
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TABLE 5. BYTE TRANSFER SELECTION
[W1:W0] BYTES TRANSFERRED
00
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
1
01
10
11
2
3
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
4 or more
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 6. The data format is twos complement.
Figures 46 and 47 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
TABLE 6. OFFSET ADJUSTMENTS
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
PARAMETER
Steps
Bit 7 SDO Active
Bit 6 LSB First
255
255
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
+5LSB (+1.75mV)
0.04LSB (0.014mV)
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
TABLE 7. COARSE GAIN ADJUSTMENT
Device Information
0x22[3:0] core 0
0x26[3:0] core 1
NOMINAL COARSE GAIN ADJUST
(%)
ADDRESS 0X08: CHIP_ID
Bit3
Bit2
Bit1
Bit0
+2.8
+1.4
-2.8
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
-1.4
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ISLA216S
clock signals gets used to cause the sampling event, by “slipping” the
TABLE 8. MEDIUM AND FINE GAIN ADJUSTMENTS
sampling event by one input clock period each time phase_slip is
asserted.
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
PARAMETER
Steps
The clkdivrst feature can work in conjunction with phase_slip.
After well-timed assertion of the clkdivrst signal (via overloading
on the SYNC inputs), the sampling edge position with respect to
the incoming clock rate will have been reset, allowing the system
to “slip” whatever desired number of incoming clock periods
from a known state.
256
-2%
256
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
0.00%
+2%
+0.2%
0.016%
0.0016%
ADDRESS 0X72: CLOCK_DIVIDE
ADDRESS 0X25: MODES
The ADC has a selectable clock divider that can be set to divide
by two or one (no division). By default, the tri-level CLKDIV pin
selects the divisor This functionality can be overridden and
controlled through the SPI, as shown in Table 10. This register is
not changed by a Soft Reset.
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 17). This functionality
can be overridden and controlled through the SPI. This register is
not changed by a Soft Reset.
TABLE 10. CLOCK DIVIDER SELECTION
TABLE 9. POWER-DOWN CONTROL
0x25[2:0]
0x72[2:0]
CLOCK DIVIDER
VALUE
000
VALUE
POWER DOWN MODE
Pin Control
000
Pin Control
001
Divide by 1
001
Normal Operation
Nap Mode
010
Divide by 2
010
other
Not Allowed
100
Sleep Mode
ADDRESS 0X73: OUTPUT_MODE_A
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The output_mode_A register controls the logical coding of the
sample data. Data can be coded in three possible formats: two’s
complement(default), Gray code or offset binary. See Table 11.
The input offset of ADC core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 6. The data format is two’s complement.
This register is not changed by a Soft Reset.
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
VALUE
OUTPUT FORMAT
Two’s Complement (Default)
Gray Code
000
010
100
Offset Binary
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Gain of ADC core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
TABLE 12. DLL RANGES
Global Device Configuration/Control
DLL RANGE
Slow
MIN
40
MAX
100
250
UNIT
MSPS
MSPS
ADDRESS 0X71: PHASE_SLIP
When using the clock_divide feature, the sample clock edge that the
ADC uses to sample the analog input signal can be one of several
different edges on the incoming higher frequency sample clock. For
example, in clock_divide = 2 mode, every other incoming sample clock
edge gets used by the ADC to sample the analog input. The phase_slip
feature allows the system to control which edge of the incoming sample
Fast
80
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24
ISLA216S
ADDRESS 0X77: SYNC_FUNCTION
ADDRESS 0XC5: USER_PATT3_LSB
Bit 0 Clkdivrst
ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3.
This bit controls the functionality of the SYNCP, SYNCN pins on
this device. By default, this bit equals ‘0’, which means that the
functionality of the SYNCP, SYNCN pins is the JESD204 SYNC.
Setting this bit equal to ‘1’ modifies the functionality of the
SYNCP, SYNCN pins to be clkdivrst, which is a synchronous
divider reset on all internal dividers in the device. Usage of this
clkdivrst functionality is required to support multi-chip time
alignment and deterministic latency for devices that use
interleaved product configurations (ISLA214S50 and
ISLA214S35), and for any other product configuration that uses
clkdiv > 1. In both states, the setup and hold times with respect
to the sample clock remain the same. Contact the factory for
more details.
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
ADDRESS 0XB6: CALIBRATION STATUS
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
DEVICE TEST
The device can produce preset or user defined patterns on the
digital outputs to facilitate in-situ testing. A user can pick from
preset built-in patterns by writing to the output test mode field
[7:4] at 0xC0 or user defined patterns by writing to the user test
mode field [2:0] at 0xC0. The user defined patterns should be
loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 27 for more detail. The test mode is
enabled asynchronously to the sample clock, therefore several
sample clock cycles may elapse before the data is present on the
output bus.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0xDF - 0xF3: JESD204 REGISTERS
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode
Address 0xDF-0xEE: JESD204A Parameter
INTERFACE
This set of registers controls the JESD204 transmitter
configuration. By programming these parameters, the system
can select between efficient and simple packing, select the
number of powered up SERDES lanes, choose the ADC resolution
transmitted, and so on. Contact the factory for details.
These bits set the test mode according to the description in “SPI
Memory Map” on page 27.
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the “SPI
Memory Map” on page 27.
0xE0 through 0xED are the JESD204A parameter registers.
These parameters are written to set the transport layer mapping
of the JESD204 transmitter in this product family. These registers
can be written to shift between efficient and simple packing, to
enable or bypass scrambling, and to reduce the number of
powered up lanes used in the link. Each speed graded product
allows downgrading of the JESD204A link (such as reducing the
number of lanes, reducing the converter resolution, etc), but not
upgrading. These parameters are communicated on every lane
of the link during the 2nd multi-frame of the initial lane
alignment sequence, and therefore can be used by a generic
JESD204A receiver the supports the given configuration. See the
JESD204A specification for additional information on how these
registers are used in a JESD204A system, including encoding
rules.
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
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ISLA216S
Bits 4:0 “S”, JESD204A Number of samples per converter per
frame cycle.
ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START
Bit 0 update_start
ADDRESS 0XEA: JESD204_CONFIG_10
This self-resetting bit is used to indicate that some or all the
JESD204A parameters (addresses 0xE0 through 0xED) are going
to be written. Writing a ‘1’ to this bit will hold the JESD204A PLL
and transmitter in a reset state while these parameters are
written, because these parameters can affect the transmitter’s
dynamic behavior (such as modifying the PLL’s frequency
multiplication). The bit will automatically reset to a ‘0’ once a ‘1’
is written to address 0xEE Bit[0] “update_config W1TC”. The
recommended sequence for modifying the JESD204A
transmitter is:
Bit 7 “HD”, JESD204A HD indicates if a converter’s sample can
be split across multiple lanes in the link (always ‘0’ for this
product family).
Bits 4:0 “CF”, JESD204A CF is the number of control fames per
frame clock (always ‘0’ for this product family).
ADDRESS 0XEB: JESD204_CONFIG_11
Bits 7:0 “RES1”, JESD204A reserved for future use.
ADDRESS 0XEC: JESD204_CONFIG_12
Bits 7:0 “RES2”, JESD204A reserved for future use.
ADDRESS 0XED: JESD204_CONFIG_13
1. Write a ‘1’ to 0xDF Bit[0]
2. Write some or all modified values to 0xE0 through 0xEC
3. Write a ‘1’ to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will
automatically be reset to a ‘0’ once configuration has been
applied to the circuitry.
Bits 7:0 “FCHK” JESD204A checksum (unsigned sum MOD 256)
of all the other JESD204A parameter register values. This is a
read-only register, as the checksum is calculated by the device.
ADDRESS 0XE0: JESD204_CONFIG_0
Bits 7:0 “DID”, JESD204A Device ID number.
ADDRESS 0XEE:
ADDRESS 0XE1: JESD204_CONFIG_1
JESD204_UPDATE_CONFIG_COMPLETE
Bits 3:0 “BID”, JESD204 Bank ID.
Bit 0 update_complete
This self-resetting bit is used to indicate that all the modifications
to the JESD204 parameters are complete.
ADDRESS 0XE2: JESD204_CONFIG_2
Bits 4:0 “LID” JESD204A Lane ID.
ADDRESS 0XEF: JESD204_PLL_MONITOR_RESET
ADDRESS 0XE3: JESD204_CONFIG_3
Bit 0 “pll_lock_mon_rst”, This self resetting register resets the
state of the 0xF0 Bit[0] “latched_pll_lockn” bit. The purpose of
this pair of bits is as a debugging feature to the system designer.
The “latched_pll_lockn” bit indicates if the JESD204A transmitter
PLL inside the device has at any time lost lock since the last ‘1’
was written to the “pll_lock_mon_rst” bit. This can be used to
help identify the source of intermittent link lost errors in the
system.
Bit 7 “SCR”, JESD204A SCR controls if scrambling across the
SERDES lane(s) is enabled (‘1’ means enabled).
Bits 4:0 “L”, JESD204A L is the number of SERDES lanes in the
link.
ADDRESS 0XE4: JESD204_CONFIG_4
Bits 7:0 “F”, JESD204A Number of octets per frame period.
ADDRESS 0XE5: JESD204_CONFIG_5
ADDRESS 0XF0: JESD204_STATUS
Bit 2 “op_cfg_wrong” indicates if the JESD204A parameters
(registers 0xE0 through 0xED) are supported by the JESD204A
transmitter (a ‘1’ indicates they are not supported, a ‘0’ indicates
they are supported).
Bits 4:0 “K” JESD204A Number of frame periods per multi-frame
period. This product family supports the full programmable range
of K (decimal 0 through 31), although note that the JESD204A
standard dictates a minimum number for this parameter that is
configuration dependent.
Bit 1“pll_lockn” indicates if the JESD204A transmitter PLL is
currently locked (a ‘1’ indicates it is not locked, a ‘0’ indicates it
is locked).
ADDRESS 0XE6: JESD204_CONFIG_6
Bits 7:0 “M” JESD204A Number of converters per device.
ADDRESS 0XE7: JESD204_CONFIG_7
Bit 0 “latched_pll_lockn” indicates if the JESD204A transmitter
PLL has lost lock since the last assertion of the
“pll_lock_mon_rst” (see register 0xEF description for more
information).
Bits 7:6 “CS”, JESD204A CS is the number of control bits per
sample (Always ‘0’ for this product family).
ADDRESS 0XF1: JESD204_SYNC
Bits 4:0 “N”, JESD204A N is the converter resolution.
ADDRESS 0XE8: JESD204_CONFIG_8
Bit 0 “sync_req” this register provides a SPI-programmable
interface that can be used to assert and de-assert the JESD204A
SYNC~ functionality. Certain systems may benefit from the
elimination of SYNC~ as a separate board-level LVDS signal (and
the power, PCB space, and pins it consumes), and these systems
can use this register to functionally assert and de-assert SYNC~.
Bits 4:0 “N’”, JESD204A N’ is the total number of bits per sample.
ADDRESS 0XE9: JESD204_CONFIG_9
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ISLA216S
For this bit to have any effect, a ‘1’ must have previously been
written to the SYNC_FUNCTION (Address 0x77, bit 0).
different control character when reoccurrence of octets occurs at
the end of a multi-frame.
A ‘1’ written to this bit will result in behavior identical to the
assertion of SYNC~ (comma character generation), and ‘0’ will
result in the behavior identical to the de-assertion of SYNC~
(initial lane alignment sequence followed by converter data).
Usage of this SPI SYNC~ capability may compromise the
system’s ability to perform multi-chip time alignment, as the
SYNC~ asserted to de-asserted transition using this register is
not well timed with respect to sample clock.
Bit 1 “trans_pat_max_len” There is some ambiguity of the proper
length of the JESD204 rev A section 5.1.6.2 required transport
layer test pattern. Specifically, that the description perhaps
should have “max()” in place of “min()” for the equation defining
the length of the pattern. Setting bit 1 in this register to a ‘0’ (also
the power-on default) and issuing this test pattern by writing to
0xC0 will cause the pattern to assume a “min()” interpretation of
the pattern described in section 5.1.6.2. Setting the bit to a ‘1’
will assume a “max()” interpretation of the described pattern.
ADDRESS 0XF2: JESD204_TRANS_PAT_CONFIG
ADDRESS 0XF3: JESD204_CML_POLARITY
Bit 0 “no_mf_lane_sync”, By default, this device family assumes
that both sides of the link support lane synchronization. As per
the JESD204 rev A standard, in this case continuous frame
alignment monitoring via character substitution (section 5.3.3.4)
is modified such that a different control character is substituted
when the octet reoccurrence happens at the end of a multi-
frame. This behavior occurs when bit 0 is ‘0’ (the power on
default). Writing a ‘1’ to bit 0 will inform the JESD204 transmitter
than the receiving device does not support lane synchronization,
and therefore the transmitter will no longer substitute this
0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the
system designer to invert the sense of the SERDES pins on a per
lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to
functionally become LANE0P and LANE0P to become LANE0N.
This feature allows the system designer to avoid having to
crossover P and N sides of the CML pair on the board to match
pin out and layout of the transmitter and receiver. Typically, a
trace crossover would require vias, which can degrade the signal
integrity of the high-speed SERDES lanes.
SPI Memory Map
ADDR.
BIT 7
(MSB)
BIT 0
(LSB)
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
port_config
Reserved
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
00
01
SDO Active LSB First Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
Reserved
02
burst_end
Burst end address [7:0]
Reserved
00h
03-07
Reserved
08
09
chip_id
chip_version
Reserved
Chip ID #
Chip Version #
Reserved
Read only
Read only
0A-0F
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ISLA216S
SPI Memory Map (Continued)
ADDR.
BIT 7
BIT 0
(LSB)
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
Reserved
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
10-1F
20
Reserved
offset_coarse_adc0
offset_fine_adc0
gain_coarse_adc0
gain_medium_adc0
gain_fine_adc0
modes_adc0
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
21
22
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
Reserved
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
26
27
28
29
2A
2B
offset_coarse_adc1
offset_fine_adc1
gain_coarse_adc1
gain_medium_adc1
gain_fine_adc1
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
Reserved
Coarse Gain
Medium Gain
Fine Gain
modes_adc1
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
2C-6F
70
Reserved
skew_diff
phase_slip
Reserved
Differential Skew
Reserved
80h
00h
71
Next Clock
Edge
72
clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
00h
NOT reset by
Soft Reset
Other codes = Reserved
73
74
output_mode_A
output_mode_B
Output Format [2:0]
000 = Two’s Complement (Default) NOT reset by
00h
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
Soft Reset
DLL Range
0 = Fast
1 = Slow
00h
NOT reset by
Soft Reset
Default=’0’
75-76
77
Reserved
SYNC_function
Reserved
Reserved
Clkdivrst
78-B5
B6
Reserved
Reserved
cal_status
Calibration Read Only
Done
B7-BF
Reserved
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ISLA216S
SPI Memory Map (Continued)
ADDR.
BIT 7
BIT 0
(LSB)
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
test_io
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
C0
Output Test Mode [7:4]
JESD Test
User Test Mode [2:0]
User Test Mode (Single ADC products
only)
00h
<7:4>=Output Test, <3> = JESD Test
JESD Test=0
Output Test =
0 = user pattern 1 only
1 = cycle pattern 1 through 2
2 = cycle pattern 1 through 3
3 = cycle pattern 1 through 4
4 = cycle pattern 1 through 5
5 = cycle pattern 1 through 6
6 = cycle pattern 1 through 7
7 = cycle pattern 1 through 8
User Test Mode (Dual and interleaved
ADC products only)
0 = cycle pattern 1 through 2
1 = cycle pattern 1 through 4
2 = cycle pattern 1 through 6
3 = cycle pattern 1 through 8
4 -7 = NA
0x0= Output Test Mode Off. During calibration MSB justified
constant output 0xCCCC
0x1 = Midscale adjusted by numeric format
0x2 = Plus full scale, adjusted by numeric format
0x3 = Minus full scale adjusted by numeric format
0x4 = Checkboard output - 0xAAAA, 0x5555
0x5 = reserved
0x6 = reserved
0x7 = 0xFFFF, 0x0000 all on pattern
0x8 = User pattern 8 deep, MSB justified with output
0x9 = reserved
0xA, Count-up ramp
0xB, PRBS-9
0xC, PRBS-15
0xD, PRBS-23
0xE, PRBS-31
0xF = reserved
JESD Test=1
Output Test =
0x0 =Link Layer Repeat K28.5+Lane Alignment Sequence
0x1, Link Layer Repeat K28.5
0x2, Link Layer Repeat D21.5
0x3, Link Layer Repeat K28.7
0x4, Link Layer PRBS-7
0x5, Link Layer PRBS-23
0x6, Link Layer All Zeros
0x7, Link Layer All Ones
0x8-0xE, reserved
0xF, JESD204A section 5.1.6.2 Transport Layer Test Pattern
C1
C2
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
user_patt3_lsb
user_patt3_msb
user_patt4_lsb
user_patt4_msb
user_patt5_lsb
user_patt5_msb
user_patt6_lsb
user_patt6_msb
user_patt7_lsb
user_patt7_msb
user_patt8_lsb
user_patt8_msb
Reserved
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
C3
C4
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C5
C6
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C7
C8
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C9
CA
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CB
CC
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CD
CE
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CF
D0
D1-DE
B15
B14
B13
B12
B11
B10
Reserved
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29
ISLA216S
SPI Memory Map (Continued)
ADDR.
BIT 7
BIT 0
(LSB)
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
DF
JESD204_update_config_start
update_
start
00h
E0
E1
E2
E3
E4
E5
E6
E7
JESD204_config_0
JESD204_config_1
JESD204_config_2
JESD204_config_3
JESD204_config_4
JESD204_config_5
JESD204_config_6
JESD204_config_7
DID (Device ID Number)
00h
BID (Bank ID Number)
LID (Lane ID Number)
L (Number of Lanes per Device)
F (Number of Octets per Frame)
K (Number of frames per multi-frame)
M (Number of Converters per Device)
SCR
CS (Number of Control
N (Converter Resolution in bits)
bits per Sample)
E8
E9
EA
EB
EC
ED
EE
JESD204_config_8
JESD204_config_9
JESD204_config_10
JESD204_config_11
JESD204_config_12
JESD204_config_13
N’ (Total number of bits per Sample)
S (Number of Samples per Converter per Frame)
HD
CF (Number of Control Words per Frame per Link)
RES1
RES2
FCHK (Checksum)
JESD204_update_config_compl
ete
update_
complete
00h
00h
00h
EF
F0
JESD204_PLL_monitor_reset
pll_lock_
mon_rst
JESD204_status
op_confg_ pll_lockn latched_
wrong
pll_lockn
F1
F2
JESD204_sync
sync_req
JESD204_trans_pat_config
trans_pat_ no_mf_
max_len lane_sync
F3
JESD204_CML_polarity
Reserved
lane_2_
polarity
lane_1_
polarity
lane_0_
polarity
00h
F4-FF
Reserved
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ISLA216S
Equivalent Circuits
AVDD
AVDD
AVDD
TO
CSAMP
CLOCK-PHASE
GENERATION
4pF
TO
CHARGE
PIPELINE
INP
INN
CLKP
AVDD
E2
E3
E3
E1
600
AVDD
11k
11k
CSAMP
4pF
18k
TO
CHARGE
PIPELINE
E2
E1
18k
AVDD
CLKN
FIGURE 48. ANALOG INPUTS
FIGURE 49. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
75k
OVDD
AVDD
TO
SENSE
LOGIC
75k
280
OVDD
20k
INPUT
INPUT
TO
LOGIC
280
75k
75k
FIGURE 50. TRI-LEVEL DIGITAL INPUTS
FIGURE 51. DIGITAL INPUTS
OVDD
OVDD
50
50
LANE[2:0]P
LANE[2:0]N
AVDD
OVDD
VCM
+
1.0V
–
DATA
DATA
16mA
FIGURE 53. VCM_OUT OUTPUT
FIGURE 52. CML OUTPUTS
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31
ISLA216S
importance of maintaining an open eye to achieve low BER,
ADC Evaluation Platform
signal integrity simulations are recommended, especially when
the data lane rate exceeds 3Gbps and/or the trace or cable
length between the ADC and the reciever gets larger than 20cm.
Intersil offers ADC Evaluation platforms which can be used to
evaluate any of Intersil’s high speed ADC products. Each platform
consists of a FPGA based data capture motherboard and a family
of ADC daughtercards. The USB interface and evaluation
platform control software allow a user to quickly evaluate the
ADC’s performance at a user’s specific application frequency
requirements. More information is available at
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal ADC
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Definitions
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Bypass and Filtering
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins, as longer traces
between the ceramic bypass capacitors and the device pins will
increase inductance, which can result in diminished dynamic
performance. Best practices bypassing is especially important on
the AVDD and OVDD(PLL) power supply pins. Whenever possible,
each supply pin should have its own 0.1uF bypass capacitor.
Make sure that connections to ground are direct and low
impedance. Avoid forming ground loops.
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
ADC’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
CML Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
short, and minimize bends and vias where possible. Avoid
crossing ground and power-plane breaks with signal traces. Keep
good clearance (at least 5 trace widths) between the SERDES
traces and other signals. Given the speed of these outputs and
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
N
V
/(2 - 1) where N is the resolution in bits.
FS
FN7996.0
February 2, 2012
32
ISLA216S
Missing Codes are output codes that are skipped and will never
appear at the ADC output. These codes cannot be reached with
any input value.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the ADC FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7996.0
CHANGE
February 2, 2012
Initial Release
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISLA216S13, ISLA216S20, ISLA216S25.
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7996.0
February 2, 2012
33
ISLA216S
Package Outline Drawing
L48.7x7G
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 1/10
6
4X
5.5
7.00
A
PIN #1
INDEX
AREA
6
B
37
48
PIN 1
INDEX AREA
36
1
44X 0.50
EXP. DAP
5.70 SQ.
12
25
0.15
(4X)
24
13
48X 0.40
48x 0.20
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
1.00 MAX
C
C
0.10
0.08 C
SEATING PLANE
( 44X 0 . 5 )
6 .80 SQ
SIDE VIEW
5.70 SQ
0 . 2 REF
5
C
( 48X 0 . 20 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7996.0
February 2, 2012
34
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