ISL98012IUZ [INTERSIL]
1.8V Input PWM Step-Up Regulator; 1.8V输入电压PWM升压调节器
| 型号： | ISL98012IUZ |
| 厂家： | 
Intersil |
| 描述： | 1.8V Input PWM Step-Up Regulator |
| 文件： | 总10页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL98012
®
Data Sheet
October 15, 2008
FN6654.0
1.8V Input PWM Step-Up Regulator
Features
The ISL98012 is a high frequency, high efficiency step-up
DC/DC regulator operated in fixed frequency PWM mode.
With an integrated 1.4A MOSFET, it can deliver up to 600mA
output current at up to 92% efficiency. The adjustable
switching frequency is up to 750kHz, making it ideal for
common boost applications.
• Up to 92% Efficiency
• Up to 600mA I
OUT
< 17V
• 4.5V < V
OUT
• 1.8V < V < 13.2V
IN
• Up to 750kHz Adjustable Frequency
• <1µA Shutdown Current
• Adjustable Soft-Start
When shut down, it draws <1µA of current. This feature,
along with the minimum starting voltage of 1.8V, makes it
suitable for portable equipment powered by 1 Lithium Ion, 3
to 4 NiMH cells, or 2 cells of alkaline battery.
• Low Battery Detection
The ISL98012 is available in a 10 Ld MSOP package, with a
maximum height of 1.1mm. With proper external
components, the whole converter takes less than 0.25in
• Internal Thermal Protection
2
• 1.1mm Max Height 10 Ld MSOP Package
• Pb-Free (RoHS compliant)
PCB space.
This device is specified for operation over the full -40°C to
+85°C temperature range.
Applications
• 1.8V to 15V Converters - OLED
• 5V to 12V Converters
• 3V to 5V and 3V to 12V Converters
• TFT-LCD
Pinout
ISL98012
(10 LD MSOP)
TOP VIEW
PGND
SGND
RT
LX
1
2
3
4
5
10
9
• Portable Equipment
VDD
FB
Ordering Information
8
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EN
SS
7
LBI
LBO
6
ISL98012IUZ
98012
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
MDP0043
MDP0043
MDP0043
ISL98012IUZ-T* 98012
ISL98012IUZ-TK* 98012
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL98012
Typical Application
L
1
D
1
V
OUT
V
IN
(1.8V TO 9V)
(15V UP TO
200mA)
C
R
10µH
5
C
4
1
5k
22µF
10µF
1
2
3
4
5
PGND
SGND
RT
LX 10
C
4
0.1µF
VDD
9
8
7
6
R
2
R
3
113kΩ
FB
SS
R
C
1
10
C
56kΩ
3
10kΩ
4.7nF
EN
1.8V TO 12V
EN
20nF
LBI
LBO
FN6654.0
October 15, 2008
2
ISL98012
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
FB, SS, RT, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, 6.5V
LX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +18V
VDD, EN, LBI, LBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +12V
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
152
JA
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature: . . . . . . . . . . . . . . . . . . . . . +135°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Operating Conditions
Maximum Operating Frequency. . . . . . . . . . . . . . . . . . . . . . .750kHz
Minimum Operating Frequency . . . . . . . . . . . . . . . . . . . . . . .380kHz
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
.
Electrical Specifications
V
= 5V, V
OUT
= 12V, L = 10µH, I
= 0mA, R = 56kΩ, T = +25°C, Unless Otherwise Specified.
IN
OUT
T
A
PARAMETER
DESCRIPTION
Input Voltage Range
CONDITIONS
MIN
1.8
TYP
MAX
13.2
17
UNIT
V
V
V
R
must ensure V
≤ 12V
DD
IN
4
Output Voltage Range
Quiescent Current - Shut-down
Quiescent Current
Note 2
4.5
V
OUT
IQ1
IQ2
V
V
= 0, feedback resistors disconnected
= 2V, Continuous operation
1
µA
mA
V
EN
EN
1.4
2
V
Feedback Voltage
1.29
1.33
1.37
0.10
FB
I
Feedback Input Bias Current
Maximum Duty Cycle
Current Limit - Max Peak Input Current
Enable Input Bias Current
LBI Threshold Voltage
LBO Output Low
0 < V < 1.5V
FB
µA
%
FB
D
89.5
1
92
MAX
I
I
1.4
A
LIM
EN
1
250
0.2
2
µA
mV
V
V
V
180
220
0.1
LBI
I
= 1mA
OL-LBO
LEAK-LBO
LBO
I
LBO Output Leakage Current
Switch On Resistance
Switch Leakage Current
Line Regulation
V
= 250mV, V
= 5V
0.02
220
µA
mΩ
µA
%/V
%
LBI
LBO
R
At 12V output
LX = 18V
DS(ON)
I
1
LEAK-SWITCH
ΔV
ΔV
/ΔV /V
OUT IN OUT
3V < V < 6V, V
IN
= 12V, no load
0.4
1
OUT
/V
OUT OUT
Load Regulation
I
= 50mA to 150mA
OUT
I
Soft Start Current
0 < V < 0.1V
12
µA
V
SS
SS
V
Voltage at R for Bias Current
T
R
R
= 56kΩ
= 56kΩ
1.34
670
RT
T
f
Switching Frequency
600
1.6
750
0.5
kHz
V
OSC1
T
VHI_EN
VLO_EN
EN Input High Threshold
EN Input Low Threshold
V
NOTE:
2. Minimum V
of 4.5V is tested with V = 1.8V.
IN
OUT
FN6654.0
October 15, 2008
3
ISL98012
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
2
3
PGND
SGND
RT
Power ground; connected to the source of internal N-Channel power MOSFET
Signal ground; ground reference for all the control circuitry; needs to have only a single connection to PGND
Timing resistor to adjust the oscillation frequency of the converter. Resistor value on RT pin determines
frequency. Range varies from R = 49.9kΩ for 750kHz and R = 100kΩ for 380kHz
T
T
4
5
6
7
EN
LBI
LBO
SS
Chip enable; connects to logic HI (>1.6V) for chip to function
Low battery input; connects to a sensing voltage, or connect to GND if function is not used
Low battery detection output; connected to the open drain of a MOSFET; able to sink 1mA current
Soft-start; connects to a capacitor to control the start-up of the converter. During start-up, V controls the
SS
current limit and hence the in-rush current.
8
9
FB
VDD
LX
Voltage feedback input; needs to connect to resistor divider to decide V
Control circuit positive supply
O
10
Inductor drive pin; connected to the drain of internal N-Channel power MOSFET
Block Diagram
V
= 15V
OUT
10µA
113k
V
IN
5kΩ
0.1µF
10kΩ 4.7nF
22µF
10µF
FB
V
LX
DD
THERMAL
SHUT-DOWN
MAX_DUTY
R
T
REFERENCE
GENERATOR
56kΩ
V
REF
PWM
LOGIC
PWM
COMPARATOR
0.2Ω
V
RAMP
EN
LBO
12µA
LBI
-
-
START-UP
OSCILLATOR
+
+
I
LOUT
80mΩ
7.2kΩ
220mV
SGND
SS
PGND
20nF
FN6654.0
October 15, 2008
4
ISL98012
Typical Performance Curves
92
90
88
86
84
82
80
90
80
V
@ 1.8V
IN
V
@ 3.3V
IN
70
60
0
50
100
150
(mA)
200
250
300
0
100 200 300 400 500 600 700
(mA)
I
I
OUT
OUT
FIGURE 1. EFFICIENCY vs I
, V = 15V
FIGURE 2. EFFICIENCY vs I
, V = 3.3V, V = 5V
OUT IN
OUT
O
O
94
92
90
88
86
84
82
80
78
1.6
V
= 10V, V = 12V TO 17V
O
DD
CONTINUOUS MODE
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0
100
200
300
(mA)
400
500
600
300
400
500
600
700
800
I
FREQUENCY (kHz)
OUT
FIGURE 3. EFFICIENCY vs I
, V = 5V, V = 12V
OUT IN
FIGURE 4. I
vs F
DD S
O
80
70
60
50
40
30
R
R
= 51.1kΩ
T
T
V
= 10V
DD
750
= 71.5kΩ
R
R
= 100kΩ
= 200kΩ
T
T
200
0
40
60
80
R (kΩ)
100
120
5
6
7
8
9
10
11
12
V
(V)
DD
FIGURE 5. F vs V
S
FIGURE 6. F vs R
S T
DD
FN6654.0
October 15, 2008
5
ISL98012
Typical Performance Curves (Continued)
OUTPUT RIPPLE
INPUT RIPPLE
OUTPUT RIPPLE
INPUT RIPPLE
LX
LX
ILX
ILX
FIGURE 7. STEADY STATE OPERATION (INDUCTOR
FIGURE 8. STEADY STATE OPERATION (INDUCTOR
CONTINUOUS CONDUCTION), V = 3.3V,
DISCONTINUOUS CONDUCTION), V = 3.3V,
IN
IN
V
= 15V, I < 1mA
O
V
= 15V, I = 30mA
O O
O
ΔV
50mV/DIV
10V/DIV
ΔV
50mV/DIV
IN
IN
V
LX
10V/DIV
V
LX
20mV/DIV
ΔV
O
ΔV
20mV/DIV
0.5A/DIV
O
I
L
I
0.5A/DIV
L
1.0µs/DIV
1.0µs/DIV
FIGURE 9. STEADY STATE OPERATION (INDUCTOR
DISCONTINUOUS CONDUCTION), V = 5V,
FIGURE 10. STEADY STATE OPERATION (INDUCTOR
CONTINUOUS CONDUCTION), V = 5V,
IN
IN
V
= 12V, I = 30mA
V = 12V, I = 300mA
O O
O
O
2V/DIV
5V/DIV
ΔV
IN
V
ILX
O
0.5A/DIV
I
L
0.5ms/DIV
FIGURE 11. POWER-UP, V = 3.3V, V = 15V, I = 30mA
IN
FIGURE 12. POWER-UP, V = 5V, V = 12V, I = 300mA
IN
O
O
O
O
FN6654.0
October 15, 2008
6
ISL98012
Typical Performance Curves (Continued)
I
100mA/DIV
0.5V/DIV
O
O
OUTPUT LOAD CURRENT
ΔV
0.2ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE 10mA TO 30mA,
FIGURE 14. LOAD TRANSIENT RESPONSE, V = 5V,
IN
V
= 1.8V, FREQ = 56.2k, V = 15V,
V = 12V, I = 50mA TO 300mA
IN
= 10mA TO 30mA
O
O O
I
O
10mV/DIV
10mV/DIV
FIGURE 15. OUTPUT RIPPLE, V = 1.8V, V = 15V, I = 30mA
FIGURE 16. OUTPUT RIPPLE, V = 3.3V, V = 15V, I = 30mA
IN
IN
O
O
O
O
Soft-start is provided by ramping up the current limit
comparator. An internal 12µA current source charges the
external CSS capacitor. The peak MOSFET current is limited
by the voltage on this capacitor. This in turn controls the
rising rate of the output voltage.
Applications Information
The ISL98012 is a fixed frequency step-up pulse-width
modulation (PWM) regulator. The input voltage range is 1.8V
to 13.2V and output voltage range is 4.5V to 17V. The
switching frequency (up to 750kHz) is decided by the
resistor connected to RT pin.
The regulator goes through the same start-up sequence as
well after the EN signal is pulled to HI.
Start-Up
Steady-State Operation
During start-up, as V
DD
reaches a threshold of about 1.6V, a
start-up oscillator generates a fixed duty-ratio of 0.5 to 0.7 at
a frequency of several hundred kHz. This will boost the
output voltage.
When the output reaches the preset voltage, the regulator
operates in steady state. Depending on the input/output
conditions and component values, the inductor operates in
either continuous-conduction mode or discontinuous-conduction
mode.
When V
reaches about 3.7V, the PWM comparator takes
DD
over control. The duty ratio will be decided by the least of the
multiple-input direct summing comparator, the Max_Duty
signal (about 92% duty-ratio), or the Current Limit
Comparator.
In continuous-conduction mode, inductor current is a
triangular waveform and LX voltage a pulse waveform. In
discontinuous-conduction mode, inductor current has
FN6654.0
October 15, 2008
7
ISL98012
completely dried out before the MOSFET is turned on again.
The inductor has peak and average current decided by
Equations 4 and 5:
The input voltage source, the inductor, and the MOSFET and
output diode parasitic capacitors form a resonant circuit.
Oscillation will occur in this period. This oscillation is normal
and will not affect regulation.
ΔI
L
(EQ. 4)
--------
I
I
= I
+
LPK
LAVG
2
I
O
(EQ. 5)
-------------
=
At very low load, the MOSFET will skip pulses sometimes;
this is normal.
LAVG
1 – D
The inductor should be chosen to handle this current.
Furthermore, due to fixed internal compensation, it is
recommended that maximum inductance of 10µH and 15µH
be used in the 5V and 12V or higher output voltage,
respectively.
Current Limit
The MOSFET current limit is nominally 1.4A and guaranteed
1A. This restricts the maximum output current I
on Equation 1:
based
OMAX
ΔI
V
IN
V
O
L
⎛
⎝
⎞
⎠
(EQ. 1)
The output diode has an average current of I and peak
O
--------
---------
I
=
1 –
×
OMAX
2
current is the same as the inductor's peak current. A
Schottky diode is recommended and it should be able to
handle those currents.
where:
• ΔI is the inductor peak-to-peak current ripple and is
decided by Equation 2:
L
The output voltage ripple can be calculated as Equation 6:
I
× D
V
O
D
f
S
IN
(EQ. 6)
---------------------
(EQ. 2)
ΔV
=
+ I
× ESR
LPK
--------- ----
ΔI
=
×
O
L
F
× C
O
L
S
• D is the MOSFET turn-on ratio and is decided by
Equation 3:
Where:
• C is the output capacitance.
O
V
– V
IN
O
(EQ. 3)
-----------------------
D =
• The ESR is the output capacitor ESR value.
V
O
Low ESR capacitors should be used to minimize output
voltage ripple. Multilayer ceramic capacitors (X5R and X7R)
are preferred for output capacitors since they have a low
ESR and small packages. Tantalum capacitors also can be
used, but they take more board space and have higher ESR.
A minimum of 22µF output capacitor is sufficient for high
output current application. For lower output current, the
output capacitor can be smaller, like 4.7µF. The capacitor
should always have enough voltage rating. In addition to the
voltage rating, the output capacitor should also be able to
handle the RMS current, which is given by Equation 7:
• f is the switching frequency
S
Table1 gives typical values:
TABLE 1. MAX CONTINUOUS OUTPUT CURRENTS
V
V
L
f
I
IN
O
S
OMAX
(mA)
(V)
(V)
(µH)
(kHz)
750
750
750
750
750
750
750
750
750
750
2
5
10
10
10
10
10
10
10
10
10
10
360
190
140
600
310
230
470
340
630
670
2
9
2
12
5
3.3
3.3
3.3
5
2
⎛
⎞
⎟
⎟
⎠
ΔI
1
12
L
(EQ. 7)
⎜
9
------------------- ------
I
=
(1 – D) × D +
×
× I
CORMS
LAVG
⎜
⎝
2
I
LAVG
12
9
Output Voltage
5
12
12
15
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. The current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network less than 300kΩ is recommended.
9
12
Component Considerations
It is recommended that C is larger than 10µF.
IN
Theoretically, the input capacitor has a ripple current of ΔI .
L
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. A larger capacitor
will reduce the ripple further.
FN6654.0
October 15, 2008
8
ISL98012
The boost converter output voltage is determined by the
relationship in Equation 8:
Layout Considerations
The layout is very important for the converter to function
properly. power ground ( ) and signal ground ( ) should
be separated to ensure that the high pulse current in the
power ground never interferes with the sensitive signals
connected to signal ground. They should only be connected
at one point.
R
⎛
⎞
⎟
⎠
2
(EQ. 8)
------
V
= V × 1 +
⎜
OUT
FB
R
1
⎝
where V slightly changes with V
FB
.
DD
RC Filter
The trace connected to pin 8 (FB) is the most sensitive trace.
It needs to be as short as possible and in a “quiet” place,
preferably between PGND or SGND traces.
The maximum voltage rating for the VDD pin is 12V. An RC
filter is recommended to clean the output ripple before
bootstrapping the part. For bootstrapped applications with
In addition, the bypass capacitor connected to the VDD pin
needs to be as close to the pin as possible.
V
greater than 10V, R can drop V
OUT
for coupling into
OUT
4
the VDD pin and is given by Equation 9:
The heat of the chip is mainly dissipated through the SGND
pin. Maximizing the copper area around it is preferable. In
addition, a solid ground plane is always helpful for the EMI
performance.
V
– 10
O
I
(EQ. 9)
--------------------
R
=
4
DD
where I
is shown in the I vs f curve. Otherwise, R
DD S 4
DD
can be 10Ω to 51Ω with C = 0.1µF.
4
The demo board is a good example of layout based on these
principles. Please refer to the ISL98012 Technical Brief for
the layout. http://www.intersil.com/data/tb/tb429.pdf
Thermal Performance
The ISL98012 uses a fused-lead package, which has a
reduced θ of +100°C/W on a four-layer board and
JA
+115°C/W on a two-layer board. Maximizing copper around
the ground pins will improve the thermal performance.
This chip also has internal thermal shut-down set at around
+135°C to protect the component.
FN6654.0
October 15, 2008
9
ISL98012
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3¬¨¬®¬
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6654.0
October 15, 2008
10
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