ISL97652IRZ-T [INTERSIL]
4-Channel Integrated LCD Supply with Dual VCOM Amplifiers; 四通道集成LCD电源与双VCOM放大器
| 型号： | ISL97652IRZ-T |
| 厂家： | 
Intersil |
| 描述： | 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers |
| 文件： | 总25页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97652
®
Data Sheet
December 21, 2006
FN9287.0
4-Channel Integrated LCD Supply with
Dual V Amplifiers
Features
COM
• 8V to 15V input supply
The ISL97652 represents a high power, integrated LCD
supply IC targeted at large panel LCD displays. The
ISL97652 integrates a high power, boost converter for A
• A
VDD
2.8APEAK FET
boost up to 19.5V (OVP threshold), with integrated
VDD
charge
• Overvoltage protection (OVP)
generation, delay switch, regulated V
and V
OFF
ON
slicing circuitry, a buck regulator for logic supply
pumps, V
• 2A integrated A
delay FET, with short circuit protection
• Dual charge pump controllers for V and V
ON
VDD
generation and dual high power V
amplifiers.
COM
ON
buck with integrated 2.5APEAK FET
OFF
Operating at 650kHz or 1.3MHz, the A
boost converter
VDD
• V
• V
LOGIC
features a 2.8A boost FET. A short circuit protected A
VDD
delay switch is integrated to provide sequencing of the A
slicing
ON
VDD
output. Feedback is taken from the far side of the delay FET
for improved regulation and an OVP circuit protects output
side components. The boost features programmable
soft-start.
• Dual high speed V
amplifiers
COM
• 650kHz/1.3MHz switching frequency
• Integrated sequencing
The asynchronous buck converter features an integrated
2.5A FET. It also operates from the 650kHz or 1.3MHz
internal clock and features separate enable and soft-start
control.
• UVLO and OTP protection
• Thermally enhanced 7x7 QFN package
• Pb-free plus anneal available (RoHS compliant)
The dual charge pump controllers used for V
and V
OFF
ON
switching frequency to allow
Applications
generation uses the full F
OSC
the use of small output components for board space
efficiency. V is further processed through an integrated
• LCD-TVs (up to 40”)
• Industrial/medical LCD displays
ON
circuit for reduced flicker.
V
ON-SLICE
Pinout
The integrated amplifiers feature high slew-rate and high
output current capability. They are permanently enabled
when AVIN is present.
ISL97652
(48 LD QFN)
TOP VIEW
Available in the 48 Ld 7mmx7mm QFN package, the
ISL97652 is specified for ambient operation over the
-40°C to +85°C temperature range.
POS1
OUT1
VGL
1
2
3
4
5
6
7
8
9
36 PGND3
35 PGND2
34 PGND1
33 EN1
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TAPE &
REEL
PACKAGE
(Pb-Free)
PKG.
DWG. #
CE
ISL97652IRZ
ISL97652IRZ
-
48 Ld 7x7 QFN L48.7x7
48 Ld 7x7 QFN L48.7x7
VFLK
VDPM
RE
32 EN2
THERMAL
PAD
31 VC
ISL97652IRZ-T ISL97652IRZ
13”
(4k pcs)
30 SS
VGHM
VGH
29 DLY2
28 FREQ
27 VDC
ISL97652IRZ-TK ISL97652IRZ
13”
(1k pcs)
48 Ld 7x7 QFN L48.7x7
FBP 10
GND 11
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
26 PVIN2
25 PVIN1
12
DRVP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL97652
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Maximum Pin Voltages, All Pins Except Below . . . . . . . -0.3 to 6.5V
SW, SUP, DRVP, DRVN, SUI, SWO, AVIN, POS1, NEG1, OUT1,
POS2, NEG2, OUT2, VGL . . . . . . . . . . . . . . . . . . -0.3 to 22V
SWI,SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 24V
SUI . . . . . . . . . . . . . . . . . . . . . . . V(SWI) - 6.5V to V(SWI) +0.3V
PVIN, SWB, VFLK, VDPM, EN1, EN2, FREQ . . . . . -0.3 to 15.5V
VGH, VGHM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 36V
Thermal Resistance
θ
(°C/W)
26
θ
(°C/W)
1.5
JA
JC
7x7 QFN Package (Notes 1, 2) . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Power Dissipation
T
≤ +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.7W
= +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W
= +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W
A
T
A
T
Recommended Operating Conditions
A
Input Voltage Range, V . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 15V
IN
Boost Output Voltage, A
. . . . . . . . . . . . . . . . . . . . . . . . . . +15V
VDD
V
V
Output Range, V
. . . . . . . . . . . . . . . . . . . . . . +15V to +32V
. . . . . . . . . . . . . . . . . . . . . . .-15V to -5V
OFF
ON
ON
Output Range, V
OFF
Logic Output Voltage Range, V
. . . . . . . . . . . . +1.5V to +3.3V
LOGIC
Input Capacitance, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2x10µF
IN
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH
Output Capacitance, C
. . . . . . . . . . . . . . . . . . . . . . . . . .2x22µF
OUT
Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH
Operating Ambient Temperature Range . . . . . . . . . -40°C to +85°C
Operating Junction Temperature Range . . . . . . . . -40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of
the device even before +150°C, since this number is specified as typical.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 12V, V
= V
= 15V, V
ON
= 25V, V = -8V, over temperature from -40°C to +85°C, unless
OFF
IN
BOOST
SUP
otherwise stated.
PARAMETER
SUPPLY PINS
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
PV
Supply Voltage
Charge Pumps Positive Supply
Positive Supply
8
8
12
15
20
30
20
6
V
V
IN
V
SUP
VGH
AVIN
V
8
V
ON-SLICE
Op-AmpV Positive Supply
Quiescent Current into PV
4.5
V
PI
Enabled, no switching
Disabled
3
mA
µA
mA
VIN
IN
0.5
5
I
V
Supply Current
Enabled, no switching and
0.5
SUP
SUP
VP
= V
OUT
Disabled
For AVIN range
= +25°C
SUP
5
µA
mA
V
I
A
Supply Current
7
AVIN
VIN
V
Reference Voltage
T
1.252
1.240
1100
550
1.265
1.265
1300
650
1.278
1.290
1500
750
REF
A
V
F
Oscillator Frequency for Buck, Boost, V
FREQ = V
IN
kHz
kHz
OSC
ON
and V
Functions
OFF
FREQ = GND
A
BOOST
VDD
I
Boost Switch Peak Current
Peak Efficiency
Boost Peak Current limit
2.8
A
BOOST
EFF
See graphs and component
recommendations
91
%
BOOST
FN9287.0
December 21, 2006
2
ISL97652
Electrical Specifications
V
= 12V, V
= V
= 15V, V
ON
= 25V, V = -8V, over temperature from -40°C to +85°C, unless
OFF
IN
BOOST
SUP
otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
125
MAX
UNIT
mΩ
%
r
Switch On Resistance
200
DS(ON)
ΔV
/ΔV
BOOST
Line Regulation
Vin = 8V to 12V at Iload=200mA,
see “Typical Performance
Curves” on page 6
0.08
IN
ΔV
/ΔI
BOOST OUT
Load Regulation
100mA to 500mA, see “Typical
Performance Curves” on page 6
0.5
%
V
Boost Feedback Voltage
T
= +25°C
1.252
1.240
1.265
1.265
90
1.278
1.290
V
V
FB
A
Dmax_boost
Dmin_boost
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
FOSC = 650kHz
FOSC = 1.3MHz
FOSC = 650kHz
FOSC = 1.3MHz
%
%
%
%
85
10
20
A
DELAY SWITCH
VDD
R
R
180
240
mΩ
V
PD
DS(ON)
SWI
Maximum SWI Voltage
21
MAX
IdelayFET
FETtimeout
Ipull-Down
Delay FET RMS Current Limit
Delay FET Fault Timeout
1.5
2
A
I(SWO) > IdelayFET
100
65
µs
µA
Pull-down Current Applied to FET Gate and
SUI
V
SUI Voltage When Switch is Fully Switched On
SWI Leakage Current When Disabled
V(SWI) - 5
V
GATE
SWI
V
= 15V, SWI = 21V, SWO = 0V,
1
µA
LEAK
IN
EN1 = EN2 = 0V
VDS
VDS
Drain Source Voltage When Boost is Enabled SWI =16.5V
15.7
1.4
V
V
OK
Hysteresis on VDS
Spec
SWI =16.5V
HYS
OK
V
BUCK
LOGIC
I
Buck Switch Current
Peak Efficiency
Current limit
2.5
A
BUCK
EFF
BUCK
See graphs and component
recommendations
85
%
R
Switch On Resistance
Line Regulation
170
250
mΩ
DS(ON) BK
ΔV
/ΔV
BUCK
Vin = 8V to 12V at Iload = 200mA,
see “Typical Performance
Curves” on page 6
0.05
%
IN
ΔV
/ΔI
BUCK OUT
Load Regulation
200mA to 1000mA, see “Typical
Performance Curves” on page 6
0.1
%
V
FBL Regulation Voltage
Buck Maximum Duty Cycle
Buck Minimum Duty Cycle
) CHARGE PUMP
T
= +25°C
1.252
1.240
1.265
1.265
90
1.278
1.290
V
V
FBB
A
Dmax_buck
Dmin_buck
F
F
F
F
= 650kHz
= 1.3MHz
= 650kHz
= 1.3MHz
%
%
%
%
OSC
OSC
OSC
OSC
85
10
20
NEGATIVE (V
OFF
V
V
Output Voltage Range
1X Charge Pump
>5V
V
+ 1.4V
0
V
OFF
OFF
SUP
ILoad_NCP_min External Load Driving Capability
V
30
mA
SUP
FN9287.0
December 21, 2006
3
ISL97652
Electrical Specifications
V
= 12V, V
= V
= 15V, V
ON
= 25V, V = -8V, over temperature from -40°C to +85°C, unless
OFF
IN
BOOST
SUP
otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
11
UNIT
Ω
Ron(DRVN)H
RON(DRVN)L
Ipu(DRVN)lim
Ipd(DRVN)lim
I(DRVN)leak
High-Side Driver ON Resistance at DRVN
Low-Side Driver ON Resistance at DRVN
Pull-Up Current Limit in DRVN
Pull-Down Current Limit in DRVN
Leakage Current in DRVN
I(DRVN) = +60mA
I(DRVN) = -60mA
10
Ω
V(DRVN) = 0V to V(SUP)-0.5V
V(DRVN) = 0.36V to V(VSUP)
V(FBN) < 0 or EN1 = LOW
60
270
mA
mA
µA
V
-200
-60
2
-2
V
FBN Regulation Voltage
T
= +25°C
0.48
0.47
0.5
0.5
50
0.52
0.53
FBN
A
V
D_NCP_max
Rpd(FBN)off
Max Duty Cycle of the Negative Charge Pump
Pull-Down Resistance, Not Active
%
I(FBN) = 500µA
2.5
3.5
4.5
34
kΩ
POSITIVE (V ) CHARGE PUMP
ON
V
V
Output Voltage Range
2X or 3X charge pump
V + 2V
SUP
V
mA
Ω
ON
ON
ILoad_PCP_min External Load Driving Capability
30
Ron(DRVP)H
Ron(DRVP)L
Ipu(DRVP)lim
Ipd(DRVP)lim
I(DRVP)leak
High-Side Driver ON Resistance at DRVP
Low-Side Driver ON Resistance at DRVP
Pull-Up Current Limit in DRVP
I(DRVP) = +60mA
11
10
I(DRVP) = -60mA
Ω
V(DRVP) = 0V to V(SUP)-0.5V
V(DRVP) = 0.36V to V(VSUP)
60
-2
270
mA
mA
µA
Pull-Down Current Limit in DRVP
Leakage Current in DRVP
-200
-60
2
VFBP > VREF or EN1 or EN2 =
low
V
FBP Regulation Voltage
T
= +25°C
1.225
1.22
1.25
1.25
50
1.275
1.28
V
V
FBP
A
D_PCP_max
LOGIC INPUTS
VHI
Max Duty Cycle of the Positive Charge Pump
%
Logic “HIGH”
EN1, EN2, VFLK, VDPM
EN1, EN2, VFLK, VDPM
2.0
V
V
VLO
Logic “LOW”
0.8
25
IL_pd
Logic Pin Pull-Down Current
V
> VLO
µA
LOGIC
V
SLICE
ON
VGH
VGH Voltage
8
30
V
µA
µA
V
I
VGH Input Current
VFLK = 0, RE=33K
300
40
VGH
VFLK = 5V, RE=33K
VGL
VGL Voltage
3
VGH - 2
I
VGL Input Current
VGH to VGH_M On Resistance
DELAY Time
-2
0.1
15
10
2
µA
Ω
VGL
R
30
ONVGH
T
CE = 470pF
µs
DEL
VCOM AMPLIFIERS
Icont Maximum Continuous Current Per Amplifier
50
mA
V
V
Supply Voltage
4.5
20
SAMP
I
Supply Current per amplifier
Offset Voltage
3
3
0
mA
mV
nA
V
SAMP
V
20
OS
I
Noninverting Input Bias Current per amplifier
Common Mode Input Voltage Range
150
B
CMIR
0
AVIN
FN9287.0
December 21, 2006
4
ISL97652
Electrical Specifications
V
= 12V, V
= V
= 15V, V
= 25V, V = -8V, over temperature from -40°C to +85°C, unless
OFF
IN
BOOST
SUP
ON
otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
50
TYP
70
MAX
UNIT
dB
CMRR
PSRR
VOH
VOH
VOL
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
70
85
dB
Output Voltage Swing High
Output Voltage Swing High
Output Voltage Swing Low
Output Voltage Swing Low
Output Short Circuit Current per amplifier
Slew Rate
I
I
I
I
= 5mA
AVIN - 50
AVIN - 450
50
mV
mV
mV
mV
mA
V/µs
MHz
OUT(SOURCE)
OUT(SOURCE)
= 50mA
= 5mA
OUT(SINK)
OUT(SINK)
VOL
= 50mA
450
I
300
400
SC
SR
50
BW
Gain Bandwidth
-3dB gain point
AVDD rising
30
FAULT DETECTION THRESHOLDS
OVP
OVP
Overvoltage Protection Threshold
18.8
7.4
19.5
0.8
20
V
V
Overvoltage Protection Threshold Hysteresis
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
Thermal Shut-Down
HYS
PV rising
IN
7.8
8.0
V
VLOR
VLOF
PV falling
IN
7.6
V
T
T
Temperature rising
150
100
1.14
1.14
1.14
0.525
64
°C
°C
V
OFF
Reset after Thermal Shut-Down
Temperature falling
ON
Vth_A
Vth_V
(FB)
A
Boost Short Detection
V(FBFBB) falling less than
V(FBB) falling less than
V(FBP) falling less than
V(FBN) rising more than
VDD
VDD
(FBB) V
Buck Short Detection
V
LOGIC
LOGIC
Vth_POUT(FBP)
Vth_NOUT(FBN)
TFD
P
Charge Pump Short Detection
Charge Pump Short Detection
V
OUT
N
V
OUT
Fault Delay Time to Chip Turns Off
µs
START-UP SEQUENCING
ISS
SS, SSB Current
SS, SSB ≤1.5V
6
µA
µA
V
IDLY
DLY1, DLY2 Current
DLY1, DLY2 <1.5V
6
SSTH1
SSTH2
DELTH1
DELTH2
SS, SSB Voltage to Give Max Current Limit
SS, SSB Voltage to Enable Fault Checking
DEL1, DEL2 Voltage to Give Max Current Limit
DEL1, DEL2 Voltage to Enable Fault Checking
1.27
2.05
1.27
2.05
V
V
V
FN9287.0
December 21, 2006
5
ISL97652
Typical Performance Curves
100
95
95
90
85
80
75
70
65
60
55
50
90
8V V TO 14V V
IN
OUT
85
13V V TO 14V V
IN
OUT
13V V TO 14V V
IN OUT
12V V TO 14V V
IN
OUT
8V V TO 14V V
IN
80
75
70
65
60
OUT
12V V TO 14V V
IN
OUT
0
500
1000
1500
2000
0
500
1000
1500
I
(mA)
I
(mA)
OUT
OUT
FIGURE 1. BOOST EFFICIENCY @ 650kHz
FIGURE 2. BOOST EFFICIENCY @ 1.3MHz
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
12V V TO 14V V
IN OUT
8V V TO 14V V
IN
OUT
13V V TO 14V V
IN
OUT
13V V TO 14V V
IN
OUT
12V V TO 14V V
IN
8V V TO 14V V
IN
OUT
OUT
0
500
1000
(mA)
1500
2000
0
500
1000
1500
2000
I
(mA)
I
OUT
OUT
FIGURE 4. BOOST LOAD REGULATION @ 1.3MHz
FIGURE 3. BOOST LOAD REGULATION @ 650kHz
0.09
CH3 = I
OUT
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
fs = 1.3MHz
fs = 650kHz
CH4 = AVDD (AC COUPLED)
8
9
10
11
12
(V)
13
14
15
16
V
IN
FIGURE 6. BOOST TRANSIENT RESPONSE @ 650kHz
FIGURE 5. BOOST LINE REGULATION
FN9287.0
December 21, 2006
6
ISL97652
Typical Performance Curves (Continued)
100
90
80
70
60
50
40
30
20
10
0
CH3 = I
OUT
8V V TO 3.3V V
IN
OUT
13V V TO 3.3V V
IN
12V V TO 3.3V V
OUT
IN
OUT
CH4 = AVDD (AC COUPLED)
0
500
1000
1500
2000
I
(mA)
OUT
FIGURE 7. BOOST TRANSIENT RESPONSE @ 1.3MHz
FIGURE 8. BUCK EFFICIENCY @ 650kHz
0
90
85
80
75
8V V TO 3.3V V
IN
-0.05
-0.1
OUT
-0.15
-0.2
8V V TO 3.3V V
IN
12V V TO 3.3V V
IN
OUT
OUT
70
65
60
55
50
12V V TO 3.3V V
IN OUT
-0.25
-0.3
13V V TO 3.3V V
IN
OUT
13V V TO 3.3V V
IN
OUT
-0.35
0
500
1000
I
1500
2000
2500
0
500
1000
I
1500
(mA)
2000
2500
(mA)
OUT
OUT
FIGURE 10. BUCK LOAD REGULATION @ 650kHz
FIGURE 9. BUCK EFFICIENCY @ 1.3MHz
0
CH3 = I
OUT
-0.05
-0.1
8V V TO 3.3V V
IN
OUT
-0.15
-0.2
12V V TO 3.3V V
IN
OUT
-0.25
-0.3
13V V TO 3.3V V
IN
OUT
-0.35
-0.4
CH4 = V
(AC COUPLED)
LOGIC
0
500
1000
1500
(mA)
2000
2500
I
OUT
FIGURE 11. BUCK LOAD REGULATION @ 1.3MHz
FIGURE 12. BUCK TRANSIENT RESPONSE @ 650kHz
FN9287.0
December 21, 2006
7
ISL97652
Typical Performance Curves (Continued)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
CH3 = I
OUT
CH4 = V
(AC COUPLED)
LOGIC
0
10
20
30
40
(mA)
50
60
70
I
OUT
FIGURE 13. BUCK TRANSIENT RESPONSE @ 1.3MHz
FIGURE 14. V
LOAD REGULATION
ON
0.2
0.15
0.1
CH3 = V
FLK
0.05
0
-0.05
-0.1
-0.15
-0.2
CH4 = V _M
gh
0
5
10
15
20
(mA)
25
30
35
I
OUT
FIGURE 16. GPM WAVEFORM
+
FIGURE 15. V
LOAD REGULATION
OFF
INPUT SIGNAL
OUTPUT SIGNAL
FIGURE 17. V
RISING SLEW RATE
COM
FN9287.0
December 21, 2006
8
ISL97652
Pin Descriptions
PIN NUMBER
PIN NAME
POS1
OUT1
VGL
DESCRIPTION
1
2
Op-amp 1 non-inverting input
Op-amp 1 output
3
GPM lower supply pin
GPM delay pin
4
CE
5
VFLK
VDPM
RE
GPM control pin
6
GPM enable pin
7
GPM output voltage slope adjust pin
GPM output voltage
8
VGHM
VGH
9
GPM higher supply pin
Positive charge pump feedback voltage
10
11
12
13
14
15
16
17
18
19
20
21
22
FBP
GND
Positive and negative charge pump Ground connection
Positive charge pump driver output pin
Positive and negative charge pump supply
Negative charge pump driver output pin
Device analog Ground
DRVP
SUP
DRVN
AGND
FBN
Negative charge pump feedback voltage
Reference voltage for all internal functions and external V
Buck and negative charge pump delay pin
Buck soft-start pin
REF
feedback
OFF
DLY1
SSB
VCB
Buck compensation pin
FBB
Buck feedback voltage
CBOOT
Buck boot-strap capacitor
23, 24
25, 26
27
SWB1, SWB2
PVIN1, PVIN2
VDC
Buck FET source connection
Input supply
Internal regulated 5V supply - attach external decoupling capacitor
Switching frequency select pin
28
FREQ
DLY2
29
Boost and positive charge pump delay pin
Boost soft-start pin
30
SS
31
VC
Boost compensation pin
32
EN2
Boost and positive charge pump enable
Buck and negative charge pump enable
Device power GND
33
EN1
34
PGND1
35, 36
37, 38
39
PGND2, PGND3 Boost FET source connection
SW1, SW2
SWI
Boost FET drain connection
A
delay switch source connection
start-up in-rush control
VDD
40
SUI
A
VDD
41
FB
Boost feedback voltage
A delay switch drain connection
VDD
42
SWO
AVIN
43
VCOM amplifier positive supply pin
Op-amp 2 inverting input
Op-amp 2 non-inverting input
Op-amp 2 output
44
NEG2
POS2
OUT2
OGND
NEG1
45
46
47
Op-amp ground
48
Op-amp 1 inverting input
FN9287.0
December 21, 2006
9
ISL97652
Block Diagram
SSB
VCB
FBB
FB
VC
SS
FREQ
OSC
CBOOT
SW1
SW2
-
-
F/F
+
+
REF
S
PVIN1
PVIN2
F/F
Q
-
S
OSC
R
SLOPE
+
∑
COMPENSATION
Q
+
-
R
-
BOOST CONVERTER
PGND2
+
∑
SWB1
SWB2
PGND3
SUI
FOSC
BUCK CONVERTER
SWI
GATE
CONTROL
PGND1
SWO
UVLO AND THERMAL
PROTECTION
AVIN
AVIN
POS2
NEG2
POS1
NEG1
+
+
-
-
OGND
OUT1
OUT2
DLY1
DLY2
REF
BIAS AND
SEQUENCE
CONTROL
EN1
EN2
SUP
V
OFF
CHARGE
PUMP
DRVN
GND
F
OSC
5V
PVIN2
VDC
CONTROL
REGULATOR
0.5V
+
-
FBN
SUP
RE
CE
V
ON
V
ON
CHARGE
PUMP
DRVP
F
SLICE CIRCUIT
VGH VGHM VGHL VFLK
10
OSC
VDPM
CONTROL
1.265V
+
-
FBP
AGND
FN9287.0
December 21, 2006
ISL97652
Typical Application Diagram
L1
A
V
D1
VDD
MAIN
V
C11
IN
6.8µH
C
C
OUT
IN
3 x 10µF
100nF
3 x
*
R3
0
R1
226k
10µF
1x100nF
SW1
SW2
FB
VGL
SWI
PVIN2
PVIN1
FREQ
C
AVDD
4 x 10µF
V
SUP
REF
IN
C12
C
*
VIN
0.1µF
R2
20k
*
R4
C
SUI
REF
R5
40.2k
C
SUI
0.1µF
C2*
C3*
220nF
SWO
VC
R
FBN
C
R6
453k
10k
C
N
0.1µF
C
SS
0.1µF
C
C
4.7nF
SS
DLY1
DLY2
CE
D4
V
A
VDD
OFF
C
D1
0.1µF
DRVN
C
C
OFF
4.7µF
R9
100k
D2
0.1µF
D3
CE
10nF
POS1
NEG1
OUT1
R10
100k
COMMON
BACK-PLANE
RE
GATE DRIVER
SUPPLY
VGHM
POS2
NEG2
OUT2
R
E
V
10k
ON
VGH
COMMON
BACK-PLANE
R7
232k
C
ON
4.7µF
C4*
A
AVIN
VDD
C
AVIN
0.1µF
FBP
CBOOT
470nF
PGND3
PGND2
PGND1
R8
10k
CB
L2
T
BIAS
SWB1
SWB2
C5*
CON
C21
D7
6.8µH
D5
C
P
D6
C
R11
340
B
0.1µF
*
2x10µF
DRVP
VFLK
VDPM
EN2
A
VDD
FBB
SSB
C22
R12
200
VCB
C
*
SSB
0.1µF
VDC GND OGND AGND EN1
R
CB
10k
C
DC
4.7µF
C
4.7nF
CB
*Optional components.
NOTE: Separate PGND and SGND planes must be used, see PCB layout procedure section.
Boost Converter
Applications Information
The boost converter is a current mode PWM converter
operating at either 650kHz or 1.3MHz. 650kHz operation
allows operation down to lower duty cycles. It can operate in
both discontinuous conduction mode (DCM) at light load or
when operating duty cycle is lower than the minimum duty
cycle and continuous mode (CCM). In continuous current
mode, current flows continuously in the inductor during the
entire switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by:
The ISL97652 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate A
voltage for column drivers, one
VDD
buck converter to provide voltage to logic circuit in the LCD
panel, integrated V and V charge pump controllers,
ON
OFF
and dual high speed VCOM
ON-SLICE
A
delay FET, V
VDD
amplifiers. With the high output current capability, this part is
ideal for big screen LCD TV and monitor panel application.
The integrated boost converter and buck converter operate
at either 650kHz or 1.3MHz which allow the use of multilayer
ceramic capacitors and low profile inductor which result in
low cost, compact and reliable system.
V
1
BOOST
V
(EQ. 1)
-----------------------
-------------
=
1 – D
IN
Where D is the duty cycle of the switching MOSFET.
FN9287.0
December 21, 2006
11
ISL97652
The boost converter uses a summing amplifier architecture
consisting of gm stages for voltage feedback, current
feedback and slope compensation. A comparator looks at
the peak inductor current cycle by cycle and terminates the
PWM cycle if the current limit is reached.
higher frequency option is selected. The minimum boost
duty cycle of the ISL97652 is ~10% for 650kHz and ~20%
for 1.3MHz. When the operating duty cycle is lower than the
minimum duty cycle, the part will not switch in some cycles
randomly, which will cause some LX pulses to be skipped. In
this cas, LX pulses are not consistent any more, but the
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by the
following equation:
output voltage (A
) is still regulated by the ratio of R1 and
VDD
R2. Because some LX pulses are skipped, the ripple current
in the inductor will become bigger. Under the worst case, the
ripple current will be from 0 to the threshold of the current
limit. In turn, the bigger ripple current will increase the output
voltage ripple. Hence, it will need more output capacitors to
keep the output ripple at the same level. When the input
voltage equals, or is larger than, the output voltage, the
boost converter will stop switching. The boost converter is
not regulated any more, but the part will still be on and other
channels are still regulated.
R
+ R
2
1
(EQ. 2)
--------------------
V
=
× V
BOOST
FB
R
2
Boost Converter Input Capacitor
The current through the MOSFET is limited to 2.8Apeak.
This restricts the maximum output current (average) based
on the following equation:
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. A ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 2
for input capacitor.
ΔI
V
IN
V
O
L
(EQ. 3)
⎛
⎝
⎞
⎠
--------
---------
I
=
I
–
LMT
×
OMAX
2
Where ΔIL is peak to peak inductor ripple current, and is set by:
V
D
f
S
IN
(EQ. 4)
TABLE 2. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
--------- ----
ΔI
=
×
L
L
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
where f is the switching frequency
s
1210 TDK
The following table gives typical values (margins are
considered 10%, 3%, 20%, 10% and 15% on V , V , L, f
10µF/25V
1210 Murata
IN
O
S
and I
):
OMAX
Boost Inductor
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH should be selected to match the
internal slope compensation. The inductor must be able to
handle the following average and peak current:
V
(V)
V
(V)
L (µH)
6.8
f
(MHz)
0.65
1.3
I
(mA)
IN
O
s
OMAX
12
15
1890
12
12
12
8
15
18
18
15
15
18
18
6.8
1955
1500
1590
1200
1275
950
6.8
0.65
1.3
I
O
(EQ. 5)
6.8
-------------
I
=
LAVG
1 – D
6.8
0.65
1.3
ΔI
8
6.8
L
--------
+
(EQ. 6)
I
= I
LPK
LAVG
2
8
6.8
0.65
1.3
Some inductors are recommended in Table 3.
8
6.8
1050
TABLE 3. BOOST INDUCTOR RECOMMENDATION
When operating at the lower frequency option, 650kHz, the
potential increase in ripple current in the inductor can be
avoided by increasing the inductor by the same factor. This
allows the slope compensation in the boost feedback to
remain the same as the 1.3MHz case and this will maintain
stability of the converter over the widest operating range.
Operation at 650kHz allows boost operation down to lower
minimum duty cycles, where the output voltage required is
closer to the input voltage than can be achieved when the
DIMENSIONS
INDUCTOR
(mm)
VENDOR
PART NUMBER
6.8µH/
7.3x6.8x3.2 TDK
RLF7030T-6R8N3R0
3A
PEAK
6.8µH/
7.6X7.6X3.0 Sumida
CDR7D28MNNP-6R8NC
CD1-5R2
2.9A
PEAK
5.2µH/
4.55A
10x10.1x3.8 Cooper
Bussmann
PEAK
FN9287.0
December 21, 2006
12
ISL97652
examined with an oscilloscope set to AC 100mV/div and the
Rectifier Diode (Boost Converter)
amount of ringing observed when the load current changes.
Reduce excessive ringing by reducing the value of the
resistor in series with the VC pin capacitor.
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements. The
following table is some recommendations for boost converter
diode.
A
Delay Switch
VDD
The ISL97652 integrates a PMOS disconnect switch for the
boost output to disconnect V from A when the
A
VDD
IN VDD
EN2 input is not selected. When EN2 is taken high, the
PMOS FET is turned on to connect power to the display. The
CSUI capacitor provide soft-start control for the connection
of this switch.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
V /I
R AVG
The operation of the AVDD delay switch is controlled by
internal VDSOK and VDSHYS control signals which operate
as follows:
DIODE
SS23
SL23
RATING
30V/2A
30V/2A
PACKAGE
SMB
VENDOR
Fairchild Semiconductor
Vishay Semiconductor
SMB
During start-up (or during fault conditions):
VDSOK goes to 1 when V(SWI - SWO) becomes less than
~0.5V. This will turn-on the boost function.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage consists
of two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor.
VDSOK goes to 0 when VDS_pfet becomes greater than
~1.1V. This will turn-off the boost function.
The threshold voltages have a Vin dependence such that:
For Vin1 = 8V: VDSOK goes to 1 occurs at ~0.5V and
VDSOK goes to 0 occurs at ~1.1V.
V
– V
I
O
1
O
IN
(EQ. 7)
----------------------- ------------------- ---
V
= I
× ESR +
LPK
×
×
For Vin1 =18.5V: VDSOK goes to1 occurs at ~1.13V and
VDSOK goes to 0 occurs at ~2.65V.
RIPPLE
V
C
f
s
O
AVDD
For low ESR ceramic capacitors, the output ripple is
V(SWI - SWO) is the VDS voltage across the internal PFET
protection switch. If this voltage exceeds 1.1V for some
reason (e.g. under fault conditions or during start-up if
VMAIN rises faster than AVDD) the boost is turned-off to
allow the AVDD (SWO) potential to catch-up with VMAIN
(SWI).
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then
VDSHYS is the VDS hysteresis level;
increases. C
in Equation 7 above assumes the effective
OUT
Once VDSOK goes to 1 the voltage V(SWI - SWO) then
needs to exceed 1.1V for VDSOK goes to 0.
value of the capacitor at a particular voltage and not the
manufacturer's stated value, measured at zero volts.
During normal operation VDS will be ~Ron_PFET * Iload
(~ 0.18x2 = 0.36V for max AVDD load).
The following table shows some selections of output
capacitors.
If a fault develops on AVDD, which causes VDS to exceed
1.1V, then the boost operation is interrupted by the internal
VDSOK goes to 0 signal and fault timers will start to operate
while the rising/falling character of AVDD is monitored.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
1210 TDK
A Delay Switch Fault Operation
VDD
10µF/25V
1210 Murata
When enabled, the gate of the PFET is pulled down with a
30µA current, turning on the FET switch. The speed of this
turn-on can be controlled by placing a capacitor from SWI to
SUI. In normal operation the gate (and SUI pin) are pulled
Loop Compensation (Boost Converter)
The boost converter of ISL97652 can be compensated by a
RC network connected from V pin to ground. C = 4.7nF
C
C
down to 5V below SWI. The A
delay switch circuitry
VDD
and R = 10k RC network is used in the demo board. A
C
constantly monitors both the current in the switch and the
voltage at SWO. If the current exceeds the current limit of
2A, the gate of the FET (and also the SUI pin) will be pulled
up to the correct level to limit the current to 2A. In this mode
the switch acts like a 2A current source. this current cannot
be maintained indefinitely due to the power dissipation on
higher resistor value can be used to lower the transient load
change A
overshoot - however, this may be at the
VDD
expense of stability to the loop.
The stability can be examined by repeatedly changing the
load between 100mA and a max level that is likely to be
used in the system being used. The A
voltage should be
VDD
FN9287.0
December 21, 2006
13
ISL97652
chip. Therefore, three separate fault mechanisms are
operated.
Feedback Resistors
The buck converter output voltage is determined by the
following equation:
1. The SWO output range is constantly monitored and
expected to rise if the PFET is in current limit. The rate of
rise at SWO can be calculated from the current limit and
the capacitance on SWO by using the equation
R
+ R
12
11
(EQ. 11)
--------------------------
V
=
× V
LOGIC
FBB
R
12
dV/dt = Ilimit/Cavdd. The SWO voltage range is split into
sections of approximately 0.7V such that every time the
output rises by this amount the circuit detects that the
voltage is rising. Should the circuit remain in current limit
for more than 100µs with no such rise taking place the
circuit will fault out. In this scenario, the PFET will
immediately switch itself off and the rest of the ISL97652
Where R11 and R12 are the feedback resistors of buck
converter to set the output voltage. Current drawn by the
resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 1kΩ is recommended.
will later fault out due to the boost voltage at A
away.
falling
VDD
Buck Converter Input Capacitor
2. As well as monitoring any rise in the voltage at SWO, the
circuit also monitors any falls in this level. If the output
falls by more than a certain amount while it is in current
limit the circuit will fault out immediately. This amount
varies from about 1V to about 1.4V depending on the
output level before the fall. In this scenario, the PFET will
immediately switch itself off and the rest of the ISL97652
will later fault out due to the boost voltage falling away.
The capacitor should support the maximum AC RMS current
which happens when D = 0.5 and maximum output current.
(EQ. 12)
I
(C ) = D ⋅ (1 – D) ⋅ I
O
ACRMS IN
Where I is the output current of the buck converter. The
o
following table shows some recommendations for input
3. Once the ISL97652 has successfully sequenced the
boost on and the boost soft-start capacitor has charged
up, a third fault check is also added. After this point if the
PFET enters current limit for greater than the global
timeout of 40µs then the chip will fault out. In this scenario
the whole chip will be disabled with the PFET
immediately switched off.
capacitor.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION
CAPACITOR
10µF/16V
10µF/10V
22µF/16V
SIZE
1206
0805
1210
VENDOR
TDK
PART NUMBER
C3216X7R1C106M
GRM21BR61A106K
C3225X7R1C226M
Murata
Murata
Buck Converter
The buck converter is the step down converter, which
supplies the current to the logic circuit of the LCD system.
The ISL97652 integrates an 20V N-Channel MOSFET to
save cost and reduce external component count. In the
continuous current mode, the relationship between input
voltage and output voltage is as follows:
Buck Inductor
An 3.3µH-10µH inductor is the good choice for the buck
converter. Besides the inductance, the DC resistance and
the saturation current are also the factor needed to be
considered when choosing buck inductor. Low DC
resistance can help maintain high efficiency, and the
saturation current rating should be 2.5A. Here are some
recommendations for buck inductor.
V
LOGIC
(EQ. 8)
---------------------
= D
V
IN
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of buck
converter is lower than input voltage.
TABLE 7. BUCK INDUCTOR RECOMMENDATION
DIMENSIONS
INDUCTOR
(mm)
VENDOR
PART NUMBER
The peak current limit of buck converter is set to 2.5A, which
restricts the maximum output current (average) based on the
following equation:
4.7µH/
5.7x5.0x4.7 Murata
LQH55DN4R7M01K
2.7A
PEAK
6.8µH/
7.3x6.8x3.2 TDK
RLF7030T-6R8M2R8
DO3308P-103
(EQ. 9)
I
= 2.5A – ΔI
PP
OMAX
3A
PEAK
10µH/
2.4A
Where ΔI is the ripple current in the buck inductor as the
12.95x9.4x3.0 Coilcraft
PP
following equation:
PEAK
V
LOGIC
(EQ. 10)
---------------------
ΔI
=
⋅ (1 – D)
PP
L ⋅ f
Rectifier Diode (Buck Converter)
s
A Schottky diode is recommended due to fast recovery and low
forward voltage. The reverse voltage rating should be higher
Where L is the buck inductor, f is the switching frequency.
s
FN9287.0
December 21, 2006
14
ISL97652
than the maximum input voltage. The peak current rating is 2A,
and the average current should be as the following equation,
Regulated Charge Pump Controllers (V
ON
OFF
and
V
)
(EQ. 13)
The ISL97652 includes 2 independent charge pumps (see
charge pump block and connection diagram). The negative
I
= (1 – D)*I
o
AVG
charge pump inverters the V
voltage and provides a
Where I is the output current of buck converter. The
o
following table shows some diode recommended.
SUP
regulated negative output voltage. The positive charge pump
doubles or triples the V voltage and provided a regulated
SUP
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
V /I
positive output voltage. The regulation of both the negative
and positive charge pumps is generated by internal
comparator that senses the output voltage and compares it
with the internal reference.
R AVG
RATING
DIODE
PACKAGE
SOD323F Philips
Semiconductors
Fairchild
Semiconductor
VENDOR
PMEG2020EJ
20V/2A
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps can
SS22
20V/2A
SMB
provide 30mA for V
and 20mA for V
.
ON
OFF
Output Capacitor (Buck Converter)
Positive Charge Pump Design Consideration
Four 10µF or two 22µF ceramic capacitors are recommended
for this part. The overshoot and undershoot will be reduced
with more capacitance, but the recovery time will be longer.
The positive charge pump can drive multiple stages for 2X/
3X step up ratios, or higher. Internal switches (M1 and M2)
drive external steering diodes via the pump capacitor CP.
Figure 18A shows 2X configuration and Figure 18B shows
3X configuration. The output voltage is divided by feedback
resistors R7 and R8, which is then compared to the internal
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/6.3V
10µF/6.3V
22µF/6.3V
100µF/6.3V
SIZE
0805
0805
1210
1206
VENDOR
TDK
PART NUMBER
C2012X5R0J106M
GRM21BR60J106K
C3216X5R0J226M
GRM31CR60J107M
reference via comparator A1. The maximum V
charge
ON
pump current can be estimated from the following equations
assuming a 50% switching duty:
Murata
TDK
I
(2x) ∼ min of 50mA or
MAX
Murata
2 • V
– 2 • V
(2 • I
) – V(V
)
ON
SUP
DIODE
MAX
----------------------------------------------------------------------------------------------------------------------
• 0.95A
• 0.95A
(2 • (R
+ R
))
PI Loop Compensation (Buck Converter)
ONH
ONL
(EQ. 14)
The buck converter of ISL97652 can be compensated by a
RC network connected from VCB pin to ground. C = 4.7nF
CB
I
(3x) ∼ min of 50mA or
MAX
and R
CB
= 10k RC network is used in the demo board. The
3 • V
– 4 • V
(2 • I
) – V(V
)
ON
SUP
DIODE
MAX
larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
----------------------------------------------------------------------------------------------------------------------
4 • (R
+ R
)
ONL
ONH
The stability can be optimized in a similar manner to that
described in the section on "PI Loop Compensation (Boost
Converter)”.
Bootstrap Capacitor (C )
B
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
470nF is recommended for ISL97652. A low value capacitor
can lead to overcharging and in turn damage the part.
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage.
In this case, if V -V
<1.5V, the internal MOSFET
pull-up device may be unable to turn-on until V falls.
IN BUCK
LOGIC
Hence, there is a minimum load requirement in this case.
The minimum load can be adjusted by the feedback
resistors to FBB.
FN9287.0
December 21, 2006
15
ISL97652
C4
100pF
V
VDC
SUP
A2
FAULT
C5
2.2nF
R8
10k
1.14V
FBP
A1
R7
232k
1.265V
F
OSC
STOP
V
M2
M1
SUP
D6
CLK
C
P
0.1µF
D7
DRVP
GND
V
(30V)
ON
C
1µF
ON
PWM
CONTROL
EN
FIGURE 18A. V
FUNCTION DIAGRAM (VOLTAGE DOUBLER)
ON
V
SUP
D6
C
P
D7
D6’
D7’
0.1µF
DRVP
V
(30V)
ON
C
ON
1µF
C
ON’
1µF
C
P’
0.1µF
FIGURE 18B. VOLTAGE TRIPLER
FIGURE 18.
In voltage doubler configuration, the maximum V
ON
is as given by the following equation:
V
= 2 • (V
– V
) – 2 • I
• (R
+ R
)
ONL
ON_MAX(2x)
SUP
DIODE
OUT
ONH
(EQ. 15)
For Voltage Tripler using additional external diodes and capacitors (Figure 18B):
V
= 3 • V
– 4 • V
– 2 • I
• (R
+ R
)
(EQ. 16)
(EQ. 17)
ON_MAX(3x)
SUP
DIODE
OUT
ONH
ONL
V
output voltage is determined by the following equation:
R7
ON
⎛
⎞
⎠
-------
V
= V
× 1 +
ON
FBP
⎝
R8
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher
M1, M2 which drives external steering diodes Dx and Dx via
a pump capacitor (CN) to generate the negative V
OFF
supply. An internal comparator (A1) senses the feedback
voltage on FBN and turns on M1 for a period up to half a
CLK period to maintain V
in regulated operation at
(FBN)
0.5V. External feedback resistor R5 is referenced to V
.
REF
FN9287.0
December 21, 2006
16
ISL97652
V
C3
REF
100pF
V
VDC
SUP
A2
FAULT
C2
820pF
R5
40.2k
0.53V
FBN
A1
R6
453k
0.5V
F
OSC
STOP
M2
M1
CLK
C
N
0.1µF
D4
DRVN
GND
V
(-8V)
OFF
C
OFF
1µF
D3
PWM
CONTROL
EN
FIGURE 19. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
The maximum V
output voltage of a single stage charge pump is:
OFF
V
(2x) = – V
+ V
+ 2 • I
• (R (NOUT)H + R (NOUT)L)
OUT ON ON
(EQ. 18)
OFF_MAX
SUP
DIODE
R5 and R6 in the Typical Application Diagram determine
(without the boost running) is large enough to satisfy the
regulated VOFF supply.
V
output voltage.
OFF
R6
R5
R6
R5
⎛
⎞
⎠
⎛
⎝
⎞
⎠
(EQ. 19)
-------
-------
V
= V
• 1 +
– V
•
REF
Improving Charge Pump Noise Immunity
OFF
FBN
⎝
Depending on PCB layout and environment, noise pick-up at
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the Application
Diagram, C4 and C5 for the positive charge pump).
Set R7 • C4 = R8 • C5 with C4 ~ 100pF.
Charge Pump Supply
The magnitude of the SUP supply will determine the charge
pump diode configuration; whether x2 or x3 for the positive
charge pump or x1 or x2 for the negative charge pump.
An independent charge pump supply pin 13 (SUP) is
provided and this may be connected to Vin, Vmain, AVDD or
some other suitable supply.
V
Circuit Operation
ON-SLICE
The Von slice circuit functions as a three way multiplexer,
switching VGHM between ground, VGL and VGH (typ 15-
30V). Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). HIGH to LOW delay and slew
control is provided by external components on pins CE and
RE respectively. The block diagram of the VON-SLICE
circuit is shown in Figure 3.
Note that if AVDD is chosen for the SUP supply, then a
potential fault-like interaction with the supply sequencing
and fault checking is present; when EN1 goes high (with
EN2 low), fault checking on the VOFF charge pump is
started by the voltage ramp on DEL1. If this pin reaches
~1.9V before VOFF is within 90% of it's regulation voltage
then the buck converter (Tcon bias) and Voff will be
continually re-started. This condition will arise if the SUP
supply has not been activated by EN2 going high before
DEL1 has reached 1.9V. One solution would be to increase
the capacitance on DEL1 to overlap enough in time with the
EN2 going high. This does have the disadvantage of
lengthening the fault detection time of the VOFF charge
pump under true fault conditions and it also lengthens the
initial VOFF turn-on time. Another solution would be to
supply SUP from Vmain as long as the magnitude of Vmain
When VDPM is LOW, the block is disabled and VGHM is
grounded.
When VDPM is HIGH, VGHM is determined by VFLK; when
VFLK goes LOW, there is a delay controlled by the capacitor
attached to the CE pin, following which VGHM is driven to
VGL, with a slew rate controlled by the resistor attached to
the RE pin. Note that VGL is used only as a reference
voltage for an amplifier, thus does not have to source or sink
a significant DC current. When VFLK goes HIGH, VGHM is
FN9287.0
December 21, 2006
17
ISL97652
driven HIGH at a rate primarily controlled by the P1 switch
resistance (RONVGH) and the external capacitive load.
external capacitor to VREF. This creates a delay, equal to
CE*21300. For example, the delay time is ~10µs for 470pF
CE capacitor. At this point, VGHM begins to slew down from
VGH to VGL. The slew current is equal to Isl=300/(RE+5kΩ),
and the dv/dt slew rate is Isl/Cload.
VGHM HIGH to LOW transitions are more complex; take the
case where the block is already enabled (VDPM is HIGH).
When VFLK is HIGH, pin CE is grounded. On the falling
edge of VFLK, a current is passed into pin CE to charge an
where Cload is the load capacitance applied to VGHM.
VGH
VGHM
VDPM
VGL
x248
VREF
RE
60µA
CE
CONTROL
VFLK
AND TIMING
FIGURE 20. VON-SLICE BLOCK DIAGRAM
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18
ISL97652
VGH
VGHM
SLOPE CONTROLLED
BY RE AND LOAD
CAPACITANCE
VGL
0
t
VFLK
0
t
DELAY TIME CONTROLLED BY CE
~1.94V
T
CE
CE
~1.265V
0
t
FIGURE 21. VON-SLICE TIMING WAVEFORM
charge. Once the threshold is reached, the negative charge
pump will begin. Removing the DLY1 capacitor will cause the
negative charge pump to start immediately once the buck
regulator reaches 90% of the target value. The delay time
and soft-start times are determined using the following
equations:
High Performance V
COM
Amplifiers
The integrated high performance amplifiers are designed to
drive the V plane in TFT-LCD displays. Under normal
COM
operational conditions, the amplifiers are permanently
enabled when the AVIN supply is present. Under fault
conditions and with EN1 active, the temperature shut-down
V
(T
exceeded) will disable the amplifiers until the
DL1
OFF
(EQ. 20)
--------------
T
= C
×
DL1
DLY1
I
temperature drops to T . Temperature shut-down of the
ON
DL1
amplifiers is disabled if EN1 is disabled.
V
SSB
(EQ. 21)
--------------
T
= C
×
SSB
The amplifiers integrated in to the ISL97652 feature high
output current of 50mA minimum and high slew rate of
50V/µs. Both inputs and outputs have rail-to-rail capability.
SSB
I
SSB
The EN2 pin is used to control the boost and positive charge
pump circuits.Note that EN2 is ignored until the buck
converter has reached 90% of it's target value. When taken
high, the internal PFET is turned on to connect the input to
Start-Up Sequence Control
The ISL97652 features extensive start-up sequence control
options. Two enable pins and two delay control pins are
used to set the start-up sequence.
the A
output. A capacitor connected to SUI provides
VDD
control over the soft connect to limit inrush current. Next, the
boost converter starts to operate. The soft-start time for the
boost is set using the capacitor tied to the SS pin. Once the
output reaches 90% of the target value, the DLY2 timer
The EN1 enable pin controls the buck regulator and negative
charge pump controller. When EN1 goes H, the internal 5.3V
regulator starts up. Once the regulator output on pin 27
(VDC) exceeds it's UVLO threshold, the REF pin starts to
charge up to the normal output level. Once REF is within
15% of it's final value, the buck regulator will start to operate.
starts. Once completed, the positive V
charge pump
starts to operate. If CDL2 is not present, the V charge
ON
ON
pump will start immediately once the boost is in regulation.
Note that if V
moves more than 15% from it's target
The delay time is determined using the following equation:
REF
value, all major functions will be disabled until REF returns to
it's normal range. This involves the chip going through the
normal start-up sequence from buck start-up onwards,
depending on the state of the enable signals EN1, EN2. The
soft-start time is set using the capacitor connected to SSB.
Once the output reaches 90% the DLY1 capacitor begins to
V
DL2
(EQ. 22)
(EQ. 23)
--------------
T
T
= C
×
DLY2
SS
DL2
V
I
DL2
SS
-----------
= C
×
SS
I
SS
FN9287.0
December 21, 2006
19
ISL97652
Variations on the start-up sequence can be seen in Figures
22, 23 and 24.
The Gate pulse modulator is enabled when both of the
following conditions are met:
•
VDPM is H
• V is over 90% of it's target value.
ON
T
SSB
DLY2
EN1
EN2
DLY1
V
TCON
T
SS
V
OFF
V
MAIN
V
- DIODE
IN
V
- 2 x DIODE
V
- 2 x DIODE
IN
MAIN
V
ON
V
- DIODE
IN
A
VDD
FIGURE 22. TIMING DIAGRAM 1
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20
ISL97652
T
SSB
DLY2
EN1
EN2
DLY1
T
SS
V
TCON
V
OFF
V
- DIODE
IN
V
MAIN
V
- 2 x DIODE
MAIN
V
- 2 x DIODE
IN
V
ON
V
- DIODE
IN
A
VDD
FIGURE 23. TIMING DIAGRAM 2
FN9287.0
December 21, 2006
21
ISL97652
EN2
DLY2
VDPM
V
- DIODE
IN
V
- DIODE OR
V
IN
MAIN
V
DIODE
MAIN
V
ON
A
VDD
VFLK
VGHM
FIGURE 24. TIMING DIAGRAM 3
Switching Frequency Control
Fault Detection
The ISL97652 can operate at either 650kHz or 1.3MHz
depending on the state of the FREQ pin. When connected to
The ISL97652 includes extensive fault handling circuitry,
which interacts with the start-up sequence circuitry if a fault
is detected.
GND, 650kHz is selected. When connected to V , 1.3MHz
IN
is selected. Higher frequencies enable the selection of
smaller inductors and capacitors. Lower frequencies allow
closer input/output ratios to be supported. The charge pump
circuits switch at half the frequency selected.
During normal operation, if EN1 goes L, all major functions
are disabled immediately, including the 5V regulator. If EN2
goes L, but EN1 remains H, boost, V
and GPM are
ON
disabled immediately. When EN1 and/or EN2 return H, the
start-up sequence restarts from the appropriate point.
Undervoltage Lockout
The integrated undervoltage lockout circuit is designed to
power down the TFT-LCD if the input voltage falls below a
preset threshold. The ISL97652 will not start if the input
voltage is below the UVLO threshold.
If the over-temperature threshold (+150°C nominal) is
exceeded, or if V drops below the specified lower UVLO
IN
limit, all major functions are disabled immediately, excluding
the 5.3V regulator. If/when the temperature drops below
+100°C, or V returns to a level above the upper UVLO
threshold the start-up sequence will re-commence by
enabling REF.
IN
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +150°C, the device will shut
down. Operation with die temperatures between +125°C and
150°C can be tolerated for short periods of time, however, in
order to maximize the operating life of the IC, it is
Timed “Faults”
The four ramp voltages, SSB, SS, DEL1 and DEL2 all ramp
linearly from 0V to approximately 2.7V, where they are
soft-clamped. The 2V thresholds of each are used to enable
timed fault checking on related blocks. Therefore, external
capacitor values should be chosen such that all major
recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
FN9287.0
December 21, 2006
22
ISL97652
outputs are in regulation by the time this threshold is
reached. For example, SSB controls step-down regulator
(Route the following tracks on the PGND (top) metal layer:
PGND1,2,3 [a single wide track] to CIN, Cout and CB, D5.
SW1,2 [a single wide track] to L1/D1, SWB1,2 [a single wide
track] to L2/D5.)
fault checking, DEL1 controls V
fault checking, SS
OFF
controls step-up regulator and PFET fault checking, DEL2
controls V and GPM fault checking. If a fault on any of the
ON
Reserve the bottom (or an intermediate layer) for the signal
ground plane (SGND) and signal routing. It is recommended
that all feedback inputs and any other sensitive tracks are
routed to the SGND layer using a VIAs as close to the chip
as possible. This prevents unwanted interference pick-up
and allows the supply smoothing capacitors to be places as
close to the chip as possible.
major blocks is detected continuously for a predetermined
time interval (currently set to 63µs), when fault checking is
enabled for that function, the fault latch will be set. This
causes all major functions to be disabled immediately,
including the 5.3V regulator. Once VDC falls below its
internal UVLO limit (typically 3.6V), the FAULT latch is reset.
This will initiate an automatic restart. If the fault has been
cleared, the restart will be successful; if the fault persists, the
FAULT latch will again be set, and the cycle will repeat itself.
(Route the following tracks on the SGND (bottom or
intermediate) metal layer: FB, FBB, FBP, FBN, POS1,2, )
Buck, boost and V
target values.
circuits have fault thresholds at 90% of
Star Ground
ON
A star ground system is where a number of different grounds
(e.g. PGND, SGND°¦) come together at a single location
which then becomes the reference ground point for the
system as a whole. Star grounding ensures minimum
interference between different functions in a system.
The V
OFF
fault threshold is set at 125mV above the 0.5V
regulation point.
GPM fault detection is designed to detect a short circuit on
the output, by monitoring whether VGHM fails to pull up to
Practically, it is difficult to achieve an ideal (single location)
ground point due to the physical dimensions of the chip,
smoothing capacitors and track routing, however, the
exposed die plate and the area immediately next to the
PGND1,2,3 pins is defined as the star ground for this chip.
VGH on two consecutive F
clock periods.
OSC
The A
VDD
PFET also has fault checking, which will protect
the FET in the event of an output short circuit.
Note that the V amplifiers are independently biased,
COM
and are enabled at all times, except if an over-temperature
fault is detected. If this behavior is not desired, then there is
The negative smoothing capacitor terminals of: Cout, CB
and CIN must be located as close as possible to the
PGND1,2,3 pins. The smoothing capacitors for VIN, Cout
and CB come as a block of three or four capacitors with
(usually) one small capacitor whose role is to reduce the
total effective ESR of the capacitors. It is recommended that
the small capacitor and at least one of the large capacitors
from each capacitor block is placed as physically close to the
chip PGND pins as possible. The other capacitors from each
block can be placed a little further away, if necessary.
an option to power the V
amplifiers from A , which
VDD
COM
will keep them disabled until the boost is enabled.
Note also that it is possible to prevent timed fault checking
on any or all of the major functions, simply by externally
clamping SSB, SS, DEL1 and/or DEL2 to a voltage between
1.3V and 2V.
PCB Layout Procedure
To ensure the user gets the best chip performance with
minimum amount of PCB rework in the development phase,
the following PCB layout procedure is strongly
recommended.
Exposed Die plate connection
The exposed die plate connection to the underside of the
chip must directly connect the PGNDs (pins 34,35,36) and
AGND (pin 15) with an equivalent area of metal. The other
ground pins (amplifier OGND and charge pump GND pins
may also be connected to the die plate.
PCB metal layers
Reserve the top PCB metal layer for direct power ground
(PGND) connections to the supply pins and switching
outputs (buck/boost/charge-pumps). The goal is to ensure
there are no VIAS in the boost and buck paths to the
smoothing capacitors. The top layer may also be used for
general routing of non-sensitive tracks as long as this does
not compromise the supply track widths which should be as
wide as possible.
The exposed die plate connection must have multiple VIAs
(use a 4x4 array) connecting the top metal PGND layer to
the bottom SGND metal layer. The bottom SGND metal area
around the VIA array should be maximized in order to keep
the thermal resistance of the chip and PCB system as low as
possible. This will optimise operation at high currents or in
high ambient temperature applications.
Note that using VIAs in series with smoothing capacitors
(even if implemented as multiply parallel VIAs) increases the
effective high frequency ESR of the capacitors and WILL
cause degraded system operation.
Order of component placement
The order of component placement should be as follows.
This procedure minimizes the high current PGND and supply
track impedance to the chip pins.
FN9287.0
December 21, 2006
23
ISL97652
1). Cout, Cin, CB ®C get these components as close to
PGND1,2,3 as possible and use wide tracks on the top
PGND layer with no VIAs.
2). L1, D1, L2, D5 ®C get these components as close to the
chip pins as possible having observed 1/ and use wide
tracks on the top PGND layer with no VIAs.
3). Feedback resistor networks connected to FB, FBB, FBP,
FBN, POS1,2 - keep tracks as short as possible, having first
observed 1/ and 2/. Routing on the SGND layer should be
used. Avoid routing this tracks under switching tracks on the
top surface.
4). All other components - keep all switching output tracks
(SW1,2, SWB1,2, CBOOT, DRVP, DRVN, VGHM, VFLK) on
the PGND layer shielded from adjacent tracks.
Evaluation PCB
A two layer evaluation PCB is available which follows the
above procedure and may be useful as a reference to guide
the PCB layout engineer. For example, the smoothing
capacitor positive rail to PVin does contain VIAs in series ®C
however, a small capacitor has been used directly at the
PVin pins which overcomes the ESR objection.
FN9287.0
December 21, 2006
24
ISL97652
Quad Flat No-Lead Plastic Package (QFN)
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)
Micro Lead Frame Plastic Package (MLFP)
2X
0.15
C A
MILLIMETERS
D
A
SYMBOL
MIN
0.80
-
NOMINAL
0.90
MAX
1.00
0.05
NOTES
D/2
A
A1
A3
b
-
-
-
2X
0.20 REF
0.23
-
N
0.15 C
B
6
0.18
4.15
4.15
0.30
4.45
4.45
5, 8
INDEX
AREA
1
2
3
E/2
D
7.00 BSC
4.30
-
D2
E
7, 8
E
B
7.00 BSC
4.30
-
E2
e
7, 8
0.50 BSC
-
-
TOP VIEW
k
0.25
0.30
-
-
L
0.40
0.50
8
A
/ /
0.10 C
N
48
2
C
0.08 C
Nd
Ne
12
3
12
3
SEATING PLANE
A3 A1
SIDE VIEW
Rev. 2 5/06
NOTES:
5
NX b
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
0.10 M C A B
D2
8
7
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
NX k
D2
(DATUM B)
(DATUM A)
2
N
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
(Ne-1)Xe
REF.
E2
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
6
8
7
E2/2
INDEX
AREA
3
2
1
NX L
N
e
8
(Nd-1)Xe
REF.
BOTTOM VIEW
A1
NX b
5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9287.0
December 21, 2006
25
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