ISL9305IRTHWCLBZ-T [INTERSIL]
3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible; 3MHz的双1.5A降压型转换器和双通道低输入LDO,具有I2C兼容型号: | ISL9305IRTHWCLBZ-T |
厂家: | Intersil |
描述: | 3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible |
文件: | 总16页 (文件大小:650K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3MHz Dual 1.5A Step-Down Converters and Dual
2
Low-Input LDOs with I C Compatible Interface
ISL9305H
Features
ISL9305H is an integrated mini Power Management IC (mini-
PMIC) for powering low-voltage microprocessor, or applications
using a single Li-Ion or Li-Polymer cell battery to power multiple
voltage rails. ISL9305H integrates two high-efficiency 3MHz
synchronous step-down converters (DCD1 and DCD2) and two
low-input, low-dropout linear regulators (LDO1 and LDO2).
• Dual 1.5A, Synchronous Step-down Converters and Dual
300mA, General-purpose LDOs
• Input Voltage Range
- DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
- LDO1/LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
2
• 400kb/s I C-Bus Series Interface Transfers the Control Data
The 3MHz PWM switching frequency allows the use of very
small external inductors and capacitors. Both step-down
converters can enter skip mode under light load conditions to
further improve the efficiency and maximize the battery life.
For noise sensitive applications, they can also be programmed
Between the Host Controller and the ISL9305H
• Adjustable Output Voltage
- DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to V
IN
2
- Fixed Output I C Programmability
2
through I C interface to operate in forced PWM mode
2
• At 25mV/Step . . . . . . . . . . . . . . . . . . . . . . . . . .0.825V to 3.6V
regardless of the load current condition. The I C interface
2
supports on-the-fly slew rate control of the output voltage from
0.825V to 3.6V at 25mV/step size for dynamic power saving.
Each step-down converter can supply up to 1.5A load current.
The default output voltage can be set from 0.8V to VIN using
external feedback resistors on the adjustable version, or the
ISL9305H can be ordered in factory pre-set power-up default
voltages in increments of 100mV from 0.9V to 3.6V.
• LDO1/LDO2 Output Voltage I C Programmability
- At 50mV/Step . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.3V
• 50μA I (Typ) with DCD1/DCD2 in Skip Mode; 20μA I (Typ)
Q
Q
for Each Enabled LDO
2
• On-the-fly I C Programming of DC/DC and LDO Output
Voltages
2
ISL9305H also provides two 300mA low dropout (LDO)
• DCD1/DCD2 I C Programmable Skip Mode Under Light
regulators. The input voltage range is 1.5V to 5.5V allowing them
to be powered from one of the on-chip step-down converters or
directly from the battery. The default LDO output comes with
factory pre-set fixed output voltage options between 0.9V to 3.3V.
Load or Forced Fixed Switching Frequency PWM Mode
• Small, Thin 4mmx4mm TQFN Package
Applications
• Cellular Phones, Smart Phones
ISL9305H is available in a 4mmx4mm 16 Ld TQFN package.
• PDAs, Portable Media Players, Portable Instruments
• Single Li-Ion/Li-Polymer Battery-Powered Equipment
• DSP Core Power
Related Literature
• FN7605, ISL9305 Data Sheet
• AN1564 “ISL9305IRTZEVAL1Z and ISL9305HIRTZEVAL1Z
Evaluation Boards”
L
= 1.5µH
1
2
1.5A
PG
SW1
FB1
2.5V TO 5.5V
VINDCD1
*
R
1
C
10µF
4
VINDCD2
R
C
10µF
2
10
L
= 1.5µH
1.5A
SDAT
SCLK
SW2
FB2
*
ISL9305H
R
3
C
5
10µF
1.5V TO 5.5V
R
4
VINLDO1
C
1µF
2
300mA
300mA
VOLDO1
VOLDO2
1.5V TO 5.5V
VINLDO2
GNDDCD1 GNDDCD2
C
1µF
3
C
1µF
C
7
1µF
GNDLDO
6
*ONLY FOR ADJUSTABLE OUTPUT VERSION. FOR FIXED OUTPUT VERSION, DIRECTLY
CONNECT THE FB PIN TO THE OUTPUT OF THE BUCK CONVERTER.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
November 8, 2010
FN7724.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL9305H
TABLE 1. TYPICAL APPLICATION PART LIST
PARTS
DESCRIPTION
MANUFACTURER
Sumida
PART NUMBER
CDRH2D14NP-1R5
SPECIFICATIONS
SIZE
L1, L2 Inductor
1.5µH/1.80A/50mΩ
10µF/6.3V
3.0mmx3.0mmx1.55mm
C1
Input capacitor
Murata
Murata
Murata
Murata
Various
GRM21BR60J106KE19L
GRM185R60J105KE26D
GRM21BR71A106KE51L
GRM185R60J105KE26D
0805
0603
0805
0603
0603
C2, C3 Intput capacitor
C4, C5 Output capacitor
C6, C7 Output capacitor
1µF/6.3V
10µF/6.3V
1µF/6.3V
R1, R2, Resistor
R3, R4
1%, SMD, 0.1W
Pin Configuration
ISL9305H
(16 LD 4X4 TQFN)
TOP VIEW
16
15
14
13
12
11
10
9
VINDCD1 1
VINDCD2
FB2
2
3
4
FB1
E-PAD
DCDPG
GNDLDO
SCLK
SDAT
5
6
7
8
Pin Descriptions
PIN NUMBER
(TQFN)
NAME
DESCRIPTION
1
VINDCD1
Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog
circuits.
2
FB1
Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD1 output.
2
3
4
SCLK
I C interface clock pin.
2
SDAT
I C interface data pin.
5
VINLDO1
VOLDO1
VOLDO2
VINLDO2
GNDLDO
DCDPG
Input voltage for LDO1.
6
Output voltage of LDO1.
Output voltage of LDO2.
Input voltage for LDO2.
7
8
9
Power ground for LDO1 and LDO2.
10
The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1
and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter
voltages are within the power good range. The pin will be pulled low if either DCD is outside their range. When only
one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state
can be programmed for a delay of up to 200ms before being released to rise high. The programming range is
2
1ms~200ms through the I C interface.
FN7724.0
November 8, 2010
2
ISL9305H
Pin Descriptions(Continued)
PIN NUMBER
(TQFN)
NAME
FB2
DESCRIPTION
11
Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD2 output.
12
13
VINDCD2
SW2
Input voltage for buck converter DCD2.
Switching node for DCD2, connect to one terminal of the inductor.
Power ground for DCD2.
14
GNDDCD2
GNDDCD1
SW1
15
Power ground for DCD1.
16
Switching node for DCD1, connect to one terminal of the inductor.
Exposed Pad. Connect to system ground.
E-PAD
E-PAD
Block Diagram
ANALOG/LOGIC
CIRCUIT INPUT
SHORT
CIRCUIT
VINDCD1
DCDPG
10µF
PROTECTION
1.5µH
SW1
FB1
DCD1
BUCK
10µF
CONVERTER
GNDDCD1
VINDCD2
PGOOD WITH
1~200ms
DELAY TIME
OVERCURRENT
PROTECTION
10µF
1.5µH
SW2
DCD2
10µF
FB2
UVLO
VREF
OSC
BUCK
CONVERTER
GNDDCD2
VINLDO1
VOLDO1
VINLDO2
THERMAL
SHUTDOWN
1µF
LDO1
300mA
10µF
SDAT
SCLK
I2C
INTERFACE
1µF
VOLDO2
GNDLDO
LDO2
300mA
10µF
FN7724.0
November 8, 2010
3
ISL9305H
Ordering Information
FBSEL
DCD1
(V)
FBSEL
DCD2
(V)
SLV
LDO1
(V)
SLV
LDO2
(V)
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL9305IRTHAANLZ-T 9305I HAANLZ
ISL9305IRTHWBNLZ-T 9305I HWBNLZ
ISL9305IRTHWCLBZ-T 9305I HWCLBZ
ISL9305IRTHWCNYZ-T 9305I HWCNYZ
ISL9305IRTHWCNLZ-T 9305I HWCNLZ
ISL9305IRTHWLNCZ-T 9305I HWLNCZ
ISL9305IRTHBCNLZ-T 9305I HBCNLZ
ISL9305IRTHBFNCZ-T 9305I HBFNCZ
NOTES:
Adj
1.2
1.2
1.2
1.2
1.2
1.5
1.5
Adj
1.5
1.8
1.8
1.8
2.9
1.8
2.5
3.3
3.3
2.9
3.3
3.3
3.3
3.3
3.3
2.9
2.9
1.5
0.9
2.9
1.8
2.9
1.8
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
16 Ld TQFN
L16.4x4G
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9305H. For more information on MSL please see techbrief TB363.
FN7724.0
November 8, 2010
4
ISL9305H
Absolute Maximum Ratings (Refer to ground)
Thermal Information
SW1, SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.6V
GNDDCD1, GNDDCD2, GNDLDO. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Ratings
Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . .3.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 2.2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . 225V
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
16 Ld TQFN Package (Notes 4, 5) . . . . . . .
Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C
Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
42
θ
(°C/W)
5
JA
JC
Recommended Operating Conditions
VINDCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
VINDCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to VINDCD1
VINLDO1 and VINLDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to VINDCD1
DCD1 and DCD2 Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.5A
LDO1 and LDO2 Output Current . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. θ , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the
typical specifications are measured at the following conditions: T = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For
A
LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH,
C1 = 10µF, C4 = C5 = 10µF, C2 = C3 = C6 = C7 = 1µF, IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see “TYPICAL
APPLICATION DIAGRAM” on page 1 for more details).
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNIT
VINDCD1, VINDCD2 Voltage Range
2.5
-
5.5
2.3
-
V
V
VINDCD1, VINDCD2 Undervoltage
Lockout Threshold
V
Rising
Falling
-
2.2
2.1
40
60
UVLO
1.9
V
Quiescent Supply Current on VINDCD1
I
I
Only DCD1 enabled, no load and no switching on DCD1
-
-
60
95
µA
µA
VIN1
VIN2
Only DCD1 and LDO1 enabled, with no load and no
switching on DCD1
I
Both DCD1 and DCD2 enabled, no load and no switching
on both DCD1 and DCD2
-
50
75
µA
VIN3
I
I
Only LDO1 and LDO2 enabled
-
-
75
100
130
µA
µA
VIN4
VIN5
DCD1, DCD2, LDO1 and LDO2 are enabled, with no load
and no switching on both DCD1 and DCD2
100
I
Only one DCD in forced PWM mode, no load
-
-
4
7.5
5
mA
µA
VIN6
Shutdown Supply Current
I
VINDCD1 = 5.5V, DCD1, DCD2, LDO1 and LDO2 are
0.15
SD
2
disabled through I C interface, VINDCD1 = 4.2V
Thermal Shutdown
-
-
155
30
-
-
°C
°C
Thermal Shutdown Hysteresis
DCD1 AND DCD2
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Output Voltage Accuracy
Line Regulation
V
0.785
0.8
0.001
-
0.815
V
µA
%
FB
I
FB = 0.75V
-
-3
-
-
+3
-
FB
V
V
= V + 0.5V to 5.5V (minimal 2.5V), 1mA load
O
IN
= V + 0.5V to 5.5V (minimal 2.5V)
0.1
%/V
IN
O
FN7724.0
November 8, 2010
5
ISL9305H
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the
typical specifications are measured at the following conditions: T = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For
A
LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH,
C1 = 10µF, C4 = C5 = 10µF, C2 = C3 = C6 = C7 = 1µF, IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see “TYPICAL
APPLICATION DIAGRAM” on page 1 for more details). (Continued)
MIN
MAX
PARAMETER
Maximum Output Current
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNIT
1500
-
-
mA
Ω
P-Channel MOSFET ON-resistance
V
V
V
V
= 3.6V, I = 200mA
-
-
-
0.14
0.24
0.11
0.18
2.5
0.20
0.40
0.20
0.34
2.75
-
IN
IN
IN
IN
O
= 2.3V, I = 200mA
Ω
O
N-Channel MOSFET ON-resistance
= 3.6V, I = 200mA
Ω
O
= 2.3V, I = 200mA
O
Ω
P-Channel MOSFET Peak Current Limit
SW Maximum Duty Cycle
SW Leakage Current
I
2.1
A
PK
-
100
0.005
3.0
%
V
V
= 5.5V
-
1
µA
MHz
ns
Ω
IN
PWM Switching Frequency
SW Minimum ON-time
Bleeding Resistor
f
2.6
3.4
-
S
= 0.75V
-
-
70
FB
115
-
PG
Output Low Voltage
Sinking 1mA, FB1 = FB2 = 0.7V
-
-
1.1
30
0.25
V
ms
µs
µA
%
Rising Delay Time
Based on 1ms programmed nominal delay time
Based on 1ms programmed nominal delay time
PG = VINDCD1 = VINDCD2 = 3.6V
0.6
1.8
Falling Delay Time
-
-
-
-
-
-
-
PG Pin Leakage Current
PG Low Rising Threshold
PG Low Falling Threshold
PG High Rising Threshold
PG High Falling Threshold
LDO1 AND LDO2
0.005
91
0.1
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
-
-
-
-
87
%
112
109
%
%
VINLDO1, VINLDO2 Supply Voltage
No higher than VINDCD1
1.5
-
5.5
1.46
-
V
VINLDO1, VINLDO2 Undervoltage
Lockout Threshold
V
Rising
Falling
-
1.41
1.37
425
120
100
80
V
UVLO
1.33
V
Internal Peak Current Limit
Dropout Voltage
350
540
250
200
170
-
mA
mV
mV
mV
dB
I
I
I
I
= 300mA, V ≤ 2.1V
-
-
-
-
-
O
O
O
O
O
= 300mA, 2.1V < V ≤ 2.8V
O
= 300mA, V > 2.8V
O
Power Supply Rejection Ratio
Output Voltage Noise
NOTE:
= 300mA @ 1kHz, V = 3.6V, V = 2.6V, T = +25°C
IN
55
O
A
V
= 4.2V, I = 10mA, T = +25°C, BW = 10Hz to 100kHz
45
-
µV
RMS
IN
O
A
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7724.0
November 8, 2010
6
ISL9305H
Theory of Operation
DCD1 and DCD2 Introduction
Both the DCD1 and DCD2 converters on ISL9305H use the
peak-current-mode pulse-width modulation (PWM) control scheme
for fast transient response and pulse-by-pulse current limiting.
Both converters are able to supply up to 1.5A load current. The
default output voltage ranges from 0.8V to 3.6V depending on the
vEAMP
vCSA
d
2
factory pre-set configuration and can be programmed via the I C
iL
interface in the range of 0.825V to 3.6V at 25mV/step with a
programmable slew rate. An open-drain DCDPG (DCD Power-Good)
signal is also provided to monitor the DCD1 and DCD2 output
voltages. Optionally, both DCD1 and DCD2 can be programmed to
be actively discharged via an on-chip bleeding resistor (typical
115Ω) when the converter is disabled.
vOUT
FIGURE 2. PWM OPERATION WAVEFORMS
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Skip Mode (PFM Mode) for DCD1/DCD2
Under light load condition, the DCD1 and DCD2 can be programmed
to automatically enter a pulse-skipping mode to minimize the
switching loss by reducing the switching frequency. Figure 3
illustrates the skip mode operation. A zero-cross sensing circuit
monitors the current flowing through SW node for zero crossing.
When it is detected to cross zero for 16 consecutive cycles, the
regulator enters the skip mode. During the 16 consecutive cycles,
the inductor current could be negative. The counter is reset to zero
when the sensed current flowing through SW node does not cross
zero during any cycle within the 16 consecutive cycles. Once the
converter enters the skip mode, the pulse modulation is controlled
by an internal comparator while each pulse cycle remains
synchronized to the PWM clock. The P-Channel MOSFET is turned on
at the rising edge of the clock and turned off when its current
reaches ~20% of the peak current limit. As the average inductor
current in each cycle is higher than the average current of the load,
the output voltage rises cycle-over-cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the P-Channel
MOSFET is turned off immediately and the inductor current is fully
discharged to zero and stays at zero. The output voltage reduces
gradually due to the load current discharging the output capacitor.
When the output voltage drops to the nominal voltage, the P-
Channel MOSFET will be turned on again, repeating the previous
operations.
Soft-Start
The soft-start reduces the in-rush current during the start-up stage.
The soft-start block limits the current rising speed so that the
output voltage rises in a controlled fashion.
Overcurrent Protection
The overcurrent protection for DCD1 and DCD2 is provided on
ISL9305H for when an overload condition occurs. When the current
at P-Channel MOSFET is sensed to reach the current limit, the
internal protection circuit is triggered to turn off the P-Channel
MOSFET immediately.
DCD Short-Circuit Protection
The ISL9305H provides Short-Circuit Protection for both DCD1 and
DCD2. The feedback voltage is monitored for output short-circuit
protection. When the output voltage is sensed to be lower than a
certain threshold, the internal circuit will change the PWM oscillator
frequency to a lower frequencies in order to protect the IC from
damage. The P-Channel MOSFET peak current limit remains active
during this state.
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
IL
0
1.015*VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 3. SKIP MODE OPERATION WAVEFORMS
FN7724.0
November 8, 2010
7
ISL9305H
Undervoltage Lockout (UVLO)
Active Output Voltage Discharge For
DCD1/DCD2
An undervoltage lockout (UVLO) circuit is provided on ISL9305H. The
UVLO circuit block can prevent abnormal operation in the event that
the supply voltage is too low to guarantee proper operation. The
UVLO on VINDCD1 is set for a typical 2.2V with 100mV hysteresis.
VINLDO1 and VINLDO2 are set for a typical 1.4V with 50mV
hysteresis. When the input voltage is sensed to be lower than the
UVLO threshold, the related channel is disabled.
The ISL9305H offers a feature to actively discharge the output
voltage of DCD1 and DCD2 via an internal bleeding resistor
(typical 115Ω) when the channel is disabled. This feature is
enabled by default, but can be individually outputs can be
disabled through programming the control bit in
DCD_PARAMETER register.
DCDPG (DCD Power-Good)
Thermal Shutdown
ISL9305H offers an open-drain Power-Good signal with
programmable delay time for monitoring the converters DCD1
and DCD2 output voltages status.
The ISL9305H provides built-in thermal protection function with
thermal shutdown threshold temperature set at +155°C with
+25°C hysteresis (typical). When the die temperature is sensed
to reach +130°C, the regulator is completely shut down and as
the temperature is sensed to drop to +105°C (typical), the device
resumes normal operation starting from the soft-start.
When both DCD1 and DCD2 are enabled and their output voltages
are within the power-good window, an internal power-good signal is
issued to turn off the open-drain MOSFET so the DCDPG pin voltage
can be externally pulled high after a programmed delay time. If
either DCD1 or DCD2 output voltages or both of them are not within
the power-good window, the DCDPG outputs an open-drain logic low
signal after the programmed delay time.
2
I C Compatible Interface
2
The ISL9305H offers an I C compatible interface, using two pins:
SCLK for the serial clock and SDAT for serial data respectively.
2
According to the I C specifications, a pull-up resistor is needed for
When there is only one DCD converter (either DCD1 or DCD2) is
enabled, then the DCDPG only indicates the status of this active
DCD converter. For example, if only DCD1 converter is enabled
and DCD2 converter is disabled, when DCD1 output is within the
power-good window, internal power-good signal will be issued to
turn off the open-drain MOSFET so the DCDPG pin voltage is
externally pulled high after the programmed delay time. If output
voltage of DCD1 is outside the power-good window, the DCDPG
outputs an open-drain logic low signal after the programmed
delay time. It is similar when only DCD2 is enabled and DCD1 is
disabled. When both converters are disabled, DCDPG always
outputs the open-drain logic low signal.
the clock and data signals to connect to a positive supply. When the
ISL9305 and the host use different supply voltages, the pull-up
resistors should be connected to the higher voltage rail.
2
Signal timing specifications should satisfy the standard I C bus
specification. The maximum bit rate is 400kb/s and more details
2
regarding the I C specifications can be found from Philips.
2
I C Slave Address
The ISL9305H serves as a slave device and the 7-bit default chip
2
address is 1101000, as shown in Figure 4. According to the I C
specifications, here the value of Bit 0 determines the direction of
the message (“0” means “write” and “1” means “read”).
Low Dropout Operation
MSB
LSB
Both DCD1 and DCD2 converters feature the low dropout operation
to maximize the battery life. When the input voltage drops to a level
that the converter can no longer operate under switching regulation
to maintain the output voltage, the P-Channel MOSFET is completely
turned on (100% duty cycle). The dropout voltage under such a
condition is the product of the load current and the ON-resistance of
1
1
0
1
0
0
0
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
the P-Channel MOSFET. Minimum required input voltage V under
IN
such condition is the sum of output voltage plus the voltage drop
across the inductor and the P-Channel MOSFET switch.
2
FIGURE 4. I C SLAVE ADDRESS
2
I C Protocol
Figures 5, 6, and 7 show three typical I C-bus transaction protocols.
2
FN7724.0
November 8, 2010
8
ISL9305H
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
DATA BYTE 1
A
SYSTEM HOST
ISL9305H
R/W
AUTO INCREMENT
REGISTER ADDRESS
OPTIONAL
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
DATA BYTE 2
A
DATA BYTE N
A
P
P – STOP
AUTO INCREMENT
AUTO INCREMENT
REGISTER ADDRESS
REGISTER ADDRESS
2
FIGURE 5. I C WRITE
S
SLAVE ADDRESS
0
A
A
REGISTER ADDRESS
A
S
SLAVE ADDRESS
1
A
SYSTEM HOST
ISL9305H
R/W
R/W
OPTIONAL
A
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
DATA BYTE 1
DATA BYTE 2
DATA BYTE N
N
P
P – STOP
AUTO INCREMENT
AUTO INCREMENT
AUTO INCREMENT
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
2
FIGURE 6. I C READ SPECIFYING REGISTER ADDRESS
OPTIONAL
S
SLAVE ADDRESS
1
A
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
N
P
AUTO INCREMENT
REGISTER ADDRESS
AUTO INCREMENT
REGISTER ADDRESS
AUTO INCREMENT
REGISTER ADDRESS
R/W
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
SYSTEM HOST
ISL9305H
P – STOP
2
FIGURE 7. I C READ NOT SPECIFYING REGISTER ADDRESS
FN7724.0
November 8, 2010
9
ISL9305H
2
TABLE 2. BUCK CONVERTERS OUTPUT VOLTAGE CONTROL REGISTER
I C Control Registers
BIT
All the registers are reset at initial start-up.
NAME
ACCESS
-
RESET
DESCRIPTION
B7 Reserve
0
0
0
1
0
0
0
0
Refer to Table 3
DCD OUTPUT VOLTAGE CONTROL REGISTER
B6 DCDxOUT-6
B5 DCDxOUT-5
B4 DCDxOUT-4
B3 DCDxOUT-3
B2 DCDxOUT-2
B1 DCDxOUT-1
B0 DCDxOUT-0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DCD1OUT, address 0x00h; DCD2OUT, address 0x01h
Caution: Disable DCD prior to changing from fixed output voltage
to adjustable output voltage or from adjustable output voltage to
2
fixed output voltage using I C.
Refer to Table 3
TABLE 3. DCD1 AND DCD2 OUTPUT VOLTAGE SETTING
DCD OUTPUT
VOLTAGE
(V)
DCD OUTPUT
VOLTAGE
(V)
DCD OUTPUT
VOLTAGE
(V)
DCD OUTPUT
VOLTAGE
(V)
DCDOUT
<7:0>
DCDOUT
<7:0>
DCDOUT
<7:0>
DCDOUT
<7:0>
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.225
2.250
2.275
2.300
2.325
2.350
2.375
2.400
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
2.425
2.450
2.475
2.500
2.525
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
3.025
3.050
3.075
3.100
3.125
3.150
3.175
3.200
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
3.550
3.575
3.600
FN7724.0
November 8, 2010
10
ISL9305H
LDO1 AND LDO2 OUTPUT VOLTAGE CONTROL
REGISTERS
TABLE 4. LDOX OUTPUT VOLTAGE CONTROL REGISTERS
BIT
NAME
ACCESS
-
RESET
DESCRIPTION
LDO1OUT, address 0x02h and LDO2OUT, address 0x03h.
B7 Reserve
0
0
0
0
1
1
0
0
Refer to Table 5 for
output voltage
settings
B6 Reserve
-
B5 LDOxOUT-5
B4 LDOxOUT-4
B3 LDOxOUT-3
B2 LDOxOUT-2
B1 LDOxOUT-1
B0 LDOxOUT-0
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 5. LDOX OUTPUT VOLTAGE SETTINGS
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<7:0>
LDO OUTPUT
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
VOLTAGE (V)
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0.9
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
3.30
3.35
3.40
3.45
3.50
3.55
3.60
0.95
1.00
1.05
1.1
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
FN7724.0
November 8, 2010
11
ISL9305H
DCD1 AND DCD2 CONTROL REGISTER
DCD OUTPUT VOLTAGE SLEW RATE CONTROL
REGISTER
DCD_PARAMETER, address 0x04h
DCD_SRCTL, address 0x06h
TABLE 6. DCD_PARAMETER REGISTER
TABLE 8. DCD OUPUT VOLTAGE SLEW RATE CONTROL
REGISTER
BIT
B7
NAME
-
ACCESS RESET
DESCRIPTION
Reserved
-
0
0
BIT
NAME
ACCESS RESET
DESCRIPTION
B6 DCD_PHASE R/W
DCD1 and DCD2 PWM switch
selection. 0-in phase; 1 to 180°
out-of-phase.
B7 DCD2SR_2 R/W
B6 DCD2SR_1 R/W
B5 DCD2SR_0 R/W
0
0
1
DCD2 Slew Rate Setting, DCD2SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
B5 DCD2_ULTRA R/W
B4 DCD1_ULTRA R/W
0
0
1
Ultrasonic feature under PFM mode
for DCD2. 0-disabled; 1-enabled.
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to immediate
Ultrasonic feature under PFM mode
for DCD1. 0-disabled; 1-enabled.
B3 DCD2_BLD
B2 DCD1_BLD
R/W
R/W
Selection of DCD2 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
B4 Reserve
-
0
0
0
1
Reserved
B3 DCD1SR_2 R/W
B2 DCD1SR_1 R/W
B1 DCD1SR_0 R/W
DCD1 Slew Rate Setting, DCD1SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
1
1
1
Selection of DCD1 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
B1 DCD2_MODE R/W
B0 DCD1_MODE R/W
Selection on DCD2 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to immediate
Selection on DCD1 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
B0 Reserve
-
0
Reserved
SYSTEM CONTROL REGISTER
SYS_PARAMETER, address 0x05h
TABLE 7. SYS_PARAMETER REGISTER
ACCESS RESET DESCRIPTION
BIT
B7
B6
NAME
-
-
0
Reserved
2
2
I C_EN
R/W
0
I C function enable. 0-disabled;
1-enabled
B5 DCDPOR_1 R/W
B4 DCDPOR_0 R/W
1
0
DCDPG Delay Time Setting,
DCDPG[1:0]:
00 to 1ms
01 to 50ms
10 to 150ms
11 to 200m
B3 LDO2_EN
B2 LDO1_EN
R/W
R/W
1
1
1
1
LDO2 enable selection. 0-disable,
1-enable.
LDO1 enable selection. 0-disable,
1-enable
B1 DCD2_EN R/W
B0 DCD1_EN R/W
DCD2 enable selection. 0-disable,
1-enable.
DCD2 enable selection. 0-disable,
1-enable
FN7724.0
November 8, 2010
12
ISL9305H
Typical Operating Conditions
FIGURE 8. DCD OUTPUT RIPPLE (V = 4.2V, PFM, TIME SCALE = 1µs)
IN
FIGURE 9. DCD OUTPUT RIPPLE (V = 4.2V, FULL LOADING @
IN
CH1: VODCD1 (20mV/DIV), CH2: IL1 (500mA/DIV),
CH3: VODCD2 (20mV/DIV), CH4: IL2 (500mA/DIV)
VODCD1 AND VODCD2, TIME SCALE = 200ns)
CH1: SW1 (5V/DIV), CH2: VODCD1 (20mA/DIV),
CH3: SW2 (5V/DIV), CH4: VODCD2 (20mA/DIV)
FIGURE 10. INDUCTOR CURRENT RIPPLE (V = 3.6V, PFM,
IN
FIGURE 11. INDUCTOR CURRENT RIPPLE (V = 3.6V, FULL LOADING,
IN
TIME SCALE = 200ns) CH1: SW1 (2V/DIV),
CH2: IL1 (200mA/DIV), CH3: SW2 (2V/DIV),
CH4: IL2 (200mA/DIV)
PWM, TIME SCALE = 200ns) CH1: SW1 (2V/DIV),
CH2: IL1 (500mA/DIV), CH3: SW2 (2V/DIV),
CH4: IL2 (500mA/DIV)
FIGURE 12. DCD1 TRANSIENT RESPONSE (V = 3.6V, STEP LOAD:
IN
FIGURE 13. DCD2 TRANSIENT RESPONSE (V = 3.6V, STEP LOAD:
IN
150mA TO 1500mA) CH1: VODCD1 (100mV/DIV, AC),
150mA TO 1500mA) CH1: VODCD1 (100mV/DIV, AC),
CH2: VODCD2 (50mV/DIV, AC, CH4: IL4 (500mA/DIV)
CH2: VODCD2 (50mV/DIV, AC, CH4: IL4 (500mA/DIV)
FN7724.0
November 8, 2010
13
ISL9305H
Typical Operating Conditions(Continued)
FIGURE 14. 4-CHANNEL DEFAULT START-UP @ NO LOAD
CH1: VODCD1 (2V/DIV), CH2: VODCD2 (1V/DIV),
CH3: VOLDO1 (1V/DIV), CH4: VOLDO2 (2V/DIV)
FIGURE 15. 4-CHANNEL DEFAULT START-UP @ FULL LOAD
CH1: VODCD1 (2V/DIV), CH2: VODCD2 (1V/DIV),
CH3: VOLDO1 (1V/DIV), CH4: VOLDO2 (2V/DIV)
90
80
70
100
90
80
70
V
= 3.6V
V
= 2.8V
IN
IN
V
= 5.5V
IN
60
50
40
30
V
= 5.5V
V
= 3.6V
V
= 2.8V
IN
IN
IN
60
50
40
30
1
10
100
OUTPUT CURRENT (mA)
1000
10000
1
10
100
OUTPUT CURRENT (mA)
1000
10000
FIGURE 16. EFFICIENCY vs LOAD (V
= 1.8V, PFM/PWM)
FIGURE 17. EFFICIENCY vs LOAD (V
= 1.2V, FORCED PWM)
OUT
OUT
1.23
1.22
1.21
1.20
1.83
1.82
1.81
1.80
V
= 5.5V
V
= 3.6V
IN
IN
V
= 3.6V
V
= 2.8V
V
= 5.5V
IN
IN
1.79
1.78
1.77
1.76
IN
V
= 2.8V
IN
1.19
1.18
1.17
1
10
100
OUTPUT CURRENT (mA)
1000
10000
1
10
100
OUTPUT CURRENT (mA)
1000
10000
FIGURE 18. DCD OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 19. DCD OUTPUT VOLTAGE vs OUTPUT CURRENT
(V = 1.2V, PFM/PWM)
(V
= 1.8V, PFM/PWM)
OUT
OUT
FN7724.0
November 8, 2010
14
ISL9305H
Typical Operating Conditions(Continued)
70
60
50
40
30
20
10
0
58
56
54
52
50
48
46
44
42
40
+85°C
+25°C
-40°C
PSRR
V
V
= 3.6V
IN
V
= 1.2V
O
= 2.6V
OUT
DCD1 = DCD2 = NO SWITCHING, NO LOAD
LDO1 = LDO2 = DISABLED
LOAD = 300mA
0.1
1
10
100
1000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (kHz)
INPUT VOLTAGE (V)
FIGURE 20. RIPPLE REJECTION RATIO vs FREQUENCY
FIGURE 21. QUIESCENT CURRENT vs INPUT VOLTAGE
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7724.0
CHANGE
11/8/10
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL9305H
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7724.0
November 8, 2010
15
ISL9305H
Package Outline Drawing
L16.4x4G
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/10
4X
1.95
4.00
0.65
12X
A
6
B
13
16
PIN #1
INDEX AREA
6
PIN 1
INDEX AREA
1
12
2 . 10 ± 0 . 10
9
4
(4X)
0.15
8
5
0.10 M C A B
0.30 ± 0.05
16X 0 . 50 ± 0 . 1
TOP VIEW
4
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0.75
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 3 . 6 TYP )
(
( 12X 0 . 65 )
2 . 10 )
5
0 . 2 REF
C
( 16X 0 . 30 )
( 16 X 0 . 70 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
JEDEC reference drawing: MO220K.
7.
FN7724.0
November 8, 2010
16
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3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface
RENESAS
ISL9305IRTHWLNCZEV1Z
3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface
RENESAS
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