ISL9011AIRMNZ_技术文档

ISL9011A

®

Data Sheet

January 30, 2007

FN6437.0

Dual LDO with Low Noise, Low I , and

Q

Features

High PSRR

• Integrates two high performance LDOs

- VO1 - 150mA output

ISL9011A is a high performance dual LDO capable of

sourcing 150mA current from Channel 1 and 300mA from

Channel 2. The device has a low standby current and high-

PSRR and is stable with output capacitance of 1μF to 10μF

with ESR of up to 200mΩ.

- VO2 - 300mA output

• Excellent transient response to large current steps

• Excellent load regulation: <1% voltage change across full

range of load current

A reference bypass pin allows an external capacitor for

adjusting a noise filter for low noise and high PSRR

applications.

• High PSRR: 70dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Extremely low quiescent current: 45µA (both LDOs active)

• Low dropout voltage: typically 120mV @ 150mA

The quiescent current is typically only 45µA with both LDO’s

enabled and active. Separate enable pins control each

individual LDO output. When both enable pins are low, the

device is in shutdown, typically drawing less than 0.1μA.

• Low output noise: typically 30µV

RMS

@ 100µA (1.5V)

• Stable with 1µF to 10µF ceramic capacitors

• Separate enable pins for each LDO

Several combinations of voltage outputs are standard.

Others are available on request. Output voltage options for

each LDO range from 1.2V to 3.6V.

• Soft-start to limit input current surge during enable

• Current limit and overheat protection

Pinout

ISL9011A

(10 LD 3x3 DFN)

TOP VIEW

• ±1.8% accuracy over all operating conditions

• Tiny 10 Ld 3mmx3mm DFN package

• -40°C to +85°C operating temperature range

• Pin compatible with Micrel MIC2211

1

2

3

4

5

10 VO1

VIN

EN1

9

8

7

6

VO2

NC

• Pb-free plus anneal available (RoHS compliant)

EN2

NC

CBYP

NC

Applications

GND

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3 Players

• Handheld Devices including Medical Handhelds

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL9011A

Ordering Information

PART NUMBER

VO1 VOLTAGE VO2 VOLTAGE

PACKAGE

(Pb-free)

(Notes 1, 2, 3)

ISL9011AIRNNZ

ISL9011AIRNJZ

ISL9011AIRNFZ

ISL9011AIRNCZ

ISL9011AIRMNZ

ISL9011AIRMMZ

ISL9011AIRMGZ

ISL9011AIRLLZ

ISL9011AIRKNZ

ISL9011AIRKKZ

ISL9011AIRKJZ

ISL9011AIRKFZ

ISL9011AIRKPZ

ISL9011AIRKCZ

ISL9011AIRJNZ

ISL9011AIRJMZ

ISL9011AIRJRZ

ISL9011AIRJCZ

ISL9011AIRJBZ

ISL9011AIRGPZ

ISL9011AIRGCZ

ISL9011AIRFJZ

ISL9011AIRFDZ

ISL9011AIRFCZ

ISL9011AIRPLZ

ISL9011AIRPPZ

ISL9011AIRCJZ

ISL9011AIRCCZ

ISL9011AIRBLZ

ISL9011AIRBJZ

ISL9011AIRBCZ

ISL9011AIRBBZ

NOTES:

PART MARKING

(V)

3.3

2.8

2.5

1.8

3.3

3.0

2.7

2.9

3.3

2.85

2.8

2.5

1.85

1.8

3.3

3.0

2.6

1.8

1.5

1.85

1.8

2.8

2.0

1.8

2.9

1.85

2.8

1.8

2.9

2.8

1.8

1.5

TEMP RANGE (°C)

-40 to +85

PKG. DWG. #

L10.3x3C

DGPA

DGNA

DGMA

DGLA

DGKA

DGJA

DGHA

DGGA

DGEA

DGDA

DGCA

DGBA

DGFA

DFYA

DFVA

DFTA

DWFA

DFSA

DFRA

DFPA

DFNA

DFMA

DFLA

DFKA

DGRA

DGSA

DFJA

DFHA

DFGA

DFFA

DFEA

DFDA

3.3

10 Ld 3x3 DFN

3.3

L10.3x3C

3.3

3.0

2.9

2.85

2.8

2.7

2.5

1.85

1.8

1.5

1. Add -T to part number for tape and reel.

2. For availability and lead time of devices with voltage combinations not listed in the table, contact Intersil Marketing.

3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN6437.0

January 30, 2007

2

ISL9011A

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

Thermal Resistance (Notes 4, 5)

θ

(°C/W)

50

θ

(°C/W)

10

JA

JC

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V +0.3)V

IN

3x3 DFN Package . . . . . . . . . . . . . . . .

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Recommended Operating Conditions

Ambient Temperature Range (T ) . . . . . . . . . . . . . . .-40°C to +85°C

A

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

5. θ , “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

JC

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T = -40°C to +85°C; V = (V +1.0V) to 6.5V with a minimum V of 2.3V;

A

IN

O

IN

C

= 1μF; C = 1μF; C

BYP

= 0.01μF

IN

O

PARAMETER

DC CHARACTERISTICS

Supply Voltage

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

2.3

6.5

V

IN

Ground Current

Quiescent condition: I = 0µA; I = 0µA

O1 O2

I

One LDO active

Both LDO active

@ +25°C

25

45

40

60

µA

V

DD1

DD2

DDS

I

Shutdown Current

UVLO Threshold

I

0.1

2.1

1.8

1.0

2.3

2.0

+1.8

V

1.9

1.6

UV+

V

UV-

Regulation Voltage Accuracy

Variation from nominal voltage output, V = V +0.5 to 5.5V,

IN

-1.8

%

O

T = -40°C to +125°C

J

Line Regulation

Load Regulation

V

= (V

+1.0V relative to highest output voltage) to 5.5V

OUT

-0.2

0

0.2

0.7

1.0

%/V

%

IN

I

= 100µA to 150mA (VO1 and VO2)

= 100µA to 300mA (VO2)

0.1

OUT

%

Maximum Output Current

I

VO1: Continuous

VO2: Continuous

150

300

350

mA

mV

°C

MAX

Internal Current Limit

I

V

T

475

125

300

250

200

145

110

600

200

500

400

325

LIM

Dropout Voltage (Note 6)

I

= 150mA; V > 2.1V (VO1)

O

DO1

DO2

DO3

DO4

SD+

O

= 300mA; V < 2.5V (VO2)

O

= 300mA; 2.5V ≤ V ≤ 2.8V (VO2)

O

= 300mA; V > 2.8V (VO2)

O

Thermal Shutdown Temperature

T

°C

SD-

AC CHARACTERISTICS

Ripple Rejection

I

= 10mA, V = 2.8V(min), V = 1.8V, C

IN

= 0.1μF

BYP

O

@ 1kHz

70

55

40

30

dB

@ 10kHz

@ 100kHz

Output Noise Voltage

I

= 100μA, V = 1.5V, T = +25°C, C

= 0.1μF

µV

RMS

O

A

BYP

BW = 10Hz to 100kHz

FN6437.0

January 30, 2007

3

ISL9011A

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T = -40°C to +85°C; V = (V +1.0V) to 6.5V with a minimum V of 2.3V;

A

IN

O

IN

C

= 1μF; C = 1μF; C

= 0.01μF (Continued)

IN

SYMBOL

DEVICE START-UP CHARACTERISTICS

O

BYP

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Device Enable TIme

t

Time from assertion of the ENx pin to when the output voltage

reaches 95% of the VO(nom)

250

30

500

60

µs

EN

LDO Soft-Start Ramp Rate

t

Slope of linear portion of LDO output voltage ramp during start-

up

µs/V

SSR

EN1, EN2 PIN CHARACTERISTICS

Input Low Voltage

V

-0.3

1.4

0.5

V

IL

Input High Voltage

Input Leakage Current

Pin Capacitance

V

+0.3

IH

IN

I , I

IL IH

0.1

µA

pF

C

Informative

5

NOTE:

6. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V.

FN6437.0

January 30, 2007

4

ISL9011A

Typical Performance Curves

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

0.8

0.6

0.4

V

= 3.8V

= 3.3V

V

I

= 3.3V

IN

O

= 0mA

LOAD

0.2

-40°C

+25°C

0.0

-0.2

+25°C

+85°C

-0.4

-0.6

-0.8

+85°C

0

50

100

150

200

250

300

350

400

3.4

3.8

4.2

4.6

5.0

5.4

5.8

6.2

6.6

LOAD CURRENT - I (mA)

O

INPUT VOLTAGE (V)

FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE

(3.3V OUTPUT)

FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT

3.4

0.10

V

= 3.8V

= 3.3V

IN

O

V

1 = 3.3V

O

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

I

= 0mA

O

3.3

3.2

3.1

3.0

2.9

2.8

I

= 0mA

LOAD

I

= 150mA

O

-0.08

-0.10

3.1

3.6

4.1

4.6

5.1

5.6

6.1

6.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

INPUT VOLTAGE (V)

FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE

FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE

(V 1 = 3.3V)

O

2.9

350

300

250

200

150

100

50

V

2 = 2.8V

O

I

= 0mA

O

2.8

2.7

2.6

2.5

2.4

2.3

V

2 = 2.8V

O

I

= 150mA

O

I

= 300mA

O

V

1 = 3.3V

200

O

0

2.6

3.1

3.6

4.1

4.6

5.1

5.6

6.1 6.5

0

50

100

150

250

300

350

400

INPUT VOLTAGE (V)

OUTPUT LOAD (mA)

FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE

(V 2 = 2.8V)

FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT

O

FN6437.0

January 30, 2007

5

ISL9011A

Typical Performance Curves (Continued)

55

50

45

40

35

30

25

175

V

1 = 3.3V

O

150

125

100

75

+125°C

+25°C

+85°C

+25°C

-40°C

50

V

1 = 3.3V

2 = 2.8V

O

25

I

(BOTH CHANNELS) = 0µA

O

0

3.0

3.5

4.0

4.58

5.0

5.5

6.0

6.5

0

25

50

75

100

125

150

175

200

OUTPUT LOAD (mA)

INPUT VOLTAGE (V)

FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT

FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE

55

200

180

160

50

45

40

35

+85°C

140

120

+25°C

100

80

-40°C

60

40

V

= 3.8V

= 3.3V

IN

O

V

= 3.8V

1 = 3.3V

2 = 2.8V

IN

30

25

O

I

= 0µA

20

0

LOAD

BOTH OUTPUTS ON

0

50

100

150

200

250

300

350

400

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

LOAD CURRENT (mA)

FIGURE 10. GROUND CURRENT vs TEMPERATURE

FIGURE 9. GROUND CURRENT vs LOAD

V

1 = 3.3V

2 = 2.8V

V 2 (10mV/DIV)

O

5

I 1 = 150mA

L

V

= 5.0V

1 = 3.3V

2 = 2.8V

IN

O

VIN

IN

I 2 = 300mA

L

3

2

1

0

5

0

4

3

2

1

0

VO1

O1

I 1 = 150mA

L

I 2 = 300mA

L

C -1, C -2 = 1µF

L

VO2

O

C

= 0.01µF

BYP

0

100 200 300 400 500 600 700 800 900 1000

TIME (µs)

0

1

2

3

4

5

6

7

8

9

10

TIME (s)

FIGURE 12. TURN-ON/TURN-OFF RESPONSE

FIGURE 11. POWER-UP/POWER-DOWN

FN6437.0

January 30, 2007

6

ISL9011A

Typical Performance Curves (Continued)

VO1 = 3.3V

VO2 = 2.8V

O

I

= 150mA

I

= 300mA

LOAD

C

= 1μF

C

= 1µF

LOAD

= 0.01μF

LOAD

= 0.01µF

BYP

4.3V

3.6V

4.2V

3.5V

10mV/DIV

400μs/DIV

400µs/DIV

FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT

FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT

100

V

= 3.6V

= 1.8V

IN

O

90

80

70

60

50

40

30

20

10

0

I

= 10mA

O

V

(25mV/DIV)

O

C

= 0.1μF

BYP

= 1μF

LOAD

V

= 1.8V

= 2.8V

O

IN

300mA

I

LOAD

100μA

0.1

1k

10k

100k

1M

100μs/DIV

FREQUENCY (Hz)

FIGURE 15. LOAD TRANSIENT RESPONSE

FIGURE 16. PSRR vs FREQUENCY

1000

100

10

V

= 3.6V

= 1.8V

IN

O

I

= 10mA

LOAD

C

= 0.1μF

1

BYP

= 1μF

IN

= 1μF

LOAD

0.1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY

FN6437.0

January 30, 2007

7

ISL9011A

Pin Descriptions

PIN #

NAME

TYPE

DESCRIPTION

1

VIN

Analog I/O

Supply Voltage/LDO Input:

Connect a 1µF capacitor to GND.

2

3

4

EN1

EN2

Low Voltage Compatible

CMOS Input

LDO-1 Enable.

Low Voltage Compatible

CMOS Input

LDO-2 Enable.

CBYP

Analog I/O

Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01μF to 1μF

between this pin and GND to tune in the desired noise and PSRR performance.

5, 7, 8

NC

GND

VO2

VO1

NC

No Connection

6

9

Ground

GND is the connection to system ground. Connect to PCB Ground plane.

LDO-2 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

LDO-1 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

Analog I/O

10

Typical Application

ISL9011A

10

9

1

2

VIN (2.3V to 6.5V)

ON

VOUT 1

VOUT 2

VIN

VO1

VO2

EN1

ENABLE 1

ON

OFF

8

7

3

4

EN2

NC

ENABLE 2

OFF

CBYP

6

5

NC

GND

C1

C2

C3

C4

C1, C3, C4: 1µF X5R ceramic capacitor

C2: 0.1µF X5R ceramic capacitor

FN6437.0

January 30, 2007

8

ISL9011A

Block Diagram

VIN

IS1

LDO

VREF

TRIM

VO1

VO2

ERROR

1V

VO1

AMPLIFIER

QEN1

~1.0V

LDO-1

LDO-2

EN1

EN2

CONTROL

LOGIC

BANDGAP AND

TEMPERATURE

SENSOR

VOLTAGE

REFERENCE

GENERATOR

1.00V

UVLO

GND

CBYP

mode. During this condition, all on-chip circuits are off, and

the device draws minimum current, typically less than 0.1μA.

When one or both of the enable pins are asserted, the

device first polls the output of the UVLO detector to ensure

that VIN voltage is at least about 2.1V. Once verified, the

device initiates a start-up sequence. During the start-up

sequence, trim settings are first read and latched. Then,

sequentially, the bandgap, reference voltage and current

generation circuitry power-up. Once the references are

stable, a fast-start circuit quickly charges the external

reference bypass capacitor (connected to the CBYP pin) to

the proper operating voltage. After the bypass capacitor has

been charged, the LDO’s power-up.

Functional Description

The ISL9011A contains all circuitry required to implement

two high performance LDOs. High performance is achieved

through a circuit that delivers fast transient response to

varying load conditions. In a quiescent condition, the

ISL9011A adjusts its biasing to achieve the lowest standby

current consumption.

The device also integrates current limit protection, smart

thermal shutdown protection, staged turn-on and soft-start.

Smart Thermal shutdown protects the device against

overheating. Staged turn-on and soft-start minimize start-up

input current surges without causing excessive device turn-

on time.

If EN1 is brought high, and EN2 goes high before the VO1

output stabilizes, the ISL9011A delays the VO2 turn-on until

the VO1 output reaches its target level.

Power Control

The ISL9011A has two separate enable pins (EN1 and EN2)

to individually control power to each of the LDO outputs.

When both EN1 and EN2 are low, the device is in shutdown

If EN2 is brought high, and EN1 goes high before VO2 starts

its output ramp, then VO1 turns on first and the ISL9011A

FN6437.0

January 30, 2007

9

ISL9011A

delays the VO2 turn-on until the VO1 output reaches its

target level.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain

operational amplifier driving a PMOS pass transistor. The

design of the ISL9011A provides a regulator that has low

quiescent current, fast transient response, and overall

stability across all operating and load current conditions.

LDO stability is guaranteed for a 1μF to 10μF output

capacitor that has a tolerance better than 20% and ESR less

than 200mΩ. The design is performance-optimized for a 1μF

capacitor. Unless limited by the application, use of an output

capacitor value above 4.7μF is not recommended as LDO

performance improvement is minimal.

If EN2 is brought high, and EN1 goes high after VO2 starts

its output ramp, then the ISL9011A immediately starts to

ramp up the VO1 output.

If both EN1 and EN2 are brought high at the same time, the

VO1 output has priority, and is always powered up first.

During operation, whenever the VIN voltage drops below

about 1.8V, the ISL9011A immediately disables both LDO

outputs. When VIN rises back above 2.1V, the device re-

initiates its start-up sequence and LDO operation will

resume automatically.

Soft-start circuitry integrated into each LDO limits the initial

ramp-up rate to about 30μs/V to minimize current surge. The

ISL9011A provides short-circuit protection by limiting the

output current to about 475mA.

Reference Generation

The reference generation circuitry includes a trimmed

bandgap, a trimmed voltage reference divider, a trimmed

current reference generator, and an RC noise filter. The filter

includes the external capacitor connected to the CBYP pin.

A 0.01μF capacitor connected CBYP implements a 100Hz

lowpass filter, and is recommended for most high

Each LDO uses an independently trimmed 1V reference. An

internal resistor divider drops the LDO output voltage down

to 1V. This is compared to the 1V reference for regulation.

The resistor division ratio is programmed in the factory.

performance applications. For the lowest noise application, a

0.1μF or greater CBYP capacitor should be used. This filters

the reference noise to below the 10Hz to 1kHz frequency

band, which is crucial in many noise-sensitive applications.

Overheat Detection

The bandgap outputs a proportional-to-temperature current

that is indicative of the temperature of the silicon. This

current is compared with references to determine if the

device is in danger of damage due to overheating. When the

die temperature reaches about +145°C, one or both of the

LDO’s momentarily shut down until the die cools sufficiently.

In the overheat condition, only the LDO sourcing more than

50mA will be shut off. This does not affect the operation of

the other LDO. If both LDOs source more than 50mA and an

overheat condition occurs, both LDO outputs are disabled.

Once the die temperature falls back below about +110°C,

the disabled LDO(s) are re-enabled and soft-start

The bandgap generates a zero temperature coefficient (TC)

voltage for the reference divider. The reference divider

provides the regulation reference and other voltage

references required for current generation and

over-temperature detection.

The current generator outputs references required for

adaptive biasing as well as references for LDO output

current limit and thermal shutdown determination.

automatically takes place.

FN6437.0

January 30, 2007

10

ISL9011A

Dual Flat No-Lead Plastic Package (DFN)

L10.3x3C

2X

0.10 C

A

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

A

D

MILLIMETERS

2X

0.10

C B

SYMBOL

MIN

0.85

-

NOMINAL

0.90

MAX

0.95

0.05

NOTES

A

A1

A3

b

-

E

0.20 REF

0.25

-

6

INDEX

AREA

0.20

2.33

1.59

0.30

2.43

1.69

5, 8

D

3.00 BSC

2.38

-

TOP VIEW

B

A

D2

E

7, 8

3.00 BSC

1.64

-

// 0.10

0.08

C

E2

e

7, 8

C

0.50 BSC

-

A3

C

SIDE VIEW

k

0.20

0.35

-

SEATING

PLANE

L

0.40

0.45

8

N

10

2

D2

D2/2

2

7

8

(DATUM B)

Nd

5

3

Rev. 1 4/06

1

6

NOTES:

INDEX

AREA

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

NX k

E2

(DATUM A)

3. Nd refers to the number of terminals on D.

E2/2

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

NX L

N

N-1

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX b

8

e

5

(Nd-1)Xe

REF.

M

0.10

C A B

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

BOTTOM VIEW

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

C

L

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

(A1)

NX (b)

L

9

5

e

SECTION "C-C"

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C C

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6437.0

January 30, 2007

11


型号：	ISL9011AIRMNZ
厂家：	Intersil
描述：	Dual LDO with Low Noise, Low IQ, and High PSRR 双路LDO具有低噪声，低智商，和高PSRR 调节器光电二极管输出元件
文件：	总11页 (文件大小：208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL9011AIRMNZ [INTERSIL]

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