ISL84522IBZ [INTERSIL]
Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches; 低电压，单电源和双电源，四路SPST ，模拟开关
| 型号： | ISL84522IBZ |
| 厂家： | 
Intersil |
| 描述： | Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches |
| 文件： | 总12页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84521, ISL84522, ISL84523
®
Data Sheet
August 2004
FN6031.3
Low-Voltage, Single and Dual Supply,
Quad SPST, Analog Switches
Features
• Drop-in Replacements for MAX4521 - MAX4523
• Four Separately Controlled SPST Switches
• Pin Compatible with DG411, DG412, DG413
The Intersil ISL84521, ISL84523, ISL84523 devices are
CMOS, precision, quad analog switches designed to operate
from a single +2V to +12V supply or from a ±2V to ±6V supply.
Targeted applications include battery powered equipment that
benefit from the devices’ low power consumption (<1µW), low
leakage currents (1nA max), and fast switching speeds
• ON Resistance (R
Max.) . . . . . . . . . . . . . . . . . . . 100Ω
Matching Between Channels. . . . . . . . . . . . . . . . . .<1Ω
ON
• R
ON
(t
= 45ns, t
= 15ns). A12Ω maximum R flatness
• Low Power Consumption (P ) . . . . . . . . . . . . . . . . . . . .<1µW
ON
OFF
ON
D
ensures signal fidelity, while channel-to-channel mismatch is
guaranteed to be less than 4Ω.
• Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA
• Fast Switching Action
The ISL84521, ISL84522, ISL84523 are quad
single-pole/ single-throw (SPST) devices. The ISL84521 has
four normally closed (NC) switches; the ISL84522 has four
normally open (NO) switches; the ISL84523 has two NO and
two NC switches and can be used as a dual SPDT, or a dual
2:1 multiplexer.
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
OFF
• Break before Make Timing
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
Table summarizes the performance of this family. For higher
performance, pin compatible versions and 3mm x 3mm Quad
No-Lead Flatpack (QFN) package see the ISL43140,
ISL43142 data sheet.
• Pb-free available
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
TABLE 1. FEATURES AT A GLANCE
ISL84521
4
ISL84522
4
ISL84523
4
- Pagers
Number of Switches
Configuration
- Laptops, Notebooks, Palmtops
All NC
65Ω
All NO
65Ω
2 NC/2 NO
65Ω
• Communications Systems
- Military Radios
±5V R
ON
- RF “Tee” Switches
±5V t /t
ON OFF
45ns/15ns
125Ω
45ns/15ns
125Ω
45ns/15ns
125Ω
• Test Equipment
- Ultrasound
5V R
ON
5V t /t
60ns/20ns
260Ω
60ns/20ns
260Ω
60ns/20ns
260Ω
ON OFF
3V R
- Electrocardiograph
ON
• Heads-Up Displays
3V t /t
120ns/40ns 120ns/40ns 120ns/40ns
16 Ld SOIC (N), 16 Ld TSSOP
ON OFF
• Audio and Video Switching
Packages
• General Purpose Circuits
- +3V/+5V DACs and ADCs
- Digital Filters
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84521, ISL84522, ISL84523
Pinouts (Note 1)
ISL84521 (SOIC, TSSOP)
ISL84522 (SOIC, TSSOP)
TOP VIEW
TOP VIEW
IN1
COM1
NC1
V-
1
2
3
4
5
6
7
8
16 IN2
IN1
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NC2
13 V+
COM1
NO1
V-
15 COM2
14 NO2
13 V+
GND
NC4
COM4
IN4
12 N.C.
11 NC3
10 COM3
GND
NO4
COM4
IN4
12 N.C.
11 NO3
10 COM3
9
IN3
9
IN3
ISL84523 (SOIC, TSSOP)
TOP VIEW
IN1
COM1
NO1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NC2
13 V+
GND
NO4
COM4
IN4
12 N.C.
11 NC3
10 COM3
9
IN3
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
Ordering Information
TEMP.
ISL84521
SW 1, 2, 3, 4
On
ISL84522
ISL84523
RANGE
o
PKG.
DWG. #
LOGIC
SW 1, 2, 3, 4
SW 1, 4 SW 2, 3
PART NO.
ISL84521IB
( C)
PACKAGE
0
1
Off
On
Off
On
On
Off
-40 to 85 16 Ld SOIC (N)
M16.15
ISL84521IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL84521IV -40 to 85 16 Ld TSSOP M16.173
ISL84521IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ISL84522IB -40 to 85 16 Ld SOIC (N) M16.15
ISL84522IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL84522IV -40 to 85 16 Ld TSSOP M16.173
ISL84522IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ISL84523IB -40 to 85 16 Ld SOIC (N) M16.15
ISL84523IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ISL84523IV -40 to 85 16 Ld TSSOP M16.173
Off
NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.
Pin Descriptions
PIN
V+
V-
FUNCTION
Positive Power Supply Input
Negative Power Supply Input. Connect to GND for
Single Supply Configurations.
GND
IN
Ground Connection
Digital Control Input
ISL84523IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
No Internal Connection
*Add “-T” suffix to part number for tape and reel packaging.
NOTE:
2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die
attach materials and 100% matte tin plate termination finish, which is compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
NC
N.C.
2
ISL84521, ISL84522, ISL84523
Absolute Maximum Ratings
Thermal Information
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
All Other Pins (Note 3). . . . . . . . . . . . . .((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
Thermal Resistance (Typical, Note 4)
θ
( C/W)
JA
16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
115
150
o
Maximum Junction Temperature (Plastic Package). . . . . . . . 150 C
Moisture Sensitivity (See Technical Brief TB363)
All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Storage Temperature Range . . . . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . > 2kV
o
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL8452XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications +5V Supply
Test Conditions: V
Unless Otherwise Specified
= ±4.5V to ±5.5V, GND = 0V, V
= 2.4V, V
= 0.8V (Note 5),
SUPPLY
INH
INL
TEMP (NOTE 6)
(NOTE 6)
MAX
o
PARAMETER
TEST CONDITIONS
( C)
MIN
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
V-
-
-
V+
100
125
4
V
Ω
ON Resistance, R
ON
V
V
V
V
= ±5V, I
= 1.0mA, V
COM NO
or V
NC
= ±3V (Figure 5)
65
S
S
S
S
Full
25
-
-
Ω
R
Matching Between Channels,
= ±5V, I
= ±5V, I
= 1.0mA, V
= 1.0mA, V
or V
or V
= ±3V
-
1
Ω
ON
∆R
COM
COM
NO
NO
NC
NC
ON
Flatness, R
Full
25
-
-
6
Ω
R
= ±3V (Note 8)
-
7
12
15
1
Ω
ON
FLAT(ON)
Full
25
-
-
Ω
NO or NC OFF Leakage Current,
or I
= ±5.5V, V
= ±4.5V, V
= ±4.5V, V
or V
= +4.5V
= +4.5V
-1
-10
-1
-10
-2
-20
0.01
nA
nA
nA
nA
nA
nA
COM
COM
NO
NC
I
(Note 7)
NO(OFF)
NC(OFF)
Full
25
-
0.01
-
10
1
COM OFF Leakage Current,
V
= ±5.5V, V
or V
S
NO
NC
I
(Note 7)
COM(OFF)
Full
25
10
2
COM ON Leakage Current,
V
= ±5.5V, V
= V
or V = ±4.5V (Note 7)
NC
0.01
-
S
COM
NO
I
COM(ON)
Full
20
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V
= ±5.5V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
S
V
V
= ±4.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
45
-
80
100
30
40
-
ns
ns
ns
ns
ns
ON
S
NO
NC
L
L
= 0 to 3V (Figure 1)
IN
Turn-OFF Time, t
V
V
= ±4.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
-
15
-
OFF
S
NO
NC
L
L
= 0 to 3V (Figure 1)
IN
Full
25
-
Break-Before-Make Time Delay
(ISL84523), t
V
V
= ±5.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
5
20
S
NO
NC
L
L
= 0 to 3V (Figure 3)
D
IN
Charge Injection, Q
C
= 1.0nF, V = 0V, R = 0Ω (Figure 2)
25
25
25
-
-
-
1
2
2
5
-
pC
pF
pF
L
G
G
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= 0V (Figure 7)
= 0V (Figure 7)
OFF
NO
NC
COM
COM
COM OFF Capacitance,
= V
-
NO
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V (Figure 7)
25
-
5
-
pF
COM(ON)
NO
NC
COM
3
ISL84521, ISL84522, ISL84523
Electrical Specifications +5V Supply
Test Conditions: V
Unless Otherwise Specified (Continued)
= ±4.5V to ±5.5V, GND = 0V, V
= 2.4V, V
= 0.8V (Note 5),
SUPPLY
INH
INL
TEMP (NOTE 6)
(NOTE 6)
MAX
o
PARAMETER
TEST CONDITIONS
( C)
MIN
TYP
>90
UNITS
dB
OFF Isolation
R
= 50Ω, C = 15pF, f = 100kHz,
25
-
-
-
-
L
L
V
or V
= 1V
, (See Figures 4 and 6)
RMS
NO
NC
Crosstalk, (Note 9)
25
<-90
dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
±2
-1
-1
-1
-1
-
0.05
-
±6
1
V
Positive Supply Current, I+
Negative Supply Current, I-
NOTES:
V
= ±5.5V, V = 0V or V+, Switch On or Off
IN
µA
µA
µA
µA
S
Full
25
1
0.05
-
1
Full
1
5. V = Input voltage to perform proper function.
IN
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
o
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25 C.
8. Flatness is defined as the delta between the maximum and minimum R
9. Between any two switches.
values over the specified voltage range.
ON
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
200
250
8
V
Ω
ON Resistance, R
ON
V+ = 4.5V, I
(Figure 5)
= 1.0mA, V
or V
NO NC
= 3.5V
125
COM
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 5V, I
COM
= 1.0mA, V
NO
or V
= 3.5V
-
2
Ω
ON
NC
∆R
ON
Full
25
-
-
10
1
Ω
NO or NC OFF Leakage Current,
V+ = 5.5V, V
(Note 7)
= 1V, 4.5V, V
= 1V, 4.5V, V
or V
= 4.5V, 1V
= 4.5V, 1V
-1
-10
-1
-10
-2
-20
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NC
I
or I
NO(OFF)
NC(OFF)
Full
25
-
10
1
COM OFF Leakage Current,
V+ = 5.5V, V
(Note 7)
or V
0.01
NO
NC
I
COM(OFF)
Full
25
-
-
-
10
2
COM ON Leakage Current,
V+ = 5.5V, V
= 1V, 4.5V (Note 7)
I
COM(ON)
Full
20
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V+ = 5.5V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 4.5V, V
or V
NC
= 3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
60
-
100
150
50
75
-
ns
ns
ns
ns
ns
ON
NO
= 0 to 3V (Figure 1)
L
L
V
IN
V+ = 4.5V, V
Turn-OFF Time, t
or V
NC
= 3V, R = 300Ω, C = 35pF,
-
20
-
OFF
NO
= 0 to 3V (Figure 1)
L
L
V
IN
Full
25
-
Break-Before-Make Time Delay
(ISL84523), t
V+ = 5.5V, V
or V
NC
= 3V, R = 300Ω, C = 35pF,
10
30
NO
= 0 to 3V (Figure 3)
IN
L
L
V
C
D
Charge Injection, Q
= 1.0nF, V = 0V, R = 0Ω (Figure 2)
25
-
1
5
pC
L
G
G
4
ISL84521, ISL84522, ISL84523
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 5.5V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
µA
µA
µA
µA
-
0.05
-
Negative Supply Current, I-
Full
Electrical Specifications 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
260
-
V+
500
600
V
Ω
Ω
ON Resistance, R
ON
V+ = 2.7V, I
= 0.1mA, V
or V = 1V
NC
COM
NO
Full
-
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V+ = 3.6V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
25
Full
25
-
-
120
-
250
300
80
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to V+ (Figure 1)
IN
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
-
40
-
OFF
NO
NC
L
L
V
= 0 to V+ (Figure 1)
IN
Full
25
-
100
-
Break-Before-Make Time Delay
(ISL84523), t
V+ = 3.6V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
15
50
NO
= 0 to 3V (Figure 3)
IN
NC
L
L
V
C
D
Charge Injection, Q
= 1.0nF, V = 0V, R = 0Ω (Figure 2)
25
-
0.5
5
pC
L
G
G
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
µA
µA
µA
µA
-
0.05
-
Negative Supply Current, I-
Full
Test Circuits and Waveforms
V+
3V
t < 20ns
r
t < 20ns
f
C
LOGIC
INPUT
50%
SWITCH
INPUT
0V
NX
C
t
V
OFF
OUT
NO OR NC
SWITCH
INPUT
V
NX
V
COM
V
OUT
IN
90%
90%
C
35pF
R
300Ω
L
L
GND
SWITCH
OUTPUT
0V
LOGIC
INPUT
t
ON
C
V-
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
(ON)
L
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
5
ISL84521, ISL84522, ISL84523
Test Circuits and Waveforms (Continued)
V+
C
SWITCH
OUTPUT
∆V
OUT
V
R
OUT
G
NO OR NC
COM
V
OUT
3V
0V
ON
ON
LOGIC
INPUT
V
OFF
GND
G
IN
C
L
LOGIC
INPUT
C
Q = ∆V
x C
L
OUT
V-
Repeat test for all switches. C includes fixture and stray
L
capacitance.
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
C
3V
V
OUT1
NO1
NC2
IN1
LOGIC
INPUT
V
NX
COM1
COM2
C
V
R
L1
L1
35pF
OUT2
0V
300Ω
R
90%
C
35pF
90%
L2
300Ω
SWITCH
L2
OUTPUT
IN2
V
0V
0V
OUT1
LOGIC
INPUT
GND
90%
90%
SWITCH
OUTPUT
C
V
OUT2
V-
t
t
D
D
C
includes fixture and stray capacitance.
L
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY)
V+
V+
C
C
R
= V /1mA
1
ON
SIGNAL
GENERATOR
NO OR NC
NO OR NC
V
NX
1mA
0V OR 2.4V
0.8V OR 2.4V
IN
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
C
C
V-
V-
Repeat test for all switches.
FIGURE 5. R
Repeat test for all switches.
TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
ON
6
ISL84521, ISL84522, ISL84523
Test Circuits and Waveforms (Continued)
V+
C
V+
SIGNAL
GENERATOR
50Ω
NO1 OR NC1
IN2
COM1
NO OR NC
0V OR 2.4V
IN
0V or 2.4V
0V OR 2.4V
IMPEDANCE
ANALYZER
IN2
NO
COM
NO2 OR NC2
CONNECTION
COM2
ANALYZER
GND
GND
R
L
C
V-
V-
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Detailed Description
The ISL84521, ISL84522, ISL84523 quad analog switches
offer precise switching capability from a bipolar ±2V to ±6V or
a single 2V to 12V supply with low on-resistance (65Ω) and
OPTIONAL PROTECTION
DIODE
high speed switching (t
= 45ns, t = 15ns). The devices
ON
OFF
V+
are especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2V),
low power consumption (1µW) and low leakage currents (1nA
max). High frequency applications also benefit from the wide
bandwidth, and the very high OFF isolation and crosstalk
rejection.
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
V
NO OR NC
COM
Supply Sequencing And Overvoltage Protection
V-
As with any CMOS device, proper power supply sequencing
is required to protect the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes from the pin to V+ and to
V- (Figure 8). To prevent forward biasing these diodes, V+
and V- must be applied before any input signals, and input
signal voltages must remain between V+ and V-. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8452X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL8452X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This family of switches performs equally well when operated
with bipolar or single voltage supplies, and bipolar supplies
need not be symmetrical. The minimum recommended
supply voltage is 2V or ±2V. It is important to note that the
input signal range, switching times, and ON-resistance
degrade at lower supply voltages. Refer to the electrical
specification tables and Typical Performance Curves for
details.
Adding a series resistor to the switch input defeats the
purpose of using a low R
switch, so two small signal
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
7
ISL84521, ISL84522, ISL84523
V+ and GND power the internal logic (thus setting the digital
another. Figure 16 details the high OFF Isolation and
Crosstalk rejection provided by this family. At 10MHz, OFF
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters -
especially R
ON
- are strong functions of both supplies.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
Leakage Considerations
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
to 10V. At 12V the V level is about 2.7V, so for best results
IH
use a logic family the provides a V
OH
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
300MHz (Figure 15), with a small signal -3dB bandwidth in
excess of 400MHz, and a large signal bandwidth exceeding
300MHz.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. OFF Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified
A
90
80
70
60
50
300
250
200
150
100
I
= 1mA
V
I
= (V+) - 1V
V- = -5V
COM
COM
= 1mA
o
COM
85 C
o
85 C
o
25 C
o
25 C
o
-40 C
V+ = 2.7V
V- = 0V
o
-40 C
40
50
225
250
V- = 0V
o
85 C
200
150
100
50
175
125
o
o
85 C
25 C
V+ = 3.3V
V- = 0V
o
-40 C
o
25 C
75
140
o
V+ = 5V
V- = 0V
85 C
o
-40 C
110
80
o
25 C
o
-40 C
0
50
3
4
5
6
7
8
9
10
11
12
0
1
2
V
3
4
5
V+ (V)
(V)
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
8
ISL84521, ISL84522, ISL84523
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified (Continued)
A
180
140
100
5
V = ±2V
S
I
= 1mA
COM
o
85 C
o
25 C
2.5
o
-40 C
60
120
V+ = 3.3V
V+ = 5V
0
V
= ±3V
S
100
80
o
85 C
o
25 C
2.5
o
60
-40 C
40
90
V
= ±5V
S
-5
o
V
= ±5V
85 C
S
70
50
30
o
25 C
-7.5
o
-40 C
4
-5
-2.5
0
2.5
5
-5
-4
-3
-2
-1
0
1
2
3
5
V
(V)
COM
V
(V)
COM
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
250
125
o
o
V
= (V+) - 1V
COM
V
= (V+) - 1V
25 C
o
V- = -5V
V- = -5V
25 C
COM
200
150
100
50
100
-40 C
o
-40 C
75
o
o
25 C
50
25 C
o
o
85 C
85 C
25
o
o
-40 C
-40 C
0
0
50
300
V- = 0V
V- = 0V
250
200
150
100
50
40
30
20
10
o
85 C
o
85 C
o
25 C
o
25 C
o
o
-40 C
-40 C
0
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
9
ISL84521, ISL84522, ISL84523
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified (Continued)
A
-10
10
20
30
40
50
60
70
80
90
100
V+ = 3V to 12V or
V
= ±5V
S
V
= ±2V to ±5V
R = 50Ω
L
-20
-30
-40
-50
-60
-70
-80
-90
S
3
0
V
= 0.2V
GAIN
IN
P-P
V
= 5V
-3
IN P-P
0
ISOLATION
PHASE
45
V
= 0.2V
IN
P-P
= 5V
90
CROSSTALK
V
IN
P-P
135
180
-100
-110
R
= 50Ω
L
110
1k
10k
100k
1M
10M
100M 500M
1
10
100
FREQUENCY (MHz)
600
FREQUENCY (Hz)
FIGURE 16. CROSSTALK AND OFF ISOLATION
FIGURE 15. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL84521: 188
ISL84522: 188
ISL84523: 188
PROCESS:
Si Gate CMOS
10
ISL84521, ISL84522, ISL84523
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES MILLIMETERS
INDEX
M
L
M
B
0.25(0.010)
H
SYMBOL
MIN
MAX
0.069
0.010
0.019
0.010
0.394
0.157
MIN
1.35
0.10
0.35
0.19
9.80
3.80
MAX
1.75
NOTES
AREA
E
A
A1
B
C
D
E
e
0.053
0.004
0.014
0.007
0.386
0.150
-
-B-
0.25
-
0.49
9
1
2
3
0.25
-
10.00
4.00
3
SEATING PLANE
A
4
-A-
o
D
h x 45
0.050 BSC
1.27 BSC
-
H
h
0.228
0.010
0.016
0.244
0.020
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
-C-
α
µ
5
e
A1
L
6
C
B
0.10(0.004)
N
α
16
16
7
M
M
S
B
o
o
o
o
0.25(0.010)
C
A
0
8
0
8
-
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
11
ISL84521, ISL84522, ISL84523
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
INCHES
MIN
MILLIMETERS
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
c
-
D
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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