ISL8105AIRZ_技术文档

ISL8105, ISL8105A

®

Data Sheet

December 6, 2006

FN6306.3

+5V or +12V Single-Phase Synchronous

Buck Converter PWM Controller with

Integrated MOSFET Gate Drivers

Features

• Operates from +5V or +12V Bias Supply Voltage

- 1.0V to 12V Input Voltage Range (up to 20V possible

with restrictions; see Input Voltage Considerations)

The ISL8105 is a simple single-phase PWM controller for a

synchronous buck converter. It operates from +5V or +12V bias

supply voltage. With integrated linear regulator, boot diode, and

N-channel MOSFET gate drivers, the ISL8105 reduces

external component count and board space requirements.

These make the IC suitable for a wide range of applications.

- 0.6V to V Output Voltage Range

IN

• 0.6V Internal Reference Voltage

- ±1.0% Tolerance Over the Commercial Temperature

Range (0°C to +70°C)

- ±1.5% Tolerance Over the Industrial Temperature

Range (-40°C to +85°C).

Utilizing voltage-mode control, the output voltage can be

precisely regulated to as low as 0.6V. The 0.6V internal

reference features a maximum tolerance of ±1.0% over the

commercial temperature range, and ±1.5% over the

industrial temperature range. Two fixed oscillator frequency

versions are available; 300kHz (ISL8105 for high efficiency

applications) and 600kHz (ISL8105A for fast transient

applications).

• Integrated MOSFET Gate Drivers that Operate from V

(+5V to +12V)

Bias

- Bootstrapped High-side Gate Driver with Integrated

Boot Diode

- Drives N-Channel MOSFETs

• Simple Voltage-Mode PWM Control

• Fast Transient Response

The ISL8105 features the capability of safe start-up with

pre-biased load. It also provides overcurrent protection by

monitoring the on resistance of the bottom-side MOSFET to

inhibit PWM operation appropriately. During start-up interval,

the resistor connected to BGATE/BSOC pin is employed to

program overcurrent protection condition. This approach

simplifies the implementation and does not deteriorate

converter efficiency.

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Fixed Operating Frequency

- 300kHz for ISL8105

- 600kHz for ISL8105A

• Fixed Internal Soft-Start with Pre-biased Load Capability

• Lossless, Programmable Overcurrent Protection

- Uses Bottom-side MOSFET’s r

DS(ON)

Pinouts

ISL8105

• Enable/Disable Function Using COMP/EN Pin

• Output Current Sourcing and Sinking Currents

• Pb-Free Plus Anneal Available (RoHS Compliant)

(10 LD 3X3 DFN)

TOP VIEW

BOOT

LX

1

2

3

4

5

10

9

Applications

• 5V or 12V DC/DC Regulators

TGATE

N/C

COMP/EN

FB

GND

8

• Industrial Power Systems

7

GND

N/C

• Telecom and Datacom Applications

• Test and Measurement Instruments

• Distributed DC/DC Power Architecture

• Point of Load Modules

6

BGATE/BSOC

VBIAS

ISL8105

(8 LD SOIC)

TOP VIEW

LX

8

BOOT

1

COMP/EN

7

6

5

2

3

4

TGATE

FB

GND

VBIAS

BGATE/BSOC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL8105, ISL8105A

Ordering Information

PART NUMBER

(Note)

PART

MARKING

SWITCHING

FREQUENCY (kHz)

TEMPERATURE

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL8105CRZ*

(300kHz)

5CRZ

300

600

0 to +70

10 Ld DFN

L10.3X3C

ISL8105IBZ*

(300kHz)

8105IBZ

5IRZ

-40 to +85

0 to +70

8 Ld SOIC

10 Ld DFN

8 Ld SOIC

10 Ld DFN

M8.15

ISL8105IRZ*

(300kHz)

L10.3X3C

M8.15

ISL8105ACRZ*

(600kHz)

05AZ

ISL8105AIBZ*

(600kHz)

8105AIBZ

5AIZ

-40 to +85

ISL8105AIRZ*

(600kHz)

L10.3X3C

ISL8105EVAL1

Evaluation Board

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Typical Application

V

IN

+1V TO +12V

V

C

Bias

+5V OR +12V

HF

BULK

C

DCPL

VBIAS

BOOT

COMP/EN

C

BOOT

Q1

Q2

TGATE

LX

C

1

L

OUT

C

V

2

OUT

ISL8105

R

2

C

OUT

FB

BGATE/BSOC

GND

R

BSOC

C

R

3

R

1

R

0

FN6306.3

December 6, 2006

2

ISL8105, ISL8105A

Absolute Maximum Ratings

Thermal Information

Bias Voltage, V

. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +15.0V

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +36.0V

Thermal Resistance (Note 1)

θ

(°C/W)

θ (°C/W)

JC

Bias

Boot Voltage, V

JA

BOOT

TGATE Voltage, V

SOIC Package . . . . . . . . . . . . . . . . . . .

DFN Package (Note 2). . . . . . . . . . . . .

Maximum Junction Temperature

(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

95

44

N/A

5.5

. . . . . . . . . . . . . V - 0.3V to V

+ 0.3V

TGATE

BGATE/BSOC Voltage, V

LX

BOOT

. . . . GND - 0.3 to V

BGATE/BSOC

Bias

LX Voltage, V . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

LX

Upper Driver Supply Voltage, V

BOOT

- V

. . . . . . . . . . . . . . . . . .15V

BOOT

. . . . . . . . . . . . . . . . . . . . . . . . . . . .24V

LX

Clamp Voltage, V

- V

BOOT

Bias

FB, COMP/EN Voltage . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V

ESD Classification, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

ESD Classification, MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V

ESD Classification, CDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Recommended Operating Conditions

Bias Voltage, V

. . . . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V

Bias

Ambient Temperature Range

ISL8105C, ISL8105AC . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL8105I, ISL8105AI. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

JA

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. Test conditions are guaranteed by design simulation.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

4

TYP

5.2

MAX

7

UNITS

mA

INPUT SUPPLY CURRENTS

Shutdown V

Supply Current

I

V

= 12V; Disabled

Bias

VBias_S

DISABLE

Disable Threshold (COMP/EN pin)

OSCILLATOR

V

0.375

0.4

0.425

V

DISABLE

Nominal Frequency Range

F

ISL8105C

ISL8105I

270

240

540

510

300

600

1.5

330

660

kHz

OSC

ISL8105AC

ISL8105AI

Ramp Amplitude (Note 3)

ΔV

V

OSC

P-P

POWER-ON RESET

Rising V

Threshold

V

3.9

4.1

4.3

V

Bias

POR_R

POR_H

V

POR Threshold Hysteresis

0.30

0.35

0.40

mV

Bias

REFERENCE

Nominal Reference Voltage

Reference Voltage Tolerance

V

0.6

V

%

REF

ISL8105C (0°C to +70°C)

ISL8105I (-40°C to +85°C)

-1.0

-1.5

+1.0

+1.5

ERROR AMPLIFIER

DC Gain (Note 3)

GAIN

96

20

9

dB

DC

Unity Gain-Bandwidth (Note 3)

Slew Rate (Note 3)

UGBW

SR

MHz

V/μs

GATE DRIVERS

TGATE Source Resistance

R

V

= 14.5V, 50mA Source Current

Bias

3.0

Ω

TG-SRCh

FN6306.3

December 6, 2006

4

ISL8105, ISL8105A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER

TGATE Source Resistance

TGATE Sink Resistance

BGATE Source Resistance

BGATE Sink Resistance

SYMBOL

TEST CONDITIONS

MIN

TYP

3.5

2.7

2.4

2.75

2.0

2.1

MAX

UNITS

R

V

= 4.25V, 50mA Source Current

= 14.5V, 50mA Source Current

= 4.25V, 50mA Source Current

= 14.5V, 50mA Source Current

= 4.25V, 50mA Source Current

= 14.5V, 50mA Source Current

= 4.25V, 50mA Source Current

Ω

TG-SRCl

Bias

R

TG-SNKh

R

TG-SNKl

R

BG-SRCh

R

BG-SRCl

BG-SNKh

R

BG-SNKl

OVERCURRENT PROTECTION (OCP)

BSOC Current Source

I

ISL8105C; BGATE/BSOC Disabled

ISL8105I; BGATE/BSOC Disabled

19.5

18.0

21.5

23.5

µA

BSOC

and BOOT will still be sourced by V

decoupled +5V or +12V supply to this pin.

). Connect a well

Functional Pin Description (SOIC, DFN)

Bias

BOOT (SOIC Pin 1, DFN Pin 1)

FB (SOIC Pin 6, DFN Pin 8)

This pin provides ground referenced bias voltage to the

top-side MOSFET driver. A bootstrap circuit is used to create

a voltage suitable to drive an N-channel MOSFET (equal to

This pin is the inverting input of the internal error amplifier.

Use FB, in combination with the COMP/EN pin, to

compensate the voltage-control feedback loop of the

converter. A resistor divider from the output to GND is used

to set the regulation voltage.

V

minus the on-chip BOOT diode voltage drop), with

Bias

respect to LX.

TGATE (SOIC Pin 2, DFN Pin 2)

COMP/EN (SOIC Pin 7, DFN Pin 9)

Connect this pin to the gate of top-side MOSFET; it provides

the PWM-controlled gate drive. It is also monitored by the

adaptive shoot-through protection circuitry to determine

when the top-side MOSFET has turned off.

This is a multiplexed pin. During soft-start and normal converter

operation, this pin represents the output of the error amplifier.

Use COMP/EN, in combination with the FB pin, to compensate

the voltage-control feedback loop of the converter.

GND (SOIC Pin 3, DFN Pin 4)

Pulling COMP/EN low (V

= 0.4V nominal) will

DISABLE

This pin represents the signal and power ground for the IC.

Tie this pin to the ground island/plane through the lowest

impedance connection available.

disable (shut-down) the controller, which causes the

oscillator to stop, the BGATE and TGATE outputs to be held

low, and the soft-start circuitry to re-arm. The external

pull-down device will initially need to overcome maximum of

5mA of COMP/EN output current. However, once the IC is

disabled, the COMP output will also be disabled, so only a

20µA current source will continue to draw current.

BGATE/BSOC (SOIC Pin 4, DFN Pin 5)

Connect this pin to the gate of the bottom-side MOSFET; it

provides the PWM-controlled gate drive (from V

). This

Bias

pin is also monitored by the adaptive shoot-through

protection circuitry to determine when the lower MOSFET

has turned off.

When the pull-down device is released, the COMP/EN pin

will start to rise at a rate determined by the 20µA charging up

the capacitance on the COMP/EN pin. When the COMP/EN

During a short period of time following Power-On Reset

(POR) or shut-down release, this pin is also used to

determine the current limit threshold of the converter.

pin rises above the V

trip point, the ISL8105 will

DISABLE

begin a new initialization and soft-start cycle.

Connect a resistor (R

) from this pin to GND. See

BSOC

LX (SOIC Pin 8, DFN Pin 10)

“Overcurrent Protection (OCP)” on page 7 for equations. An

overcurrent trip cycles the soft-start function, after two

dummy soft-start time-outs. Some of the text describing the

BGATE function may leave off the BSOC part of the name,

when it is not relevant to the discussion.

Connect this pin to the source of the top-side MOSFET and

the drain of the bottom-side MOSFET. It is used as the sink

for the TGATE driver and to monitor the voltage drop across

the bottom-side MOSFET for overcurrent protection. This pin

is also monitored by the adaptive shoot-through protection

circuitry to determine when the top-side MOSFET has turned

off.

VBIAS (SOIC Pin 5, DFN Pin 6)

This pin provides the bias supply for the ISL8105, as well as

the bottom-side MOSFET's gate and the BOOT voltage for

the top-side MOSFET's gate. An internal 5V regulator will

N/C (DFN Only; Pin3, Pin 7)

These two pins in the DFN package are No Connected.

supply bias if V

rises above 6.5V (but the BGATE/BSOC

Bias

FN6306.3

December 6, 2006

5

ISL8105, ISL8105A

typical values, it should add a small delay compared to the

soft-start times. The COMP/EN will continue to ramp to ~1V.

Functional Description

Initialization (POR and OCP Sampling)

From T1, there is a nominal 6.8ms delay, which allows the

VBIAS pin to exceed 6.5V (if rising up towards 12V), so that

the internal bias regulator can turn on cleanly. At the same

time, the BGATE/BSOC pin is initialized by disabling the

BGATE driver and drawing BSOC (nominal 21.5µA) through

Figure 1 shows a start-up waveform of ISL8105. The

Power-On-Reset (POR) function continually monitors the

bias voltage at the VBIAS pin. Once the rising POR

threshold is exceeded 4V (V

nominal), the POR function

POR

initiates the Overcurrent Protection (OCP) sample and hold

operation (while COMP/EN is ~1V). When the sampling is

R

. This sets up a voltage that will represent the BSOC

BSOC

trip point. At T2, there is a variable time period for the OCP

sample and hold operation (0ms to 3.4ms nominal; the

longer time occurs with the higher overcurrent setting). The

sample and hold uses a digital counter and DAC to save the

voltage, so the stored value does not degrade, for as long as

complete, V

begins the soft-start ramp.

OUT

V

BIAS

the V

is above V . See “Overcurrent Protection

Bias

POR

V

OUT

(OCP)” on page 7 for more details on the equations and

variables. Upon the completion of sample and hold at T3, the

soft-start operation is initiated, and the output voltage ramps

up between T4 and T5.

~4V POR

V

COMP/EN

Soft-Start and Pre-Biased Outputs

Functionally, the soft-start internally ramps the reference on

the non-inverting terminal of the error amp from zero to 0.6V

in a nominal 6.8ms. The output voltage will thus follow the

ramp, from zero to final value, in the same 6.8ms (the actual

ramp seen on the V

due to some initialization timing, between T3 and T4).

will be less than the nominal time),

OUT

FIGURE 1. POR AND SOFT-START OPERATION

If the COMP/EN pin is held low during power-up, the

initialization will be delayed until the COMP/EN is released

The ramp is created digitally, so there will be 64 small

discrete steps. There is no simple way to change this ramp

rate externally, and it is the same for either frequency

version of the IC (300kHz or 600kHz).

and its voltage rises above the V

DISABLE

trip point.

Figure 2 shows a typical power-up sequence in more detail.

The initialization starts at T0, when either V rises above

Bias

, or the COMP/EN pin is released (after POR). The

After an initialization period (T3 to T4), the error amplifier

(COMP/EN pin) is enabled, and begins to regulate the

converter's output voltage during soft-start. The oscillator's

triangular waveform is compared to the ramping error

amplifier voltage. This generates LX pulses of increasing

width that charge the output capacitors. When the internally

generated soft-start voltage exceeds the reference voltage

(0.6V), the soft-start is complete and the output should be in

regulation at the expected voltage. This method provides a

rapid and controlled output voltage rise; there is no large

inrush current charging the output capacitors. The entire

start-up sequence from POR typically takes up to 17ms; up

to 10.2ms for the delay and OCP sample and 6.8ms for the

soft-start ramp.

V

POR

COMP/EN will be pulled up by an internal 20µA current

source, but the timing will not begin until the COMP/EN

exceeds the V

trip point (at T1). The external

DISABLE

capacitance of the disabling device, as well as the

compensation capacitors, will determine how quickly the

20µA current source will charge the COMP/EN pin. With

BGATE

STARTS

SWITCHING

Figure 3 shows the normal curve in blue; initialization begins

at T0, and the output ramps between T1 and T2. If the output

is pre-biased to a voltage less than the expected value, as

shown by the red curve, the ISL8105 will detect that

COMP/EN

V

OUT

BGATE/BSOC

condition. Neither MOSFET will turn on until the soft-start

3.4ms

0 - 3.4ms

T2 T3 T4

T5

T0T1

ramp voltage exceeds the output; V

starts seamlessly

OUT

ramping from there. If the output is pre-biased to a voltage

above the expected value, as in the gray curve, neither

MOSFET will turn on until the end of the soft-start, at which

time it will pull the output voltage down to the final value. Any

FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION

FN6306.3

December 6, 2006

6

ISL8105, ISL8105A

resistive load connected to the output will help pull down the

Overcurrent Protection (OCP)

voltage (at the RC rate of the R of the load and the C of the

output capacitance).

The overcurrent function protects the converter from a

shorted output by using the bottom-side MOSFET's

on-resistance, r

, to monitor the current. A resistor

DS(ON)

(R

) programs the overcurrent trip level (see “Typical

BSOC

Application” on page 2). This method enhances the

converter's efficiency and reduces cost by eliminating a

current sensing resistor. If overcurrent is detected, the output

immediately shuts off, it cycles the softstart function in a

hiccup mode (2 dummy soft-start time-outs, then up to one

real one) to provide fault protection. If the shorted condition

is not removed, this cycle will continue indefinitely.

V

OVER-CHARGED

OUT

V

PRE-BIASED

NORMAL

OUT

V

OUT

Following POR (and 6.8ms delay), the ISL8105 initiates the

Overcurrent Protection sample and hold operation. The

BGATE driver is disabled to allow an internal 21.5μA current

T0

T2

T1

source to develop a voltage across R

. The ISL8105

BSOC

samples this voltage (which is referenced to the GND pin) at

the BGATE/BSOC pin, and holds it in a counter and DAC

combination. This sampled voltage is held internally as the

Overcurrent Set Point, for as long as power is applied, or

until a new sample is taken after coming out of a shut-down.

FIGURE 3. SOFT-START WITH PRE-BIAS

If the V for the synchronous buck converter is from a

IN

different supply that comes up after V

, the soft-start

Bias

would go through its cycle, but with no output voltage ramp.

The actual monitoring of the bottom-side MOSFET's

on-resistance starts 200ns (nominal) after the edge of the

internal PWM logic signal (that creates the rising external

BGATE signal). This is done to allow the gate transition

noise and ringing on the LX pin to settle out before

monitoring. The monitoring ends when the internal PWM

edge (and thus BGATE) goes low. The OCP can be detected

anywhere within the above window.

When V turns on, the output would follow the ramp of the

IN

from zero up to the final expected voltage (at close to

V

IN

100% duty cycle, with COMP/EN pin >4V). If V is too fast,

IN

there may be excessive inrush current charging the output

capacitors (only the beginning of the ramp, from zero to

V

matters here). If this is not acceptable, then consider

OUT

changing the sequencing of the power supplies, or sharing

the same supply, or adding sequencing logic to the

COMP/EN pin to delay the soft-start until the V supply is

ready (see “Input Voltage Considerations” on page 9).

If the regulator is running at high TGATE duty cycles (around

75% for 600kHz or 87% for 300kHz operation), then the

BGATE pulse width may not be wide enough for the OCP to

IN

If the IC is disabled after soft-start (by pulling COMP/EN pin

low), and then enabled (by releasing the COMP/EN pin),

then the full initialization (including OCP sample) will take

place. However, there is no new OCP sampling during

overcurrent retries. If the output is shorted to GND during

soft-start, the OCP will handle it, as described in the next

section.

properly sample the r

. For those cases, if the BGATE

DS(ON)

is too narrow (or not there at all) for 3 consecutive pulses,

then the third pulse will be stretched and/or inserted to the

425ns minimum width. This allows for OCP monitoring every

third pulse under this condition. This can introduce a small

pulse-width error on the output voltage, which will be

corrected on the next pulse; and the output ripple voltage will

have an unusual 3-clock pattern, which may look like jitter. If

the OCP is disabled (by choosing a too-high value of

If the output is shorted to GND during soft-start, the OCP will

handle it, as described in the next section.

R

, or no resistor at all), then the pulse stretching

BSOC

feature is also disabled. Figure 4 illustrates the BGATE pulse

width stretching, as the width gets smaller.

FN6306.3

December 6, 2006

7

ISL8105, ISL8105A

MOSFETs is typically in the 20mV to 120mV ballpark (500Ω

to 3000Ω). If the voltage drop across R is set too low,

BSOC

that can cause almost continuous OCP tripping and retry. It

would also be very sensitive to system noise and inrush

current spikes, so it should be avoided. The maximum

BGATE > 425ns

usable setting is around 0.2V across R

(0.4V across

BSOC

the MOSFET); values above that might disable the

protection. Any voltage drop across R that is greater

BSOC

than 0.3V (0.6V MOSFET trip point) will disable the OCP.

The preferred method to disable OCP is simply to remove

the resistor, which will be detected as no OCP.

BGATE = 425ns

Note that conditions during power-up or during a retry may

look different than normal operation. During power-up in a

12V system, the IC starts operation just above 4V; if the

supply ramp is slow, the soft-start ramp might be over well

before 12V is reached. So with bottom-side gate drive

voltages, the r

of the MOSFETs will be higher during

DS(ON)

power-up, effectively lowering the OCP trip. In addition, the

ripple current will likely be different at lower input voltage.

BGATE < 425ns

Another factor is the digital nature of the soft-start ramp. On

each discrete voltage step, there is in effect a small load

transient, and a current spike to charge the output

capacitors. The height of the current spike is not controlled; it

is affected by the step size of the output, the value of the

output capacitors, as well as the IC error amp compensation.

So it is possible to trip the overcurrent with inrush current, in

addition to the normal load and ripple considerations.

BGATE << 425ns

Internal soft-start ramp

FIGURE 4. BGATE PULSE STRETCHING

The overcurrent function will trip at a peak inductor current

(I

) determined by:

PEAK

2 × I

× R

BSOC

(EQ. 1)

BSOC

r

-----------------------------------------------------

I

=

PEAK

V_OUT

DS(ON)

where I

is the internal BSOC current source (21.5µA

BSOC

typical). The scale factor of 2 doubles the trip point of the

MOSFET voltage drop, compared to the setting on the

6.8ms

0 TO 6.8ms

T2

T0

T1

R

resistor. The OC trip point varies in a system mainly

BSOC

due to the MOSFET's r

variations (over process,

DS(ON)

current and temperature). To avoid overcurrent tripping in

FIGURE 5. OVERCURRENT RETRY OPERATION

the normal operating load range, find the R

from Equation 1 with:

resistor

BSOC

Figure 5 shows the output response during a retry of an

output shorted to GND. At time T0, the output has been

turned off, due to sensing an overcurrent condition. There

are two internal soft-start delay cycles (T1 and T2) to allow

the MOSFETs to cool down, to keep the average power

dissipation in retry at an acceptable level. At time T2, the

output starts a normal soft-start cycle, and the output tries to

ramp. If the short is still applied, and the current reaches the

BSOC trip point any time during soft-start ramp period, the

output will shut off and return to time T0 for another delay

1. The maximum r

temperature

at the highest junction

DS(ON)

2. The minimum I

BSOC

from the specification table

(ΔI)

2

----------

, where

3. Determine I

for I

PEAK

> I

OUT(MAX)

+

PEAK

ΔI is the output inductor ripple current.

For an equation for the ripple current, see “Output Inductor

Selection” on page 13.

The range of allowable voltages detected (2*I

is 0mV to 475mV; but the practical range for typical

*R )

BSOC BSOC

FN6306.3

December 6, 2006

8

ISL8105, ISL8105A

cycle. The retry period is thus two dummy soft-start cycles

typical power supply to ramp up past 6.5V before the

softstart ramps begins. This prevents a disturbance on the

output, due to the internal regulator turning on or off. If the

transition is slow (not a step change), the disturbance should

be minimal. So while the recommendation is to not have the

output enabled during the transition through this region, it

may be acceptable. The user should monitor the output for

their application to see if there is any problem.

plus one variable one (which depends on how long it takes to

trip the sensor each time). Figure 5 shows an example

where the output gets about half-way up before shutting

down; therefore, the retry (or hiccup) time will be around

17ms. The minimum should be nominally 13.6ms and the

maximum 20.4ms. If the short condition is finally removed,

the output should ramp up normally on the next T2 cycle.

Starting up into a shorted load looks the same as a retry into

that same shorted load. In both cases, OCP is always

enabled during soft-start; once it trips, it will go into retry

(hiccup) mode. The retry cycle will always have two dummy

time-outs, plus whatever fraction of the real soft-start time

passes before the detection and shutoff; at that point, the

logic immediately starts a new two dummy cycle time-out.

The V to the top-side MOSFET can share the same supply

IN

as V

but can also run off a separate supply or other

Bias

sources, such as outputs of other regulators. If V

powers

Bias

up first, and the V is not present by the time the

IN

initialization is done, then the soft-start will not be able to

ramp the output, and the output will later follow part of the

V

ramp when it is applied. If this is not desired, then

IN

change the sequencing of the supplies, or use the

COMP/EN pin to disable V until both supplies are ready.

Output Voltage Selection

OUT

Figure 6 shows a simple sequencer for this situation. If V

The output voltage can be programmed to any level between

Bias

the 0.6V internal reference, up to the V

supply. The

Bias

ISL8105 can run at near 100% duty cycle at zero load, but

the r of the top-side MOSFET will effectively limit it to

powers up first, Q1 will be off, and R3 pulling to V

will

Bias

turn Q2 on, keeping the ISL8105 in shut-down. When V

IN

DS(ON)

turns on, the resistor divider R1 and R2 determines when Q1

turns on, which will turn off Q2 and release the shut-down. If

something less as the load current increases. In addition, the

OCP (if enabled) will also limit the maximum effective duty

cycle.

V

powers up first, Q1 will be on, turning Q2 off; so the

IN

ISL8105 will start-up as soon as V

comes up. The

Bias

trip point is 0.4V nominal, so a wide variety of

An external resistor divider is used to scale the output

voltage relative to the internal reference voltage, and feed it

back to the inverting input of the error amp. See “Typical

V

DISABLE

NFET's or NPN's or even some logic IC's can be used as Q1

or Q2; but Q2 must be low leakage when off (open-drain or

open-collector) so as not to interfere with the COMP output.

Q2 should also be placed near the COMP/EN pin.

Application” on page 2 for more detail; R is the upper

1

resistor; R

(shortened to R below) is the lower one.

0

OFFSET

The recommended value for R is 1 - 5kΩ (±1% for

1

V

Bias

IN

accuracy) and then R

is chosen according to the

OFFSET

equation below. Since R is part of the compensation circuit

(see “Feedback Compensation” on page 11), it is often

1

R

3

R

1

TO COMP/EN

easier to change R

to change the output voltage;

OFFSET

that way the compensation calculations do not need to be

repeated. If V = 0.6V, then R can be left open.

R

2

Q

2

Q

1

OUT OFFSET

Output voltages less than 0.6V are not available.

(R + R )

FIGURE 6. SEQUENCER CIRCUIT

(EQ. 2)

(EQ. 3)

1

0

-------------------------

V

R

= 0.6V •

OUT

R

0

The V range can be as low as ~1V (for V

IN

as low as the

OUT

0.6V reference). It can be as high as 20V (for V

below V ). There are some restrictions for running high V

just

OUT

R

• 0.6V

1

----------------------------------

=

0

IN

V

– 0.6V

OUT

voltage.

Input Voltage Considerations

The first consideration for high V is the maximum BOOT

IN

The “Typical Application” on page 2 shows a standard

voltage of 36V. The V (as seen on LX) + V

(boot

IN Bias

configuration where V

is either 5V (±10%) or 12V

voltage - the diode drop), + any ringing (or other transients)

Bias

(±20%); in each case, the gate drivers use the V

voltage

on the BOOT pin must be less than 36V. If V is 20V, that

Bias

is allowed

IN

for BGATE and BOOT/TGATE. In addition, V

limits V

Bias

+ ringing to 16V.

Bias

to work anywhere from 6.5V up to the 14.4V maximum. The

range between 5.5V and 6.5V is NOT allowed for

long-term reliability reasons, but transitions through it to

The second consideration for high V is the maximum

IN

V

Bias

(BOOT - V

) voltage; this must be less than 24V. Since

Bias

BOOT = V + V

IN Bias

+ ringing, that reduces to (V

+

IN

ringing) must be <24V. So based on typical circuits, a 20V

voltages above 6.5V are acceptable.

There is an internal 5V regulator for bias; it turns on between

5.5 and 6.5V. Some of the delay after POR is there to allow a

maximum V is a good starting assumption; the user should

verify the ringing in their particular application.

IN

FN6306.3

December 6, 2006

9

ISL8105, ISL8105A

Another consideration for high V is duty cycle. Very low

duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)

require component selection compatible with that choice

Application Guidelines

IN

Layout Considerations

As in any high-frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

(such as low r

bottom-side MOSFET, and a good LC

DS(ON)

output filter). At the other extreme (for example, 20V in to

12V out), the top-side MOSFET needs to be low r . In

DS(ON)

addition, if the duty cycle gets too high, it can affect the

overcurrent sample time. In all cases, the input and output

capacitors and both MOSFETs must be rated for the

voltages present.

Switching Frequency

The switching frequency is either a fixed 300 or 600kHz,

depending on the part number chosen (ISL8105 is 300kHz;

ISL8105A is 600kHz; the generic name “ISL8105” may apply

to either in the rest of this document, except when choosing

the frequency). However, all of the other timing mentioned

(POR delay, OCP sample, soft-start, etc.) is independent of

the clock frequency (unless otherwise noted).

V

IN

ISL8105

TGATE

LX

Q1

Q2

L

O

V

OUT

BOOT Refresh

C

IN

In the event that the TGATE is on for an extended period of

time, the charge on the boot capacitor can start to sag,

C

O

BGATE

PGND

raising the r

of the top-side MOSFET. The ISL8105

DS(ON)

has a circuit that detects a long TGATE on-time (nominal

100µs), and forces the BGATE to go higher for one clock

cycle, which will allow the boot capacitor some time to

recharge. Separately, the OCP circuit has a BGATE pulse

stretcher (to be sure the sample time is long enough), which

can also help refresh the boot. But if OCP is disabled (no

current sense resistor), the regular boot refresh circuit will

still be active.

RETURN

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 7 shows the critical power components of the

converter. To minimize the voltage overshoot/undershoot,

the interconnecting wires indicated by heavy lines should be

part of ground or power plane in a printed circuit board. The

components shown in Figure 8 should be located as close

together as possible. Please note that the capacitors C

and C each represent numerous physical capacitors.

O

Locate the ISL8105 within three inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the ISL8105 must be sized to

handle up to 1A peak current.

Current Sinking

The ISL8105 incorporates a MOSFET shoot-through

protection method which allows a converter to sink current

as well as source current. Care should be exercised when

designing a converter with the ISL8105 when it is known that

the converter may sink current.

IN

When the converter is sinking current, it is behaving as a

boost converter that is regulating its input voltage. This

means that the converter is boosting current into the V rail.

IN

Proper grounding of the IC is important for correct operation

in noisy environments. The GND pin should be connected to

a large copper fill under the IC which is subsequently

connected to board ground at a quiet location on the board,

typically found at an input or output bulk (electrolytic)

capacitor.

If there is nowhere for this current to go, such as to other

distributed loads on the V rail, through a voltage limiting

IN

protection device, or other methods, the capacitance on the

V

bus will absorb the current. This situation will allow

IN

voltage level of the V rail (also LX) to increase. If the

IN

voltage level of the LX is increased to a level that exceeds

the maximum voltage rating of the ISL8105, then the IC will

experience an irreversible failure and the converter will no

longer be operational. Ensuring that there is a path for the

current to follow other than the capacitance on the rail will

prevent this failure mode.

FN6306.3

December 6, 2006

10

ISL8105, ISL8105A

C

2

+V

Q1

IN

BOOT

C

L

O

BOOT

V

C

R

OUT

3

R

C

2

1

LX

COMP

ISL8105

+V

-

BIAS

C

Q2

O

R

FB

1

BGATE/BSOC

+

V

E/A

BIAS

C

VBIAS

VREF

GND

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

V

OSCILLATOR

OUT

V

IN

V

OSC

Figure 8 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Locate the resistor,

PWM

CIRCUIT

L

DCR

C

TGATE

LX

R

, close to the BGATE/BSOC pin as the internal BSOC

BSOC

HALF-BRIDGE

DRIVE

current source is only 21.5µA. Minimize the loop from any

pulldown transistor connected to COMP/EN pin to reduce

antenna effect. Provide local decoupling between VBIAS

and GND pins as described earlier. Locate the capacitor,

ESR

BGATE

C

, as close as practical to the BOOT and LX pins. All

BOOT

components used for feedback compensation (not shown)

should be located as close to the IC as practical.

ISL8105

EXTERNAL CIRCUIT

FIGURE 9. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Feedback Compensation

This section highlights the design considerations for a

voltage-mode controller requiring external compensation. To

address a broad range of applications, a type-3 feedback

network is recommended (see Figure 9).

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

OUT COMP

gain, given by d /V

V

, and shaped by the output filter,

MAX IN OSC

with a double pole break frequency at F and a zero at F

.

LC CE

Figure 9 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable to the

For the purpose of this analysis, C and ESR represent the total

output capacitance and its equivalent series resistance.

ISL805 circuit. The output voltage (V

) is regulated to the

OUT

1

---------------------------

F

=

---------------------------------

F

=

LC

CE

reference voltage, V

, level. The error amplifier output

(EQ. 4)

2π ⋅ C ⋅ ESR

REF

2π ⋅ L ⋅ C

(COMP pin voltage) is compared with the oscillator (OSC)

triangle wave to provide a pulse-width modulated wave with

The compensation network consists of the error amplifier

(internal to the ISL8105) and the external R -R , C -C

an amplitude of V at the LX node. The PWM wave is

IN

1

3

1

3

smoothed by the output filter (L and C). The output filter

capacitor bank’s equivalent series resistance is represented

by the series resistor ESR.

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

frequency (F ; typically 0.1 to 0.3 of F ) and adequate

SW

0

phase margin (better than +45°). Phase margin is the

difference between the closed loop phase at F and +180°.

0dB

The equations that follow relate the compensation network’s

poles, zeros and gain to the components (R , R , R , C , C ,

1

2

3

1

2

and C ) in Figure 9. Use the following guidelines for locating

3

the poles and zeros of the compensation network:

1. Select a value for R (1kΩ to 10kΩ, typically). Calculate

1

value for R for desired converter bandwidth (F ). If

2

0

setting the output voltage to be equal to the reference set

voltage as shown in Figure 9, the design procedure can

be followed as presented.

V

⋅ R ⋅ F

1 0

OSC

---------------------------------------------

=

R

2

d

⋅ V ⋅ F

(EQ. 5)

MAX

IN

LC

FN6306.3

December 6, 2006

11

ISL8105, ISL8105A

2. Calculate C such that F is placed at a fraction of the F

,

COMPENSATION BREAK FREQUENCY EQUATIONS

1

Z1 LC

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

desired number). The higher the quality factor of the output

LC

1

--------------------------------------------

F

=

------------------------------

F

=

P1

Z1

C

⋅ C

2π ⋅ R ⋅ C

1

2

1

--------------------

⋅

2π ⋅ R

filter and/or the higher the ratio F /F , the lower the F

CE LC

Z1

2

C

+ C

2

1

frequency (to maximize phase boost at F ).

LC

1

-------------------------------------------------

2π ⋅ (R + R ) ⋅ C

------------------------------

2π ⋅ R ⋅ C

F

=

F

=

1

Z2

P2

----------------------------------------------

C

=

1

3

1

2π ⋅ R ⋅ 0.5 ⋅ F

(EQ. 6)

2

LC

(EQ. 10)

3. Calculate C such that F is placed at F

.

2

P1 CE

Figure 10 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual modulator gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

C

1

-------------------------------------------------------

=

C

2

2π ⋅ R ⋅ C ⋅ F – 1

(EQ. 7)

2

1

CE

4. Calculate R such that F is placed at F . Calculate C

3

Z2

LC

such that F is placed below F

(typically, 0.5 to 1.0

P2 SW

times F ). F

represents the regulator’s switching

SW SW

compensation gain at F against the capabilities of the error

frequency. Change the numerical factor to reflect desired

P2

placement of this pole. Placement of F lower in frequency

amplifier. The closed loop gain, G , is constructed on the

CL

P2

helps reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at the

COMP pin and minimizing resultant duty cycle jitter.

log-log graph of Figure 10 by adding the modulator gain,

G

(in dB), to the feedback compensation gain, G (in

MOD

FB

dB). This is equivalent to multiplying the modulator transfer

function and the compensation transfer function and then

plotting the resulting gain.

R

1

---------------------

R

C

=

3

F

SW

------------

– 1

(EQ. 8)

F

LC

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

P1

Z1 Z2

1

------------------------------------------------

2π ⋅ R ⋅ 0.7 ⋅ F

3

SW

F

P2

It is recommended that a mathematical model is used to plot

the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

R2

-------

⎛

⎝

⎞

⎠

20log

d

⋅ V

IN

R1

MAX

20log---------------------------------

frequency response of the modulator (G

), feedback

MOD

V

0

OSC

compensation (G ) and closed-loop response (G ):

G

FB

CL

FB

d

⋅ V

1 + s(f) ⋅ ESR ⋅ C

MAX

V

IN

G

----------------------------- -----------------------------------------------------------------------------------------------------------

G

(f) =

⋅

CL

MOD

2

OSC

1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C

G

MOD

FREQUENCY

LOG

F

0

1 + s(f) ⋅ R ⋅ C

LC

CE

2

1

----------------------------------------------------

(f) =

⋅

FB

s(f) ⋅ R ⋅ (C + C )

1

2

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

1 + s(f) ⋅ (R + R ) ⋅ C

3

1

3

-------------------------------------------------------------------------------------------------------------------------

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than +45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

C

⋅ C

⎛

⎜

⎝

⎞⎞

⎟⎟

⎠⎠

1

2

--------------------

(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R

⋅

⎜

3

2

C

+ C

2

⎝

1

G

(f) = G

(f) ⋅ G (f)

where, s(f) = 2π ⋅ f ⋅ j

CL

MOD

FB

(EQ. 9)

the switching frequency, F

.

SW

FN6306.3

December 6, 2006

12

ISL8105, ISL8105A

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL8105 will provide either 0% or 100% duty cycle in response

to a load transient. The response time is the time required to

slew the inductor current from an initial current value to the

transient current level. During this interval the difference

between the inductor current and the transient current level

must be supplied by the output capacitor. Minimizing the

response time can minimize the output capacitance required.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

The response time to a transient is different for the

application of load and the removal of load. Equation 12

gives the approximate response time interval for application

and removal of a transient load:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1.0mF

ceramic capacitors in the 1206 surface-mount package.

Follow on specifications have only increased the number

and quality of required ceramic decoupling capacitors.

L

× I

L × I

O TRAN

O

TRAN

(EQ. 12)

-------------------------------

------------------------------

t

=

t

=

FALL

RISE

V

– V

V

IN

OUT

where:

I

t

is the transient load current step

is the response time to the application of load

is the response time to the removal of load

TRAN

RISE

FALL

With a lower input source such as 1.8V or 3.3V, the worst

case response time can be either at the application or

removal of load and dependent upon the output voltage

setting. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor's ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q1 and the source of Q2.

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by Equation 11:

conservative guideline. The RMS current rating requirement

V

- V

V

OUT

V

IN

F

OUT

(EQ. 11)

------------------------------- ---------------

ΔI =

•

ΔV

= ΔI x ESR

OUT

x L

S

FN6306.3

December 6, 2006

13

ISL8105, ISL8105A

and do not adequately model power loss due to the reverse

0.60

0.50

0.40

0.30

0.20

0.10

0.00

recovery of the upper and lower MOSFET’s body diode. The

gate-charge losses are dissipated by the ISL8105 and do not

heat the MOSFETs. However, large gate charge increases

0.5Io

the switching interval, t , which increases the MOSFET

SW

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

0.25Io

ΔI = 0Io

Losses while Sourcing Current

2

1

2

--

× D + ⋅ Io × V × t

P

= Io × r

× F

SW S

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY CYCLE (D)

1

TOP

DS(ON)

IN

2

= Io x r

x (1 - D)

BOTTOM

DS(ON)

FIGURE 11. INPUT-CAPACITOR CURRENT MULTIPLIER FOR

SINGLE-PHASE BUCK CONVERTER

Losses while Sinking Current

2

P

= Io x r

x D

TOP

DS(ON)

2

1

2

for the input capacitor of a buck regulator is approximately

as shown in Equation 13.

--

× (1 – D) + ⋅ Io × V × t

P

= Io × r

× F

S

BOTTOM

DS(ON)

IN

SW

(EQ. 14)

V

2

O

ΔI

-------

2

----------

D =

I

=

I

(D – D ) +

D

IN, RMS

O

VIN

Where:

12

D is the duty cycle = V

/ V ,

IN

OUT

is the combined switch ON and OFF time, and

(EQ. 13)

OR

t

SW

FS is the switching frequency.

I

= K

• I

IN, RMS

ICM

O

When operating with a 12V power supply for V

to a minimum supply voltage of 6.5V), a wide variety of

NMOSFETs can be used. Check the absolute maximum

(or down

Bias

For a through-hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series, available from

AVX, and the 593D, available series from Sprague, are both

surge current tested.

V

rating for both MOSFETs; it needs to be above the

GS

highest V

voltage allowed in the system; that usually

rating (which typically correlates with a

Bias

means a 20V V

GS

maximum rating). Low threshold transistors

30V V

DS

(around 1V or below) are not recommended for the reasons

explained in the next paragraph.

For 5V-only operation, given the reduced available gate bias

voltage (5V), logic-level transistors should be used for both

MOSFET Selection/Considerations

N-MOSFETs. Look for r

ratings at 4.5V. Caution

The ISL8105 requires 2 N-Channel power MOSFETs. These

DS(ON)

should be exercised with devices exhibiting very low

characteristics. The shoot-through protection

should be selected based upon r

requirements, and thermal management requirements.

, gate supply

DS(ON)

V

GS(ON)

present aboard the ISL8105 may be circumvented by these

MOSFETs if they have large parasitic impedances and/or

capacitances that would inhibit the gate of the MOSFET from

being discharged below its threshold level before the

complementary MOSFET is turned on. Also avoid MOSFETs

with excessive switching times; the circuitry is expecting

transitions to occur in under 50ns or so.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components: conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the top and the bottom-side MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses

seen when sinking current. When sourcing current, the

top-side MOSFET realizes most of the switching losses. The

bottom-side switch realizes most of the switching losses

when the converter is sinking current (see Equation 14).

These equations assume linear voltage current transitions

Bootstrap Considerations

Figure 12 shows the top-side gate drive (BOOT pin) supplied

by a bootstrap circuit from V

. The boot capacitor, C

,

Bias

BOOT

develops a floating supply voltage referenced to the LX pin.

The supply is refreshed to a voltage of V less the boot

Bias

diode drop (V ) each time the lower MOSFET, Q2, turns on.

D

FN6306.3

December 6, 2006

14

ISL8105, ISL8105A

Check that the voltage rating of the capacitor is above the

maximum V voltage in the system. A 16V rating should

If V

Bias

is 12V, but V is lower (such as 5V), then another

IN

option is to connect the BOOT pin to 12V and remove the

Bias

be sufficient for a 12V system. A value of 0.1µF is typical for

BOOT cap (although, you may want to add a local cap from

many systems driving single MOSFETs.

BOOT to GND). This will make the TGATE V

GS

voltage

+V

BIAS

+

equal to (12V - 5V = 7V). That should be high enough to

drive most MOSFETs, and low enough to improve the

efficiency slightly. Do NOT leave the BOOT pin open, and try

+1V TO +12V

V

D

to get the same effect by driving BOOT through V

and

Bias

-

BOOT

the internal diode; this path is not designed for the high

current pulses that will result.

C

BOOT

Q1

ISL8105

TGATE

LX

V

_G-S≈ V

- V

BIAS D

For low V

voltage applications where efficiency is very

Bias

important, an external BOOT diode (in parallel with the

internal one) may be considered. The external diode drop

has to be lower than the internal one. The resulting higher

+V

BIAS

Q2

V

of the top-side FET will lower its r

. The modest

BGATE

G-S

DS(ON)

-

NOTE:

V

+

gain in efficiency should be balanced against the extra cost

and area of the external diode.

_G-S≈ V

BIAS

For information on the Application circuit, including a

complete Bill-of-Materials and circuit board description, can

be found in Application Note AN1258.

GND

FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION

FN6306.3

December 6, 2006

15

ISL8105, ISL8105A

Dual Flat No-Lead Plastic Package (DFN)

L10.3x3C

2X

0.10 C

A

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

A

D

MILLIMETERS

2X

0.10

C B

SYMBOL

MIN

0.85

-

NOMINAL

0.90

MAX

0.95

0.05

NOTES

A

A1

A3

b

-

E

0.20 REF

0.25

-

6

INDEX

AREA

0.20

2.33

1.59

0.30

2.43

1.69

5, 8

D

3.00 BSC

2.38

-

TOP VIEW

B

A

D2

E

7, 8

3.00 BSC

1.64

-

// 0.10

0.08

C

E2

e

7, 8

C

0.50 BSC

-

A3

C

SIDE VIEW

k

0.20

0.35

-

SEATING

PLANE

L

0.40

0.45

8

N

10

2

D2

D2/2

2

7

8

(DATUM B)

Nd

5

3

Rev. 1 4/06

1

6

NOTES:

INDEX

AREA

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

NX k

E2

(DATUM A)

3. Nd refers to the number of terminals on D.

E2/2

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

NX L

N

N-1

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX b

8

e

5

(Nd-1)Xe

REF.

M

0.10

C A B

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

BOTTOM VIEW

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

C

L

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

(A1)

NX (b)

L

9

5

e

SECTION "C-C"

TERMINAL TIP

C C

FOR ODD TERMINAL/SIDE

FN6306.3

December 6, 2006

16

ISL8105, ISL8105A

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6306.3

December 6, 2006

17


型号：	ISL8105AIRZ
厂家：	Intersil
描述：	+5V or +12V Single-Phase Synchronous Buck Converter PWM Controller with Integrated MOSFET Gate Drivers + 5V或+ 12V单相同步降压转换器的PWM控制器集成MOSFET栅极驱动器驱动器转换器栅极 MOSFET栅极驱动开关光电二极管控制器
文件：	总17页 (文件大小：642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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