ISL80138_14 [INTERSIL]
40V, Low Quiescent Current, 150mA Linear Regulator;
| 型号： | ISL80138_14 |
| 厂家： | 
Intersil |
| 描述： | 40V, Low Quiescent Current, 150mA Linear Regulator |
| 文件： | 总9页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40V, Low Quiescent Current, 150mA Linear Regulator
ISL80138
The ISL80138 is a high voltage, adjustable V
Features
• Wide V Range of 6V to 40V
IN
low quiescent
OUT
current linear regulator ideally suited for “always-on” and “keep
alive” applications. The ISL80138 operates from an input voltage
of +6V to +40V under normal operating conditions and
consumes only 18µA of quiescent current at no load.
• Adjustable Output Voltage from 2.5V to 12V
• Guaranteed 150mA Output Current
• Ultra Low 18µA Typical Quiescent Current
• Low 2µA of Typical Shutdown Current
The ISL80138 features an EN pin that can be used to put the
device into a low-quiescent current shutdown mode where it
draws only 2µA of supply current. The device features
over-temperature shutdown and current limit protection.
• ±1% Accurate Voltage Reference
• Low Dropout Voltage of 295mV at 150mA
• 40V Tolerant Logic Level (TTL/CMOS) Enable Input
• Stable Operation with 10µF Output Capacitor
• 5kV ESD HBM Rated
The ISL80138 is rated over the -40°C to +125°C temperature
range and is available in a 14 lead HTSSOP with an exposed pad
package.
• Thermal Shutdown and Current Limit Protection
• Thermally Enhanced 14 Ld Exposed Pad HTSSOP Package
TABLE 1. KEY DIFFERENCES IN FAMILY OF 40V LDO PARTS
PART NUMBER
ISL80136
MINIMUM I
50mA
ADJ OR FIXED V
OUT
OUT
ADJ
ADJ
Applications
• Industrial
ISL80138
150mA
• Telecommunications
Related Literature
• See FN7970, “ISL80136 40V, Low Quiescent Current, 50mA
Linear Regulator”
25
20
15
10
5
VIN = 14V
CIN
VOUT = 12V
OUT
IN
R1
R2
COUT
10µF
EPAD
0.1µF
EN
(GND) ADJ
0
-50
GND
0
50
100
150
TEMPERATURE (°C)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. QUIESCENT CURRENT vs TEMPERATURE (AT UNITY
GAIN). V = 14V
IN
January 11, 2012
FN7969.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80138
Block Diagram
VIN
EN
CONTROL
LOGIC
FET DRIVER
WITH CURRENT
LIMIT
+
EA
-
VOUT
ADJ
REFERENCE
+
SOFT-START
THERMAL
SENSOR
GND
Pin Configuration
ISL80138 (14 LD HTSSOP)
TOP VIEW
NC
IN
1
2
3
4
5
6
7
14 OUT
13 NC
12 ADJ
11 NC
10 NC
NC
NC
NC
NC
EN
THERMAL
PAD
(GND)
9
8
NC
GND
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 3, 4, 5, 6, 9,
10, 11, 13
NC
Pins have internal termination and can be left unconnected. Connection to ground is optional.
2
7
IN
EN
Input voltage pin. A minimum 0.1µF ceramic capacitor is required for proper operation. Range 6V to 40V.
Enable pin. High on this pin enables the device. Range 0V to V
Ground pin.
.
IN
8
GND
ADJ
OUT
EPAD
12
14
-
This pin is connected to the external feedback resistor divider which sets the LDO output voltage. Range 0V to 3V.
Regulated output voltage. A 10µF ceramic capacitor is required for stability. Range 0V to 12V.
It is recommended to solder the EPAD to the ground plane.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
TEMP. RANGE
(°C)
ENABLE
PIN
OUTPUT VOLTAGE
(V)
PACKAGE
(Pb-Free)
PKG.
DWG. #
MARKING
ISL80138IVEAJZ
ISL80138EVAL1Z
NOTES:
80138 IAJZ
Evaluation Platform
-40 to +125
Yes
ADJ
14 Ld HTSSOP
M14.173B
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80138. For more information on MSL please see techbrief TB363.
FN7969.0
January 11, 2012
2
ISL80138
Absolute Maximum Ratings
Thermal Information
IN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +45V
OUT Pin to GND Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. . .GND - 0.3V to 16V
ADJ Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .. . .GND - 0.3V to 3V
EN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VIN
Output Short-circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Rating
Thermal Resistance (Typical)
14 Ld HTSSOP Package (Notes 4, 5). . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
37
θ
(°C/W)
5
JA
JC
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 2.2kV
Latch Up (Tested per JESD78B; Class II, Level A) . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
IN pin to GND Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to +40V
OUT pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V to +12V
EN pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, unless otherwise noted. V = 14V, I
= 1mA, C = 0.1μF,
OUT IN
IN
C
= 10μF, T = T = -40°C to +125°C, unless otherwise noted. Typical specifications are at T = +25°C. Boldface limits apply over the operating
OUT
temperature range, -40°C to +125°C.
A
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8) TYP (Note 8) UNIT
Input Voltage Range
V
6
40
V
IN
Guaranteed Output
Current
I
V
= V
IN OUT
+ VDO
150
mA
OUT
ADJ Reference Voltage
Line Regulation
V
EN = High, V = 14V, I
IN OUT
= 0.1mA to 150mA
1.211 1.223 1.235
V
OUT
ΔV
ΔV
/ΔV
3V ≤ V ≤ 40V, I
= 1mA
0.04
0.3
7
0.15
0.6
33
%
OUT
IN
IN
OUT
Load Regulation
/ΔI
V
= V
+V
I
= 100µA to 150mA
= 3.3V
%
OUT
ΔV
OUT
IN
OUT
DO, OUT
Dropout Voltage
(Note 6)
I
I
I
I
= 1mA, V
= 3.3V
mV
mV
mV
mV
µA
µA
µA
µA
µA
dB
DO
OUT
OUT
OUT
OUT
OUT
= 150mA, V
380
7
525
33
OUT
OUT
= 1mA, V
= 5V
OUT
= 150mA, V
= 5V
295
2
460
3.64
24
Shutdown Current
Quiescent Current
I
EN = LOW
SHDN
IQ
EN = HIGH, I
EN = HIGH, I
EN = HIGH, I
EN = HIGH, I
f = 100Hz; V
= 0mA
18
22
34
90
66
OUT
OUT
OUT
OUT
= 1mA
42
= 10mA
= 150mA
60
125
Power Supply
PSRR
= 500mV ; Load = 150mA
P-P
IN_RIPPLE
Rejection Ratio
EN FUNCTION
EN Threshold Voltage
V
V
= Off to On
1.485
1.93
V
V
EN_H
OUT
V
V
= On to Off
= 0V
OUT
0.975
EN_L
OUT
EN Pin Current
I
V
0.026
1.65
µA
ms
EN
EN to Regulation Time
(Note 7)
t
EN
FN7969.0
January 11, 2012
3
ISL80138
Electrical Specifications Recommended Operating Conditions, unless otherwise noted. V = 14V, I
= 1mA, C = 0.1μF,
OUT IN
IN
C
= 10μF, T = T = -40°C to +125°C, unless otherwise noted. Typical specifications are at T = +25°C. Boldface limits apply over the operating
OUT
A
J
A
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8) TYP (Note 8) UNIT
PROTECTION FEATURES
Output Current Limit
Thermal Shutdown
I
V
= 0V
175
410
+165
+20
mA
°C
°C
LIMIT
OUT
T
Junction Temperature Rising
SHDN
Thermal Shutdown
Hysteresis
T
HYST
NOTES:
6. Dropout voltage is defined as (V - V
) when V
OUT
is 2% below the value of V
OUT
when V = V + 3V.
IN OUT
IN OUT
7. Enable to Regulation is the time the output takes to reach 95% of its final value with V = 14V and EN is taken from V to V in 5ns. For the adjustable
IN IL IH
versions, the output voltage is set at 5V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7969.0
January 11, 2012
4
ISL80138
Typical Performance Curves
V
= 14V, I
= 1mA, V
OUT OUT
= 5V, T = +25°C, unless otherwise specified.
J
IN
120
30
25
20
15
10
5
+125°C
100
+125°C
80
60
-40°C
+25°C
-40°C
40
+25°C
20
0
0
0
10
20
INPUT VOLTAGE (V)
30
40
0
50
100
150
LOAD CURRENT (mA)
FIGURE 3. QUIESCENT CURRENT vs LOAD CURRENT
FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (NO LOAD)
3.0
2.5
2.0
1.5
1.0
0.5
0
0.010
0.005
0
V
= 40V
= 14V
IN
V
= 5V
OUT
V
IN
V
= 3.3V
OUT
-0.005
-0.010
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE (EN = 0)
FIGURE 6. OUTPUT VOLTAGE vs TEMPERATURE (LOAD = 50mA)
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
500mV/DIV
EN
1V/DIV
+125°C
+25°C
VOUT
-40°C
TIME = 500µs/DIV
0
50
100
150
LOAD CURRENT (mA)
FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT
FIGURE 8. START-UP WAVEFORM
FN7969.0
January 11, 2012
5
ISL80138
Typical Performance Curves
V
= 14V, I
= 1mA, V = 5V, T = +25°C, unless otherwise specified. (Continued)
OUT J
IN
OUT
70
TIME = 5ms/DIV
60
V
= 3.3V
OUT
50
40
30
20
10
0
V
100mV/DIV
OUT
V
= 5V
OUT
I
0mA
OUT
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 9. POWER SUPPLY REJECTION RATIO (LOAD = 150mA)
FIGURE 10. LOAD TRANSIENT RESPONSE
FN7969.0
January 11, 2012
6
ISL80138
The output voltage is calculated using Equation 1:
Functional Description
Functional Overview
R
⎛
⎜
⎝
⎞
1
(EQ. 1)
------
V
= 1.223V ×
+ 1
⎟
⎠
OUT
R
2
The ISL80138 is a high performance, high voltage, low-dropout
regulator (LDO) with 150mA sourcing capability. The part is rated
to operate over the -40°C to +125°C temperature range.
Featuring ultra-low quiescent current, it is an ideal choice for
“always-on” applications. It works well under a “load dump
condition” where the input voltage could rise up to 40V. This LDO
device also features current limit and thermal shutdown
protection.
Power Dissipation
The junction temperature must not exceed the range specified in
“Recommended Operating Conditions” on page 3. The power
dissipation can be calculated using Equation 2:
P
= (V – V
) × I
+ V × I
OUT IN GND
(EQ. 2)
D
IN
OUT
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
the maximum allowable junction temperature rise (ΔT ), as shown
in Equation 3:
and the
will determine
J(MAX)
Enable Control
The ISL80138 has an enable pin, which turns the device on when
pulled high. When EN is low, the IC goes into shutdown mode and
draws less than 2µA. In “always-on” applications, EN can be tied
to IN.
J
(EQ. 3)
ΔT = T
– T
A(MAX)
J
J(MAX)
To calculate the maximum ambient operating temperature, use
Current Limit Protection
the junction-to-ambient thermal resistance (θ ) as shown in
JA
The ISL80138 has internal current limiting functionality to
protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current largely independent
of the output voltage. If the short or overload is removed from
Equation 4:
(EQ. 4)
T
= P
x θ + T
D(MAX) JA A
J(MAX)
V
, the output returns to normal voltage regulation mode.
Board Layout Recommendations
OUT
A good PCB layout is important to achieve expected
Thermal Fault Protection
performance. Consideration should be taken when placing the
components and routing the trace to minimize the ground
impedance and keep the parasitic inductance low. The input and
output capacitors should have a good ground connection and be
placed as close to the IC as possible. The feedback trace in the
adjustable version should be away from other noisy traces.
The 14 Ld HTSSOP package uses the copper area on the PCB as
a heat-sink. The EPAD of this package must be soldered to the
copper plane (GND plane) for effective heat dissipation.
In the event that the die temperature exceeds a typical value of
+165°C, the output of the LDO will shut down until the die
temperature cools down to a typical +145°C. The level of power
dissipated, combined with the ambient temperature and the
thermal impedance of the package, determines if the junction
temperature exceeds the thermal shutdown temperature. See
the “Power Dissipation” section on page 7 for more details.
Application Information
Input and Output Capacitors
Figure 12 shows a curve for θ of the package for different
copper area sizes.
JA
38
A minimum 0.1µF ceramic capacitor is recommended at the
input for proper operation. For the output, a ceramic capacitor
with a capacitance of 10µF is recommended for the ISL80138 to
maintain stability. The ground connection of the output capacitor
should be routed directly to the GND pin of the device and also
placed close to the IC.
36
34
32
30
28
26
Output Voltage Setting
The ISL80138 output voltage is programmed using an external
resistor divider as shown in Figure 11.
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 12. θ vs EPAD-MOUNT COPPER LAND AREA ON PCB
JA
OUT
ADJ
IN
CIN
0.1µF
COUT
10µF
R1
R2
EN
GND
FIGURE 11. OUTPUT VOLTAGE SETTING
FN7969.0
January 11, 2012
7
ISL80138
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
January 11, 2012 FN7969.0 Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL80138
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7969.0
January 11, 2012
8
ISL80138
Package Outline Drawing
M14.173B
14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP)
Rev 1, 1/10
A
1
3
3.10 ±0.10
5.00 ±0.10
8
14
SEE
DETAIL "X"
6.40
PIN #1
I.D. MARK
3.00 ±0.10
4.40 ±0.10
2
3
0.20 C B A
1
7
B
EXPOSED THERMAL PAD
BOTTOM VIEW
0.65
0.15 +0.05/-0.06
END VIEW
TOP VIEW
1.00 REF
H
0.05
C
0.90 +0.15/-0.10
1.20 MAX
5
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
0.10 CBA
0.10 C
0°-8°
0.05 MIN
0.15 MAX
0.60 ±0.15
SIDE VIEW
(3.10)
DETAIL "X"
(1.45)
(3.00)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion.
Allowable protrusion shall be 0.80mm total in excess of dimension at
maximum material condition.
Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153, variation ABT-1.
FN7969.0
January 11, 2012
9
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