ISL6884 [INTERSIL]
CCFL Brightness Controller; CCFL亮度控制器
| 型号： | ISL6884 |
| 厂家： | 
Intersil |
| 描述： | CCFL Brightness Controller |
| 文件： | 总13页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6884
®
Data Sheet
March 9, 2006
FN9265.0
CCFL Brightness Controller
Features
• Wide Supply Voltage Range of 3.0V to 5.5V
ISL6884 controls Pulse Width Modulated Dimming for up to
8 inverters to supply power to up to 40 Cold Cathode
Fluorescent Lamps (CCFL) for back lighting in large LCD
displays.
• Dimming
2
- I C dimming control input
- PWM dimming can be synchronized to an external
source or set by an internal, adjustable oscillator.
2
The ISL6884 brightness controller provides an I C interface
for dimming control, enable, status, and brightness balance.
The duty cycle of all 8 DPWM outputs is adjusted with a
Master Brightness Control register. The duty cycle of each of
the 8 DPWM outputs can be offset from the master
brightness to adjust for uniform brightness.
- 8 channel dimming allows the user to balance the
2
brightness of the CCFL lamps via I C control
- User programmable fault time out
• User Programmable Fault Time Out
2
• I C Status Output
The PWM dimming frequency can be set by an internal,
adjustable oscillator or synchronized to an external source to
minimize interference with video.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6884’s slave address is:
• 1101_1111 for reading
• 1101_1110 for writing
ISL6884
(20 LD SSOP)
TOP VIEW
1
2
20
19
18
17
16
LAMP_ON
TESTEN
GNDPLL
PLL1
VDD
REGCAP
DPWM_8
DPWM_7
DPWM_6
3
Ordering Information
4
PART
TEMP. RANGE
PKG.
o
5
EN
NUMBER
( C)
PACKAGE
DWG. #
DPWM_SYNC
OSCTEST
SCL
6
15 DPWM_5
14 DPWM_4
ISL6884IAZ
(See Note)
-40 to 85
-40 to 85
20 Ld SSOP
(Pb-free)
M20.15
7
DPWM_3
8
13
ISL6884IAZ-T
(See Note)
20 Ld SSOP Tape M20.15
and Reel
(Pb-free)
SDA
DPWM_2
9
12
GND
DPWM_1
10
11
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6884
Block Diagram
VDD
REGCAP
LAMP ON
GND
2.5V REG
BGREF
POR
ENAB
EN
I2C ENABLE
STATUS
fault timer
DPWM_8
DPWM_7
DPWM_6
DPWM_5
DPWM_4
DPWM_3
DPWM_2
DPWM_1
PWM
DIMMING
PLL
DPWM SYNC
8 CH DPWM GEN
PLL1
GNDPLL
OSC
8
BRIGHTNESS
STATUS
TESTEN
OSCTEST
SDA
SCL
I2C
interface
ENABLE (I2C)
CCFL Brightness Controller
FN9265.0
March 9, 2006
2
ISL6884
Simplified System Diagram - Central Controller and Multiple Local Controllers
ISL6884
SYSTEM I2C
SCL
SDA
CENTRAL
MASTER
CONTROLLER
CCFL
DRIVE
DRIVE
PM IN
ISL6883
DRIVER
ISL6882
LOCAL
CCFL
CCFL
IFB
VFB
DPWM
CONTROLLER
PHASE MODULATION OUT
CCFL
CCFL
CCFL
DRIVE
IFB
PM IN
DRIVE
DRIVE
DRIVE
ISL6883
DRIVER
ISL6882
LOCAL
VFB
DPWM
CONTROLLER
PHASE MODULATION OUT
CCFL
CCFL
CCFL
DRIVE
IFB
PM IN
ISL6883
DRIVER
ISL6882
LOCAL
VFB
DPWM
CONTROLLER
PHASE MODULATION OUT
CCFL
CCFL
CCFL
DRIVE
IFB
PM IN
ISL6883
DRIVER
ISL6882
LOCAL
VFB
DPWM
CONTROLLER
PHASE MODULATION OUT
FN9265.0
March 9, 2006
3
ISL6884
ISL6884 Application Schematic
external
LAMPON
hardware
output from
ISL6882
enable
Use these parts
to adjust the
internal DPWM
oscillator
VDD
LAMP_ON
VDD
1
20
19
18
17
16
15
14
13
12
11
frequency
TESTEN
GNDPLL
PLL1
REGCAP
DPWM_8
DPWM_7
DPWM_6
DPWM_5
DPWM_4
DPWM_3
DPWM_2
DPWM_1
2
3300
3
4
EN
to DPWM
dimming
inputs to
up to 8
5
2200
1uF
DPWM_SYNC
OSCTEST
SCL
ISL6884
6
7
8
ISL6882
SDA
9
GND
10
0.47uF
to the system master,
other I2C devices and
pull up resisters
0.1uF
73.2K
1uF
1uF
This is the LPF for
the DPWM PLL
0.01uF
external signal to
sync DPWM
FN9265.0
March 9, 2006
4
ISL6884
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input/Output Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Thermal Information
Thermal Resistance (Typical, Notes 1)
20 Ld SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
θ
(°C/W)
110
JA
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER ON RESET
VDD Rising
POR
POR
2.4
2.2
-
2.7
2.5
3.0
2.7
-
V
V
rising
VDD Falling
falling
POR Hysteresis
VOLTAGE REGULATOR
Regulated Voltage
POR
200
mV
hyst
V
External Capacitor = 1µF, ESR<1Ω
2.3
2.5
2.7
V
reg
LOGIC LEVEL INPUTS (EN, DPWM_SYNC, LAMPON)
V In High
VIH
2.6
-
-
V
V
LOGIC
V In Low
VIL
-
-
-
-
-
0.8
LOGIC
Hysteresis
Input Current
Vhyst
140
10
-10
-
-
-
mV
nA
nA
I
V
V
= VDD
= 0V
_IN
in
in
2
I C
V In Low
V
-
-
0.3*VDD
V
V
IL
V In High
V
0.7*VDD
-
-
-
IH
Schmitt Trigger Input Hysteresis
V Out Low
V
-
-
-
0.05*VDD
V
hys
V
I in low = 3mA
-
0.4
-
V
OL
SDA, SCL Rise Time
T
Cload = 200pF
Rpullup = 1700, 30%-70%
300
ns
rise_I2C
SDA, SCL Fall Time
T
Cload = 200pF
Rpullup = 1700, 30%-70%
-
-
300
ns
fall_I2C
FN9265.0
5
March 9, 2006
ISL6884
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DPWM
DPWM PLL Free Run Frequency
DPWM PLL Lock Frequency
Lock Time
f
-
160
-
Hz
Hz
ms
%
freerun
f
120
160
200
lock
T
-
150
-
5
lock
DPWM Duty Cycle
DPWM Duty Cycle
DPWM Duty Cycle
DPWM Output High
DPWM Output Low
DPWM Rise Time
DPWM Fall Time
DPWM
DPWM
DPWM
BRT_M = 00hex (Note 3)
3
4
50
-
DCmin
DCmid
DCmax
BRT_M = 7Fhex (Note 3)
BRT_M = FFhex (Note 3)
49
51
%
98
100
-
%
V
I
I
= 2mA
= 2mA
0.7*VDD
-
V
OH
OH
OL
V
-
-
-
-
0.3*VDD
500
500
V
OL
T
Cload = 200pF
Cload = 200pF
-
ns
ns
rise_DPWM
T
-
fall_DPWM
NOTE:
2. Master enable (0X2B) = 01, channel enable (0X2C) = FF, all other registers in default mode
GNDPLL - A separate ground terminal for the PLL. Filter
and bias components on PLL1 should be connected to this
ground with the shortest possible traces. This pin is also
connected to the system ground with a trace that is not
critical.
Pin Description
VDD - Power input for digital systems. All functions are
disabled unless this pin exceeds 3V (see Power On Reset
specs). A 0.01µF decoupling cap should be placed between
VDD and GND with the shortest possible traces.
DPWM 1:8 - Logic level outputs that control the analog and
PWM dimming of each of 8 ISL6882s. The duty cycle of the
DPWM signals range from 4% (minimum brightness) to
100% (maximum brightness). A low pass filter in the inverter
Controller converts the DPWM duty cycle to a DC voltage
that performs 3:1 analog dimming. The combined dimming
GND - Ground for digital systems.
REGCAP - An external 1µF capacitor to decouple the
internal 2.5V regulator.
EN - Logic level input signal. Voltage at this pin above a
threshold ENables circuit operation.
2
range is 100:1. The dimming value is set by I C registers.
DPWM SYNC - A logic level input signal. The dimming PWM
frequency oscillator will synchronize to this signal (if
present). If no signal is present at this pin, the internal
DPWM oscillator will free run at approximately 160Hz.
LAMP_ON - A logic level input signal. A high level on the pin
indicates that all lamps are ON and operating normally. A low
level at this pin indicates that at least one of the lamps is
either not ignited or out of the circuit. When this pin is low,
the fault timer runs. When this pin is high, the fault timer is
reset. Because this is a high impedance line that may be
routed near sources of EMI, it is recommended that a 10K
resister is placed in series between the LAMP_ON pin and
all other circuits.
PLL1 - Analog input. An RC network on these pins sets the
loop response of the DPWM Phase Locked Loop. A voltage
source or resister divider at this pin will set the DPWM
frequency. See the graph below for approximate frequency
vs voltage at PLL1.
2
SDA, SCL - Logic level input/output signals. SDA is the I C
220
200
180
160
140
120
2
data line and SCL is the I C clock line. The ISL6884
2
receives data via I C to enable or disable the inverters, set
dimming for each channel, and set the number of channels.
2
System status can be read via I C.
TESTEN and OSCTEST - These pins are used for internal
tests. They should be left unconnected in normal operation.
100
80
F_DPWM=V_PLL1*160+8
measured
60
0.5
0.7
0.9
1.1
1.3
Voltage at PLL1 (V)
FN9265.0
6
March 9, 2006
ISL6884
2
I C Register Description
Register addresses and default values are given in the
following Register Description Table.
2
I C Slave Address - ISL6884’s slave address is:
• 1101_1111 for reading
• 1101_1110 for writing
BRT_M - Master Brightness Control input. This register
controls the duty cycle of al 8 DPWM outputs.
BRT_OS[1..8] - Brightness offset. These registers allow the
system designer to increase or decrease the duty cycle of
individual channel to equalize the brightness of all lamps in a
system. Note: Value is stored as 2’s complement number.
MSTR_EN - Master Enable, This signal is AND’ed with the
EN pin to create the enable for the PWM dimming output. If
this bit OR the EN pin is low the DPWM outputs are held low.
CH_EN - Individual Channel Enables for each DPWM
output. If only DPWM 1, 3, 5 and 7 are to be used, CH_EN
bits 1, 3, 5, and 7 should be set to 1 and bits 2, 4, 6, and 8
should be set to 0.
FLT_TOUT - Fault Timer Time Out Setting. This register
controls the response of the ISL6884 to a logic low input on
the LAMPON pin (indicating that one or more lamps is NOT
ON). A value between 0X01 and 0XFF in the FLT_TOUT
register will set the time that ISL6884 will operate with a low
signal at the LAMPON pin (fault time out). The adjustment
range is from less than 0.1 second to approximately 2
seconds. The power on reset default time out is 1 second.
After a fault time out, all DPWM outputs are latched low until
power is cycled. If FLT_TOUT is set to 0X00, ISL6884 will
not time out and will continue to operate even with a low
signal at the LAMPON pin.
STATUS - indicates the status of the Time out Fault,
LAMPON input signal and ENABLE (MSTR_EN AND EN
pin).
FN9265.0
7
March 9, 2006
ISL6884
Register Description Table
Register Descriptions:
NOTES:
1. sb denotes sign bit for 2’s compliment numbers.
2. The second row shows the register’s default value loaded at Power On Reset.
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS)
WORD NAME
DESCRIPTION
BYTE
ADDRESS
MSB LABEL BIT 6 LABEL BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL BIT 2 LABEL BIT 1 LABEL LSB LABEL
POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE
Brightness Magnitude Setting
POR
BRT_M
0x00
b7
0
b6
0
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
POR
brt_os1
0x01
Brightness Offset for Light Sensor 1. Note: Value is stored as 2’s complement number
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os2
0x02
Brightness Offset for Light Sensor 2. Note: Value is stored as 2’s complement number.
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os3
0x03
Brightness Offset for Light Sensor 3. Note: Value is stored as 2’s complement number
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os4
0x04
Brightness Offset for Light Sensor 4. Note: Value is stored as 2’s complement number.
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os5
0x05
Brightness Offset for Light Sensor 5. Note: Value is stored as 2’s complement number
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os6
0x06
Brightness Offset for Light Sensor 6. Note: Value is stored as 2’s complement number.
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os7
0x07
Brightness Offset for Light Sensor 7. Note: Value is stored as 2’s complement number.
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
brt_os8
0x08
Brightness Offset for Light Sensor 8. Note: Value is stored as 2’s complement number.
sb
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
0
0
mstr_en
0x2a
Master Enable, This signal is AND’ed with the en pin to create the enable for the PWM dimming output.
mstr_en
0
POR
0
0
0
0
0
0
0
ch_en
0x2b
Individual Channel Enables for each DPWM output.
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
POR
flt_tout
Fault Timer Time Out Setting.
FN9265.0
March 9, 2006
8
ISL6884
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) (Continued)
DESCRIPTION
WORD NAME
BYTE
ADDRESS
MSB LABEL BIT 6 LABEL BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL BIT 2 LABEL BIT 1 LABEL LSB LABEL
POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE
POR
0x2c
b7
b6
b5
b4
b3
b2
b1
b0
POR
CM
1
0
0
0
0
2
0
0
0
Maximum Fails Setting. This value determines how many consecutive I C fails can occur before channel is faulted.
b1
0x2d
POR
b0
1
0
0
0
0
0
0
0
2
2
2
i c_suh
I C Setup/Hold Preset Value. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
_pres
0x2E
POR
b5
b4
0
b3
0
b2
1
b1
1
b0
0
0
0
0
2
2
2
i c_scl
I C SCL High Time Preset Value. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
_hpres
0x2f
b5
b4
0
b3
0
b2
1
b1
0
b0
0
POR
0
0
0
2
2
2
i c_scl_
I C SCL Low Time Preset Value. See I C Document for description.
lpres
0x30
POR
Caution! Changing this register from its default value may result in unpredictable behavior
b5
0
b4
1
b3
0
b2
0
b1
1
b0
0
0
0
2
2
2
i c_bfree
I C Bus Free Time Value. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
0x31
POR
b5
0
b4
0
b3
1
b2
0
b1
1
b0
1
0
0
2
2
2
i c
I C Stretch Value. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
_stretch
0x32
i2c_stretch
0
POR
0
0
0
0
0
0
0
2
toc_spd
_ctrl
Time Out Counter Speed Control. See I C Document for description
Caution! Changing this register from its default value may result in unpredictable behavior
0x33
POR
b18
b17
0
b16
0
0
0
0
0
0
0
2
toc_spd
_ctrl
Time Out Counter Speed Control. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
0x34
POR
b15
1
b14
1
b13
b12
0
b11
0
b10
1
b9
1
b8
1
1
2
toc_spd
_ctrl
Time Out Counter Speed Control. See I C Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
0x35
POR
b7
0
b6
0
b5
1
b4
1
b3
1
b2
0
b1
0
b0
0
dc_max
Duty Cycle Maximum Setting. See DPWM Document for description
Caution! Changing this register from its default value may result in unpredictable behavior
0x36
POR
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
dc_min
Duty Cycle Minimum Setting. See DPWM Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
FN9265.0
March 9, 2006
9
ISL6884
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) (Continued)
DESCRIPTION
WORD NAME
BYTE
ADDRESS
MSB LABEL BIT 6 LABEL BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL BIT 2 LABEL BIT 1 LABEL LSB LABEL
POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE
POR
0x37
POR
b7
0
b6
0
b5
0
b4
0
b3
1
b2
0
b1
0
b0
1
pwm_
sync_sel
PWM Sync Mode Select.
PWM_SYNC_SEL = xxxxxx00: INTERNAL ONLY. DPWM frequency set by an internal oscillator. External DPWM_SYNC is
ignored.
PWM_SYNC_SEL = xxxxxx01: AUTOMATIC SYNC SELECT. DPWM frequency set by an external DPWM_SYNC signal if it is
present or by the internal oscillator if no external signal is present.
PWM_SYNC_SEL = xxxxxx10: EXTERNAL ONLY. DPWM frequency set by an external signal at DPWM_SYNC. No signal at
DPWM_SYNC results in no DPWM output switching.
0x38
POR
pwm_sync
_sel2
pwm_sync
_sel1
0
0
0
0
0
0
0
1
pll_bypass
pmp1
pmp0
Bypass PLL bit = 1 forces DPWM frequency to an internal oscillator.
Charge Pump Bit1. See Plan 9 CDR Document for description.
Charge Pump Bit0. See Plan 9 CDR Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
0x39
POR
pll_bypass
pmp1
0
pmp0
0
0
0
0
0
0
0
Mux Selection for test mode mux. If the part is in test mode, the decode of this value changes the following pins:mx_sel = 0: dpwm6, dpwm7,
dpwm8 in functional mode.
mx_sel = 1: dpwm6 = vco_out, dpwm7 = div512_out, dpwm8 = div64_clk.
mx_sel = 2: dpwm6 in functional mode, dpwm7 = clk_d4, dpwm8 = dpwm_clk.
Caution! Changing this register from its default value may result in unpredictable behavior
0x3A
mx_sel
b3
b2
0
b1
0
b0
0
POR
0
0
0
0
0
FN9265.0
March 9, 2006
10
ISL6884
2
Data Validity
I C Bus General Description
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
Introduction
2
(Refer to Philips I C Specification, Rev. 2.1)
2
The I C bus is a 2 wire communication bus for integrated
2
circuits. I C, I2C or IIC are commonly used instead of the
formal name Inter-Integrated-Circuit bus. The 2 wires are the
SCL (Serial CLock) and SDA (Serial DAta). All ICs on the
bus are connected to the SCL and SDA lines. SCL and SDA
pins on each device are bidirectional and can act as either
inputs or open drain outputs. Which device is transmitting
and receiving is determined by the bus protocol which will be
described below.
SDA
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
VDD
FIGURE 2. DATA VALIDITY
I2C Slave
input
state
machine,
registers,
memory,
etc.
SCL
output
input
control
Byte Format
I2C Master
input
SDA
control
SCL
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
output
input
output
control
CPU
SDA
output
control
I2C Slave
SCL
control
input
output
input
state
machine,
registers,
memory,
etc.
SDA
output
control
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
to other
slave devices
2
A typical I C bus system is made of a ‘master’ that initiates
communication (usually a microprocessor) and one or more
‘slaves’ that respond to commands from the master. Each
slave has a device address. In a typical communication
sequence, the master will initiate communication with a ‘start
condition’ followed by the address of one of the slave
devices. The slave device must acknowledge that it
recognizes its address. After receiving the acknowledge, the
master will transmit one or more bytes of commands and
data. If the slave device is an EEPROM the command is the
address within the EEPROM that is to be read or written. If
data is to be written to the EEPROM the master transmits it
after the command.
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
SCL
8
2
1
9
START and STOP Conditions
As shown in Figure 1, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
SDA
MSB
START
ACKNOWLEDGE
FROM SLAVE
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
2
FIGURE 3. ACKNOWLEDGE ON THE I C BUS
SDA
SCL
S
P
START
STOP
CONDITION
CONDITION
FIGURE 1. START AND STOP WAVEFORMS
FN9265.0
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11
ISL6884
2
I C Transactions Between the System Master and the ISL6884
Below are typical transactions between the system master and the ISL6884.
WRITING TO ONE REGISTER IN ISL6884
SCL
1
1
0
1
1
1
1
0
SDA
ISL6884
DEVICE ADDRESS
DATA WRITTEN TO THE
REGISTER ADDRESS
REGISTER ADDRESS
WRITING N CONSECUTIVE REGISTERS TO ISL6884
SCL
SDA
0
1
1
1
1
1
1
0
DATA WRITTEN TO THE
REGISTER ADDRESS
A+n
ISL6884
DEVICE
DATA WRITTEN TO THE
REGISTER ADDRESS
A+1
DATA WRITTEN TO THE
REGISTER ADDRESS
REGISTER ADDRESS A
WRITE ADDRESS
READING ONE REGISTER IN ISL6884
SCL
SDA
0
1
0 1
1 1
1
1
1
1
1
0
1
1
1
1
ISL6884
DEVICE
ISL6884
DEVICE
REGISTER ADDRESS
DATA READ FROM THE
READ ADDRESS
WRITE ADDRESS
REGISTER ADDRESS
READING CONSECUTIVE REGISTER FROM ISL6884
SCL
SDA
0
1
0 1
1 1
1
1
1
1
1
0
1
1
1
1
ISL6884
DEVICE
DATA READ FROM
REGISTER ADDRESS
A
DATA READ FROM
ISL6884
DEVICE
FIRST REGISTER
REGISTER ADDRESS
ADDRESS
READ ADDRESS
A+n
WRITE ADDRESS
A
FN9265.0
12
March 9, 2006
ISL6884
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
N
M20.15
INDEX
0.25(0.010)
M
B M
H
AREA
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
E
GAUGE
PLANE
-B-
INCHES
MIN
0.053
0.004
-
MILLIMETERS
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.344
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
8.74
3.98
NOTES
1
2
3
A
A1
A2
B
-
L
-
0.25
0.010
SEATING PLANE
A
-
-A-
D
h x 45°
0.008
0.007
0.337
0.150
0.20
0.18
8.56
3.81
9
C
D
E
-
-C-
α
3
A2
e
A1
4
C
B
0.10(0.004)
e
0.025 BSC
0.635 BSC
-
0.17(0.007) M
C
A M B S
H
h
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
5
NOTES:
L
6
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
N
α
20
20
7
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
0°
8°
0°
8°
-
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” di-
mension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9265.0
13
March 9, 2006
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