ISL6842IRZ-T [INTERSIL]
Improved Industry Standard Single-Ended Current Mode PWM Controller; 提高行业标准的单端电流模式PWM控制器型号: | ISL6842IRZ-T |
厂家: | Intersil |
描述: | Improved Industry Standard Single-Ended Current Mode PWM Controller |
文件: | 总11页 (文件大小:306K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6840, ISL6841, ISL6842,
ISL6843, ISL6844, ISL6845
®
Data Sheet
June 28, 2005
FN9124.6
Improved Industry Standard Single-Ended
Current Mode PWM Controller
Features
• 1A MOSFET gate driver
The ISL6840, ISL6841, ISL6842, ISL6843, ISL6844,
ISL6845 family of adjustable frequency, low power, pulse
width modulating (PWM) current mode controllers is
designed for a wide range of power conversion applications
including boost, flyback, and isolated output configurations.
Peak current mode control effectively handles power
transients and provides inherent overcurrent protection.
• 60µA startup current, 100µA maximum
• 25ns propagation delay current sense to output
• Fast transient response with peak current mode control
• Adjustable switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
This advanced BiCMOS design is pin compatible with the
industry standard 384x family of controllers and offers
significantly improved performance. Features include low
operating current, 60µA start-up current, adjustable
operating frequency to 2MHz, and high peak current drive
capability with 20ns rise and fall times.
• Trimmed timing capacitor discharge current for accurate
deadtime/maximum duty cycle control
• High bandwidth error amplifier
• Tight tolerance voltage reference over line, load, and
temperature
• Tight tolerance current limit threshold
• Pb-Free Plus Anneal Available (RoHS Compliant)
PART NUMBER
ISL6840
RISING UVLO
7.0
MAX. DUTY CYCLE
100%
50%
Applications
ISL6841
7.0
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
ISL6842
14.4V
8.4V
100%
100%
50%
ISL6843
ISL6844
14.4V
8.4V
• Industrial Power Systems
• PC Power Supplies
ISL6845
50%
• Isolated Buck and Flyback Regulators
• Boost Regulators
Pinout
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
8-PIN SOIC, MSOP
TOP VIEW
COMP
FB
1
2
3
4
8
7
VREF
VDD
OUT
GND
CS
6
5
RTCT
DFN 8 LEAD
TOP VIEW
COMP
VREF
1
8
7
6
5
FB
CS
VDD
OUT
GND
2
3
4
RTCT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Ordering Information
Ordering Information
TEMP. RANGE
PKG.
TEMP. RANGE
PKG.
PART NUMBER
(°C)
PACKAGE
DWG. #
PART NUMBER
(°C)
PACKAGE
DWG. #
ISL6840IRZ-T*
(See Note)
-40 to 105
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6840IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
ISL6840IBZ
(See Note)
8 Ld SOIC
(Pb-free)
M8.15
ISL6841IRZ-T*
(See Note)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6840IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6842IRZ-T
(See Note)
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6840IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6843IRZ-T
(See Note)
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6841IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6841IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6844IRZ-T*
(See Note)
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6841IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6845IRZ-T
(See Note)
8 Ld 2x3 DFN L8.2x3
(Pb-free)
ISL6841IUZ
(See Note)
8 Ld MSOP
(Pb-free)
Add -T to part number for Tape and Reel packaging.
*Contact Factory for Availability
ISL6842IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6842IBZ
(See Note)
8 Ld SOIC
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL6842IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6842IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6843IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6843IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6843IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6843IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6844IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6844IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6844IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6844IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6845IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6845IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6845IU
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
ISL6845IUZ
(See Note)
8 Ld MSOP
(Pb-free)
FN9124.6
2
June 28, 2005
Functional Block Diagram
VREF
VDD
VREF
5.00 V
UVLO
COMPARATOR
ENABLE
VDD OK
+
-
-
VREF FAULT
+
+
-
BG
VREF
UV COMPARATOR
GND
4.65V ↓ 4.80V ↑
A
BG
2.5 V
A=0.5
PWM
COMPARATOR
CS
+
-
100mV
ERROR
AMPLIFIER
2R
R
1.1V
CLAMP
ISL6841/4/5 ONLY
+
-
FB
Q
T
Q
COMP
OUT
VREF
S
R
Q
Q
2.6V
0.7V
RESET
DOMINANT
ON
OSCILLATOR
COMPARATOR
-
RTCT
+
CLOCK
P/N
UVLO ON/OFF
7.0 / 6.6V
14.3 / 8.8V
8.4 / 7.2V
8.4mA
ON
-40, -41
-42, -44
-43, -45
Typical Application - 48V Input Dual Output Flyback
CR5
+3.3V
+1.8V
C21
+ C15
+ C16
T1
R21
VIN+
C4
R3
CR4
+
C22
+
C17
C6
C20
C2
C19
CR2
C5
RETURN
CR6
R1
36-75V
R17
R19
R18
R16
U2
C1
C3
Q1
C14
R4
R15
R22
C13
U3
VIN-
R27
R20
U4
COMP
R26
VREF
V
CS
FB
DD
OUT
RTCT
GND
ISL684x
R6
R10
CR1
Q3
C12
C8
VR1
C11
R13
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 1)
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
θ
(°C/W)
θ
(°C/W)
JC
DD
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
JA
+ 0.3V
DD
DFN Package (Note 2). . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
MSOP Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . .-55°C to 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC- Lead Tips Only)
77
100
130
6
N/A
N/A
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Operating Conditions
Temperature Range
ISL684xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical)
ISL6840/1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V -14V
ISL6843/5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V -16V
ISL6842/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V -18V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
3. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. V
A
= 15V (Note 7), Rt = 10kΩ, Ct = 3.3nF, T = -40 to 105°C (Note 4), Typical values are at
A
DD
T
= 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT
START Threshold (ISL6840, ISL6841)
START Threshold (ISL6843, ISL6845)
START Threshold (ISL6842, ISL6844)
STOP Threshold (ISL6840, ISL6841)
STOP Threshold (ISL6843, ISL6845)
STOP Threshold (ISL6842, ISL6844)
Hysteresis (ISL6840, ISL6841)
6.5
7.0
8.4
14.3
6.6
7.2
8.8
0.4
0.8
5.4
60
7.5
9.0
15.3
6.9
7.7
9.6
-
V
V
7.8
13.3
V
6.1
V
6.7
V
8.0
V
-
-
-
-
-
-
V
Hysteresis (ISL6843, ISL6845)
-
V
Hysteresis (ISL6842, ISL6844)
-
V
Startup Current, I
DD
V
< START Threshold
100
4.0
5.5
µA
mA
mA
DD
Operating Current, I
(Note 5)
3.3
4.1
DD
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
Includes 1nF GATE loading
D
Over line (V
= 12V to 18V), load,
4.925
5.000
5.050
V
DD
temperature
Long Term Stability
Fault Voltage
T
= 125°C, 1000 hours (Note 6)
-
5
4.65
4.80
165
-
-
mV
V
A
4.40
4.60
50
4.85
VREF Good Voltage
Hysteresis
VREF-0.05
V
250
mV
mA
mA
Current Limit, Sourcing
Current Limit, Sinking
-20
5
-
-
-
FN9124.6
June 28, 2005
5
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. V
A
= 15V (Note 7), Rt = 10kΩ, Ct = 3.3nF, T = -40 to 105°C (Note 4), Typical values are at
A
DD
= 25°C (Continued)
T
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT SENSE
Input Bias Current
CS Offset Voltage
V
V
V
= 1V
-1.0
95
-
1.0
105
1.30
1.03
3.5
µA
mV
V
CS
CS
CS
= 0V (Note 6)
= 0V (Note 6)
100
1.15
0.97
3.0
COMP to PWM Comparator Offset Voltage
Input Signal, Maximum
0.80
0.91
2.5
V
Gain, A
= ∆V
/∆V
0 < V < 910mV, V = 0V
CS FB
V/V
CS
COMP
CS
(Note 6)
(Note 6)
CS to OUT Delay
-
25
40
ns
ERROR AMPLIFIER
Open Loop Voltage Gain
Unity Gain Bandwidth
Reference Voltage
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
(Note 6)
(Note 6)
60
3.5
90
-
dB
MHz
V
5
-
2.55
1.0
-
V
V
V
V
V
V
= V
2.475
-1.0
1.0
2.514
FB
FB
COMP
= 0V
-0.2
µA
mA
mA
V
= 1.5V, V = 2.7V
FB
-
-
COMP
COMP
= 1.5V, V = 2.3V
FB
-0.4
4.80
0.4
-
= 2.3V
-
VREF
1.0
-
FB
FB
COMP VOL
= 2.7V
-
V
PSRR
Frequency = 120Hz, V
18V (Note 6)
= 12V to
60
80
dB
DD
OSCILLATOR
Frequency Accuracy
Initial, T = 25°C
49
52
0.2
-
55
1.0
5
kHz
%
J
Frequency Variation with V
Temperature Stability
Amplitude, Peak to Peak
RTCT Discharge Voltage
Discharge Current
OUTPUT
T = 25°C (F
- F
)/F
-
DD
18V 12V 12V
(Note 6)
-
-
%
1.9
0.7
8.4
-
V
-
-
V
RTCT = 2.0V
7.2
9.5
mA
Gate VOH
V
- OUT, I
OUT
= -200mA
= 200mA
-
-
-
-
-
1.0
1.0
1.0
20
2.0
2.0
-
V
V
DD
OUT - GND, I
Gate VOL
OUT
Peak Output Current
Rise Time
C
C
C
= 1nF (Note 6)
= 1nF (Note 6)
= 1nF (Note 6)
A
OUT
OUT
OUT
40
40
ns
ns
Fall Time
20
PWM
Maximum Duty Cycle
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844, ISL6845
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844, ISL6845
94
47
-
96
48
-
-
-
%
%
%
%
Minimum Duty Cycle
0
0
-
-
NOTES:
4. Specifications at -40°C are guaranteed by design, not production tested.
5. This is the V current consumed when the device is active but not switching. Does not include gate drive current.
DD
6. Guaranteed by design, not 100% tested in production.
7. Adjust V
above the start threshold and then lower to 15V.
DD
FN9124.6
June 28, 2005
6
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Typical Performance Curves
1.001
1
1.02
1.01
1
0.999
0.998
0.997
0.99
0.98
0.97
0.996
0.995
-40
-10
20
50
80
110
-40 -25 -10
5
20 35 50 65 80 95 110
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 1. FREQUENCY vs TEMPERATURE
3
1-10
1.002
CT=
100pF
100
10
1
1
0.998
0.996
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
0.994
-40 -25 -10
5
20 35 50 65 80 95 110
10
20 30 40
50 60
70 80 90 100
RT (kΩ)
TEMPERATURE (°C)
FIGURE 4. RTCT vs FREQUENCY
FIGURE 3. EA REFERENCE vs TEMPERATURE
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
Pin Descriptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
frequency range up to 2.0MHz. The charge time, T , the
C
discharge time, T , the switching frequency, f, and the
D
maximum duty cycle, Dmax, can be calculated from the
following equations:
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has
an internal offset of 100mV.
(EQ. 1)
T
≈ 0.583 • RT • CT
C
GND - GND is the power and small signal reference ground
for all functions.
0.0083 • RT – 4.3
(EQ. 2)
----------------------------------------------
T
≈ –RT • CT • ln
D
0.0083 • RT – 2.4
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A. This GATE
f = 1 ⁄ (T + T
)
(EQ. 3)
(EQ. 4)
C
D
output is actively held low when V
threshold.
is below the UVLO
D = T • f
DD
C
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
FN9124.6
June 28, 2005
7
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
V
- V
DD
is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
current is the sum of the operating current and the
the resonant tank of the parasitic inductances in the traces of
DD
the board and the FET’s input capacitance.
I
DD
Slope Compensation
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. The minimum amount of slope
(EQ. 5)
I
= Qg × f
OUT
To optimize noise immunity, bypass V
ceramic capacitor as close to the V
possible.
to GND with a
DD
and GND pins as
DD
compensation required corresponds to 1/2 the inductor
downslope. Adding excessive slope compensation,
however, results in a control loop that behaves more as a
voltage mode controller than as current mode controller.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Description
Features
DOWNSLOPE
CURRENT SENSE SIGNAL
The ISL684x current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
Oscillator
The ISL684x controllers have a sawtooth oscillator with a
programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Fig. 4 for the resistor
and capacitance required for a given frequency.)
Slope compensation may added to the CS signal in the
following manner.
RTCT
VREF
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
CS
VREF
COMP
GND
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
FIGURE 5. SOFT-START
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
Gate Drive
The ISL684x are capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
currents associated with the output stage. V
should be
DD
bypassed directly to GND with good high frequency
capacitors.
FN9124.6
June 28, 2005
8
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9124.6
9
June 28, 2005
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Mini Small Outline Plas tic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
L
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN9124.6
10
June 28, 2005
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Dual Flat No-Lead Plastic Package (DFN)
2X
L8.2x3
0.15
C A
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
NOTES
A
A1
A3
b
0.90
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
-
E
-
6
INDEX
0.32
1.75
1.90
5,8
AREA
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
SIDE VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
A3
C
SEATING
L
0.40
0.50
8
PLANE
N
8
2
D2
D2/2
2
7
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
0.10
M
C A B
improved electrical and thermal performance.
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9124.6
11
June 28, 2005
相关型号:
ISL6843IB
1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MS-012AA, SOIC-8
ROCHESTER
ISL6843IB-T
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MS-012AA, SOIC-8
ROCHESTER
ISL6843IBZ-T
Improved Industry-Standard Single-Ended PWM Controller; MSOP8, SOIC8; Temp Range: -40° to 85°C
RENESAS
©2020 ICPDF网 联系我们和版权申明