ISL6752 [INTERSIL]
ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control; 可调的同步整流控制ZVS全桥电流模式PWM型号: | ISL6752 |
厂家: | Intersil |
描述: | ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
文件: | 总16页 (文件大小:435K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6752
®
Data Sheet
March 10, 2005
FN9181.1
ZVS Full-Bridge Current-Mode PWM with
Adjustable Synchronous Rectifier Control
Features
• Adjustable Resonant Delay for ZVS Operation
The ISL6752 is a high-performance, low-pin-count
alternative zero-voltage switching (ZVS) full-bridge PWM
controller. Like Intersil’s ISL6551, it achieves ZVS operation
by driving the upper bridge FETs at a fixed 50% duty cycle
while the lower bridge FETs are trailing-edge modulated with
adjustable resonant switching delays. Compared to the more
familiar phase-shifted control method, this algorithm offers
equivalent efficiency and improved overcurrent and light-
load performance with less complexity in a lower pin count
package.
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Current-Mode Control
• 3% Current Limit Threshold
• Adjustable Deadtime Control
• 175µA Startup Current
• Supply UVLO
• Adjustable Oscillator Frequency Up to 2MHz
• Internal Over Temperature Protection
• Buffered Oscillator Sawtooth Output
• Fast Current Sense to Output Delay
• Adjustable Cycle-by-Cycle Peak Current Limit
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
The ISL6752 features complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision deadtime
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, Multi-Pulse
Suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
• Pb-Free (RoHS Compliant)
Ordering Information
• ELV, WEEE, and RoHS Compliant
TEMP. RANGE
(°C)
PKG.
PART NUMBER
PACKAGE
16 Ld QSOP
(Pb-free)
DWG. #
Applications
ISL6752AAZA
(Note)
-40 to 105
M16.15A
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
Add -T suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• Industrial Power Systems
Pinout
ISL6752 (QSOP)
TOP VIEW
VADJ
VREF
VERR
CTBUF
RTD
1
2
3
4
5
6
7
8
16 VDD
15 OUTLL
14 OUTLR
13 OUTUL
12 OUTUR
11 OUTLLN
10 OUTLRN
RESDEL
CT
9
GND
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD
VDD
OUTUL
OUTUR
50%
VREF
UVLO
PWM
DELAY/
ADVANCE
TIMING
STEERING
LOGIC
OVER-
OUTLL
OUTLR
CONTROL
TEMPERATURE
PROTECTION
PWM
OUTLLN
OUTLRN
GND
VREF
RESDEL
VADJ
OSCILLATOR
CT
+
-
CS
1.00V
RTD
70ns
LEADING
EDGE
OVERCURRENT
COMPARATOR
BLANKING
CTBUF
80mV
+
-
0.33
PWM
COMPARATOR
VREF
1mA
VERR
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
VIN+
CR2
CR3
T3
Q2
Q5A
Q5B
R10
R11
Q8A
Q8B
Q1
C9
C8
+
T1
C1
R12
C12
400 VDC
+ Vout
L1
Q12
C10
Q10A
Q10B
Q9A
Q9B
C7
C15
+
R1
Q13
R13
RETURN
C13
Q3
Q7A
Q6A
Q6B
Q7B
Q4
VIN-
R18
R17
R19
R16
T2
VADJ
VDD
CR1
VREF
OUTLL
R8
VERR
CTBUF
RTD
OUTLR
OUTUL
OUTUR
OUTLLN
OUTLRN
GND
R23
C14
EL7212
U5
EL7212
U4
C5
T4
R2
R20
CR4
RESDEL
CT
R3
CS
R7
C11
R4
U1
R15
R24
Q11
R23
R24
Q14
U3
VDD
U2
C4
R14
C3
C17
C2
C16
R22
VR1
R21
C6
R5
R6
Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter
VIN+
T3
1:1:1
Q1
Q2
Q6
Q5
CR2
T1
R13
CR3
R12
Np:Ns:Ns=9:2:2
Ns
R15
C12
Np
+ Vout
L1
Q16
C10
Ns
Q10A
Q10B
Q9A
Q9B
C14
C13
+
+
400 VDC
C1
R14
C11
Q15
T4
1:1:1
Q4
Q3
CR5
CR4
Q8A
Q8B
R10
Q7A
Q7B
RETURN
R11
C8
C9
C7
Q11A
Q11B
Q12A
Q12B
Q13A
Q13B
VIN-
VREF
R7
T2
VADJ
VDD
CR1
R17
VREF
OUTLL
R8
VERR
CTBUF
RTD
OUTLR
OUTUL
OUTUR
OUTLLN
OUTLRN
GND
Q14A
Q14B
C17
C16
R9
RESDEL
CT
Q17
CS
R1
R6
U1
R16
C15
R18
SECONDARY
BIAS SUPPLY
R20
VREF
U3
-
R22
+
R4
C2
R5
R21
R19
C6
C3
C4
C5
R2
R3
C18
ISL6752
Absolute Maximum Ratings
Thermal Information
Thermal Resistance Junction to Ambient (Typical)
16 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . .-55°C to 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(QSOP- Lead Tips Only)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
θ
(°C/W)
95
JA
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
+ 0.3V
REF
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Operating Conditions
Temperature Range
ISL6752AAxx . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . 9-16 VDC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VDD< 20V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Supply Voltage
-
-
20
400
15.5
9.00
7.50
-
V
µA
mA
V
Start-Up Current, I
DD
V
= 5.0V
-
-
175
11.0
8.75
7.00
1.75
DD
Operating Current, I
R
, C = 0
DD
LOAD OUT
UVLO START Threshold
UVLO STOP Threshold
Hysteresis
8.00
6.50
-
V
V
REFERENCE VOLTAGE
Overall Accuracy
I
= 0-10mA
4.850
-
5.000
5.150
V
VREF
Long Term Stability
Operational Current (source)
Operational Current (sink)
Current Limit
T
= 125°C, 1000 hours (Note 4)
3
-
-
mV
mA
mA
mA
A
-10
5
-
-
-
VREF = 4.85V
-15
-
-100
CURRENT SENSE
Current Limit Threshold
CS to OUT Delay
VERR = VREF
Excl. LEB (Note 4)
(Note 4)
0.97
1.00
35
70
-
1.03
50
V
ns
ns
ns
Ω
-
50
-
Leading Edge Blanking (LEB) Duration
CS to OUT Delay + LEB
100
130
20
T
= 25°C
A
CS Sink Current Device Impedance
Input Bias Current
V
V
= 1.1V
= 0.3V
-
-
CS
CS
-6.00
65
-
-2.00
95
µA
mV
CS to PWM Comparator Input Offset
PULSE WIDTH MODULATOR
VERR Pull-Up Current Source
VERR VOH
T
= 25°C
80
A
VERR = 2.50V
= 0mA
0.80
4.20
1.00
-
1.30
-
mA
V
I
LOAD
FN9181.1
5
March 10, 2005
ISL6752
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VDD< 20V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C (Continued)
A
PARAMETER
Minimum Duty Cycle
TEST CONDITIONS
VERR < 0.6V
MIN
TYP
-
MAX
0
UNITS
%
-
Maximum Duty Cycle (per half-cycle)
VERR = 4.20V, V = 0V (Note 5)
CS
-
-
94
97
99
-
-
%
RTD = 2.00kΩ, CT = 220pF
RTD = 2.00kΩ, CT = 470pF
-
%
-
-
%
Zero Duty Cycle VERR Voltage
VERR to PWM Comparator Input Offset
VERR to PWM Comparator Input Gain
Common Mode (CM) Input Range
OSCILLATOR
0.85
0.7
0.31
0
1.20
0.9
0.35
4.45
V
T
= 25°C
0.8
0.33
-
V
A
V/V
V
(Note 4)
(Note 4)
Frequency Accuracy, Overall
165
-10
-
183
201
10
kHz
%
Frequency Variation with VDD
Temperature Stability
T
= 25°C, (F
- - F
)/F
0.3
4.5
1.5
-200
20
1.7
%
A
20V 10V 10V
VDD = 10V, |F - F |/F
-
-
%
-40°C 0°C 0°C
|F
0°C
- F
|/F
(Note 4)
-
-
%
105°C 25°C
= 25°C
Charge Current
T
-193
19
-207
23
µA
µA/µA
V
A
Discharge Current Gain
CT Valley Voltage
CT Peak Voltage
CT Pk-Pk Voltage
RTD Voltage
Static Threshold
Static Threshold
Static Value
0.75
2.75
1.92
1.97
0
0.80
2.80
2.00
2.00
-
0.88
2.88
2.05
2.03
2.00
2.05
0.44
0.10
V
V
V
RESDEL Voltage Range
V
CTBUF Gain (V
/V
CTBUFp-p CTp-p
)
V
V
= 0.8V, 2.6V
= 0.8V
1.95
0.34
-
2.0
0.40
-
V/V
V
CT
CT
CTBUF Offset from GND
CTBUF VOH
∆V(I
CT
= 0mA, I
= -2mA),
V
LOAD
= 2.6V
LOAD
V
CTBUF VOL
∆V(I
CT
= 2mA, I
= 0mA),
-
-
0.10
V
LOAD
LOAD
V
= 0.8V
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Rise Time
I
I
= -10mA, VDD - VOH
= 10mA, VOL - GND
-
0.5
1.0
1.0
V
V
OUT
OUT
-
0.5
C
= 220pF, VDD = 15V (Note 4)
= 220pF, VDD = 15V (Note 4)
-
110
200
150
1.25
3
ns
ns
V
OUT
OUT
Fall Time
C
-
90
-
UVLO Output Voltage Clamp
VDD = 7V, I
LOAD
= 1mA (Note 6)
-
-
Output Delay/Advance Range
V
= 2.50V (Note 4)
< 2.425V
-
ns
ns
ns
V
ADJ
OUTLLN/OUTLRN relative to OUTLL/OUTLR
V
-40
40
-
-300
300
5.000
2.425
ADJ
V
> 2.575V
-
ADJ
Delay/Advance Control Voltage Range
OUTLxN Delayed
OUTLxN Advanced
2.575
0
-
OUTLLN/OUTLRN relative to OUTLL/OUTLR
-
V
FN9181.1
6
March 10, 2005
ISL6752
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VDD< 20V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C (Continued)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VADJ Delay Time
T
= 25°C (OUTLx Delayed)
VADJ = 0
A
280
92
300
105
70
320
118
80
ns
ns
ns
ns
ns
VADJ = 0.5V
VADJ = 1.0V
VADJ = 1.5V
VADJ = 2.0V
61
48
55
65
41
50
58
T
= 25°C (OUTLxN Delayed)
VADJ = VREF
A
280
86
300
100
68
320
114
77
ns
ns
ns
ns
ns
VADJ = VREF - 0.5V
VADJ = VREF - 1.0V
VADJ = VREF - 1.5V
VADJ = VREF - 2.0V
59
47
55
62
41
48
55
THERMAL PROTECTION
Thermal Shutdown
(Note 4)
(Note 4)
(Note 4)
130
115
-
140
125
15
150
135
-
°C
°C
°C
Thermal Shutdown Clear
Hysteresis, Internal Protection
NOTES:
3. Specifications at -40°Cand 105°C are guaranteed by 25°C test with margin limits.
4. Guaranteed by design, not 100% tested in production.
5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 - 3.
6. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
Typical Performance Curves
25
24
23
22
21
20
19
18
1.02
1.01
1
0.99
0.98
-40 -25 -10
5
20
35
50 65
80 95 110
0
200
400
600
800
1000
TEMPERATURE (°C)
RTD CURRENT (µA)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
FN9181.1
7
March 10, 2005
ISL6752
Typical Performance Curves (Continued)
3
1-10
4
CT =
1-10
1000pF
680pF
470pF
330pF
220pF
3
1-10
100pF
100
10
100
10
RTD =
10kΩ
50kΩ
100kΩ
0
10 20 30 40 50 60 70 80 90 100
RTD (kΩ)
0.1
1
10
CT (nF)
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
OUTUL and OUTUR - These outputs control the upper
Pin Descriptions
bridge FETs and operate at a fixed 50% duty cycle in
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200 µA
current source and discharged with a user adjustable current
source controlled by RTD.
OUTLL and OUTLR - These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
OUTLLN and OUTLRN - These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1.00 V nominal.
The CS pin is shorted to GND at the termination of either
PWM output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
VADJ - A 0 - 5V control voltage applied to this input sets the
relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
FN9181.1
8
March 10, 2005
ISL6752
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above
2.575V result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50 V ±75mV results in zero
phase difference. A weak internal 50% divider from VREF
results in no phase delay if this input is left floating.
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
3
T
T
≈ 11.5 ⋅ 10 ⋅ CT
S
(EQ. 1)
(EQ. 2)
C
D
–9
≈ (0.06 ⋅ RTD ⋅ CT) + 50 ⋅ 10
S
The range of phase delay/advance is either zero or 40 to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(∆t/∆V) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
1
SW
T
= T + T = ------------
S
(EQ. 3)
SW
C
D
F
where T and T are the charge and discharge times,
C
D
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, T is the
SW
is the oscillator frequency. One
oscillator period, and F
SW
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a
nominal 1mA pull-up current source.
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
The ISL6752 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features,
a highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
T
C
(EQ. 4)
D = ------------
T
SW
DT = 1 – D
(EQ. 5)
Implementing Soft-Start
The ISL6752 does not have a soft-start feature. Soft-start
can be implemented externally using the components shown
below. The RC network governs the rate of rise of the
transistor’s base which clamps the voltage at VERR.
If synchronous rectification is not required, please consider
the ISL6753 controller.
Oscillator
The ISL6752 has an oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor and capacitor.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
FN9181.1
9
March 10, 2005
ISL6752
accomplished by summing an external ramp with the current
1
2
3
4
5
6
7
8
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
VREF
VERR
R
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
ISL6752
1
C
Fm = -------------------
(EQ. 7)
SnTsw
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
FIGURE 5. IMPLEMENTING SOFT-START
1
1
(EQ. 8)
Fm = -------------------------------------- = ---------------------------
(Sn + Se)Tsw m SnTsw
c
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The soft-
start duration may be calculated from Equation. 6.
where Se is slope of the external ramp and
Se
m
= 1 + -------
(EQ. 9)
c
Sn
V
– V
be
SS
(EQ. 6)
t = –RC ⋅ ln 1 – -------------------------------------------
S
0.001R
VREF + -------------------
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
β
where V is the soft-start clamp voltage, V is the base-
SS be
emitter voltage drop of the transistor, and β is the DC gain of
the transistor. If β is sufficiently large, that term may be
ignored. The schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
1
(EQ. 10)
Q = -------------------------------------------------
π(m (1 – D) – 0.5)
Gate Drive
c
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50Ω.
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields
1
1
(EQ. 11)
-------------
S
= S
-- + 0.5
– 1
e
n
1 – D
π
Overcurrent Operation
Since S and S are the on time slopes of the current ramp
n
e
The cycle-by-cycle peak current control results in pulse-by-
pulse duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the
threshold, the active output pulse is immediately terminated.
This results in a well controlled decrease in output voltage as
the load current increases beyond the current limit threshold.
The ISL6752 will operate continuously in an overcurrent
condition.
and the external ramp, respectively, they can be multiplied
by T to obtain the voltage change that occurs during T
.
ON ON
1
1
-------------
V
= V
-- + 0.5
– 1
(EQ. 12)
e
n
1 – D
π
where V is the change in the current feedback signal during
n
the on time and V is the voltage that must be added by the
e
external ramp.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
V can be solved for in terms of input voltage, current
n
transducer components, and output inductance yielding
T
⋅ V ⋅ R
N
N
P
SW
N
CS
O
S
1
----------------------------------------- -------
V
=
⋅
-- + D – 0.5
V
(EQ. 13)
e
⋅ L
π
CT
O
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
where R
is the current sense burden resistor, N is the
CT
CS
current transformer turns ratio, L is the output inductance,
O
V
is the output voltage, and N and N are the secondary
S P
O
and primary turns, respectively.
FN9181.1
10
March 10, 2005
ISL6752
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields
peak amplitude of CT (0.4 - 4.4 V). A typical application
sums this signal with the current sense feedback and applies
the result to the CS pin as shown in Figure 6.
N
N
⋅ R
⋅ N
D ⋅ T
N
N
S
CS
SW
S
------------------------
--------------------
-------
(EQ. 14)
V
=
I
+
V
⋅
– V
O
V
CS
O
IN
2L
1
P
CT
O
P
2
3
4
5
6
7
8
ISL6752
where V
is the voltage across the current sense resistor
CS
and I is the output current at current limit.
O
CTBUF
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
R9
V
+ V
= 1
CS
(EQ. 15)
CS
e
R6
RCS
C4
Substituting Equations 13 and 14 into Equation 15 and
solving for R yields
CS
⋅ N
N
1
P
CT
----------------------- ------------------------------------------------------
R
=
⋅
Ω
(EQ. 16)
CS
N
V
S
O
1
D
-------
I
+
T
-- + ---
SW
π
O
L
2
O
FIGURE 6. ADDING SLOPE COMPENSATION
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
(D(V
– 0.4) + 0.4) ⋅ R6
R6 + R9
CTBUF
(EQ. 20)
V
– ∆V
= ------------------------------------------------------------------------------
CS
V
e
Rearranging to solve for R9 yields
V
⋅ DT
(D(V
– 0.4) – V + ∆V
+ 0.4) ⋅ R6
CS
IN
SW
(EQ. 17)
CTBUF
e
∆I = -------------------------------
A
R9 = ------------------------------------------------------------------------------------------------------------------
– ∆V
Ω
P
L
V
m
e
CS
(EQ. 21)
where V is the input voltage that corresponds to the duty
IN
The value of R
CS
determined in Equation 16 must be
cycle D and L is the primary magnetizing inductance. The
m
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 14. The divider created
by R6 and R9 makes this necessary.
effect of the magnetizing current at the current sense
resistor, R , is
CS
∆I ⋅ R
P
CS
(EQ. 18)
R6 + R9
∆V
= -------------------------
V
CS
----------------------
(EQ. 22)
R′
=
⋅ R
N
CS
CS
CT
R9
Example:
If ∆V
CS
is greater than or equal to V , then no additional
e
slope compensation is needed and R
becomes
CS
V
V
L
= 280V
= 12V
IN
N
CT
R
= -------------------------------------------------------------------------------------------------------------------------------------
CS
O
N
DT
2L
N
N
V
⋅ DT
S
SW
S
IN
SW
-------
----------------
-------
⋅ I
+
⋅ V
⋅
– V
+ -------------------------------
O
IN
O
= 2.0µH
N
O
L
P
O
P
m
(EQ. 19)
Np/Ns = 20
Lm = 2mH
If ∆V is less than Ve, then Equation 16 is still valid for the
CS
value of R , but the amount of slope compensation added
CS
I
= 55A
O
by the external ramp must be reduced by ∆V
.
CS
Oscillator Frequency, Fsw = 400kHz
Duty Cycle, D = 85.7%
Adding slope compensation may be accomplished in the
ISL6752 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-
N
= 50
CT
R6 = 499Ω
FN9181.1
11
March 10, 2005
ISL6752
Solve for the current sense resistor, R , using Equation 16.
CS
and Equation 21 becomes:
(2D – V + ∆V ) ⋅ R6
R
= 15.1Ω.
CS
e
CS
(EQ. 24)
R9 = ------------------------------------------------------------
Ω
V
– ∆V
e
CS
Determine the amount of voltage, V , that must be added to
e
the current feedback signal using Equation 13.
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 18.
∆V
CS
= 91mV
ZVS Full-Bridge Operation
Using Equation 21, solve for the summing resistor, R9, from
CTBUF to CS.
The ISL6752 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
R9 = 30.1kΩ
Determine the new value of R , R’ , using Equation 22.
CS CS
R’
CS
= 15.4Ω
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
CT
If the application requires deadtime less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400ns. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
DEADTIME
PWM
PWM
OUTLL
OUTLR
OUTUR
PWM
PWM
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
1
2
3
4
5
6
7
8
VREF
FIGURE 8. BRIDGE DRIVE SIGNAL TIMING
ISL6752
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
R9
CT
CS
VIN+
UL
UR
R6
D1
VOUT+
RTN
LL
RCS
C4
CT
LL
LR
D2
VIN-
FIGURE 7. ADDING SLOPE COMPENSATION USING CT
FIGURE 9. IDEALIZED FULL-BRIDGE
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 20
and 21 require modification. Equation 20 becomes:
In Figure 9, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
2D ⋅ R6
V
– ∆V
= ----------------------
CS
V
(EQ. 23)
e
R6 + R9
FN9181.1
March 10, 2005
12
ISL6752
parasitic capacitance in the circuit including winding
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 25.
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 10, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
π
2
1
-------------------------------------
τ =
(EQ. 25)
2
1
R
-------------- – ---------
2
L
L C
L
P
4L
are indicated by I and I , respectively.
P
S
where τ is the resonant transition time, L is the leakage
L
VIN+
inductance, C is the parasitic capacitance, and R is the
P
UL
UR
IS
D1
equivalent resistance in series with L and C .
L
P
VOUT+
RTN
LL
The resonant delay is always less than or equal to the
deadtime and may be calculated using the following
equation.
IP
LL
LR
V
resdel
D2
-------------------
τ
=
⋅ DT
S
(EQ. 26)
resdel
2
VIN-
FIGURE 10. UL - LR POWER TRANSFER CYCLE
where τ
resdel
is the desired resonant delay, V
voltage between 0 and 2V applied to the RESDEL pin, and
DT is the deadtime (see Equations 1 - 5).
is a
resdel
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR which charges
the node to VIN and then forward biases the body diode of
upper switch UR.
When the upper switches toggle, the primary current that
was flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
RESDEL is set properly, switch LL will be turned on at this
time.
VIN+
VIN+
UL
UR
IS
UL
UR
IS
D1
D1
VOUT+
RTN
LL
VOUT+
RTN
LL
IP
IP
LL
LR
LL
LR
D2
D2
VIN-
VIN-
FIGURE 11. UL - UR FREE-WHEELING PERIOD
FIGURE 12. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The primary leakage inductance, L , maintains the current
L
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated below.
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. This condition persists through the
remainder of the half-cycle.
VIN+
UL
LL
UR
LR
D1
VOUT+
RTN
LL
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
D2
VIN-
FIGURE 13. UR - LL POWER TRANSFER CYCLE
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
FN9181.1
13
March 10, 2005
ISL6752
in the primary must find an alternate path. The current flows
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
into the parasitic switch capacitance which charges the node
to VIN and then forward biases the body diode of upper
switch UL. The primary leakage inductance, L , maintains
L
the current, which now circulates around the path of switch
UR, the transformer primary, and switch UL. When switch LL
opens, the output inductor current free-wheels through both
output diodes, D1 and D2. This condition persists through
the remainder of the half-cycle.
CT
OUTLL
OUTLR
VIN+
UL
UR
IS
D1
VOUT+
RTN
OUTLLN
(SR1)
LL
IP
OUTLRN
(SR2)
LL
LR
D2
VIN-
FIGURE 16. BASIC WAVEFORM TIMING
FIGURE 14. UR - UL FREE-WHEELING PERIOD
Referring to Figure 16, the SRs alternate between being
both on during the free-wheeling portion of the cycle
(OUTLL/LR off), and one or the other being off when OUTLL
or OUTLR is on. If OUTLL is on, its corresponding SR must
also be on, indicating that OUTLRN is the correct SR control
signal. Likewise, if OUTLR is on, its corresponding SR must
also be on, indicating that OUTLLN is the correct SR control
signal.
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
A useful feature of the ISL6752 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and the their complements (OUTLLN, OUTLRN) by
±300ns. This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to VADJ controls the
phase relationship.
UL
UR
IS
D1
VOUT+
RTN
LL
IP
LL
LR
D2
VIN-
FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
CT
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
OUTLL
fully charge the parasitic capacitances. Since the energy
2
stored is proportional to the square of the current (1/2 L I
,
L P
OUTLR
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
OUTLLN
(SR1)
OUTLRN
(SR2)
Synchronous Rectifier Outputs and Control
The ISL6752 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
FIGURE 17. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < VADJ < 2.425V
FN9181.1
14
March 10, 2005
ISL6752
If the application requires that all outputs be off, then the
supply voltage, VDD, must be removed from the IC. This
may be accomplished as shown below.
CT
+Vdd
OUTLL
ISL6752
VADJ
VREF
VDD
OUTLR
OUTLL
VERR
CTBUF
RTD
OUTLR
OUTUL
OUTUR
OUTLLN
OUTLRN
GND
OUTLLN
(SR1)
ON/OFF
(OPEN = OFF
GND = ON)
RESDEL
CT
OUTLRN
(SR2)
CS
FIGURE 18. WAVEFORM TIMING WITH SR OUTPUTS
DELAYED, 2.575V < VADJ < 5.00V
FIGURE 19. ON/OFF CONTROL USING VDD
Setting VADJ to VREF/2 results in no delay on any output.
The no delay voltage has a ±75mV tolerance window.
Control voltages below the VREF/2 zero delay threshold
cause the PWM outputs, OUTLL/LR, to be delayed. Control
voltages greater than the VREF/2 zero delay threshold
cause the SR outputs, OUTLLN/LRN, to be delayed. It
should be noted that when the PWM outputs, OUTLL/LR,
are delayed, the CS to output propagation delay is increased
by the amount of the added delay.
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs
are disabled low. When the fault condition clears the outputs
are re-enabled.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
Thermal Protection
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as
may be experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required
using external resistors, capacitors, and diodes.
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed 140°C. There is
approximately 15°C of hysteresis.
Ground Plane Requirements
When the PWM outputs are delayed, the 50% upper outputs
are equally delayed, so the resonant delay setting is
unaffected.
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
On/Off Control
The ISL6753 does not have a separate enable/disable
control pin. The PWM outputs, OUTLL/OUTLR, may be
disabled by pulling VERR to ground. Doing so reduces the
duty cycle to zero, but the upper 50% duty cycle outputs,
OUTUL/OUTUR, will continue operation. Likewise, the SR
outputs OUTLLN/OUTLRN will be active high.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
FN9181.1
15
March 10, 2005
ISL6752
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
M
M
B
0.25(0.010)
H
AREA
3
E
INCHES
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MIN
MAX
MIN
1.55
0.102
1.40
0.20
0.191
4.80
3.81
MAX
1.73
0.249
1.55
0.31
0.249
4.98
3.99
NOTES
A
A1
A2
B
0.061
0.004
0.055
0.008
0.0075
0.189
0.150
0.068
0.0098
0.061
0.012
0.0098
0.196
0.157
-
1
2
-
L
-
0.25
0.010
SEATING PLANE
A
9
-A-
D
h x 45°
C
D
E
-
3
-C-
4
α
A2
e
A1
e
0.025 BSC
0.635 BSC
-
C
B
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
0.10(0.004)
M
M
S
B
0.17(0.007)
C
A
5
L
6
NOTES:
N
α
16
16
7
1. Symbols are defined in the “MO Series Symbol List” in Section
0°
8°
0°
8°
-
2.2 of Publication Number 95.
Rev. 2 6/04
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9181.1
16
March 10, 2005
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