ISL6741IVZ中文资料_数据手册_规格书

ISL6740, ISL6741

®

Data Sheet

July 2004

FN9111.3

Flexible Double Ended Voltage and

Current Mode PWM Controllers

Features

• Precision Duty Cycle and Deadtime Control

The ISL6740, ISL6741 family of adjustable frequency, low

power, pulse width modulating (PWM) voltage mode

(ISL6740) and current mode (ISL6741) controllers is

designed for a wide range of power conversion applications

using half-bridge, full bridge, and push-pull configurations.

These controllers provide an extremely flexible oscillator that

allows precise control of frequency, duty cycle, and

deadtime.

• 95µA Startup Current

• Adjustable Delayed Over Current Shutdown and Re-Start

(ISL6740)

• Adjustable Short Circuit Shutdown and Re-Start

• Adjustable Oscillator Frequency Up to 2MHz

• Bidirectional Synchronization

• Inhibit Signal

This advanced BiCMOS design features low operating

current, adjustable switching frequency up to 1MHz,

adjustable soft start, internal and external over temperature

protection, fault annunciation, and a bidirectional SYNC

signal that allows the oscillator to be locked to paralleled

units or to an external clock for noise sensitive applications.

• Internal Over Temperature Protection

• System Over Temperature Protection Using a Thermistor

or Sensor

• Adjustable Soft Start

• Adjustable input Under Voltage Lockout

• Fault Signal

Ordering Information

TEMP. RANGE

PKG.

DWG. #

o

PART NUMBER

( C)

PACKAGE

• Tight Tolerance Voltage Reference Over Line, Load, and

Temperature

ISL6740IB

-40 to 105

16 Ld SOIC

M16.15

• Pb-free available

ISL6740IBZ

(See Note)

16 Ld SOIC

(Pb-free)

Applications

ISL6740IV

-40 to 105

16 Ld TSSOP M16.173

• Telecom and Datacom Power

• Wireless Base Station Power

• File Server Power

ISL6740IVZ

(See Note)

16 Ld TSSOP M16.173

(Pb-free)

ISL6741IB

-40 to 105

16 Ld SOIC

M16.15

ISL6741IBZ

(See Note)

16 Ld SOIC

(Pb-free)

• Industrial Power Systems

• DC Transformers and Buss Regulators

ISL6741IV

-40 to 105

16 Ld TSSOP M16.173

ISL6741IVZ

(See Note)

16 Ld TSSOP M16.173

(Pb-free)

Pinout

ISL6740, ISL6741 (SOIC, TSSOP)

Add -T suffix to part number for tape and reel packaging

TOP VIEW

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

OUTA

GND

1

2

3

4

5

6

7

8

16 OUTB

15

14

V

REF

DD

SCSET

C

13 R

TD

T

SYNC

CS

12 R

TC

x =

0

CONTROL MODE

Voltage Mode

11 OTS

10 FAULT

V

ERROR

1

Current Mode

9

SS

UV

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6740, ISL6741

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V

OUTA, OUTB, Signal Pins . . . . . . . . . . . . . . . . .GND - 0.3V to V

Thermal Resistance Junction to Ambient (Typical)

θ

( C/W)

DD

JA

REF

16 Lead SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . .

16 Lead TSSOP (Note 1). . . . . . . . . . . . . . . . . . . . .

77

102

VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

ESD Classification

Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1500V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V

o

Maximum Junction Temperature . . . . . . . . . . . . . . . -55 C to 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

(SOIC, TSSOP- Lead Tips Only)

Operating Conditions

Temperature Range

o

ISL6740Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 105 C

ISL6741Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 105 C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . 9VDC-16 VDC

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. All voltages are with respect to GND.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

o

Schematic. 9V < V

< 20 V, R = 51.1kΩ, R = 10kΩ, C = 470pF, T = -40 C to 105 C (Note 4), Typical

DD

TD

TC

T

A

o

values are at T = 25 C

A

PARAMETER

SUPPLY VOLTAGE

Start-Up Current, I

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

< START Threshold

DD

-

95

140

8.0

µA

mA

V

DD

Operating Current, I

R

C

, C

LOAD OUTA,B

= 0

-

5.0

DD

= 1nF

-

7.0

12.0

8.00

7.50

0.75

OUTA,B

UVLO START Threshold

UVLO STOP Threshold

Hysteresis

6.50

6.00

0.25

7.25

6.75

0.50

V

REFERENCE VOLTAGE

Overall Accuracy

I

= 0, -20mA

o

4.900

-

5.000

3

5.050

-

V

mV

V

VREF

Long Term Stability

Fault Voltage

T = 125 C, 1000 hours (Note 4)

A

4.10

4.25

4.55

4.75

VREF Good Voltage

V

REF

-.05

250

-

Hysteresis

75

-20

5

165

mV

mA

Operational Current (source)

Operational Current (sink)

Current Limit

-

-25

-100

CURRENT SENSE

Current Limit Threshold

CS to OUT Delay

V

= V

0.55

0.6

35

10

-

0.65

V

ERROR

REF

-

50

ns

CS Sink Current

-

mA

µA

mV

V/V

Input Bias Current

-1.00

1.00

CS to PWM Comparator Input Offset (ISL6741)

Gain (ISL6741)

(Note 4)

= ∆V

-

80

4

-

A

/∆V

(Note 4)

CS

ERROR

7

ISL6740, ISL6741

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

o

Schematic. 9V < V

< 20 V, R = 51.1kΩ, R = 10kΩ, C = 470pF, T = -40 C to 105 C (Note 4), Typical

DD

TD

TC

T

A

o

values are at T = 25 C (Continued)

A

PARAMETER

SCSET Input Impedance

TEST CONDITIONS

MIN

TYP

-

MAX

UNITS

MΩ

1

-

SC Setpoint Accuracy

10

%

PULSE WIDTH MODULATOR

V

Input Impedance

400

-

kΩ

%

V

ERROR

Minimum Duty Cycle

V

< CS Offset (ISL6741)

-

0

ERROR

< C Valley Voltage (ISL6740)

T

-

0

Maximum Duty Cycle

> 4.75V (Note 6)

-

83

1.0

0.25

0.4

0.5

0.2

-

V

to PWM Comparator Input Offset (ISL6741) (Note 4)

0.4

1.25

ERROR

to PWM Comparator Input Gain (ISL6741)

to PWM Comparator Input Gain (ISL6740)

(Note 4)

-

V/V

C

T

SS to PWM Comparator Input Gain (ISL6740)

SS to PWM Comparator Input Gain (ISL6741)

OSCILLATOR

o

Frequency Accuracy

T = 25 C

A

333

351

2

369

3

kHz

%

o

Frequency Variation with V

T = 105 C (F

- - F )/F

20V 9V 9V

-

DD

o

T = -40 C (F

- - F )/F

20V 9V 9V

2

3

%

Temperature Stability

Charge Current Gain

Discharge Current Gain

(Note 4)

-

8

-

%

1.88

45

0.75

2.70

-

2.0

55

2.12

65

0.85

2.90

-

µA/µA

V

C

Valley Voltage

Peak Voltage

0.80

2.80

2.000

T

V

T

RTD, RTC Voltage

R

= 0

V

LOAD

SYNCHRONIZATION

Input High Threshold (VIH), Minimum

Input Low Threshold (VIL), Maximum

Input Impedance

4.0

-

0.8

-

V

4.5

-

kΩ

Hz

Input Frequency Range

(Note 4)

0.6x

Free

Running

High Level Output Voltage (VOH)

Low Level Output Voltage (VOL)

SYNC Output Current

I

= -1mA

-

4.5

-

V

LOAD

= 10µA

-

100

-

mV

mA

ns

VOH > 2.0V (Note 4)

-10

250

SYNC Output Pulse Duration (minimum)

SYNC Advance

(Notes 4, 5)

400

SYNC rising edge to GATE falling edge,

C

= C

= 100pF

-

5

-

ns

GATE

SYNC

(Note 4)

SOFTSTART

Charging Current

SS Clamp Voltage

SS = 2V

-45

-55

4.5

-75

µA

4.35

4.65

V

8

ISL6740, ISL6741

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

o

Schematic. 9V < V

< 20 V, R = 51.1kΩ, R = 10kΩ, C = 470pF, T = -40 C to 105 C (Note 4), Typical

DD

TD

TC

T

A

o

values are at T = 25 C (Continued)

A

PARAMETER

TEST CONDITIONS

MIN

0.20

13

TYP

0.25

18

MAX

0.30

23

UNITS

V

Sustained Over Current Threshold Voltage (ISL6740) Charged Threshold minus:

Over Current/Short Circuit Discharge Current

Fault SS Discharge Current

Reset Threshold Voltage

FAULT

SS = 2V

µA

-

10.0

0.27

-

mA

V

0.25

0.33

Fault High Level Output Voltage (VOH)

Fault Low Level Output Voltage (VOL)

Fault Rise Time

I

= -10mA

= 10mA

2.85

3.5

0.4

15

-

0.9

-

V

LOAD

-

LOAD

C

= 100pF (Note 4)

ns

LOAD

Fault Fall Time

15

-

OUTPUT

High Level Output Voltage (VOH)

V

I

- OUTA or OUTB,

= -50mA

-

0.5

1.0

V

REF

OUT

Low Level Output Voltage (VOL)

Rise Time

OUTA or OUTB - GND, I

= 50mA

-

0.5

50

40

1.0

100

80

V

OUT

C

= 1nF, V

= 15V (Note 4)

ns

GATE

DD

Fall Time

THERMAL PROTECTION

Thermal Shutdown

o

(Note 4)

135

120

-

145

130

15

155

140

-

C

o

Thermal Shutdown Clear

Hysteresis, Internal Protection

Reference, External Protection

Hysteresis, External Protection

SUPPLY UVLO/INHIBIT

Input Voltage Low/Inhibit Threshold

Hysteresis, Switched Current Amplitude

Input High Clamp Voltage

Input Impedance

C

o

C

2.375

18

2.50

25

2.625

30

V

µA

0.97

7

1.00

1.03

V

µA

V

10

-

15

-

4.8

1

-

MΩ

NOTES:

o

3. Specifications at -40 C and 105 C are guaranteed by design, not production tested.

4. Guaranteed by design, not 100% tested in production.

5. SYNC pulse width is the greater of this value or the CT discharge time.

6. This is the maximum duty cycle achievable using the specified values of R , R , and C . Larger or smaller maximum duty cycles may be

TC TD

T

obtained using other values for these components. See Equations 2-4.

9

ISL6740, ISL6741

Typical Performance Curves

1.001

65

60

55

50

45

40

1

0.999

0.998

0.997

-40 -25 -10

5

20 35 50 65 80 95 110

0

50 100 150 200 250 300 350 400 450 500

RTD CURRENT (µA)

TEMPERATURE (°C)

FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 2. OSCILLATOR CT DISCHARGE CURRENT GAIN

4

6

1•10

CT (pF) =

1000

680

470

330

220

100

3

1•10

5

1•10

RTD = 10K

CT (pF) =

100

10

220

680

330

470

1000

60

4

1•10

10

20

30

40

50

60

70

80

90 100

10

20

30

40

50

70

80

90 100

RTD (kΩ)

RTC (kΩ)

FIGURE 3. DEADTIME (TD) vs CAPACITANCE

FIGURE 4. CAPACITANCE vs FREQUENCY

Pin Descriptions

V

- V

is the power connection for the IC. To optimize

to GND with a ceramic

and GND pins as possible.

R

- This is the oscillator timing capacitor charge current

DD

TC

noise immunity, bypass V

capacitor as close to the V

control pin. A resistor is connected between this pin and

GND. The current flowing through the resistor determines

the magnitude of the charge current. The charge current is

nominally twice this current. The PWM maximum ON time is

determined by the timing capacitor charge duration.

DD

The total supply current, I , will be dependent on the load

DD

applied to outputs OUTA and OUTB. Total I

current is the

DD

sum of the quiescent current and the average output current.

Knowing the operating frequency, Fsw, and the output

loading capacitance charge, Q, per output, the average

output current can be calculated from:

R

- This is the oscillator timing capacitor discharge current

TD

control pin. A resistor is connected between this pin and

GND. The current flowing through the resistor determines

the magnitude of the discharge current. The discharge

current is nominally 50x this current. The PWM deadtime is

determined by the timing capacitor discharge duration.

I

= 2 • Q • F

A

(EQ. 1)

OUT

SW

SYNC - A bidirectional synchronization signal used to

C - The oscillator timing capacitor is connected between

T

coordinate the switching frequency of multiple units.

this pin and GND.

Synchronization may be achieved by connecting the SYNC

signal of each unit together or by using an external master

V

- The inverting input of the PWM comparator. The

ERROR

error voltage is applied to this pin to control the duty cycle.

Increasing the signal level increases the duty cycle. The

node may be driven with an external error amplifier or opto-

coupler.

clock signal. The oscillator timing capacitor, C , is always

T

required regardless of the synchronization method used.

The paralleled unit with the highest oscillator frequency

assumes control.

10

ISL6740, ISL6741

The ISL6740, ISL6741 features a built-in soft start. Soft start

is implemented as a clamp on the error voltage input.

When the soft start voltage reaches 0.27V (Reset Threshold)

a soft start cycle begins.

OTS - The non-inverting input to the over temperature

shutdown comparator. The signal input at this pin is

An over current condition must be absent for 50µs before the

delayed shutdown control resets. If the over current condition

ceases, and an additional 50µs period elapses before the

shutdown threshold is reached, no shutdown occurs. The SS

charging current is re-enabled and the soft start voltage is

allowed to recover.

compared to an internal threshold of V

/2. If the voltage at

REF

this pin exceeds the threshold, the Fault signal is asserted

and the outputs are disabled until the condition clears. There

is a nominal 25µA switched current source used for

hysteresis. The amount of hysteresis is adjustable by varying

the source impedance of the signal into this pin.

ISL6741 - The ISL6741 current mode controller does not

shutdown due to an overcurrent condition. The pulse-by-

pulse current limit characteristic of peak current mode

control limits the output current to acceptable levels.

OTS may be used to monitor parameters other than

temperature, such as voltage. Any signal for which a high

out-of-bounds monitor is desired may utilize the OTS

comparator.

GND - Reference and power ground for all functions on this

device. Due to high peak currents and high frequency

operation, a low impedance layout is necessary. Ground

planes and short traces are highly recommended.

FAULT - The Fault signal is asserted high whenever the

outputs, OUTA and OUTB, are disabled. This occurs during

an over temperature fault, an input UV fault, a V

UV fault,

REF

OUTA and OUTB - Alternate half cycle output stages. Each

output is capable of 0.5A peak currents for driving logic level

power MOSFETs or MOSFET drivers. Each output provides

very low impedance to overshoot and undershoot.

or during an over current (ISL6740) or short circuit shutdown

fault. Fault can be used to disable synchronous rectifiers

whenever the outputs are disabled.

Fault is a three-state output and is high impedance during

the soft start cycle. Adding a pull-up resistor to VREF or a

pull-down resistor to ground determines the state of Fault

during soft start. This feature allows the designer to use the

Fault signal to enable or disable output synchronous

rectifiers during soft start.

VREF - The 5.00V reference voltage output. +1/-2%

tolerance over line, load and operating temperature. Bypass

to GND with a 0.047µF to 2.2µF ceramic capacitor.

Capacitors outside of this range may cause oscillation.

SS - Connect the soft start timing capacitor between this pin

and GND to control the duration of soft start. The value of

the capacitor determines the rate of increase of the duty

cycle during start up, controls the over current shutdown

delay (ISL6740), and the over current and short circuit

hiccup restart period.

UV - Undervoltage monitor input pin. A resistor divider

between the input source voltage and GND sets the under

voltage lock out threshold. The signal is compared to an

internal 1.00V reference to detect an under voltage or inhibit

condition.

SCSET - Sets the duty cycle threshold that corresponds to a

CS - This is the input to the current sense comparator(s).

The IC has the PWM comparator for peak current mode

control (ISL6741) and an over current protection comparator.

The over current comparator threshold is set at 0.600V

nominal.

short circuit condition. A resistive divider between R and

TC

GND or R and GND, or a voltage between 0 and 2V may

TD

be used to adjust the SCSET threshold. If using a resistor

divider from either RTC or RTD, the impedance to GND

affects the oscillator timing and should be considered when

determining the oscillator timing components. Connecting

SCSET to GND disables short circuit shutdown and hiccup.

The CS pin is shorted to GND at the end of each switching

cycle. Depending on the current sensing source impedance,

a series input resistor may be required due to the delay

between the internal clock and the external power switch.

This delay may allow an overlap such that the CS signal may

be discharged while the current signal is still active. If the

current sense source is low impedance it will cause

increased power dissipation.

Functional Description

Features

The ISL6740, ISL6741 PWMs are an excellent choice for low

cost bridge and push-pull topologies for applications

requiring accurate duty cycle and deadtime control. With its

many protection and control features, a highly flexible design

with minimal external components is possible. Among its

many features are current mode control (ISL6741),

adjustable soft start, over current protection, thermal

protection, bidirectional synchronization, fault indication, and

adjustable frequency.

ISL6740 - Exceeding the over-current threshold will start a

delayed shutdown sequence. Once an over current condition

is detected, the soft start charge current source is disabled.

The soft start capacitor begins discharging through a 25µA

current source, and if it discharges to less than 4.25V

(Sustained Over Current Threshold), a shutdown condition

occurs and the OUTA and OUTB outputs are forced low.

11

ISL6740, ISL6741

being prematurely terminated by the external SYNC pulse.

Oscillator

Consequently, the timing capacitor is not fully charged when

the discharge cycle begins. This effect is only a concern

when an external master clock is used, or if units with

different operating frequencies are paralleled.

The ISL6740, ISL6741 have an oscillator with a

programmable frequency range to 2MHz, which can be

programmed with two resistors and capacitor. The use of

three timing elements, R , R , and C allow great

TC TD

T

flexibility and precision when setting the oscillator frequency.

Soft Start Operation

The switching period may be considered the sum of the

timing capacitor charge and discharge durations. The charge

The ISL6740, ISL6741 feature a soft start using an external

capacitor in conjunction with an internal current source. Soft

start reduces stresses and surge currents during start up.

duration is determined by R and C . The discharge

TC

T

duration is determined by R and C .

TD

T

Upon start up, the soft start circuitry clamps the error voltage

input (V

pin) indirectly to a value equal to the soft

(EQ. 2)

ERROR

T

≈ 0.5 • R

• C

T

S

C

TC

start voltage. The soft start clamp does not actually clamp

the error voltage input as is done in many implementations.

Rather the PWM comparator has two inverting inputs such

that the lower voltage is in control.

(EQ. 3)

(EQ. 4)

T

≈ 0.02 • R

• C

T

S

D

TD

1

= T + T = ------------

S

SW

C

D

The output pulse width increases as the soft start capacitor

voltage increases. This has the effect of increasing the duty

cycle from zero to the regulation pulse width during the soft

start period. When the soft start voltage exceeds the error

voltage, soft start is completed. Soft start occurs during

start-up, after recovery from a Fault condition or over

current/short circuit shutdown. The soft start voltage is

clamped to 4.5V.

F

SW

where T and T are the charge and discharge times,

C

D

respectively, T

is the oscillator free running period, and f

SW

is the oscillator frequency. One output switching cycle

requires two oscillator cycles. The actual times will be

slightly longer than calculated due to internal propagation

delays of approximately 10ns/transition. This delay ads

directly to the switching duration, but also causes overshoot

of the timing capacitor peak and valley voltage thresholds,

effectively increasing the peak-to-peak voltage on the timing

capacitor. Additionally, if very low charge and discharge

currents are used, there will be increased error due to the

The Fault signal output is high impedance during the soft

start cycle. A pull-up resistor to VREF or a pull-down resistor

to ground should be added to achieve the desired state of

Fault during soft start.

Gate Drive

input impedance at the C pin.

T

The ISL6740, ISL6741 are capable of sourcing and sinking

0.5A peak current, but are primarily intended to be used in

conjunction with a MOSFET driver due to the 5V drive level.

To limit the peak current through the IC, an external resistor

may be placed between the totem-pole output of the IC

(OUTA or OUTB pin) and the gate of the MOSFET. This

small series resistor also damps any oscillations caused by

the resonant tank of the parasitic inductances in the traces of

the board and the FET’s input capacitance.

The maximum duty cycle, D, and percent deadtime, DT, can

be calculated from:

T

C

(EQ. 5)

D = ------------

T

SW

DT = 1 – D

(EQ. 6)

Implementing Synchronization

Under Voltage Monitor and Inhibit

The oscillator can be synchronized to an external clock

applied to the SYNC pin or by connecting the SYNC pins of

multiple ICs together. If an external master clock signal is

used, the free running frequency of the oscillator should be

~10% slower than the desired synchronous frequency. The

external master clock signal should have a pulse width

greater than 20ns. The SYNC circuitry will not respond to an

external signal during the first 60% of the oscillator switching

cycle.

The UV input is used for input source under voltage lockout

and inhibit functions. If the node voltage falls below 1.00V a

UV shutdown fault occurs. This may be caused by low

source voltage or by intentional grounding of the pin to

disable the outputs. There is a nominal 10µA switched

current source used to create hysteresis. The current source

is active only during an UV/Inhibit fault; otherwise, it is

inactive and does not affect the node voltage. The

magnitude of the hysteresis is a function of the external

resistor divider impedance. If the resistor divider impedance

results in too little hysteresis, a series resistor between the

UV pin and the divider may be used to increase the

hysteresis. A soft start cycle begins when the UV/Inhibit fault

clears.

The SYNC input is edge triggered and its duration does not

affect oscillator operation. However, the deadtime is affected

by the SYNC frequency. A higher frequency signal applied to

the SYNC input will shorten the deadtime. The shortened

deadtime is the result of the timing capacitor charge cycle

12

ISL6740, ISL6741

The voltage hysteresis created by the switched current

The duration of the OC shutdown period can be increased

by adding a resistor between VREF and SS. The value of the

resistor must be large enough so that the minimum specified

SS discharge current is not exceeded. Using a 422kΩ

resistor, for example, will result in a small current being

injected into SS, effectively reducing the discharge current.

This will increase the OFF time by about 60%, nominally.

The external pull-up resistor will also decrease the SS

duration, so its effect should be considered when selecting

the value of the SS capacitor.

source and the external impedance is generally small due to

the large resistor divider ratio required to scale the input

voltage down to the UV threshold level. A small capacitor

placed between the UV input and ground may be required to

filter noise out.

V

IN

R1

R2

Latching OC shutdown is also possible by using a lower

valued resistor between VREF and SS. If the SS node is not

allowed to discharge below the SS reset threshold, the IC

will not recover from an over-current fault. The value of the

resistor must be low enough so that the maximum specified

discharge current is not sufficient to pull SS below 0.33V. A

200kΩ resistor, for example, prevents SS from discharging

below ~0.4V. Again, the external pull-up resistor will

decrease the SS duration, so its effect should be considered

when selecting the value of the SS capacitor.

1.00V

+

-

R3

10µA

ON

FIGURE 5. UV HYSTERESIS

ISL6741 - Over current results in pulse-by-pulse duty cycle

reduction as occurs in any peak current mode controller. This

results in a well controlled decrease in output voltage with

increasing current beyond the over current threshold. An over

current condition in the ISL6741 will not cause a shutdown.

As V decreases to a UV condition, the threshold level is:

IN

R1 + R2

R2

V

= ----------------------

V

(EQ. 7)

IN(DOWN)

The hysteresis voltage, ∆V, is:

Short Circuit Operation

–5

R1 + R2







〉

----------------------

∆V = 10 • 〈 R1 + R3 •

V

(EQ. 8)

A short circuit condition is defined as the simultaneous

occurrence of current limit and a reduced duty cycle. The

degree of reduced duty cycle is user adjustable using the

SCSET input. A resistor divider between either R or R

and GND to RCSET sets a threshold that is compared to the



R2

Setting R3 equal to zero results in the minimum hysteresis,

and yields:

TD TC

–5

voltage on the timing capacitor, C . The resistor divider

T

∆V = 10 • R1

V

(EQ. 9)

percentage corresponds to the fraction of the maximum duty

cycle below which a short circuit may exist. If the timing

capacitor voltage fails to exceed the threshold before an over

current pulse is detected, a short circuit condition exists. A

shutdown and soft start cycle will begin if 8 short circuit

events occur within 32 oscillator cycles. Connecting SCSET

to GND disables this feature.

As V increases from a UV condition, the threshold level is:

IN

(EQ. 10)

V

= V

+ ∆V

IN(DOWN)

V

IN(UP)

Over Current Operation

Since the current sourced from both R and R determine

the charge and discharge currents for the timing capacitor,

the effect of the SCSET divider must be included in the

ISL6740 - Over current delayed shutdown is enabled once

the soft start cycle is complete. If an over current condition is

detected, the soft start charging current source is disabled

and the soft start capacitor is allowed to discharge through a

15µA source. At the same time a 50µs re-triggerable one-

shot timer is activated. It remains active for 50µs after the

over current condition ceases. If the soft start capacitor

discharges by more then 0.25V to 4.25V, the output is

disabled and the Fault signal asserted. This state continues

until the soft start voltage reaches 270mV, at which time a

new soft start cycle is initiated. If the over current condition

stops at least 50µs prior to the soft start voltage reaching

4.25V, the soft start charging currents revert to normal

operation and the soft start voltage is allowed to recover.

TC

TD

timing calculations. Typically the resistor between R and

TC

GND is formed by two series resistors with the center node

connected to SCSET.

Alternatively, SCSET may be set using a voltage between 0V

and 2V. This voltage divided by 2 determines the percentage

of the maximum duty cycle that corresponds to a short circuit

when current limit is active. For example, if the maximum

duty cycle is 95% and 1V is applied to SCSET, then the short

circuit duty cycle is 50% of 95% or 47.5%.

13

ISL6740, ISL6741

If a PTC is desired, then position R2 may be substituted. The

Fault Conditions

threshold with increasing temperature is set by making the

fixed resistance equal in value to the thermistor resistance at

the desired trip temperature.

A fault condition occurs if V

falls below 4.65V, the UV

REF

input falls below 1.00V, the thermal protection is triggered, or

if OTS faults. When a fault is detected, OUTA and OUTB

outputs are disabled, the Fault signal is asserted, and the

soft start capacitor is quickly discharged. When the fault

condition clears and the soft start voltage is below the reset

threshold, a soft start cycle begins. The Fault signal is high

impedance during the soft start cycle.

V

↑ = 2.5V and R1 = R2 (HOT)

TH

To determine the value of the hysteresis resistor, R3, select

the value of thermistor resistance that corresponds to the

desired reset temperature.

5

10 • (R1 – R2) – R1 • R2

An over current condition that results in shutdown (ISL6740),

or a short circuit shutdown also cause assertion of the Fault

signal. The difference between a current fault and the faults

described earlier is that the soft start capacitor is not quickly

discharged. The initiation of a new soft start cycle is delayed

while the soft start capacitor is discharged at a 15µA rate.

This keeps the average output current to a minimum.

----------------------------------------------------------------------

(EQ. 11)

R3 =

Ω

R1 + R2

If the hysteresis resistor, R3, is not desired, the value of the

thermistor resistance at the reset temperature can be

determined from:

2.5 • R2

R1 = ----------------------------------------

–5

Ω

(NTC)

(EQ. 12)

2.5 – 10 • R2

Thermal Protection

Two methods of over temperature protection are provided.

The first method is an on board temperature sensor that

protects the device should the junction temperature exceed

145°C. There is approximately 15°C of hysteresis.

2.5 • R1

R2 = ----------------------------------------

–5

(EQ. 13)

Ω

(PTC)

2.5 + 10 • R1

The OTS comparator may also be used to monitor signals

other than suggested above. It may also be used to monitor

any voltage signal for which an excess requires a response

as described above. Input or output voltage monitoring are

examples of this.

The second method uses an internal comparator with a 2.5V

reference (V

/2). The non-inverting input to the

REF

comparator is accessible through the OTS pin. A thermistor

or thermal sensor located at or near the area of interest may

be connected to this input. There is a nominal 25µA switched

current source used to create hysteresis. The current source

is active only during an OT fault; otherwise, it is inactive and

does not affect the node voltage. The magnitude of the

hysteresis is a function of the external resistor divider

impedance. Either a positive temperature coefficient (PTC)

or a negative temperature coefficient (NTC) thermistor may

be used. If a NTC is desired, position R1 may be substituted.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

device. A good ground plane must be employed. V

should

DD

be bypassed directly to GND with good high frequency

capacitance.

Typical Application

The Typical Application Schematic features the ISL6740 in

an unregulated half-bridge DC-DC converter configuration,

often referred to as a DC Transformer or Bus Regulator. The

ISL6740EVAL1 demonstration unit implements this design

and is available for evaluation.

V

REF

V

REF

ON

The input voltage range is 48 ±10%V DC. The output is a

nominal 12V when the input voltage is at 48V. Since this is

an unregulated topology, the output voltage will vary

proportionately with input voltage. The load regulation is a

function of resistance between the source and the converter

output. The output is rated at 8A.

R1

R2

25µA

+

-

/2

REF

V

R3

FIGURE 6. OTS HYSTERESIS

14

ISL6740, ISL6741

energy, the number of turns that have to be wound, and

Circuit Element Descriptions

the wire gauge needed. Often the window area (the

space used for the windings) and power loss determine

the final core size.

The converter design may be broken down into the following

functional blocks:

Input Filtering: L1, C1, R1

• Determine maximum desired flux density. Depending

on the frequency of operation, the core material

selected, and the operating environment, the allowed

flux density must be determined. The decision of what

flux density to allow is often difficult to determine

initially. Usually the highest flux density that produces

an acceptable design is used, but often the winding

geometry dictates a larger core than is indicated based

on flux density alone.

Half-Bridge Capacitors: C2, C3

Isolation Transformer: T1

Primary Snubber: C13, R10

Start Bias Regulator: CR3, R2, R7, C6, Q5, D1

Supply Bypass Components: R3, C15, C4, C5

Main MOSFET Power Switch: QH, QL

Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10, C14

• Determine the number of primary turns.

• Select the wire gauge for each winding.

• Determine winding order and insulation requirements.

• Verify the design.

Control Circuit: U3, RT1, R14, R19, R13, R15, R17, R18,

C16, C18, C17

Output Rectification and Filtering: QR1, QR2, QR3, QR4, L2,

C9, C8

n

SR

S

Secondary Snubber: R8, R9, C11, C12

FET Driver: U1

n

P

S

ZVS Resonant Delay (Optional): L3, C7

SR

Design Criteria

The following design requirements were selected:

FIGURE 7. TRANSFORMER SCHEMATIC

Switching Frequency, Fsw: 235kHz

For this application we have selected a planar structure to

achieve a low profile design. A PQ style core was selected

because of its round center leg cross section, but there are

many suitable core styles available.

V

: 48 ±10%V

IN

: 12V (nominal) @ I

= 8A

OUT

P

: 100W

OUT

Since the converter is operating open loop at nearly 100%

duty cycle, the turns ratio, N, is simply the ratio of the input

voltage to the output voltage divided by 2.

Efficiency: 95%

Ripple: 1%

Transformer Design

V

48

12 • 2

IN

(EQ. 14)

N = ------------------------ = --------------- = 2

The design of a transformer for a half-bridge application is a

straight forward affair, although iterative. It is a process of

many compromises, and even experienced designers will

produce different designs when presented with identical

requirements. The iterative design process is not presented

here for clarity.

V

• 2

OUT

The factor of 2 divisor is due to the half-bridge topology. Only

half of the input voltage is applied to the primary of the

transformer.

A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from

TDK were selected for the transformer core. The ferrite

material is PC44.

The abbreviated design process follows:

• Select a core geometry suitable for the application.

Constraints of height, footprint, mounting preference,

and operating environment will affect the choice.

The core parameter of concern for flux density is the

effective core cross sectional area, Ae. For the PQ core

pieces selected:

• Determine the turns ratio.

2

Ae = 0.62cm or 6.2e -5m

• Select suitable core material(s).

Using Faraday’s Law, V = N dΦ/dt, the number of primary

turns can be determined once the maximum flux density is

set. An acceptable Bmax is ultimately determined by the

• Select maximum flux density desired for operation.

• Select core size. Core size will be dictated by the

capability of the core structure to store the required

15

ISL6740, ISL6741

2

allowable power dissipation in the ferrite material and is

influenced by the lossiness of the core, core geometry,

operating ambient temperature, and air flow. The TDK

datasheet for PC44 material indicates a core loss factor of

yields 555mils (0.785 sq. mils/c.m.). Dividing by the trace

width results in a copper thickness of 4.44mils (0.112mm).

Using 1.3mils/oz. of copper requires a copper weight of

3.4oz. For reasons of cost, 3oz. copper was selected.

3

~400 mW/cm with a ± 2000 gauss 100kHz sinusoidal

One layer of each secondary winding also contains the

synchronous rectifier winding. For this layer the secondary

trace width is reduced by 0.025 inches to 0.100 inches(0.015

inches for the SR winding trace width and 0.010 inches

spacing between the SR winding and the secondary

winding).

excitation. The application uses a 235kHz square wave

excitation, so no direct comparison between the application

and the data can be made. Interpolation of the data is

3

required. The core volume is approximately 1.6cm , so the

estimated core loss is

f

3

mW

-----------

3

200kHz

100kHz

act

The choice of copper weight may be validated by calculating

the DC copper losses of the secondary winding as follows.

Ignoring the terminal and lead-in resistance, the resistance

of each layer of the secondary may be approximated using

EQ. 18.

---------------

---------------------

P

≈

• cm

•

= 0.4 • 1.6 •

= 1.28

W

loss

f

meas

cm

(EQ. 15)

1.28W of dissipation is significant for a core of this size.

Reducing the flux density to 1200 gauss will reduce the

dissipation by about the same percentage, or 40%.

Ultimately, evaluation of the transformer’s performance in the

application will determine what is acceptable.

2πρ

R = -----------------------

Ω

(EQ. 18)

r













2

----

t • ln

r

1

From Faraday’s Law and using 1200 gauss peak flux density

(∆B = 2400 gauss or 0.24 tesla)

where

R = Winding resistance

–6

V

• T

ON

53 • 2 • 10

IN

N = ----------------------------- = ---------------------------------------------------- = 3.56

turns

(EQ. 16)

ρ = Resistivity of copper = 669e-9Ω-inches at 20°C

t = Thickness of the copper (3 oz.) = 3.9e-3 inches

–5

2 • A • ∆B

e

2 • 6.2 • 10 • 0.24

Rounding up yields 4 turns for the primary winding. The

peak flux density using 4 turns is ~1100 gauss. From EQ. 1,

the number of secondary turns is 2.

r = Outside radius of the copper trace = 0.324 or 0.299

2

inches

r = Inside radius of the copper trace = 0.199 inches

1

The volts/turn for this design ranges from 5.4V at V = 43V

IN

The winding without the SR winding on the same layer has a

DC resistance 2.21mΩ. The winding that shares the layer

with the SR winding has a DC resistance of 2.65mΩ. With

the secondary configured as a 4 turn center tapped winding

(2 turns each side of the tap), the total DC power loss for the

secondary at 20°C is 486mW.

to 6.6V at V = 53V. Therefore, the synchronous rectifier

IN

(SR) windings may be set at 1 turn each with proper FET

selection. Selecting 2 turns for the synchronous rectifier

windings would also be acceptable, but the gate drive losses

would increase.

The next step is to determine the equivalent wire gauge for

the planar structure. Since each secondary winding

conducts for only 50% of the period, the RMS current is

The primary windings have an RMS current of approximately

5 A (I

x N /N at ~ 100% duty cycle). The primary is

OUT

S P

configured as 2 layers, 2 turns per layer to minimize the

winding stack height. Allowing 0.020 inches edge clearance

and 0.010 inches between turns yields a trace width of

0.0575 inches. Ignoring the terminal and lead-in resistance,

and using EQ. 18, the inner trace has a resistance of

4.25mΩ, and the outer trace has a resistance of 5.52mΩ.

The resistance of the primary then is 19.5mΩ at 20°C. The

total DC power loss for the secondary at 20°C is 489mW.

(EQ. 17)

I

= I

•

OUT

D = 10 • 0.5 = 7.07

A

RMS

where D is the duty cycle. Since an FR-4 PWB planar

winding structure was selected, the width of the copper

traces is limited by the window area width, and the number

of layers is limited by the window area height. The PQ core

selected has a usable window area width of 0.165 inches.

Allowing one turn per layer and 0.020 inches clearance at

the edges allows a maximum trace width of 0.125 inches.

Using 100 circular mils(c.m.)/A as a guideline for current

density, and from EQ. 17, 707c.m. are required for each of

the secondary windings (a circular mil is the area of a circle

0.001 inches in diameter). Converting c.m. to square mils

Improved efficiency and thermal performance could be

achieved by selecting heavier copper weight for the

windings. Evaluation in the application will determine its

need.

16

ISL6740, ISL6741

The order and geometry of the windings affects the AC

resistance, winding capacitance, and leakage inductance of

the finished transformer. To mitigate these effects,

interleaving the windings is necessary. The primary winding

is sandwiched between the two secondary windings. The

winding layout appears below.

FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING

FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR

WINDINGS

FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING

FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING

FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR

WINDINGS

∅0.689

∅0.358

0.807

0.639

FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING

0.403

0.169

0.000

0.000 0.184

0.479

0.774

1.054

FIGURE 7G. PWB DIMENSIONS

17

ISL6740, ISL6741

devices are used in parallel for a total of four SR FETs. The

FDS5670 is rated at 60V and 10A (r = 14mΩ).

MOSFET Selection

DS(ON)

The criteria for selection of the primary side half-bridge FETs

and the secondary side synchronous rectifier FETs is largely

based on the current and voltage rating of the device.

However, the FET drain-source capacitance and gate charge

cannot be ignored.

Oscillator Component Selection

The desired operating frequency of 235kHz for the converter

was established in the Design Criteria section. The

oscillator frequency operates at twice the frequency of the

converter because two clock cycles are required for a

complete converter period.

The zero voltage switch (ZVS) transition timing is dependent

on the transformer’s leakage inductance and the

capacitance at the node between the upper FET source and

the lower FET drain. The node capacitance is comprised of

the drain-source capacitance of the FETs and the

During each oscillator cycle the timing capacitor, C , must be

T

charged and discharged. Determining the required

discharge time to achieve zero voltage switching (ZVS) is the

critical design goal in selecting the timing components. The

discharge time sets the deadtime between the two outputs,

and is the same as ZVS transition time. Once the discharge

time is determined, the remainder of the period becomes the

charge time.

transformer parasitic capacitance. The leakage inductance

and capacitance form an LC resonant tank circuit which

determines the duration of the transition. The amount of

energy stored in the LC tank circuit determines the transition

voltage amplitude. If the leakage inductance energy is too

low, ZVS operation is not possible and near or partial ZVS

operation occurs. As the leakage energy increases, the

voltage amplitude increases until it is clamped by the FET

The ZVS transition duration is determined by the

transformer’s primary leakage inductance, L , by the FET

lk

body diode to ground or V , depending on which FET

Coss, by the transformer’s parasitic winding capacitance,

and by any other parasitic elements on the node. The

parameters may be determined by measurement,

calculation, estimate, or by some combination of these

methods.

IN

conducts. When the leakage energy exceeds the minimum

required for ZVS operation, the voltage is clamped until the

energy is transferred. This behavior increases the time

window for ZVS operation. This behavior is not without

consequences, however. The transition time and the period

of time during which the voltage is clamped reduces the

effective duty cycle.

π L • (2C

+ C

)

xfrmr

lk

oss

(EQ. 19)

-------------------------------------------------------------------

t

≈

S

zvs

2

The gate charge affects the switching speed of the FETs.

Higher gate charge translates into higher drive requirements

and/or slower switching speeds. The energy required to drive

the gates is dissipated as heat.

Device output capacitance, Coss, is non-linear with applied

voltage. To find the equivalent discrete capacitance, Cfet, a

charge model is used. Using a known current source, the

time required to charge the MOSFET drain to the desired

operating voltage is determined and the equivalent

capacitance is calculated.

The maximum input voltage, V , plus transient voltage,

IN

determines the voltage rating required. With a maximum

input voltage of 53V for this application, and if we allow a

10% adder for transients, a voltage rating of 60V or higher

will suffice.

Ichg • t

(EQ. 20)

Cfet = -------------------

F

V

Once the estimated transition time is determined, it must be

verified directly in the application. The transformer leakage

inductance was measured at 125nH and the combined

capacitance was estimated at 2000pF. Calculations indicate

a transition period of ~ 25ns. Verification of the performance

The RMS current through the each primary side FET can be

determined from EQ. 17, substituting 5A of primary current

for I

. The result is 3.5A RMS. Fairchild FDS3672 FETs,

OUT

rated at 100V and 7.5A (r

the half-bridge switches.

= 22mΩ), were selected for

DS(ON)

yielded a value of T closer to 45ns.

D

The synchronous rectifier FETs must withstand

approximately one half of the input voltage assuming no

switching transients are present. This suggests a device

capable of withstanding at least 30V is required. Empirical

testing in the circuit revealed switching transients of 20V

were present across the device indicating a rating of at least

60V is required.

The remainder of the switching half-period is the charge

time, T , and can be found from

C

–9

1

2 • F

1

T

= --------------- – T = ---------------------------------- – 45 • 10

= 2.08

µs

C

D

3

S

2 • 235 • 10

(EQ. 21)

where F is the converter switching frequency.

S

The RMS current rating of 7.07A for each SR FET requires a

Using Fig. 4, the capacitor value appropriate to the desired

oscillator operating frequency of 470kHz can be selected. A

low r

to minimize conduction losses, which is difficult to

DS(ON)

find in a 60V device. It was decided to use two devices in

parallel to simplify the thermal design. Two Fairchild FDS5670

C value of 100pF, 220pF, or 330pF is appropriate for this

T

frequency. A value of 220pF was selected.

18

ISL6740, ISL6741

To obtain the proper value for R , EQ. 3 is used. Since

there is a 10ns propagation delay in the oscillator circuit, it

ripple current under steady state operation increases

significantly as the duty cycle decreases.

TD

must be included in the calculation. The value of R

TD

14

selected is 8.06kΩ.

V (L1:1)

I (L1)

A similar procedure is used to determine the value of R

TC

13

using EQ. 2. The value of R selected is the series

TC

12

11

combination of 17.4kΩ and 1.27kΩ. See section Over

Current Component Selection for further explanation.

Output Filter Design

10

9

The output filter inductor and capacitor selection is simple

and straightforward. Under steady state operating conditions

the voltage across the inductor is very small due to the large

duty cycle. Voltage is applied across the inductor only during

the switch transition time, about 45ns in this application.

Ignoring the voltage drop across the SR FETs, the voltage

8

0.9950

0.9960

0.9970

0.9980

0.9990

1.000

TIME (ms)

across the inductor during the ON time with V = 48V is

IN

FIGURE 8. STEADY STATE SECONDARY WINDING

VOLTAGE AND INDUCTOR CURRENT

V

• N • (1 – D)

S

2N

P

IN

-----------------------------------------------

(EQ. 22)

V

= V – V =

OUT

≈ 250

mV

L

S

15

where

V is the inductor voltage

V (L1:1)

I (L1)

L

V is the voltage across the secondary winding

S

V

is the output voltage

OUT

10

If we allow a current ramp, ∆I, of 5% of the rated output

current, the minimum inductance required is

V

• T

ON

∆I

L

0.25 • 2.08

------------------------

(EQ. 23)

L ≥

= ---------------------------- = 1.04

µH

0.5

5

0.986 0.988

0.990 0.992 0.994 0.996 0.998 1.000

TIME (ms)

An inductor value of 1.4µH, rated for 18A was selected.

With a maximum input voltage of 53V, the maximum output

voltage is about 13V. The closest higher voltage rated

capacitor is 16V. Under steady state operating conditions the

ripple current in the capacitor is small, so it would seem

appropriate to have a low ripple current rated capacitor.

However, a high rated ripple current capacitor was selected

based on the nature of the intended load, multiple buck

regulators. To minimize the output impedance of the filter, a

Sanyo OSCON 16SH150M capacitor in parallel with a 22µF

ceramic capacitor were selected.

FIGURE 9. SECONDARY WINDING VOLTAGE AND

INDUCTOR CURRENT DURING CURRENT LIMIT

OPERATION

Figures 8 and 9 show the behavior of the inductor ripple

under steady state and over current conditions. In this

example, the peak current limit is set at 11A. The peak

current limit causes the duty cycle to decrease resulting in a

reduction of the average current through the inductor. The

implication is that the converter can not supply the same

output current in current limit that it can supply under steady

state conditions. The peak current limit setpoint must take

this behavior into consideration. A 3.32Ω current sense

resistor was selected for the rectified secondary of current

transformer T2, corresponding to a peak current limit

setpoint of 16.5A.

Over Current Component Selection

There are two circuit areas to consider when selecting the

components for over current protection, current limit and

short circuit shutdown. The current limit threshold is fixed at

0.6V while the short circuit threshold is set to a fraction of the

duty cycle the designer wishes to define as a short circuit.

The short circuit protection involves setting a voltage

between 0 and 2V on the SCSET pin. The applied voltage

divided by 2 is the percent of maximum duty cycle that

corresponds to a short circuit when the peak current limit is

active. A divider from RTC to ground provides an easy

method to achieve this. The divider between RTC and GND

The current level that corresponds to the over current

threshold must be chosen to allow for the dynamic behavior

of an open loop converter. In particular, the low inductor

19

ISL6740, ISL6741

formed by R13 and R15 determines the percent of maximum

duty cycle that corresponds to a short circuit. The divider

ratio formed by R13 and R15 is

regulation is not required, such as those application that use

downstream DC-DC converters, this design approach is

viable.

R13

1.27k

---------------------------- = ------------------------------------ = 0.068

(EQ. 24)

Waveforms

R13 + R15 1.27k + 17.4k

Typical waveforms can be found in the following Figures.

Figure 13 shows the output voltage during start up.

Therefore, the duty cycle that corresponds to a short circuit

is 6.8% of D max (97.9%), or ~6.6%.

Performance

The major performance criteria for the converter are

efficiency, and to a lesser extent, load regulation. Efficiency,

load regulation and line regulation performance are

demonstrated in the following Figures.

100

95

90

85

80

75

70

9

8

0

1

2

3

4

5

6

7

FIGURE 13. OUTPUT SOFT START

LOAD CURRENT (A)

FIGURE 10. EFFICIENCY vs LOAD V = 48V

IN

Figure 14 shows the output voltage ripple and noise at a 5A

load.

t

12.5

12.25

12

11.75

11.5

11.25

11

9

8

0

1

2

3

4

5

6

7

LOAD CURRENT (A)

FIGURE 11. LOAD REGULATION AT V = 48V

IN

14

13.5

13

FIGURE 14. OUTPUT RIPPLE AND NOISE - 20MHz BW

12.5

12

Figures 15 and 16 show the voltage waveforms at the

switching node shared by the upper FET source and the lower

FET drain. In particular, Figure 16 shows near ZVS operation

at 8A of load when the upper FET is turning off and the lower

FET turning on. There is insufficient energy stored in the

leakage inductance to allow complete ZVS operation.

However, since the energy stored in the node capacitance is

11.5

11

45 46 47 48 49 50 51 52 53 54

INPUT VOLTAGE (V)

FIGURE 12. LINE REGULATION AT I

= 1A

OUT

2

proportional to V , a significant portion of the energy is still

As expected, the output voltage varies considerably with line

and load when compared to an equivalent converter with

closed loop feedback. However, for applications where tight

recovered. Figure 17 shows the switching transition between

outputs, OUTA and OUTB during steady state operation. The

deadtime duration of 48.6ns is clearly shown.

20

ISL6740, ISL6741

Component List

REFERENCE

DESIGNATOR VALUE

DESCRIPTION

C1

1.0µF

3.3µF

1.0µF

Capacitor, 1812, X7R, 100V, 20%

TDK C4532X7R2A105M

C2, C3

C4, C6

Capacitor, 1812, X5R, 50V, 20%

TDK C4532X5R1H335M

Capacitor, 0805, X5R, 16V, 10%

TDK C2012X5R1C105K

C5, C15, C16 0.1µF

Capacitor, 0603, X7R, 50V, 10%

TDK C1608X7R1H104K

C7

C8

Open

Capacitor, 0603, Open

22µF

Capacitor, 1812, X5R, 16V, 20%

TDK C4532X5R1C226M

FIGURE 15. FET DRAIN-SOURCE VOLTAGE

C9

150µF Capacitor, Radial, Sanyo 16SH150M

C10, C11,

C12, C13, C14

1000pF Capacitor, 0603, X7R, 50V, 10%

TDK C1608X7R1H102K

C17

220pF Capacitor, 0603, COG, 16V, 5%

TDK C1608COG1C221J

C18

0.047µF Capacitor, 0603, X7R, 16V, 10%

TDK C1608X7R1C473K

CR1, CR2

Diode, Schottky, BAT54S

Diode, Schottky, BAT54

CR3

D1

L1

Zener, 10V, Philips BZX84C10ZXCT-ND

190nH Pulse, P2004T

L2

1.5µH

Pulse, PG0077.142

L3

Short

Jumper or Optional Discrete Leakage

Inductance

Q5

Transistor, ON MJD31C

FET, Fairchild FDS3672

FET, Fairchild FDS5670

QL, QH

QR1, QR2,

QR3, QR4

FIGURE 16. FET D-S VOLTAGE NEAR-ZVS TRANSITION

R1, R10

R2

3.3

Resistor, 2512, 5%

Resistor, 2512, 1%

Resistor, 0603, 1%

Resistor, 0805, 1%

Resistor, 0603, 1%

Resistor, 0603, Open

Resistor, 0603, 1%

Midcom 31718

3.01K

10.0

R3, R6

R5

3.32

R7

75.0K

20.0

R8, R9

R11

R12

R13

R14

R15

R17

R18

R19, RT1

T1

100

8.06K

17.4K

Open

1.27K

97.6K

3.01K

10.0K

FIGURE 17. OUTA - OUTB TRANSITION

T2

Pulse P8205T

U1

Intersil HIP2101IB

ISL6740IB

U3

21

ISL6740, ISL6741

Other duty ranges are possible, but are still limited to a 2:1

ratio. The voltage applied to V must be scaled to the

Adding Line Only Regulation - Feed Forward

ERROR

Output voltage variation caused by changes in the supply

voltage may be virtually removed through a technique known

as feed forward compensation. Using feed forward, the duty

cycle is directly controlled based on changes in the input

voltage only. No closed loop feedback system is required.

Voltage feed forward may be implemented as shown below.

peak-to-peak voltage on CT, and offset by the valley voltage.

Since the peak-to-peak CT voltage is 2.00V nominal, the

voltage at the output of U100A must be divided by 2.0V to

obtain the desired duty cycle. For example, if an 80% duty

cycle was required at the minimum operating voltage, the

output of U100A must be 1.60V (80% of 2.00V). From (EQ.

25), the divider voltage must be set to 1.4V for the input

voltage that corresponds to the 80% duty cycle.

R110

698

R111

806

R109

3.48K

VREF

1.5V

0.8V

It should be noted that the synchronous rectifiers (SRs),

being driven from the transformer secondary, are only gated

on during the ON time of the primary FETs. Conduction

continues through the body diodes during the OFF time

when operating in continuous inductor current mode. This

mode of operation usually results in significant conduction

and switching losses in the SR FETs. These losses may be

reduced considerably by either adding schottky diodes in

parallel to the SR FETs or by driving the SR FETs directly

with a control signal.

+VIN

R103

49.9K

R106

100K

R100

69.8K

U100A

+

-

U100B

+

-

R105

100K

R102

100K

to V_ERROR

R104

100K

R101

2K

R107

100K

Adding Regulation - Closed Loop Feedback

R108

100K

C100

1nF

The second Typical Application schematic adds closed loop

feedback with isolation. The ISL6740EVAL2 demonstration

platform implements this design and is available for

evaluation. The input voltage range was increased to 36V -

75V, which necessitates a few modifications to the open loop

design. The output inductor value was increased to 4.0µH,

schottky rectifier CR4 was added to minimize SR FET body

diode conduction, the turns ratio of the main transformer was

changed to 4:3, and the synchronous rectifier gate drives

were modified. The design process is essentially the same

as it was for the unregulated version, so only the feedback

control loop design will be discussed.

FIGURE 18. VOLTAGE FEED FORWARD CIRCUIT

The circuit provides feed forward compensation for a 2:1

input voltage range. Resistors R100 and R101 set the input

voltage divider to generate a 1.00 volt signal at the input

voltage that corresponds to maximum duty cycle (V

IN

minimum). Resistors R109, R110, and R111 form a voltage

divider from VREF to create reference voltages for the

amplifiers. The first stage uses U100A, R102, R103, R104,

and C100 to form a unity gain inverting amplifier. Its output

varies inversely with input voltage and ranges from 1 to 2V.

The bandwidth of the circuit may be controlled by varying the

value of C100. The gain of the first amplifier stage is:

The major components of the feedback control loop are a

programmable shunt regulator and an opto-coupler. The

opto-coupler is used to transfer the error signal across the

isolation barrier. The opto-coupler offers a convenient means

to cross the isolation barrier, but it adds complexity to the

feedback control loop. It adds a pole at about 10kHz and a

significant amount of gain variation due the current transfer

ratio (CTR). The CTR of the opto-coupler varies with initial

tolerance, temperature, forward current, and age.

(EQ. 25)

V

= –V + 3.00

V

A

D

where:

V = Output voltage of U100A

A

V

= The input divider voltage

D

The second stage uses U100B, R105, R106, R107, and

R108 to form a summing amplifier which offsets the first

stage output by 0.8V (the value of CT valley voltage). The

signal applied to the V

input now matches the offset

ERROR

and amplitude of the oscillator sawtooth so that the duty

cycle varies linearly from 100% to 50% of maximum with a

2:1 input voltage variation.

22

ISL6740, ISL6741

A block diagram of the feedback control loop follows in

Figure 19.

40

30

20

10

0

POWER

STAGE

PWM

V

OUT

ERROR AMPLIFIER

Z

2

ISOLATION

-10

-20

-

Z

1

REF

+

3

4

5

6

10

100

1•10

FREQUENCY (Hz)

FIGURE 21A. CONTROL-TO-OUTPUT GAIN

FIGURE 19. CONTROL LOOP BLOCK DIAGRAM

50

The loop compensation is placed around the Error Amplifier

(EA) on the secondary side of the converter. A Type 3 error

amplifier configuration was selected.

0

-50

V

OUT

-100

-150

-200

-

V

ERR

REF

+

3

4

5

6

10

100

1•10

FIGURE 20. TYPE 3 ERROR AMPLIFIER

FREQUENCY (Hz)

FIGURE 21B. CONTROL-TO-OUTPUT PHASE

The control to output transfer function may be represented

as [1]

The Type 3 compensation configuration has three poles and

two zeros. The first pole is at the origin, and provides the

integration characteristic which results in excellent DC

regulation. Referring to the Typical Application Schematic for

the regulated output, the remaining poles and zeros for the

compensator are located at:

s

1 + ------

V

N

ω

v

IN

• 2

S

z

o

---------------- ------- -------------------------------------------------

----- =

•

(EQ. 26)

2

V

N

P

v

c

s

S









------

1 + ---------------- +

ω

(Q)ω

o

where

1

f

= ----------------------------------------

2π • R21 • C20

(EQ. 27)

p2

p3

R

o

Q = ---------------

ω

• L

1

o

-------------------------------------

f

≈

C19 » C20

(EQ. 28)

2π • R4 • C22

1

ω

= -----------

or

f

= -------------------

2π LC

o

z

o

LC

(EQ. 29)

(EQ. 30)

1

f

= ----------------------------------------

2π • R21 • C19

z1

z2

1

= -----------

f

= ------------------

z

R C

2πR C

c

1

----------------------------------------

≈

R23 » R4

R = Output Load Resistance

o

2π • R23 • C22

L = Output Inductance

C = Output Capacitance

From (EQ. 26), it can be seen that the control to output

transfer function frequency dependence is a function of the

output load resistance, the value of output capacitor and

inductor, and the output capacitance ESR. These variations

must be considered when compensating the control loop.

The worst case small signal operating point for a voltage

mode converter tends to be at maximum Vin, maximum load,

maximum Cout, and minimum ESR.

R = Output Capacitance ESR

c

V = Sawtooth Ramp Amplitude

S

Gain and phase plots of (EQ. 26) appear below using L =

4.0µH, C = 150µF, Rc = 28mΩ, Ro = 1.2Ω, and Vin = 75V.

23

ISL6740, ISL6741

The higher the desired bandwidth of the converter, the more

The following compensation components were selected

difficult it is to create a solution that is stable over the entire

operating range. A good rule of thumb is to limit the

bandwidth to about Fsw/4, where Fsw is the switching

frequency of the converter. However, due to the bandwidth

constraints of the opto-coupler and the LM431 shunt

regulator, the bandwidth was reduced to about 25kHz.

R23 = 9.53kΩ

R24 = 2.49kΩ

R4 = 499Ω

R21 = 4.22kΩ

The first pole is placed at the origin by default (C20 is an

integrating capacitor). If the two zeroes are placed at the

C22 = 1nF

C20 = 82pF

same frequency, they should be placed at f /2, where f is

LC LC

the resonant frequency of the output L-C filter. To reduce the

gain peaking at the L-C resonant frequency, the two zeroes

are often separated. When they are separated, the first zero

C19 = 0.22µF

From (EQ. 27-30), the poles and zeroes are:

may be placed at f /5, and the second at just above f

.

f

= 171Hz

LC LC

z1

z2

p2

p3

The second pole is placed at the lowest expected zero cause

by the output capacitor ESR. The third, and last pole is

placed at about 1.5 times the cross over frequency.

= 16.7kHz

= 460kHz

= 319kHz

Some liberties where taken with the generally accepted

compensation procedure described above due to the

transfer characteristics of the opto coupler. The effects of the

opto-coupler tend to dominate over those of the LM431 so

the GBWP effects of the LM431 are not included here.

The calculated gain and phase plots of the error amplifier

appear below using an ideal op amp.

20

The gain and phase characteristics of the opto coupler are

shown below.

10

0

5

0

-5

-10

-15

-20

-10

3

4

5

6

10

100

1•10

FREQUENCY (Hz)

FIGURE 23A. IDEAL ERROR AMPLIFIER GAIN

3

4

5

6

10

100

1•10

FREQUENCY (Hz)

90

45

0

FIGURE 22A. OPTO COUPLER GAIN

90

45

0

-45

-90

-45

-90

3

4

5

6

10

100

1•10

FREQUENCY (Hz)

FIGURE 23B. IDEAL ERROR AMPLIFIER PHASE

3

4

5

6

10

100

1•10

FREQUENCY (Hz)

FIGURE 22B. OPTO COUPLER

24

ISL6740, ISL6741

The gain and phase plots combined with the opto coupler’s

transfer characteristics appear below:

Using the control-to-output transfer function combined with

the EA transfer function, the loop gain and phase may be

predicted. The predicted loop gain and phase margin of the

converter appear below:

30

50

40

20

10

0

30

20

10

0

-10

-20

-30

-40

-50

-10

10

3

4

5

6

100

1•10

FREQUENCY (Hz)

3

4

5

100

1•10

FREQUENCY (Hz)

FIGURE 24A. EA PLUS OPTO COUPLER GAIN

FIGURE 25A. PREDICTED LOOP GAIN

90

45

0

225

180

135

90

-45

-90

45

0

-135

-45

-90

-135

-180

10

3

4

5

6

100

1•10

FREQUENCY (Hz)

3

4

5

100

1•10

FIGURE 24B. EA PLUS OPTO COUPLER GAIN

FREQUENCY (Hz)

FIGURE 25B. PREDICTED LOOP PHASE MARGIN

25

ISL6740, ISL6741

The actual loop gain and phase margin measured on the

Performance

ISL6740EVAL2 demonstration board appear below:

The major performance criteria for the converter are

efficiency and load regulation. These quantities are detailed

in the following Figures.

50

40

30

95

93

91

89

87

85

20

10

0

-10

-20

-30

-40

-50

0.1

1

10

100

FREQUENCY (kHz)

2

3

4

5

6

7

8

9

10

FIGURE 26A. MEASURED LOOP GAIN

LOAD CURRENT (A)

FIGURE 27. EFFICIENCY vs LOAD V = 48V

IN

t

225

180

135

90

12.015

12.01

12.005

12

45

0

-45

-90

-135

0.1

1

10

100

FREQUENCY (kHz)

11.995

0

1

2

3

4

5

6

7

8

9

10

FIGURE 26B. MEASURE LOOP PHASE MARGIN

LOAD CURRENT (A)

FIGURE 28. LOAD REGULATION AT V = 48V

IN

The only major discrepancies between the predicted

behavior and the measured results are the Q of the L-C filter

and the phase behavior above 60kHz. The actual Q appears

to be significantly less than predicted resulting in less gain

peaking and a less rapid phase shift near the resonant

frequency. This is most likely the result of neglecting other

losses in the converter’s output, such as the FET on

resistance, copper losses, and inductor resistance. The

phase discrepancy above 60kHz is not particularly relevant

to the loop performance since it occurs well above the cross

over frequency. The predicted behavior indicates a much

gentler drop off of phase than was observed in the measured

performance. The discrepancy was not investigated.

The efficiency, although very good, could be further

improved using a controlled SR method instead of using a

self-driven method with an auxiliary schottky diode. The

schottky diode conducts when the main switching FETs are

off. Its forward voltage drop is considerably larger than that

of the SR FETs and causes a measurable reduction in

efficiency. The effect becomes more significant as the input

voltage is increased due to the reduction of duty cycle (and

consequent increase in the OFF time).

26

ISL6740, ISL6741

Component List

Component List (Continued)

REFERENCE

DESIGNATOR VALUE

DESCRIPTION

DESIGNATOR VALUE

DESCRIPTION

Resistor, 0603, 1%

C1

1.0µF

3.3µF

1.0µF

Capacitor, 1812, X7R, 100V, 20%

TDK C4532X7R2A105M

R6

200

R7

75.0K

18

Resistor, 0805, 1%

Resistor, 2512, 5%

Resistor, 0603, 1%

Resistor, 0603, Open

Resistor, 0603, 1%

Resistor, 0805, 1%

Resistor, 0603, 1%

Midcom 31660

C2, C3

C4, C6

Capacitor, 1812, X5R, 50V, 20%

TDK C4532X5R1H335M

R8, R9, R10

R11

R12

R13

R14

R15

R16, R19

R17

R18

R20

R21

R23

R24

R26, R27

RT1

T1

205

Capacitor, 0805, X5R, 16V, 10%

TDK C2012X5R1C105K

8.06K

18.2K

Open

1.27K

1.00K

97.6K

3.01K

2.00K

4.22K

9.53K

2.49K

5.11

C5, C15, C16 0.1µF

Capacitor, 0603, X7R, 50V, 10%

TDK C1608X7R1H104K

C7

Open

Capacitor, 0603, Open

C8, C21

22µF

Capacitor, 1812, X5R, 16V, 20%

TDK C4532X5R1C226M

C9

150µF

Capacitor, Radial, Sanyo 16SH150M

C10, C14, C22 1000pF Capacitor, 0603, X7R, 50V, 10%

TDK C1608X7R1H102K

C11, C12

560 pF Capacitor, 0603, X7R, 100V, 10%

TDK C1608X7R2A561K

C13

220pF

Capacitor, 0603, X7R, 100V, 10%

TDK C1608X7R2A221K

C17

220pF

Capacitor, 0603, COG, 16V, 5%

TDK C1608COG1C221J

10.0K

C18

0.047µF Capacitor, 0603, X7R, 16V, 10%

TDK C1608X7R1C473K

T2

Pulse P8205T

C19

0.22µF Capacitor, 0603, X7R, 16V, 10%

TDK C1608X7R1C224K

U1

Intersil HIP2101IB

NEC PS2801-1

C20

82pF

Capacitor, 0603, X7R, 16V, 10%

TDK C1608X7R1C820K

U2

U3

ISL6740IB

CR1, CR2

CR3, CR5, CR6

CR4

Diode, Schottky, BAT54S

Diode, Schottky, BAT54

U4

National LM431BIM3/N1C

Diode, Schottky, IR 12CWQ06FN

References

[1] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode

Power Supply Design Seminar, SEM-700, 1990.

D1

Zener, 10V, Philips BZX84C10ZXCT-

ND

D2

Zener, 6.8V, Philips BZX84C6Z8XCT-

ND

L1

L2

L3

Q5

190nH

4.0µH

Short

Pulse, P2004T

BI Technologies, HM65-H4R0

0 Ohm Jumper

Transistor, ON MJD31C

FET, Fairchild FDS3672

QL, QH, QR1,

QR2, QR3,

QR4

R1

3.3

Resistor, 2512, 5%

Resistor, 2512, 2%

Resistor, 0603, 1%

Resistor, 0805, 1%

R2

3.01K

10.0

499

R3

R4, R25

R5

2.20

27

ISL6740, ISL6741

Thin Shrink Small Outline Plastic Packages (TSSOP)

M16.173

N

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

MIN

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

GAUGE

PLANE

SYMBOL

MAX

0.043

0.006

0.037

0.012

0.008

0.201

0.177

MIN

-

MAX

1.10

0.15

0.95

0.30

0.20

5.10

4.50

NOTES

A

A1

A2

b

-

0.002

0.033

0.0075

0.0035

0.193

0.169

0.05

0.85

0.19

0.09

4.90

4.30

-

1

2

3

-

L

0.25

0.010

0.05(0.002)

SEATING PLANE

A

9

-A-

c

-

D

3

-C-

E1

e

4

α

0.026 BSC

0.65 BSC

-

A2

e

A1

c

E

0.246

0.020

0.256

0.028

6.25

0.50

6.50

0.70

-

b

0.10(0.004)

L

6

0.10(0.004) M

C

A M B S

N

16

7

o

0

8

0

8

-

α

NOTES:

Rev. 1 2/02

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.15mm (0.006

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact. (Angles in degrees)

28

ISL6740, ISL6741

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

SYMBOL

MIN

MAX

0.069

0.010

0.019

0.010

0.394

0.157

MIN

1.35

0.10

0.35

0.19

9.80

3.80

MAX

1.75

NOTES

AREA

E

A

A1

B

C

D

E

e

0.053

0.004

0.014

0.007

0.386

0.150

-

-B-

0.25

-

0.49

9

1

2

3

L

0.25

-

10.00

4.00

3

SEATING PLANE

A

4

-A-

o

D

h x 45

0.050 BSC

1.27 BSC

-

H

h

0.228

0.010

0.016

0.244

0.020

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

-C-

α

µ

5

e

A1

L

6

C

B

0.10(0.004)

N

α

16

7

M

S

B

o

0.25(0.010)

C

A

0

8

0

8

-

Rev. 1 02/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.

However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

29

型号	制造商	描述	替代类型	文档
ISL6741IV	INTERSIL	Flexible Double Ended Voltage and Current Mode PWM Controllers	类似代替
ISL6741IVZ-T	INTERSIL	Flexible Double Ended Voltage and Current Mode PWM Controllers	类似代替

型号	制造商	描述	价格	文档
ISL6741IVZ-T	INTERSIL	Flexible Double Ended Voltage and Current Mode PWM Controllers	获取价格
ISL6741IVZ-T	RENESAS	Flexible Double Ended Voltage and Current Mode PWM Controllers; TSSOP16; Temp Range: -40&deg; to 85&deg;C	获取价格
ISL6742	INTERSIL	Advanced Double-Ended PWM Controller	获取价格
ISL6742	RENESAS	Advanced Double-Ended PWM Controller with Synchronous Rectifier Control and Average Current Limit	获取价格
ISL6742AAZA	INTERSIL	Advanced Double-Ended PWM Controller	获取价格
ISL6742AAZA-T	INTERSIL	Advanced Double-Ended PWM Controller	获取价格
ISL6742B	RENESAS	Advanced Double-Ended PWM Controller	获取价格
ISL6742BAAZA	RENESAS	Advanced Double-Ended PWM Controller	获取价格
ISL6742BEVAL3Z	RENESAS	Advanced Double-Ended PWM Controller	获取价格
ISL6744	INTERSIL	Intermediate Bus PWM Controller	获取价格

ISL6741IVZ

ISL6741IVZ 概述

ISL6741IVZ 数据手册

ISL6741IVZ CAD模型

ISL6741IVZ 替代型号

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