ISL6730AEVAL1Z_技术文档

Power Factor Correction Controllers

ISL6730A, ISL6730B, ISL6730C, ISL6730D

The ISL6730A, ISL6730B, ISL6730C, ISL6730D are active

Power Factor Correction (PFC) controller ICs that use a boost

topology. The controllers are suitable for AC/DC power

systems, up to 2kW and over the universal line input.

Features

• Reduce component size requirements

- Enables smaller, thinner AC/DC adapters

- Choke and cap size can be reduced

- Lower cost of materials

The ISL6730A, ISL6730B, ISL6730C, ISL6730D operate in

Continuous Conduction Mode (CCM). Accurate input current

shaping is achieved with a current error amplifier. A patent

pending breakthrough negative capacitance technology

minimizes zero crossing distortion and reduces the magnetic

components size. The small external components result in a

low cost design without sacrificing performance.

• Excellent power factor over line and load regulation

- Internal current compensation

- CCM Mode with Patent pending IP for smaller EMI filter

• Better light load efficiency

- Automatic pulse skipping

The internally clamped 12.5V gate driver delivers 1.5A peak

current to the external power MOSFET. The ISL6730A,

ISL6730B, ISL6730C, ISL6730D provide a highly reliable

system that is fully protected. Protection features include

cycle-by-cycle overcurrent, over power limit, over-temperature,

input brownout, output overvoltage and undervoltage

protection.

- Programmable or automatic shutdown

• High reliable design

- Cycle-by-cycle current limit

- Input average power limit

- OVP and OTP protection

- Input brownout protection

The ISL6730A, ISL6730B provide excellent power efficiency

and transitions into a power saving skip mode during light load

conditions, thus improving efficiency automatically. The

ISL6730A, ISL6730B, ISL6730C, ISL6730D can be shut down

by pulling the FB pin below 0.5V or grounding the BO pin. The

ISL6730C, ISL6730D have no skip mode.

• Small 10 Ld MSOP package

Applications

• Desktop computer AC/DC adaptor

• Laptop computer AC/DC adaptor

• TV AC/DC power supply

Two switching frequency options are provided. The ISL6730B,

ISL6730D switch at 62kHz, and the ISL6730A, ISL6730C

switch at 124kHz.

• AC/DC brick converters

100

95

V

I

+

V_LINE

V_OUT

90

85

80

75

70

65

60

ISL6730A, SKIP

ISL6730C

VCC

ISEN

GATE

GND

ICOMP

ISL6730

VIN

FB

COMP

BO

VREG

0

20

40

60

80

100

OUTPUT POWER (W)

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. PFC EFFICIENCY

TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6730

VERSION

Switching Frequency

Skip Mode

ISL6730A

124kHz

ISL6730B

62kHz

ISL6730C

ISL6730D

62kHz

No

124kHz

No

Yes-Fixed

August 8, 2013

FN8258.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Pin Configuration

ISL6730A, ISL6730B, ISL6730C, ISL6730D

(10 LD MSOP)

TOP VIEW

1

2

3

4

5

GATE

VCC

GND

ISEN

ICOMP

VIN

10

9

8

VREG

FB

7

BO

6

COMP

Pin Descriptions

PIN # I/O SYMBOL

DESCRIPTION

1

2

3

4

-

GND

ISEN

Ground pin. All voltage levels refer to this pin.

Current sense pin. The current through this pin is proportional to the inductor current.

I

I/O ICOMP Current error amplifier output pin.

I

VIN

BO

Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider from

the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the input current.

The phase lag is required to compensate the phase lead generated by the EMI filter.

5

I/O

This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will follow

the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R . The decoupling capacitor provides ripple

IS

filtering. When the voltage at the BO pin (V ) drops below brownout voltage threshold, the controller enters shutdown mode

BO

and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling threshold.

6

7

I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will slowly

ramp up the voltage of the COMP pin.

I

FB

Voltage feed back pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage. When

the FB pin voltage exceeds 104% of the reference voltage, overvoltage-protection is triggered and gate drive is disabled. When

the FB pin is below 10%, the device is put into shutdown mode. There is an internal pull-down current source for open loop

protection.

8

-

VREG Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND with

a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.

9

I

VCC

Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.

10

O

GATE

Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and 1.5A

source capability.

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6730AFUZ

6730A

6730B

6730C

6730D

-40 to +125

10 Ld MSOP

M10.118

ISL6730BFUZ

ISL6730CFUZ

ISL6730DFUZ

ISL6730AEVAL1Z

ISL6730BEVAL1Z

NOTES:

10 Ld MSOP

Evaluation Board

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page. For more information on MSL please see techbrief TB363.

FN8258.1

August 8, 2013

2

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Absolute Maximum Ratings

Thermal Information

VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V

GATE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V

VIN, BO, ISEN, FB and COMP to GND. . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6.3V

ESD Rating

Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . .2.5kV

Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD-C101E. . . . . . . . . . . . . . . . . 1kV

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Thermal Resistance (Typical)

MSOP Package (Notes 4, 5) . . . . . . . . . . . .

θ

(°C/W)

136.9

θ

(°C/W)

39.4

JA

JC

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to + 20V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. For θ , the "case temp" location is taken at the package top center.

JC

Electrical Specifications Operating Conditions: V = 15V, T = +25°C. Boldface limits apply over the operating temperature range,

CC

A

-40°C to +125°C.

MIN

MAX

PARAMETER

SUPPLY CURRENT

SYMBOL

TEST CONDITIONS

(Note 8)

TYP

(Note 8) UNITS

V

CC

Start Up Current

I

V

= 1V, V < V (ON)

CC CC

73

179

580

3.0

106

237

690

3.7

139

295

800

4.2

µA

mA

START

FB

Standby Current

I

= GND, V > V (ON)

CC CC

STDN

Skip Mode Current

Operating Current (Note 6)

VCC UVLO

I

= 2.5V, COMP = SKIP*0.25 +1V

CCSKIP

I

GATE is floating

CC

UVLO Rising Threshold

UVLO Falling Threshold

UVLO Threshold Hysteresis

REGULATOR VOLTAGE VREG

Overall Accuracy

V

9

6.7

-

10

7.5

2.5

11

8.3

-

V

CC(ON)

V

CC(OFF)

V

CC(HYS)

V

I

= 0 to -10mA, V = 15V, Load Capacitor = 47nF

5.1

30

5.4

50

5.6

70

V

REG

REG CC

Current Limit

mA

PWM CONVERTERS

Maximum Duty Cycle

f

= 124kHz for ISL6730A/C and

= 62kHz for ISL6730B/D

94.8

96.5

-

%

SW

OSCILLATOR

Free Running Frequency, ISL6730A/C

Free Running Frequency, ISL6730B/D

PWM Ramp Amplitude

T

= -40°C to +125°C, V = 0.6V

IN

98

114

47

107

125

54

116

136

61

kHz

V

A

T

= -40°C to +125°C, V = 2.5V

IN

A

T

= -40°C to +125°C, V = 0.6V

IN

A

T

= -40°C to +125°C, V = 2.5V

IN

57

64

71

A

V

1.33

1.46

1.59

m

GATE DRIVER

Gate Drive Pull-Down Resistance

Gate Drive Pull-Up Voltage Drop

V

= 15V, I

= 15mA

-

2.33

0.3

4.46

0.45

Ω

CC

GATE

= 9V, I

GATE

0.15

V

CC

FN8258.1

August 8, 2013

6

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Electrical Specifications Operating Conditions: V = 15V, T = +25°C. Boldface limits apply over the operating temperature range,

CC

A

-40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 8)

TYP

1.5

(Note 8) UNITS

Gate Drive Max. Sourcing/Sinking

Current

-

A

ns

V

Rise Time

C

= 2.2nF, V = 15V, Gate Voltage Rise Time from 10%

CC

-

34

12

62

O

to 90% of V

GC

Fall Time

C

= 2.2nF, V = 15V, Gate Voltage Fall Time from 10%

CC

57

O

to 90% of V

GC

Gate Clamp Voltage

V

10.5

13.5

GC

VOLTAGE REFERENCE

Reference Voltage

V

2.48

2.5

65

2.52

V

REF

Feedback Pin Pull-Down Current

Rising Threshold to Enable Converter

Falling Threshold to Disable Converter

Enable Hysteresis

I

-

nA

FB

FB_EN

FB_DIS

FB_Hys

280

190

-

300

202

100

320

214

-

mV

VOLTAGE ERROR AMPLIFIER

Error Amp Transconductance

ISource/Sink

Gmv

50

-

77

13

104

-

µA/V

µA

V

COMP Offset Voltage

V

0.95

0.58

1.01

0.64

1.07

0.75

COMP_OFF

COMP Soft-Start Enable Voltage

INPUT VOLTAGE SENSING

VIN Leakage Current

V

COMP_EN

-

9

-

nA

MULTIPLIER GAIN

GMUL

COMP = 2.5V, V = 1.0V, BO = 1.0V, I

IN

= 50µA

0.196

0.25

0.296

V/V

SEN

CURRENT ERROR AMPLIFIER

Current DC Gain

A

ΔI

/ΔI

ISEN

1.6

205

-

1.9

268

60

2

2.2

331

-

A/A

µA/V

µA

iDC

ICOMP

I = ±20µA

ICOMP

Error Amp Transconductance

ICOMP Source/Sink Current (Note 7)

Current Sensing Input Offset

Gmi

-3

7

mV

LIGHT LOAD EFFICIENCY ENHANCEMENT AND OVERPOWER PROTECTION

Skip Mode COMP Threshold

COMP Upper Limit

V

Applied for ISL6730A/B

1.32

3.53

2.5

1.36

3.85

2.83

88

1.4

4.17

3.16

89

V

SCMT

V

CUL

COMP Valid Range

V

-1V

V

CUL

FB Exit Threshold Voltage

V

Fraction of the set point (V

), I

REF ISEN

= 0µA, Applied for

87

%

FB_EXIT

ISL6730A/B

ISEN Exit Threshold Current

BROWNOUT DETECTION

Brownout Rising Threshold

Brownout Falling Threshold

OVERVOLTAGE PROTECTION

Overvoltage Protection

I

V

= 2.5V, Applied for ISL6730A/B

FB

-38

-29

-20

µA

SEN_EXIT

V

478

387

494

401

510

415

mV

BO_R

V

BO_F

V

Fraction of the set point (V

); ~1µs noise filter

REF

102.9

104.1

105.3

%

OVP

FN8258.1

August 8, 2013

7

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Electrical Specifications Operating Conditions: V = 15V, T = +25°C. Boldface limits apply over the operating temperature range,

CC

A

-40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

OVERCURRENT PROTECTION

Overcurrent Threshold

SYMBOL

TEST CONDITIONS

(Note 8)

TYP

(Note 8) UNITS

I

-197

-177

-159

µA

OC

THERMAL SHUTDOWN

Shutdown Temperature (Note 7)

Thermal Shutdown Hysteresis (Note 7)

NOTES:

-

160

25

-

°C

6. This is the V current consumed when the device is active but not switching. Does not include gate drive current.

CC

7. Limits should be considered typical and are not production tested.

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Typical Performance Curves

101.0

100.50

100.25

100.00

100.5

100.0

99.5

V

= 2.5V

IN

99.75

99.50

V

= 0.6V

80

IN

99.0

-40

-20

0

20

40

60

80

100

120 140

-40

-20

0

20

40

60

100

120 140

TEMPERATURE (°C)

FIGURE 3. FEEDBACK ACCURACY

FIGURE 4. F

vs TEMPERATURE, V = 15V

CC

SW

105

100

95

101

100

99

90

85

98

80

97

75

0

0.5

1.0

1.5

(V)

2.0

2.5

3.0

-40

-20

0

20

40

60

80

100

120 140

V

TEMPERATURE (°C)

IN

FIGURE 5. A

vs TEMPERATURE

FIGURE 6. F

vs V T = +25°C

IN, A

IDC

SW

FN8258.1

August 8, 2013

8

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Typical Performance Curves (Continued)

102

101

100

102

101

100

99

I

START

HYSTERSIS

I

CC

(GATE FLOATING)

UP

THRESHOLD

99

98

DOWN

THRESHOLD

98

-40

-20

0

20

40

60

80

100

120 140

-40

-20

0

20

40

60

80

100

120 140

TEMPERATURE (°C)

FIGURE 8. V SUPPLY CURRENT vs TEMPERATURE

CC

FIGURE 7. UVLO THRESHOLDS vs TEMPERATURE

112

110

108

106

104

102

100

98

FALL TIME

RISE TIME

96

-40

-20

0

20

40

60

80

100

120 140

TEMPERATURE (°C)

FIGURE 9. GATE DRIVER ABILITY vs TEMPERATURE (LOAD = 2.2nF)

FN8258.1

August 8, 2013

9

ISL6730A, ISL6730B, ISL6730C, ISL6730D

EMI CHOKE

Functional Description

VCC Undervoltage Lockout (UVLO)

The ISL6730A, ISL6730B, ISL6730C, ISL6730D start

automatically once the voltage at VCC exceeds the UVLO

threshold.

V

C

LINE

C

F3

F2

L

m

D

F1

Shutdown

D

F2

When the VFB pin is below 0.2V, the controller is disabled and

the PWM output driver is tri-stated. When disabled, the IC power

will be reduced. During shutdown, the COMP pin is discharged to

GND and the controller is disabled. The Over-Temperature

Protection (OTP) is still alive to prevent the controller from

starting up in a high temperature ambient condition.

R

IN2

VIN

BO

R

C

IN1

BO

In the event that the FB pin is disconnected from the feedback

resistors, the FB pin is pulled to ground by an internal current

FIGURE 10. INPUT VOLTAGE SENSING SCHEMATIC

source I . When the FB pin voltage drops below 0.2V, the gate

driver is disabled. The ISL6730A, ISL6730B, ISL6730C,

ISL6730D enters shutdown mode.

FB

The BO pin also utilizes the VIN resistor divider for voltage

sensing. Set the resistor divider ratio to satisfy the brownout

requirement.

Soft-Start

First, calculate the resistor divider ratio, K_BO.

V

The COMP pin is released once the soft-start operation begins. A

13µA current sources out to the RC network connected from the

COMP pin until the FB pin voltage reaches 90% of the reference

voltage.

BORMAX

-------------------------------------------

K

=

(EQ. 1)

BO

V

– 2V

F

RMSmin

Where V is the forward voltage drop of the bridge rectifier and

F

the voltage drop of D

D .

F1; F2

Switching is inhibited when the COMP pin voltage is below 1V.

When the COMP pin reaches 1V, the current error amplifier and

the gate driver are activated and the converter starts switching.

Then, select the R

based on the highest reasonable resistance

IN2

value. Then select the R

based upon the desirable minimum

IN1

RMS value of the line voltage for the PFC operation.

During UVLO, Brownout and Shutdown, the COMP is pulled to the

ground.

K

BO

(EQ. 2)

--------------------

R

=

⋅ R

IN1

IN2

1 – K

BO

Input Voltage Sensing

Inductor Current Sensing

The current sensing of the converter has two purposes. One is to

force the inductor current to track the input semi-sinusoidal

waveform. The other purpose is for overcurrent protection. Refer to

Figure 11 for the current sensing scheme. The sensed current I

is in proportion to the inductor current, I as described in

The VIN pin is needed to sense the rectified input voltage. The

sensed semi-sinusoidal waveform is needed to shape inductor

current, which helps achieves unity power factor. At the same

time, the voltage on the VIN pin is used to generate the negative

capacitive element at the input. This will cancel the input filter

CS

L

capacitor, C . Canceling the effect of C will increase the

F

Equation 3.

displacement power factor and alleviate the zero crossing

distortion, which is related to the distortion power factor.

R

1

2

CS

(EQ. 3)

-- ---------------

I

=

⋅

⋅ I

CS

L

R

SEN

where:

is the current sensing resistor with low value in the return

R

CS

path to the bridge rectifier.

R

is the current scaling resistor connected between ISEN to

SEN

the R

.

CS

FN8258.1

August 8, 2013

10

ISL6730A, ISL6730B, ISL6730C, ISL6730D

BRIDGE RECTIFIER

V

L

F

I

EMI CHOKE

VOUT

COUT

L

Q1

V

LINE

C

F1

F3

F2

CF1

L

m

RCS

FIGURE 12. TYPICAL PFC INPUT FILTER CIRCUIT

CURRENT

MIRROR

BRIDGE RECTIFIER

EMI CHOKE

L

F

2:1

I

RSEN

ISEN

CS

V

LINE

C

F3

C

F1

F2

L

m

I

> 0.5 I

CS

OC

FIGURE 13. LOW COST PFC INPUT FILTER CIRCUIT

FIGURE 11. INDUCTOR CURRENT SENSING SCHEME

For applications where the output power is above 500W, the

negative capacitance helps to improve the power factor

dramatically. Please refer to Table 2 for the recommended

A high value R renders more accurate current sensing. It is

CS

recommended to use the R to render 120mV peak voltage at

CS

the maximum line voltage during full load condition.

filtering capacitor to be placed after the bridge rectifier, C

.

F1

120mV ⋅ V

⋅ η

RMSMAX

TABLE 2.

(EQ. 4)

-------------------------------------------------------------

>

R

CS

2 ⋅ P

Omax

C

Po < 100W

0.68

100W < Po < 500W Po > 500W

0.33 0.22

F1

Where η is the efficiency of the converter at the maximum line

Typical

input with full load.

C(µF)/100W

Since the R sees the average input current, high value R

CS CS

Additional C may be used to accommodate the use of small

F1

boost inductor or to eliminate the differential mode filter inductor

as long as the equipment meets the power factor or goal.

generates high power dissipation on the R . Use a reasonable

CS

R

according to the resistor power rating. The worst-case power

CS

dissipation occurs at the input low line when input current is at

its maximum. Power dissipation by the resistor is:

The equivalent negative capacitor is a function of the input

2

(EQ. 5)

P

= (I

)

⋅ R

CS

voltage divider ratio, K , the current sensing gain and current

BO

RCS

RMSMAX

compensation error integration gain.

where:

Adjusting the negative Ceq can be achieved by adjusting the

current compensation network.

I

is the maximum input RMS current at the minimum

RMSMAX

input line voltage, V

.

RMSmin

Frequency Modulation

Select the R

SEN

according to the peak current limit requirement.

The ISL6730A, ISL6730B, ISL6730C, ISL6730D can further

reduce EMI filter size by lowering the differential noise power

density. The reduction is achieved by switching frequency

modulation.

The resistor is sized for an overload current 25% more than the

peak inductor peak current.

Negative Input Capacitor Generation (Patent

Pending)

The patent pending negative capacitor generation capability of

the ISL6730A, ISL6730B, ISL6730C, ISL6730D allows the

The frequency varies with the VIN pin. The switching frequency

reaches the peak value when the VIN pin voltage is 2V as shown

in Figure 6. The peak value of ISL6730A/C is 124kHz, and the

ISL6730B/D is 62kHz.

capacitor C to be moved from before the bridge rectifier

F2

(Figure 12) to after the bridge rectifier (Figure 13). Thus, a

Output Voltage Regulation

smaller lower cost C can be used. The change in topology

F2

reduces the size of the EMI filter. Furthermore, C can be

F1

The output voltage is sensed through a resistor divider. The

middle point of the resistor divider is fed to the FB pin. The

resistor divider ratio sets the output voltage. The

increased thus decreasing the size of L (Figure 13).

F

transconductance error amplifier generates a current in

proportion to the difference between the FB pin and the 2.5V

internal reference. The PFC is stabilized by the compensation

network that is connected from the COMP pin to the ground.

The voltage of the COMP sets the input average power by

determining the amplitude of the current reference. To keep the

FN8258.1

August 8, 2013

11

ISL6730A, ISL6730B, ISL6730C, ISL6730D

harmonic distortion minimum, it is desirable to set the control

bandwidth much lower than twice of the line frequency. The

recommended voltage loop bandwidth is 10Hz.

Overvoltage Protection

If the voltage on the FB pin exceeds the reference voltage by about

4%, the gate driver is turned off. The controller resumes normal

operation after the FB pin drops below reference voltage.

During start-up, the compensation capacitors and the charging

current from the error amplifier sets the input power increase

rate. Thus, soft-start is achieved.

Over-Temperature Protection

The ISL6730A, ISL6730B, ISL6730C, ISL6730D is protected

against over-temperature conditions. When the junction

temperature exceeds +160°C, the PWM shuts down. Normal

operation is resumed when the junction temperature decreases

below +135°C.

The COMP is discharged during shutdown and fault conditions.

Light Load Efficiency Enhancement

For PC, adaptor and TV applications, it is desirable to achieve

high efficiency at light load conditions and low standby current.

The ISL6730A, ISL6730B can enter light load efficiency mode

automatically.

Application Guidelines

Layout Considerations

The voltage error amplifier output, COMP, is an indicator of the

average input power level. The controller compares the V(COMP)

and V(SKIP). If V(COMP)-1V is less than V(SKIP)*0.25, the PFC

controller stops gate switching and the COMP pin voltage is

clamped to V(SKIP)+0.6V. ISL6730A/B use a fixed V(SKIP), which

is 1.4V; for ISL6730C/D, the SKIP function are disabled.

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using wide,

short printed circuit traces. The critical components should be

located as close together as possible using ground plane

construction or single point grounding.

The controller exits skip mode when V drops to 88% (typical) of

FB

the reference voltage or when the sensed returned current

exceeds 29µA.

Figure 14 shows the critical power components; Q , D and C_OUT

.

1

Protection Circuits

Input Brownout, BO Protection

Brownout occurs when there is a drop in the line voltage. The BO

pin is a dual function pin. The BO pin detects the brownout

condition and shuts down the gate driver and controller. During

normal operation, the BO pin is used to compensate the effect of

the input line voltage change on the voltage loop. To keep the

harmonic distortion low, the corner frequency formed by the R_BO

and C_BOshould be lower than 6Hz.

To minimize the voltage overshoot, the interconnecting wires

indicated by heavy lines should be part of the ground or the

power plane in a printed circuit board. The components shown in

Figure 14 should be located as close together as possible. Please

note that the capacitors C

and C each represent numerous

VCC

O

physical capacitors. Locate the ISL6730A, ISL6730B, ISL6730C,

ISL6730D within 2 inches of the MOSFET, Q . The circuit traces

1

for the MOSFETs’ gate and source connections from the

ISL6730A, ISL6730B, ISL6730C, ISL6730D must be sized to

handle up to 1.5A peak current.

D

The BO pin is the output of the average voltage of the rectified

voltage. The PFC controller is turned off when the BO pin drops

below 0.4V. This protects the PFC power stage to enable

operation at or below brownout condition for long periods of

time. The controller resumes operation when the BO pin returns

to 0.5V.

L

C

OUT

Q

1

The BO pin is usually connected to GND through a capacitor, C_BO

.

To avoid distortion on the VIN pin, select C so that:

BO

GATE

C

» 0.22μF

(EQ. 6)

BO

VCC

C

Overcurrent Protection

VCC

The peak current limiting function prevents the inductor from

saturation. The gate driver turns off when the current goes above

the current limit.

FIGURE 14. CRITICAL CURRENT POWER COMPONENTS

Overpower Protection

The overpower protection is implemented by limiting the COMP

pin voltage higher than 3.85V (typical).

Component Selection Guidelines

A 300W, universal input, PFC converter design is provided for

demonstration. The design method is for a continuous current

mode power factor correction boost converter with the

ISL6730B/D. The switching frequency is 62kHz.

FN8258.1

August 8, 2013

12

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Table 3 shows the design parameters.

Select the bridge diode using Equation 15 and sufficient reverse

breakdown voltage. Assuming the forward voltage, V , is 1V

across each rectifier diode. The power loss of the rectifier bridge

can be calculated:

F,BR

TABLE 3. CONVERTER DESIGN PARAMETERS

PARAMETER

VLINE

CONDITIONS

MIN

85

TYP MAX UNIT

115 265 VAC

P

= 2 • V

• I

F, BR INAVE(MAX)

(EQ. 15)

BR

FLINE

47

63

Hz

W

(EQ. 16)

P

= 2 • 1V • 3.5A = 7W

BR

P

T

Maximum Output Power

Hold Up Time

300

OMAX

INPUT CAPACITOR SELECTION

20

ms

%

HOLD

Refer to Table 2 for the recommended input filter capacitor value.

Efficiency

VLINE = 115VAC

92

0.33

100

(EQ. 17)

-----------

= 0.99μF

C

= 300W •

F1

BOOST INDUCTOR SELECTION

This is the recommended capacitor used after the diode bridge.

For better power factor, less capacitance can be used. To lower

the input filter inductor size, more capacitance can be used.

First, calculate the maximum input RMS current, I

INMAX.

P

OMAX

(EQ. 7

-----------------------------------

I

=

INMAX

η • V

RMSmin

Two 0.47µF capacitors in parallel are used for C

.

F1

Where η is the converter efficiency at V

. PF is the power

(EQ. 8)

RMSmin

BOOST DIODE SELECTION

factor at V

RMSmin.

The boost diode loss is determined by the diode forward voltage

300W

0.92 • 85V

---------------------------

= 3.84A

I

=

INMAX

drop, V and the output average current. The maximum output

F

current is:

Assuming the current is sinusoidal and the peak to peak ripple at

line is 40%.

P

OMAX

--------------------

I

=

(EQ. 18)

(EQ. 19)

OUT(max)

V

OUT

The boost inductor, L , is given by the following equation:

BST

300W

---------------

I

= 0.77A

2 • V

OUT(max)

2V

⎛

⎞

⎟

⎠

390V

RMSmin

(EQ. 9)

---------------------------------------------------------------

---------------------------------------

L

≥

• 1 –

⎜

BST

V

0.4 • F

• 2 • I

⎝

OUT

sw

INMAX

The forward power loss on the diode is:

(EQ. 20)

(EQ. 21)

P

= I

• V

OUT(max) F

FD

85V

-----------------------------------------------------

2 • 85V

390V

⎛

⎞

⎠

-----------------------

L

≥

• 1 –

= 617μH

(EQ. 10)

BST

⎝

0.4 • 62kHz • 3.84A

P

= 0.77A • 1.85V = 1.42W

FD

The peak current of the inductor is the sum of the average peak

inductor current and half of the peak to peak ripple current.

Select and design the boost inductor as given by Equation 11.

The ISL6730A, ISL6730B, ISL6730C, ISL6730D provides peak

current limit function that can prevent the boost inductor

saturation. Assuming 25% margin is given to the OCP threshold,

select and design the boost inductor with saturation current

given by Equation 11 with 25% more.

The IDD03E60 part is selected.

The reverse recovery loss on the diode can be calculated. The

Q

is found from the diode datasheet. Q = 220nC when

RR

I = 3.5A.

F

The reverse recover loss on the diode can be estimated:

1

4

(EQ. 22)

(EQ. 23)

--

P

=

• Q

• V

• F

OUT

RRD

RR

sw

0.4

⎛

⎞

⎠

(EQ. 11)

-------

I

=

2 • I

• 1 +

INMAX

1

LPeak

⎝

2

--

P

=

• 220nC • 390V • 62kHz = 1.33W

4

0.4

2

The total power loss on the diode is:

⎛

⎞

(EQ. 12)

-------

I

=

2 • 3.88A • 1 +

= 6.5A

LPeak

⎝

⎠

(EQ. 24)

P

= P

+ P

= (1.42 + 1.35)W = 2.75W

RRD

D

FD

INPUT RECTIFIER

The maximum average input current is calculated:

MOSFET POWER DISSIPATION

2 • 2 • I

The power dissipation on the MOSFET is from two different types

of losses; the condition loss and the switching loss.

INMAX

(EQ. 13)

(EQ. 14)

-----------------------------------------

I

=

INAVE(max)

π

For the MOSFET, the worst case is at minimum line input voltage.

2 • 2 • 3.88A

-------------------------------------

= 3.5A

First, the drain to source RMS current is calculated:

π

V

8

3π

2

RMSmin

---------- -------------------------

I

= I

1 –

INMAX

•

(EQ. 25)

(EQ. 26)

DS(max)

V

OUT

8

2

85V

---------- -------------

I

= 3.88A 1 –

•

= 3.3A

DS(max)

3π 390V

FN8258.1

August 8, 2013

13

ISL6730A, ISL6730B, ISL6730C, ISL6730D

The MOSFET, SPP20N60C3 is selected.

2

(4πf

⋅ C

⋅ ESR) + 1

OUT

2

(EQ. 27)

(EQ. 28)

line

(EQ. 38)

(EQ. 39)

P

= I

• R

DS(on)

------------------------------------------------------------------------------

⋅

OUT(max)

V

= I

COND

DS(max)

Opp

(4πf

) ⋅ C

⋅ 0.8

OUT

line

2

P

= 3.3A • 0.3Ω = 3.27W

COND

2

(4π ⋅ 50Hz ⋅ 270μF ⋅ 0.77Ω) + 1

-------------------------------------------------------------------------------------------

= 0.77A ⋅

= 6.6V

The switching loss of the MOSFET consists of three parts: the

turn-on loss, the turn-off loss and the diode reverse recovery loss.

(4π ⋅ 50Hz) ⋅ 270μF ⋅ 0.8

The minimum OVP threshold is 103% of the nominal output

value. The maximum output peak to peak ripple should be less

From the MOSFET datasheet, the typical switching losses curves

are provided.

than 6% of the nominal value, which is 23.4V

.

P-P

When R = 3.6Ω, I = 6A, E = 0.015mJ, E

ON

= 0.007mJ.

G

D

OFF

CURRENT SENSING RESISTORS

The switching loss due to transition is calculated:

Please refer to Equation 4 for calculation of the current sensing

resistor R

(EQ. 29)

(EQ. 30)

P

= (E

+ E

) • F

OFF

sw

SW

ON

.

CS

= (0.015mJ + 0.007mJ) • 62kHz = 1.36W

120mV ⋅ 265V ⋅ 0.92

(EQ. 40)

------------------------------------------------------

= 0.069Ω

R

≥

CS

2 ⋅ 300W

The diode reverse recovery incurs additional power loss on the

MOSFET. This loss can be estimated as:

While a large R renders better current sensing accuracy, larger

CS

(EQ. 31)

P

= Q

• V

• F

OUT

sw

R

also incurs higher power dissipation. Select R from

CS

RR

available standard value resistors to determine the sense

resistor.

This loss is also related the di/dt during the MOSFET turn-on. The

di/dt can be found out from the MOSFET datasheet. At

(EQ. 41)

R

= 0.068Ω

CS

R

= 3.6Ω, the turn-on di/dt is 4000A/µs. From the Typical

G

Reverse Recovery Charge curve at T = +125°C, the

The maximum power dissipation on the R occurs at low line

CS

and full load condition. The maximum power dissipation is

J

Q

= 220nC when I = 3.5A.

RR

F

calculated:

(EQ. 32)

(EQ. 33)

P

= 220nC • 390V • 62kHz = 5.32W

RR

2

(EQ. 42)

(EQ. 43)

P

= I

• R

CS

RCSMAX

INMAX

2

THE TOTAL LOSS ON THE MOSFET

= 3.88A • 0.068Ω = 1.023W

P

+ P

SW

= 3.27W + 1.36W + 5.32W = 9.95W

RCSMAX

COND

RR

The resistor, R

Equation 3, R

sets the overcurrent protection limit. From

should be greater than:

SEN

OUTPUT CAPACITOR SELECTION

The output capacitor, C , is required to hold the output above

OUT

R

• I

• (1 + 0.25)

CS LPeak

(EQ. 44)

300V during one line cycle. For capacitors with 20% tolerance,

the tolerance should be taken into consideration. Thus, the

output capacitance should be greater than:

-------------------------------------------------------------------

≥

R

SEN

2 • 0.5 I

OC

Where |x| stands for the ABS(x) function.

2 ⋅ T

⋅ P

OMAX

HOLD

1

(EQ. 34)

---------------------------------------------------- -----------------

C

≥

⋅

OUT

2

1 – 0.2

0.068Ω • 6.6A • 1.25

V

– V

HOLD

(EQ. 45)

OUT

-------------------------------------------------------

≥ = 3.117kΩ

R

SEN

2 • 90μA

2 ⋅ 20ms ⋅ 300W

---------------------------------------------

(EQ. 35)

C

≥

⋅ 1.25 = 242μF

Select R

from available standard value resistors, the selected

OUT

SEN

is 3.16kΩ.

2

(390) – (300V)

R

SEN

Calculate the ripple RMS current through the capacitor:

CURRENT LOOP COMPENSATION

V

The input current shaping is achieved by comparing the sensed

current signal to the sensed input voltage signal. The current

error amplifier (Gmi), together with the current compensation

network, adjusts the duty cycle so that the inductor current

traces the sensed rectified voltage. Thus, unity power factor is

achieved.

8 2

3π

OUT

(EQ. 36)

(EQ. 37)

---------- -------------------------

I

= I

•

– 1

CORMS(max)

OUT(max)

V

RMSmin

8

2

390V

---------- -------------

– 1 = 1.635A

I

= 0.77A

•

3π

85V

Select the proper capacitor according to the hold time and ripple

RMS current requirement. The actual capacitance is 270µF.

The compensation network consists of the Trans-Conductance

error amplifier (Gmi) and the impedance network (Z

The

ICOMP).

goal of the compensation network is to provide a closed loop

transfer function with the sufficient 0dB crossing frequency

It is important to make sure the output peak-to-peak ripple is

less than the minimum OVP threshold as specified in the

“Electrical Specifications” table on page 6. The ESR at 2 times of

the line frequency of the capacitor is found in the capacitor

datasheet. The ESR of the output capacitor is 770mΩ at 100Hz.

(f

) and adequate phase margin. Phase margin is the

and 180°. The

0dB

difference between the open loop phase at f

0dB

following equations relate the compensation network’s poles,

zeros and gain to the components (R , C and C ) in Figure 15.

ic ic ip

FN8258.1

August 8, 2013

14

ISL6730A, ISL6730B, ISL6730C, ISL6730D

The cross over frequency of the current loop should be set

V

I

OUT

between 2kHz to 100kHz. At cross over frequency, the transfer

function from duty cycle to inductor current is well approximated

by Equation 48:

L

Q

C

1

OUT

C

F1

V

OUT

(EQ. 48)

---------------------

G

(s)=

id

L

⋅ s

BST

R

CS

It is recommended to set the cross over frequency from 1/10 to

1/6 of the switching frequency with phase margin of 60°. A high

frequency pole is set at 1/2 of the switching frequency for ripple

CURRENT

MIRROR

2:1

I

R

CS

SEN

filtering. In this example, we set the cross over, F at 1/6 of the

C

switching frequency.

F

C

ISEN

--------------------------------------------------------

F =

Z

(EQ. 49)

F

⎛

⎜

⎝

⎞

⎟

⎠

⎞

M

C

-------

tan atan

+ Φ

⎜

⎟

F

P

⎝

⎠

ICOMP

Where F = F /6 = 10.3kHz, Φ is the phase margin, which is

C

S

M

I

REF

R

IS

60°. F = F /2 = 31kHz.

P

S

Gmi

R

C

ic

Thus, the current loop compensation zero is:

C

ip

(62KHz) ⁄ 6

------------------------------------------------------------

F =

= 2.12kHz

(EQ. 50)

(EQ. 51)

Z

2

⎝ ⎠

6

⎛

⎛ ⎞

⎞

--

tan atan

+ 60deg

⎝

⎠

FIGURE 15. INDUCTOR CURRENT SENSING SCHEME

The total compensation capacitance is calculated:

2

FROM DUTY TO

⎛

⎜

⎝

⎞

⎟

⎠

V

A

R

CS

1 + (f ⁄ f )

⎛

⎜

⎝

⎞

⎟

⎠

OUT

iDC

INDUCTOR CURRENT

c

z

-------------------------------------- ------------- ---------------

L

80

C

+ C

=

ic

⋅

------------------------------

ip

2

V

R

SEN

1 + (f ⁄ f )

m

⋅ (2πf )

c

p

BST

c

40

20

COMPENSATION

GAIN

(EQ. 52)

(EQ. 53)

C

+ C = (19.8)nF

ip

ic

0

F

P

F

Z

f

-20

-40

-60

-80

-100

z

----

C

= (C + C

)

iC

ip

f

p

OPEN LOOP

GAIN

The value of the noise filtering capacitor is:

2.12kHz

31kHz

(EQ. 54)

(EQ. 55)

(EQ. 56)

CURRENT GAIN

MODULATOR GAIN

----------------------

= 1.35nF

C

= 14.9nF ⋅

ip

The value of C is:

ic

100

1k

10k

100k

C

= 19.8nF – 1.35nF = 18.4nF

FREQUENCY (Hz)

ic

FIGURE 16. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN

The value of R is:

ic

1

-----------------------------------

F =

----------------------------------------------------------

R

=

= 4.11kΩ

(EQ. 46)

(EQ. 47)

Z

ic

2π • R • C

2π ⋅ 2.12kHz ⋅ 18.4nF

ic

Select the R value from the standard value, we have:

C

1

---------------------------------------------------

=

F

P

C

• C

ic

+ C

ic

R

= 4.02kΩ, C = 18nF, C = 1.2nF. Figure 17 shows the actual

ic ip

ip

ic

bode plot of current loop gain.

-----------------------

•

2π • R

ic

C

ip

Use the following guidelines for locating the poles and zeros of

the compensation network.

FN8258.1

August 8, 2013

15

ISL6730A, ISL6730B, ISL6730C, ISL6730D

For example, C = 0.68µF, C = 0.94µF, using the low cost EMI

F2 F1

80

60

40

20

0

10.5kHz

filter shown in Figure 13. When V

= 230VAC, f = 50Hz,

LINE

P

= 60W.

O

Assuming 95% efficiency under the above test condition, the

resistive component, which is in phase to voltage:

P

o

(EQ. 62)

--------------------------------

I =

= 0.275A

a

V

⋅ 0.95

LINE

-20

The reactive current through the input capacitors:

180

10.5kHz

(EQ. 63)

(EQ. 64)

I = V

• (2π ⋅ f

) • (C + C ) = 0.117A

LINE F1 F2

c

LINE

135

90

45

0

Thus, the displacement power factor is:

I

60

45

a

-----------------------------------

PF

=

= 0.92

DIS

2

(I ) + (I )

a

c

3

10

100

1x10

FREQUENCY (Hz)

1x10

The reactive current generated by the equivalent negative

capacitor is:

FIGURE 17. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN

(EQ. 65)

I

= V

• (2π ⋅ f

) • (C

) = 0.045A

NEG

cneg

LINE

INPUT VOLTAGE SETTING

First, set the BO resistor divider gain, K according to

BO

Equations 1 and 2.

With the equivalent negative capacitor, the total reactive current

reduces to:

(EQ. 66)

Assuming the converter starts at V

= 80V

, then the BO

RMS

LINE

I

– I

= 0.072A

cneg

c

resistor divider gain, K should be:

BO

0.5V

80V – 2V

(EQ. 57)

------------------------

K

=

= 0.00641

The displacement power factor increases to:

BO

I

a

(EQ. 67)

-------------------------------------------------------

PF

=

= 0.967

DIS

In this design, two 3.3MΩ resistors in series are used for R

.

2

IN2

(I ) + (I – I )

cneg

a

c

So, R

is calculated:

IN1

0.00641

1 – 0.00641

(EQ. 58)

VOLTAGE LOOP COMPENSATION

------------------------------

⋅ (6.6MΩ) = 42.6kΩ

R

=

IN1

The average diode forward current can be approximated by:

P

in

(EQ. 68)

Using resistor from the standard value, R

IN1

= 43kΩ, the actual

---------------

I

=

D(ave)

V

OUT

K

is calculated:

BO

R

IN1

+ R

IN2

(EQ. 59)

Assuming the input current traces the input voltage perfectly. The

--------------------------------

K

=

= 0.00647

BO

R

input power is in proportion to (V

- 1V).

IN1

COMP

⎛

⎜

⎞

⎟

⎠

R

1

0.25

SEN

NEGATIVE INPUT CAPACITOR GENERATION

-------------------------------------- --------------- -----------------------------------------------

I

=

•

• Δ

D(ave)

COMP

⎜

⎝

2

R

⋅ 0.5 ⋅ R

V

OUT

CS

IS

((2 2) ⁄ π) ⋅ K

The ISL6730A, ISL6730B, ISL6730C, ISL6730D generates an

equivalent negative capacitance at the input to cancel the input

filter capacitance. Thus, more input capacitors can be used

without reducing the power factor.

BO

(EQ. 69)

Where Δ

COMP

is the V - 1V. 1V is the offset voltage.

COMP

R

is the internal current scaling resistor. R = 14.2kΩ.

IS

The input equivalent negative capacitance is a function of the

current sensing gain, BO resistor divider gain and the

compensation components.

A

(EQ. 70)

---

I

= 0.598 • Δ

D(ave)

COMP

V

R

SEN

⎛

⎜

⎝

⎞

m

(EQ. 60)

--------------- -------------------------

C

=

K

⋅ 0.8 –

(C + C )

ip

⎟

NEG

BO

ic

V

R

A

⎠

OUT

CS iDC

1.5

3.16k

⎛

⎝

⎞

--------- ---------------------------

C

=

0.00647 ⋅ 0.8 –

(18nF + 1.2nF) = 0.62μF

NEG

⎠

390 0.068 ⋅ 1.9

(EQ. 61)

This equivalent negative capacitor cancels the input filter

capacitor required for EMI filtering. Therefore, the displacement

power factor significantly improves.

FN8258.1

August 8, 2013

16

ISL6730A, ISL6730B, ISL6730C, ISL6730D

The zero, F is calculated:

Zv

VOUT

F

CV

2.5V

(EQ. 76)

(EQ. 77)

-----------------------------------------------------------------------------

F

=

Zv

tan(Φ + atan(F

⁄ (F )))

Pv

m

CV

R

FB2

FB

8Hz

------------------------------------------------------------------------------------------------

= 1.15Hz

F

=

Zv

tan(60deg + atan((8Hz) ⁄ (20Hz)))

Gmv

R

Then the total capacitance used for compensation is calculated:

FB1

I

FB

2

G

(i • (2πF )) • G

• Gmv

DIV

(F

⁄ F

)

ZV

+ 1

PS

CV

------------------------------------------------------------------------------------------

• --------------------------------------------

C

+ C

=

vp

vc

2

(2πF

)

CV

(F

⁄ F

) + 1

CV

PV

COMP

(EQ. 78)

(EQ. 79)

Rvc

Cvc

Thus, the total compensation capacitance is:

Cvp

C

+ C

= 1829nF

vp

vc

F

ZV

(EQ. 80)

(EQ. 81)

----------

C

= 1829nF •

= 105nF

FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION

vp

F

PV

Thus, the transfer function from V

COMP

to V is:

OUT

C

R

= 1829nF – 105nF = 1724nF

vc

V

(s)

I

1

OUT

D(ave)

(EQ. 71)

(EQ. 72)

-----------------------

--------------- --------------------

G

(s)=

=

⋅

PS

Δ

C

⋅ s

Δ

COMP

1

COMP

O

(EQ. 82)

------------------------------------------

=

= 81.2kΩ

vc

2 ⋅ π ⋅ F ⋅ C

ZV

VC

I

⎛

⎜

⎝

⎞

1

0.598

D(ave)

------------------ --------------------

---------------

=

G

(s)=

⋅

⎟

PS

Choose components from the standard values. We have

C

⋅ s

Δ

C ⋅ s

⎠

O

COMP

O

C

= 100nF, C = 1500nF, R = 82.5kΩ. The actual bode plot

VP

VC VC

is shown in Figure 20.

As shown in Figure 18, the voltage loop gain is:

60

40

20

0

(EQ. 73)

(EQ. 74)

G

(s)= G (s) • G

• gmv • Z

(s)

COMP

VLOOP

PS

DIV

The output feedback resistor divider gain, G

is:

DIV

V

REF

---------------

G

=

DIV

V

0

OUT

-20

-40

The compensation gain uses external impedance networks as

shown in Figure 18, Z

(s) is given by:

COMP

R

• C • s + 1

vc

1

vc

90

-------------------------------------- ------------------------------------------------------------

Z

(s)=

•

(EQ. 75)

COMP

(C + C ) ⋅ s

R

• C • C

vc vc vp

vc

vp

75

60

-----------------------------------------

• s + 1

C

+ C

vp

vc

45

30

15

The targeted cross over frequency, F is 8Hz. The high frequency

CV

pole, F is required in order to reject the 2 time line frequency

Pv

component. F = 20Hz. The targeted phase margin is 60°.

Pv

0

1

3

F

1x10

10

100

Zv

100

80

FREQUENCY (Hz)

F

Pv

CV

FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN

60

Gmv*Z

(s)

COMP

40

G

(s)

PS

20

0

G

(s)

VLOOP

-20

-40

-60

G

DIV

1

10

100

FREQUENCY (Hz)

1k

FIGURE 19. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN

FN8258.1

August 8, 2013

17

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that

you have the latest revision.

DATE

REVISION

FN8258.1

FN8258.0

CHANGE

Added electronic specifications to parts ISL6730B/D and made necessary changes throughout document.

Initial Release.

August 8, 2013

February 26, 2013

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal

computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting

www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at

http://www.intersil.com/en/support/qualandreliability.html#reliability

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8258.1

August 8, 2013

18

ISL6730A, ISL6730B, ISL6730C, ISL6730D

Package Outline Drawing

M10.118

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

Rev 1, 4/12

5

3.0±0.05

A

DETAIL "X"

D

10

1.10 MAX

SIDE VIEW 2

0.09 - 0.20

4.9±0.15

3.0±0.05

5

0.95 REF

PIN# 1 ID

1

2

0.50 BSC

B

GAUGE

PLANE

TOP VIEW

0.25

3°±3°

0.55 ± 0.15

DETAIL "X"

0.85±010

H

C

SEATING PLANE

0.10 C

0.18 - 0.27

0.10 ± 0.05

0.08 C A-B D

M

SIDE VIEW 1

(5.80)

NOTES:

1. Dimensions are in millimeters.

(4.40)

(3.00)

2. Dimensioning and tolerancing conform to JEDEC MO-187-BA

and AMSEY14.5m-1994.

3. Plastic or metal protrusions of 0.15mm max per side are not

included.

(0.50)

4. Plastic interlead protrusions of 0.15mm max per side are not

included.

5. Dimensions are measured at Datum Plane "H".

6. Dimensions in ( ) are for reference only.

(0.29)

(1.40)

TYPICAL RECOMMENDED LAND PATTERN

FN8258.1

August 8, 2013

19


型号：	ISL6730AEVAL1Z
厂家：	Intersil
描述：	Power Factor Correction Controllers
文件：	总19页 (文件大小：420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6730AEVAL1Z [INTERSIL]

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