ISL6622BIBZ [INTERSIL]
VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers; VR11.1兼容同步整流降压MOSFET驱动器型号: | ISL6622BIBZ |
厂家: | Intersil |
描述: | VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers |
文件: | 总11页 (文件大小:254K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6622B
®
Data Sheet
March 19, 2009
FN6602.1
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
The ISL6622B is a high frequency MOSFET driver designed
to drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. The advanced
PWM protocol of ISL6622B is specifically designed to work
with Intersil VR11.1 controllers and combined with
N-Channel MOSFETs, form a complete core-voltage regulator
solution for advanced microprocessors. When ISL6622B
detects a PSI PWM protocol sent by an Intersil VR11.1
controller, it activates Diode Emulation (DE) operation;
otherwise, it operates in normal Continuous Conduction
Mode (CCM) PWM mode.
• Integrated LDO with Selectable Lower Gate Drive Voltage
for Light Load Efficiency Optimization
• 36V Internal Bootstrap Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Operation
• Diode Emulation for Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 3A Sinking Current Capability
In the 8 Ld SOIC package, the ISL6622B drives the upper
gate to 12V while the lower drive voltage is fixed at 5.75V. The
10 Ld DFN part offers more flexibility: the upper gate can be
driven from 5V to 12V via the UVCC pin, while the lower gate
has a resistor-selectable drive voltage of 5.75V, 6.75V, and
7.75V (typically). This provides the flexibility necessary to
optimize applications involving trade-offs between gate
charge and conduction losses.
- Fast Rise/Fall Times and Low Propagation Delays
• Integrated UGATE-to-PHASE Resistor for Increased
Upper MOSFET Input Bus High dV/dt Immunity
• Pre-POR Overvoltage Protection at Start-Up and
Shutdown
• Dual Flat No-Lead (DFN) Package
To further enhance light load efficiency, the ISL6622B
enables diode emulation operation during PSI mode. This
allows for Discontinuous Conduction Mode (DCM) operation
by detecting when the inductor current reaches zero and
subsequently turning off the low side MOSFET to prevent it
from sinking current.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
- Bottom Copper Pad for Enhanced Heat Sinking
• Pb-Free (RoHS Compliant)
Applications
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6622B has a 20kΩ integrated high-side MOSFET
gate-to-source resistor to prevent self turn-on due to high
input bus dV/dt. This driver also has an overvoltage
protection feature operational while VCC is below the POR
threshold: the PHASE node is connected to the gate of the
low side MOSFET (LGATE) via a 10kΩ resistor, limiting the
output voltage of the converter close to the gate threshold of
the low side MOSFET, dependent on the current being
shunted, which provides some protection to the load should
the upper MOSFET(s) be shorted prior to start-up.
• High Light-Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6622B
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
PACKAGE
(Pb-free)
PKG.
DWG. #
(°C)
ISL6622BCBZ*
ISL6622BCRZ*
ISL6622BIBZ*
ISL6622BIRZ*
6622B CBZ
0 to +70
0 to +70
-40 to +85
-40 to +85
8 Ld SOIC
M8.15
622B
10 Ld 3x3 DFN
8 Ld SOIC
L10.3x3
M8.15
6622B IBZ
22BI
10 Ld 3x3 DFN
L10.3x3
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6622B
(8 LD SOIC)
TOP VIEW
ISL6622B
(10 LD 3x3 DFN)
TOP VIEW
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
VCC
UGATE
BOOT
GD_SEL
PWM
1
2
3
4
5
10
9
PHASE
VCC
LVCC
LGATE
8
PAD
UVCC
LVCC
LGATE
GND
7
6
GND
Block Diagrams
ISL6622B
BOOT
UVCC
UGATE
LDO
GD_SEL
20k
VCC
PHASE
LVCC
+5V
LVCC
SHOOT-
10k
THROUGH
11.2k
PROTECTION
PWM
POR/
CONTROL
LOGIC
LGATE
GND
9.6k
UVCC = VCC for SOIC
LVCC = 5.75V (TYPICALLY) at 50mA for SOIC
March 19, 2009
2
ISL6622B
Typical Application Circuit
+12V
VIN
VIN
VIN
VIN
BOOT
LVCC
VCC
+5V
UGATE
PHASE
ISL6622B
DRIVER
LGATE
GND
PWM
FB
COMP VCC
DAC
REF
VDIFF
VSEN
PWM1
ISEN1-
ISEN1+
+12V
RGND
EN_VTT
BOOT
PVCC
VTT
VR_RDY
VID7
VCC
UGATE
PHASE
VID6
ISL6612
DRIVER
VID5
ISL6334
LGATE
GND
VID4
PWM
PWM2
VID3
VID2
ISEN2-
ISEN2+
VID1
VID0
PSI
+12V
BOOT
PVCC
PWM3
ISEN3-
VR_FAN
VR_HOT
µP
LOAD
VCC
UGATE
PHASE
ISEN3+
VIN
ISL6612
DRIVER
EN_PWR
LGATE
GND
PWM
GND
PWM4
ISEN4-
ISEN4+
IMON
TCOMP
TM
+12V
BOOT
OFS
FS
SS
PVCC
+5V
+5V
VCC
UGATE
PHASE
NTC
ISL6612
DRIVER
LGATE
GND
PWM
March 19, 2009
3
ISL6622B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC, UVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
BOOT Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JC
JA
BOOT-GND
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
SOIC Package (Note 1) . . . . . . . . . . . .
DFN Package (Notes 2, 3). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
100
48
N/A
7
Input Voltage (V
PWM
UGATE. . . . . . . . . . . . . . . . . . . V
- 0.3V
to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
DC
BOOT
BOOT
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
LGATE . . . . . . . . . . . . . . . . . . GND - 0.3V
to V
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
LVCCLVCC
LVCCLVCC
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to 15V
DC
DC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
<36V)
BOOT-GND
Recommended Operating Conditions
Ambient Temperature Range
ISL6622BIBZ, ISL6622BIRZ . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6622BCBZ, ISL6622BCRZ. . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
Supply Voltage Range, UVCC. . . . . . . . . . . . . . . . . . 4.75V to 13.2V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
4. Limits should be considered typical and are not production tested.
Z
Electrical Specifications Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
VCC SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
No Load Switching Supply Current
I
I
ISL6622BCBZ and ISL6622BIBZ,
-
8.6
-
mA
VCC
VCC
f
= 300kHz, V
= 12V
VCC
PWM
ISL6622BCRZ and ISL6622BIRZ,
= 300kHz, V = 12V
-
-
-
6.6
2
-
-
-
mA
mA
mA
f
PWM
VCC
I
I
UVCC
Standby Supply Current
I
ISL6622BCBZ and ISL6622BIBZ, PWM
Transition from 0V to 2.5V
5.1
VCC
I
ISL6622BCRZ and ISL6622BIRZ, PWM
Transition from 0V to 2.5V
-
-
5.0
-
-
mA
mA
VCC
0.07
UVCC
POWER-ON RESET
VCC Rising Threshold
6.25
6.45
5.0
6.70
V
V
V
V
VCC Falling Threshold
4.8
5.25
LVCC Rising Threshold (Note 4)
LVCC Falling Threshold (Note 4)
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
-
-
4.4
3.4
-
-
I
V
V
= 5V
= 0V
-
-
-
-
-
-
-
-
500
-430
3.4
-
-
-
-
-
-
-
-
µA
µA
V
PWM
PWM
PWM
PWM Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
PWM Falling Threshold
1.6
V
Tristate Lower Gate Falling Threshold
Tristate Lower Gate Rising Threshold
Tristate Upper Gate Rising Threshold
Tristate Upper Gate Falling Threshold
1.60
1.1
V
V
3.2
V
2.8
V
March 19, 2009
4
ISL6622B
Electrical Specifications Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
UGATE Rise Time
SYMBOL
TEST CONDITIONS
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
MIN
TYP
26
MAX
UNITS
ns
t
V
V
V
V
V
V
V
V
V
V
-
-
RU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LGATE Rise Time
t
-
18
-
ns
RL
UGATE Fall Time
t
-
18
-
ns
FU
LGATE Fall Time
t
-
12
-
ns
FL
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Tristate Low Delay
t
-
20
-
ns
PDHU
t
-
10
-
ns
PDHL
PDLU
t
-
10
-
ns
t
= 12V, 3nF Load
-
-
10
-
-
ns
PDLL
t
= 12V
60
ns
TSLD
Minimum LGATE ON-Time During PSI Operation
OUTPUT (Note 4)
t
= 12V
230
330
450
ns
LG_ON_DM
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
I
V
= 12V, 3nF Load
-
-
-
-
-
-
-
-
1.25
2.0
2
-
-
-
-
-
-
-
-
A
Ω
A
Ω
A
Ω
A
Ω
U_SOURCE
VCC
R
20mA Source Current
U_SOURCE
I
V
= 12V, 3nF Load
U_SINK
VCC
20mA Sink Current
V = 12V, 3nF Load
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
R
1.35
2
U_SINK
I
L_SOURCE
VCC
20mA Source Current
R
1.35
3
L_SOURCE
I
V
= 12V, 3nF Load
L_SINK
VCC
Lower Drive Sink Impedance
R
20mA Sink Current
0.90
L_SINK
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
DFN
SYMBOL
FUNCTION
1
2
1
2
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
-
3
4
GD_SEL This pin sets the LG drive voltage.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
4
5
6
-
5
6
7
8
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
LVCC
UVCC
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7
8
-
9
VCC
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
10
11
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
March 19, 2009
5
ISL6622B
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
t
t
PDLU
t
PDHU
TSLD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Description
Operation and Adaptive Shoot-through Protection
Advanced PWM Protocol (Patent Pending)
Designed for high speed switching, the ISL6622B MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
The advanced PWM protocol of ISL6622B is specifically
designed to work with Intersil VR11.1 controllers. When
ISL6622B detects a PSI protocol sent by an Intersil VR11.1
controller, it turns on diode emulation operation; otherwise, it
remains in normal CCM PWM mode.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t
], the lower gate begins to fall. Typical fall time [t ] is
PDLL
FL
Another unique feature of ISL6622B and other Intersil drivers
is the addition of a tristate shutdown window to the PWM
input. If the PWM signal enters and remains within the
shutdown window for a set holdoff time, the driver outputs are
disabled and both MOSFET gates are pulled and held low.
The shutdown state is removed when the PWM signal moves
outside the shutdown window. Otherwise, the PWM rising and
falling thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled. This feature helps prevent a negative transient on
the output voltage when the output is shut down, eliminating
the Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
provided in the “Electrical Specifications” on page 5. Following
a 25ns blanking period, adaptive shoot-through circuitry
monitors the LGATE voltage and turns on the upper gate
following a short delay time [t
] after the LGATE voltage
drops below ~1.75V. The upper gate drive then begins to rise
PDHU
[t ] and the upper MOSFET turns on.
RU
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper gate
PDLU
begins to fall [t ]. The adaptive shoot-through circuitry
FU
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [t
] after the upper MOSFET’s
PDHL
PHASE voltage drops below +0.8V or 40ns after the upper
MOSFET’s gate voltage [UGATE-PHASE] drops below ~1.75V.
Note that for a PWM low to tri-level (2.5V) transition, the
LGATE will not turn off until the diode emulation minimum
ON-time of 350ns is expired.
The lower gate then rises [t ], turning on the lower MOSFET.
RL
These methods prevent both the lower and upper MOSFETs
from conducting simultaneously (shoot-through), while adapting
the dead time to the gate charge characteristics of the
MOSFETs being used.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6622B detects the zero current crossing of the output
inductor and turns off LGATE. This prevents the low side
MOSFET from sinking current and ensures that
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.8Ω ON-resistance and 3A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum ON-time of 350ns in DCM mode.
Gate Voltage Optimization Technology (GVOT)
The ISL6622B provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. In applications when
the switching losses dominate system performance, dropping
March 19, 2009
6
ISL6622B
down to a lower drive voltage with GVOT can improve the
switching losses seen and maximize system efficiency.
takes control of the gate drives. If VCC drops below the POR
falling threshold, operation of the driver is disabled.
Figure 2 shows that the gate drive voltage optimization is
accomplished via an internal low drop out regulator (LDO)
that regulates the lower gate drive voltage. LVCC is driven to
a lower voltage depending on the GD_SEL pin impedance.
The input and output of this internal regulator are the VCC
and LVCC pins, respectively. Both VCC and LVCC should be
decoupled with a high quality, low ESR ceramic capacitor.
9.0
+120°C
+40°C
-40°C
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
GD_SEL TIED TO GND
GD_SEL TIED TO 4.5kΩ TO GND
EXTERNAL CIRCUIT
VCC
ISL6622B INTERNAL CIRCUIT
GD_SEL FLOATING
SET BY
VIN >
GD_SEL
GVOT
1µF
LDO
+
+
-
0
20
40
60
80
100
-
RCC
AVERAGE LOAD CURRENT (mA)
FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD
LVCC
1µF
LGATE
DRIVER
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low
and LGATE is connected to the PHASE pin via an internal
10kΩ (typically) resistor. By connecting the PHASE node to the
gate of the low side MOSFET, the driver offers some passive
protection to the load if the upper MOSFET(s) is or becomes
shorted. If the PHASE node goes higher than the gate
threshold of the lower MOSFET, it results in the progressive
turn-on of the device and the effective clamping of the PHASE
node’s rise. The actual PHASE node clamping level depends
on the lower MOSFET’s electrical characteristics, as well as the
characteristics of the input supply and the path connecting it to
the respective PHASE node.
RCC = OPTION FOR HIGHER LVCC
THAN PRE-SET BY GD_SEL
FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL
In the 8 Ld SOIC package, the ISL6622B drives the upper
gate to 12V while the lower drive voltage is fixed at 5.75V. The
10 Ld DFN part offers more flexibility: the upper gate can be
driven from 5V to 12V via the UVCC pin, while the lower gate
has a resistor-selectable drive voltage of 5.75V, 6.75V, and
7.75V (typically). This provides the flexibility necessary to
optimize applications involving trade-offs between gate
charge and conduction losses. Table 1 shows the LDO output
(LVCC) level set by GD_SEL pin impedance.
Internal Bootstrap Device
TABLE 1. LDO OPERATION AND OPTIONS
The ISL6622B features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces the voltage
stress on the BOOT to PHASE pins.
PWM INPUT GD_SEL PIN
LVCC @ 50mA DC LOAD
5.75V (Typical; Fixed in SOIC Package)
6.75V(Typical)
Don’t Care
Floating
4.5kΩ to GND
GND
7.75V(Typical)
Figure 3 illustrates the internal LDO’s variation with the
average load current plotted over a range of temperatures
spanning from -40°C to +120°C. Should finer tweaking of this
The bootstrap capacitor must have a maximum voltage rating
well above the maximum voltage intended for UVCC. Its
minimum capacitance value can be estimated from Equation 1:
LVCC voltage be necessary, a resistor (R ) can be used to
CC
Q
GATE
-------------------------------------
C
≥
shunt the LDO, as shown in Figure 2. The resistor thus
delivers part of the LGATE drive current, leaving less current
going through the internal LDO, elevating the LDO’s output
voltage. Further reduction in RCC’s value can raise the
LVCC voltage further, as desired.
BOOT_CAP
Q
ΔV
BOOT_CAP
(EQ. 1)
• UVCC
G1
-----------------------------------
Q
=
• N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of
Power-On Reset (POR) Function
GS1
Q1
control MOSFETs. The ΔV
BOOT_CAP
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 4.
term is defined as the
During initial start-up, the VCC voltage rise is monitored. Once
the rising VCC voltage exceeds the rising POR threshold,
operation of the driver is enabled and the PWM input signal
March 19, 2009
7
ISL6622B
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
P
= P
+ P
+ I • VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
R
R
P
Qg_Q1
⎛
⎞
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
P
=
+
•
⎜
⎝
⎟
DR_UP
R
+ R
R
+ R
EXT1
2
⎠
HI1
EXT1
LO1
R
R
P
Qg_Q2
⎛
⎜
⎝
⎞
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
•
⎟
DR_LOW
R
+ R
R
+ R
⎠
EXT2
2
HI2
EXT2
LO2
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT1
G1
EXT2
N
N
Q1
Q2
Q
= 100nC
GATE
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R and R ) and the internal gate
50nC
20nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV (V)
BOOT_CAP
G1
G2
resistors (R
and R ) of MOSFETs. Figures 5 and 6 show
FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
GI1
GI2
the typical upper and lower gate drives turn-on current paths.
Power Dissipation
UVCC
BOOT
Package power dissipation is mainly a function of the
D
switching frequency (F ), the output drive impedance, the
layout resistance, and the selected MOSFET’s internal gate
SW
C
GD
R
HI1
G
resistance and total gate charge (Q ). Calculating the power
C
G
DS
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal impedance
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
R
R
LO1
R
G1
C
L1
GS
Q1
S
PHASE
FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
D
C
GD
(EQ. 2)
P
= P
+ P
+ I • VCC
Q
Qg_TOT
Qg_Q1
Qg_Q2
2
R
HI2
G
C
DS
Q
• UVCC
G1
R
R
LO2
R
G2
C
---------------------------------------
P
=
• F
• N
• N
L2
Qg_Q1
SW
Q1
V
GS1
GS
Q2
2
Q
• LVCC
S
G2
--------------------------------------
P
=
• F
Qg_Q2
SW
Q2
V
GS2
FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q
• UVCC • N
Q
• LVCC • N
G2 Q2
⎛
⎜
⎝
⎞
⎟
⎠
G1
Q1
----------------------------------------------------- ----------------------------------------------------
I
=
+
• F
+ I
DR
SW
Q
V
V
GS2
GS1
(EQ. 3)
Application Information
where the gate charge (Q and Q ) is defined at a
particular gate to source voltage (V
G1
G2
Layout Considerations
and V
) in the
GS1
GS2
During switching of the devices, the parasitic inductances of
the PCB and the power devices’ packaging (both upper and
lower MOSFETs) leads to ringing, possibly in excess of the
absolute maximum rating of the devices. Careful layout can
help minimize such unwanted stress. The following advice is
meant to lead to an optimized layout:
corresponding MOSFET data sheet; I is the driver’s total
Q
quiescent current with no load at both drive outputs; N
Q1
and N are number of upper and lower MOSFETs,
Q2
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I VCC
Q*
product is the quiescent power of the driver without a load.
• Keep decoupling loops (LVCC-GND and BOOT-PHASE)
as short as possible.
• Minimize trace inductance, especially low-impedance lines:
all power traces (UGATE, PHASE, LGATE, GND, LVCC)
should be short and wide, as much as possible.
March 19, 2009
8
ISL6622B
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
–V
DS
⎛
⎜
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎟
⎠
---------------------------------
dV
-------
⋅ R ⋅ C
dV
dt
iss
dt
-------
V
=
⋅ R ⋅ C
1 – e
(EQ. 5)
GS_MILLER
rss
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
R = R
+ R
C
= C
C
= C
+ C
UGPH
GI
rss
GD
iss
GD
GS
VIN
UVCC
BOOT
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
C
BOOT
G
D
C
GD
UGATE
PHASE
C
DS
R
G
C
GS
Q
S
UPPER
20kΩ
Upper MOSFET Self Turn-On Effect at Start-up
FIGURE 7. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
–V
DS
⎛
⎜
⎜
⎜
⎜
⎝
⎞
---------------------------------
coupling via the internal C
of the MOSFET, the gate of the
GD
dV
⎟
⎟
⎟
⎟
⎠
-------
⋅ R ⋅ C
dV
dt
iss
dt
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
-------
V
=
⋅ R ⋅ C
1 – e
(EQ. 6)
GS_MILLER
rss
C
= C
+ C
C
= C
R = R
+ R
GI
iss
GD
GS
rss
GD
UGPH
place a resistor (R
) across the gate and source of the
UGPH
Gate Drive Voltage Options
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
Intersil provides various gate drive voltage options in the
ISL6622 product family, as shown in Table 2.
rate of rise, the C /C
ratio, as well as the gate-source
GD GS
threshold of the upper MOSFET. A higher dV/dt, a lower
/C ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The ISL6622 can drop the low-side MOSFET’s gate drive
voltage when operating in DEM, while the high-side FET’s
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
C
DS GS
The ISL6622A allows the low-side MOSFET(s) to operate
from an externally-provided rail as low as 5V, eliminating the
LDO losses, while the high-side MOSFET’s gate drive voltage
of the DFN package can be connected to VCC or LVCC.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 7 provides a visual reference for this
phenomenon and its potential solution.
The ISL6622B sets the low-side MOSFET’s gate drive voltage
at a fixed, programmable LDO level, while the highside FETs’
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
TABLE 2. ISL6622 FAMILY OPTIONS
LVCC
POWER RAILS
PSI = LOW
5.75V
PSI = HIGH
11.2V
UVCC
VCC
VCC
ISL6622
SOIC
DFN
SOIC
DFN
SOIC
DFN
Operating Voltage Ranges from 6.8V to 13.2V
Programmable
11.2V
Separate Rail
VCC
ISL6622A
ISL6622B
Separate Rail
Separate Rail
5.75V
Separate Rail
VCC
Programmable
Separate Rail
March 19, 2009
9
ISL6622B
Dual Flat No-Lead Plastic Package (DFN)
2X
L10.3x3
0.15
C A
2X
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
A
MILLIMETERS
0.15 C
B
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
A
A1
A3
b
-
-
0.18
1.95
1.55
-
0.05
-
E
0.20 REF
0.23
-
6
0.28
2.05
1.65
5,8
INDEX
AREA
D
3.00 BSC
2.00
-
D2
E
7,8
TOP VIEW
B
A
3.00 BSC
1.60
-
E2
e
7,8
0.10 C
0.08 C
0.50 BSC
-
-
k
0.25
0.30
-
-
L
0.35
0.40
8
SIDE VIEW
C
A3
SEATING
PLANE
N
10
2
Nd
5
3
7
8
Rev. 3 6/04
D2
NOTES:
(DATUM B)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
D2/2
1
2
6
3. Nd refers to the number of terminals on D.
INDEX
AREA
k
NX
E2
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
8
N
N-1
e
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
(Nd-1)Xe
0.10 M C A B
REF.
BOTTOM VIEW
C
L
0.415
NX (b)
(A1)
L
0.200
NX b
NX L
5
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
C
March 19, 2009
10
ISL6622B
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
March 19, 2009
11
相关型号:
ISL6622BIBZ-T
3A AND GATE BASED MOSFET DRIVER, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
RENESAS
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