ISL6622A,_技术文档

ISL6334, ISL6334A

®

Data Sheet

February 26, 2008

FN6482.0

VR11.1, 4-Phase PWM Controller with

Light Load Efficiency Enhancement and

Load Current Monitoring Features

Features

• Intel VR11.1 Compliant

• Proprietary Active Pulse Positioning (APP) and Adaptive

Phase Alignment (APA) Modulation Scheme

The ISL6334, ISL6334A control microprocessor core voltage

regulation by driving up to 4 interleaved synchronous-rectified

buck channels in parallel. This multiphase architecture results

in multiplying channel ripple frequency and reducing input and

output ripple currents. Lower ripple results in fewer

components, lower cost, reduced power dissipation, and

smaller implementation area.

• Proprietary Active Phase Adding and Dropping with Diode

Emulation Scheme For High Light Load Efficiency

• Precision Multiphase Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% Closed-loop System Accuracy Over Load, Line

and Temperature

Microprocessor loads can generate load transients with

extremely fast edge rates and requires high efficiency at light

load. The ISL6334, ISL6334A utilizes Intersil’s proprietary

Active Pulse Positioning (APP), Adaptive Phase Alignment

(APA) modulation scheme, active phase adding and

dropping to achieve and maintain the extremely fast

transient response with fewer output capacitors and high

efficiency from light to full load.

- Bi-directional, Adjustable Reference-Voltage Offset

• Precision resistor or DCR Differential Current Sensing

- Accurate Load-Line (Droop) Programming

- Accurate Channel-Current Balancing

- Accurate Load Current Monitoring via IMON Pin

• Microprocessor Voltage Identification Input

- Dynamic VID™ Technology for VR11.1 Requirement

- 8-Bit VID, VR11 Compatible

The ISL6334, ISL6334A is designed to be completely

compliant with Intel VR11.1 specifications. It accurately

reports the load current via IMON pin to the microprocessor,

which sends an active low PSI# signal to the controller at low

power mode. The controller then enters 1- or 2-phase

operation with diode emulation option to reduce magnetic

core and switching losses, yielding high efficiency at light

load. After the PSI# signal is de-asserted, the dropped

phase(s) are added back to sustain heavy load transient

response and efficiency.

• Average Overcurrent Protection and Channel Current Limit

• Precision Overcurrent Protection on IMON Pin

• Thermal Monitoring and Overvoltage Protection

• Integrated Programmable Temperature Compensation

• Integrated Open Sense Line Protection

• 1- to 4-Phase Operation, Coupled Inductor Compatibility

• Adjustable Switching Frequency up to 1MHz Per Phase

• Package Option

Today’s microprocessors require a tightly regulated output

voltage position versus load current (droop). The ISL6334,

ISL6334A senses the output current continuously by utilizing

patented techniques to measure the voltage across the

dedicated current sense resistor or the DCR of the output

inductor. The sensed current flows out of FB pin to develop the

precision voltage drop across the feedback resistor for droop

control. Current sensing circuits also provide the needed

signals for channel-current balancing, average overcurrent

protection and individual phase current limiting. An NTC

thermistor’s temperature is sensed via TM pin and internally

digitized for thermal monitoring and for integrated thermal

compensation of the current sense elements.

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

• Pb-Free (RoHS Compliant)

A unity gain, differential amplifier is provided for remote voltage

sensing and completely eliminates any potential difference

between remote and local grounds. This improves regulation

and protection accuracy. The threshold-sensitive enable input is

available to accurately coordinate the start-up of the ISL6334,

ISL6334A with any other voltage rail. Dynamic-VID™

technology allows seamless on-the-fly VID changes. The

offset pin allows accurate voltage offset settings that are

independent of VID setting.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6334, ISL6334A

Ordering Information

PART NUMBER

(Note)

PART

MARKING

PACKAGE

(Pb-Free)

PKG.

DWG. #

TEMP. (°C)

-40 to +85

0 to +70

ISL6334IRZ*

ISL6334AIRZ*

ISL6334CRZ*

ISL6334ACRZ*

ISL6334 IRZ

40 Ld 6x6 QFN

L40.6x6

6334A IRZ

40 Ld 6x6 QFN

L40.6x6

ISL6334 CRZ

6334A CRZ

0 to +70

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

Pinout

ISL6334, ISL6334A

(40 LD QFN)

TOP VIEW

40 39 38 37 36 35 34 33 32 31

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PSI#

OFS

IMON

ISEN3-

ISEN3+

ISEN1+

ISEN1-

PWM1

PWM4

ISEN4-

ISEN4+

ISEN2+

ISEN2-

1

2

30

29

28

27

26

25

24

23

22

21

3

4

5

GND

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

FN6482.0

February 26, 2008

2

ISL6334, ISL6334A

Controller and Driver Recommendation

CONTROLLER

COMMENTS

ISL6334

When PSI# is asserted low, the remained channel transmits a special PWM protocol that can be recognized only by the dedicated

VR11.1 drivers ISL6622/ISL6620 for Diode Emulation (DCM) operation. The dropped channel remains in tri-state.

ISL6334A

When PSI# is asserted low, the remained channel transmits normal CCM PWM that can be recognized by any Intersil driver such

as ISL6612/ISL6614, ISL6596, ISL6610, and even ISL6622/ISL6620. The dropped channel remains in tri-state.

GATE

DRIVE

VOLTAGE DRIVES

# OF

GATE

DIODE

EMULATION

(DE)

GATEDRIVE

DROP

DRIVER

(GVOT)

COMMENTS

ISL6622

12V

5V

Dual

Yes

No

For PSI# channel and its coupled channel in coupled inductor

applications or all channels

ISL6622A,

ISL6622B

For PSI# channel and its coupled channel in coupled inductor

applications or all channels.

ISL6620, ISL6620A

For PSI# channel and its coupled channel in coupled inductor

applications or all channels

ISL6612, ISL6612A

ISL6596

12V

5V

Dual

No

For dropped phases or all channels with ISL6634A

ISL6614, ISL6614A

ISL6610, ISL6610A

12V

5V

Quad

NOTE: Note: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency.

Dual = One Synchronous Channel; Quad = Two Synchronous Channels.

FN6482.0

February 26, 2008

3

ISL6334, ISL6334A

ISL6334 and ISL6334A Block Diagram

VDIFF VR_RDY

FS

PSI#

0.875

-

POWER-ON

RESET (POR)

CLOCK AND

RAMP GENERATOR

RGND

VSEN

-

+

X1

EN_VTT

+

N

-

+

EN_PWR

SOFT-START

AND

+

OVP

-

FAULT LOGIC

+175mV

APP and APA

MODULATOR

PWM1

PWM2

SS

APP and APA

MODULATOR

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

DYNAMIC

VID

D/A

APP and APA

MODULATOR

PWM3

PWM4

DAC

OFS

APP and APA

MODULATOR

OFFSET

+

REF

FB

CHANNEL

CURRENT

BALANCE

CHANNEL

DETECT

E/A

-

AND PEAK

CURRENT LIMIT

COMP

IMON

N

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

ISEN4+

ISEN4-

I_TRIP

1.11V

+

OCP

-

CHANNEL

CURRENT

SENSE

TEMPERATURE

COMPENSATION

1

N

Σ

1.11V

VR_HOT

VR_FAN

TEMPERATURE

COMPENSATION

GAIN ADJUST

THERMAL

MONITOR

TM

TCOMP

GND

FN6482.0

February 26, 2008

4

ISL6334, ISL6334A

Typical Application: 4-Phase VR with Integrated Thermal Compensation, PSI# (DE and GVOT)

+12V

VIN

BOOT

PVCC

VCC

+5V

UGATE

PHASE

ISL6622

DRIVER

LGATE

GND

PWM

COMP VCC DAC

REF

FB

VDIFF

VSEN

PWM1

ISEN1-

ISEN1+

+12V

RGND

EN_VTT

BOOT

PVCC

VTT

VR_RDY

VID7

VCC

UGATE

PHASE

ISL6334

VID6

ISL6612

DRIVER

VID5

LGATE

GND

VID4

PWM

PWM2

VID3

VID2

ISEN2-

ISEN2+

VID1

VID0

PSI#

+12V

BOOT

PVCC

VR_FAN

VR_HOT

PWM3

ISEN3-

µP

LOAD

VCC

UGATE

PHASE

VIN

ISEN3+

ISL6612

DRIVER

EN_PWR

GND

LGATE

GND

+5V

PWM

PWM4

ISEN4-

ISEN4+

IMON

TCOMP

+12V

BOOT

TM

OFS

FS

SS

PVCC

+5V

VCC

UGATE

PHASE

NTC

ISL6612

DRIVER

LGATE

GND

PWM

NTC: NTHS0805N02N6801,

6.8kΩ, VISHAY

FN6482.0

February 26, 2008

5

ISL6334, ISL6334A

Typical Application - 4-Phase VR with 1-Phase PSI# and without Diode Emulation and GVOT)

+12V

VIN

BOOT

PVCC

VCC

+5V

UGATE

PHASE

ISL6612

DRIVER

LGATE

GND

PWM

COMP VCC DAC

REF

FB

VDIFF

VSEN

PWM1

ISEN1-

ISEN1+

+12V

RGND

EN_VTT

BOOT

PVCC

VTT

VR_RDY

VID7

VCC

UGATE

PHASE

ISL6334A

ISL6334

VID6

ISL6612

DRIVER

VID5

LGATE

GND

VID4

PWM

PWM2

VID3

VID2

ISEN2-

ISEN2+

VID1

VID0

PSI#

+12V

BOOT

PVCC

PWM3

ISEN3-

VR_FAN

VR_HOT

µP

LOAD

VCC

UGATE

PHASE

ISEN3+

VIN

ISL6612

DRIVER

EN_PWR

LGATE

GND

+5V

PWM

GND

PWM4

ISEN4-

ISEN4+

IMON

TCOMP

TM

+12V

BOOT

OFS

FS

SS

PVCC

+5V

VCC

UGATE

PHASE

NTC

ISL6612

DRIVER

LGATE

GND

PWM

NTC: NTHS0805N02N6801,

6.8kΩ, VISHAY

FN6482.0

February 26, 2008

6

ISL6334, ISL6334A

Typical Application -VR with External Thermal Compensation, 2-Phase PSI# (no DE and GVOT)

NTC

+12V

+5V

^oC

VIN

BOOT1

VCC

UGATE1

PHASE1

COMP VCC DAC

REF

FB

GND

LGATE1

VDIFF

VSEN

PVCC

12V

ISL6614

DRIVER

VIN

RGND

EN_VTT

BOOT2

ISEN1+

ISEN1-

VTT

VR_RDY

VID7

PWM1

PWM2

UGATE2

PHASE2

PWM1

VID6

ISL6334A

VID5

ISL6334

LGATE2

PGND

VID4

VID3

PWM3

VID2

ISEN3-

ISEN3+

VID1

VID0

ISEN2+

ISEN2-

PSI#

VR_FAN

VR_HOT

µP

LOAD

+12V

VIN

PWM2

BOOT1

VCC

VIN

UGATE1

PHASE1

EN_PWR

GND

PWM4

+5V

GND

ISEN4-

ISEN4+

LGATE1

IMON

PVCC

12V

ISL6614

DRIVER

TCOMP

TM

VIN

BOOT2

OFS

FS

5V

SS

5V

+5V

PWM1

PWM2

UGATE2

PHASE2

NTC

LGATE2

PGND

NTC: NTHS0805N02N6801,

6.8kΩ, VISHAY

FN6482.0

February 26, 2008

7

ISL6334, ISL6334A

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V

Thermal Resistance (Notes 1, 2)

θ

(°C/W)

θ

(°C/W)

JA

JC

All Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

+ 0.3V

CC

40 Ld 6x6 QFN Package . . . . . . . . . . .

32

2

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature

ISL6334ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6334CRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature

ISL6334IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

ISL6334AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified.

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

VCC SUPPLY CURRENT

Nominal Supply

VCC = 5VDC; EN_PWR = 5VDC; R = 100kΩ,

ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA

-

16

14

20

17

mA

T

Shutdown Supply

VCC = 5VDC; EN_PWR = 0VDC; R = 100kΩ

T

POWER-ON RESET AND ENABLE

VCC Rising POR Threshold

VCC Falling POR Threshold

EN_PWR Rising Threshold

4.3

4.4

4.5

V

3.75

3.88

4.0

0.875 0.897

0.735 0.752

0.875 0.897

0.735 0.752

0.920

0.770

0.920

0.770

EN_PWR Falling Threshold

EN_VTT Rising Threshold

EN_VTT Falling Threshold

REFERENCE VOLTAGE AND DAC

System Accuracy of ISL6334CRZ, ISL6334ACRZ

(VID = 1V to 1.6V, T = 0°C to +70°C)

J

(Note 3, Closed-Loop)

-0.5

-5

-

0.5

5

%VID

mV

System Accuracy of ISL6334CRZ, ISL6334ACRZ

(VID = 0.5V to 1V, T = 0°C to +70°C)

J

System Accuracy of ISL6334IRZ, ISL6334AIRZ

(VID = 1V to 1.6V, T = -40°C to +85°C)

J

-0.6

-6

0.6

6

%VID

mV

System Accuracy of ISL6334IRZ, ISL6334AIRZ

(VID = 0.8V to 1V, T = -40°C to +85°C)

J

System Accuracy of ISL6334IRZ, ISL6334AIRZ

-7

7

mV

(VID = 0.5V to 0.8V, T = -40°C to +85°C)

J

VID Pull-up

After t

D3

30

-

40

-

50

0.4

-

µA

V

VID Input Low Level

VID Input High Level

0.8

-

V

FN6482.0

February 26, 2008

8

ISL6334, ISL6334A

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

Max DAC Source Current

Max DAC Sink Current

3.5

100

50

-

mA

µA

Max REF Source/Sink Current

PIN-ADJUSTABLE OFFSET

Voltage at OFS Pin

(Note 4)

Offset resistor connected to ground

390

400

415

mV

V

Voltage below VCC, offset resistor connected to

VCC

1.574

1.60

1.635

OSCILLATORS

Accuracy of Switching Frequency Setting

Adjustment Range of Switching Frequency

Soft-start Ramp Rate

Adjustment Range of Soft-Start Ramp Rate

PWM GENERATOR

R

= 100kΩ

225

0.08

-

250

275

1.0

-

kHz

MHz

T

(Note 4)

= 100kΩ (Notes 4, 5, 6)

-

1.563

-

R

mV/µs

SS

(Note 4)

0.625

6.25

Sawtooth Amplitude

(Note 4)

-

1.5

-

V

ERROR AMPLIFIER

Open-Loop Gain

R

= 10kΩ to ground (Note 4)

-

96

80

25

4.4

-

dB

MHz

V/µs

V

L

Open-Loop Bandwidth

Slew Rate

(Note 4)

-

Maximum Output Voltage

Output High Voltage @ 2mA

Output Low Voltage @ 2mA

REMOTE-SENSE AMPLIFIER (Note 4)

Bandwidth

3.8

3.6

-

4.9

-

V

-

1.6

V

(Note 4)

-

20

-

MHz

µA

Output High Current

VSEN - RGND = 2.5V

VSEN - RGND = 0.6

-500

500

Output High Current

-

µA

PWM OUTPUT

Sink Impedance

PWM = Low with 1mA Load

PWM = High, Forced to 3.7V

100

200

220

320

300

400

Ω

Source Impedance

PSI# INPUT

High Signal Threshold

Low Signal Threshold

-

0.8

-

V

0.4

CURRENT SENSE AND OVERCURRENT PROTECTION

Sensed Current Tolerance ISEN1 = ISEN2 = ISEN3 = ISEN4 = 40µA;

36.5

74

96

-

42

83

117

-

µA

CS Offset and Mirror Error Included, R

ISENx

= 200Ω

ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA;

-

CS Offset and Mirror Error Included, R

= 200Ω

ISENx

Overcurrent Trip Level for Average Current At Normal CS Offset and Mirror Error Included, R

CCM PWM Mode

105

121

ISENx

Overcurrent Trip Level for Average Current at PSI#

Mode

N = 4, Drop to 1 Phase

Peak Current Limit for Individual Channel

IMON Clamped and OCP Trip Level

115

129

146

µA

V

1.085

1.11

1.14

FN6482.0

February 26, 2008

9

ISL6334, ISL6334A

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

THERMAL MONITORING AND FAN CONTROL

TM Input Voltage for VR_FAN Trip

38.7

39.1

39.6

45.5

33.7

39.6

5

%VCC

µA

TM Input Voltage for VR_FAN Reset

TM Input Voltage for VR_HOT Trip

44.6

45.1

32.9

33.3

TM Input Voltage for VR_HOT Reset

38.7

39.1

Leakage Current of VR_FAN

VR_FAN Low Voltage

With external pull-up resistor connected to VCC

With 1.24k resistor pull-up to VCC, I = 4mA

-

0.3

5

V

VR_FAN

With external pull-up resistor connected to VCC

With 1.24k resistor pull-up to VCC, I = 4mA

Leakage Current of VR_HOT

VR_HOT Low Voltage

µA

0.3

V

VR_HOT

VR READY AND PROTECTION MONITORS

Leakage Current of VR_RDY

VR_RDY Low Voltage

With pull-up resistor externally connected to VCC

= 4mA

-

5

0.3

52

µA

V

I

-

VR_RDY

Undervoltage Threshold

VDIFF Falling

48

57

50

59.6

%VID

V

VR_RDY Reset Voltage

VDIFF Rising

62

Overvoltage Protection Threshold

Before valid VID

1.250 1.273

1.300

190

-

After valid VID, the voltage above VID

158

-

175

100

mV

Overvoltage Protection Reset Hysteresis

NOTES:

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Limits should be considered typical and are not production tested.

5. During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID.

6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.

7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

FN6482.0

February 26, 2008

10

ISL6334, ISL6334A

VID setting. It is an open-drain logic output. When OCP or

Functional Pin Description

OVP occurs, VR_RDY will be pulled to low. It will also be

pulled low if the output voltage is below the undervoltage

threshold.

VCC - Supplies the power necessary to operate the chip.

The controller starts to operate when the voltage on this pin

exceeds the rising POR threshold and shuts down when the

voltage on this pin drops below the falling POR threshold.

Connect this pin directly to a +5V supply.

OFS - The OFS pin can be used to program a DC offset

current, which will generate a DC offset voltage between the

REF and DAC pins. The offset current is generated via an

external resistor and precision internal voltage references.

The polarity of the offset is selected by connecting the

resistor to GND or VCC. For no offset, the OFS pin should

be left unterminated.

GND - Bias and reference ground for the IC. The bottom

metal base of ISL6334, ISL6334A is the GND.

EN_PWR - This pin is a threshold-sensitive enable input for

the controller. Connecting the 12V supply to EN_PWR

through an appropriate resistor divider provides a means to

synchronize power-up of the controller and the MOSFET

driver ICs. When EN_PWR is driven above 0.875V, the

ISL6334, ISL6334A is active depending on status of the

EN_VTT, the internal POR, and pending fault states. Driving

EN_PWR below 0.745V will clear all fault states and prime

the ISL6334, ISL6334A to soft-start when re-enabled.

TCOMP - Temperature compensation scaling input. The

voltage sensed on the TM pin is utilized as the temperature

input to adjust I

and the overcurrent protection limit to

DROOP

effectively compensate for the temperature coefficient of the

current sense element. To implement the integrated

temperature compensation, a resistor divider circuit is needed

with one resistor being connected from TCOMP to VCC of the

controller and another resistor being connected from TCOMP

to GND. Changing the ratio of the resistor values will set the

gain of the integrated thermal compensation. When integrated

temperature compensation function is not used, connect

TCOMP to GND.

EN_VTT - This pin is another threshold-sensitive enable

input for the controller. It’s typically connected to VTT output

of VTT voltage regulator in the computer mother board.

When EN_VTT is driven above 0.875V, the ISL6334,

ISL6334A is active depending on status of the EN_PWR, the

internal POR, and pending fault states. Driving EN_VTT

below 0.745V will clear all fault states and prime the

ISL6334, ISL6334A to soft-start when re-enabled.

TM - TM is an input pin for the VR temperature measurement.

Connect this pin through an NTC thermistor to GND and a

resistor to VCC of the controller. The voltage at this pin is

reverse proportional to the VR temperature. The ISL6334,

ISL6334A monitors the VR temperature based on the voltage

at the TM pin and outputs VR_HOT and VR_FAN signals.

VDIFF, VSEN and RGND - VSEN and RGND form the

precision differential remote-sense amplifier. This amplifier

converts the differential voltage of the remote output to a

single-ended voltage referenced to local ground. VDIFF is

the amplifier’s output and the input to the regulation and

protection circuitry. Connect VSEN and RGND to the sense

pins of the remote load.

VR_HOT - VR_HOT is used as an indication of high VR

temperature. It is an open-drain logic output. It will be pulled

low if the measured VR temperature is less than a certain

level, and open when the measured VR temperature

reaches a certain level. A external pull-up resistor is needed.

FB and COMP - Inverting input and output of the error

amplifier respectively. FB can be connected to VDIFF

through a resistor. A properly chosen resistor between

VDIFF and FB can set the load line (droop), because the

sensed current will flow out of FB pin. The droop scale factor

is set by the ratio of the ISEN resistors and the inductor DCR

or the dedicated current sense resistor. COMP is tied back to

FB through an external R-C network to compensate the

regulator.

VR_FAN - VR_FAN is an output pin with open-drain logic

output. It will be pulled low if the measured VR temperature

is less than a certain level, and open when the measured VR

temperature reaches a certain level. A external pull-up

resistor is needed.

PWM1, PWM2, PWM3, PWM4 - Pulse width modulation

outputs. Connect these pins to the PWM input pins of the

Intersil driver IC. The number of active channels is

determined by the state of PWM2, PWM3 and PWM4. Tie

PWM2 to VCC to configure for 1-phase operation. Tie

PWM3 to VCC to configure for 2-phase operation. Tie

PWM4 to VCC to configure for 3-phase operation. In

addition, tie PSI# to GND to configure for single phase

operation with diode emulation.

DAC and REF - The DAC pin is the output of the precision

internal DAC reference. The REF pin is the positive input of

the Error Amplifier. In typical applications, a 1kΩ, 1% resistor

is used between DAC and REF to generate a precision

offset voltage. This voltage is proportional to the offset

current determined by the offset resistor from OFS to ground

or VCC. A capacitor is used between REF and ground to

smooth the voltage transition during Dynamic VID™

operations.

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;

ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current

sense inputs to individual differential amplifiers. The sensed

current is used for channel current balancing, overcurrent

VR_RDY - VR_RDY indicates that soft-start has completed

and the output voltage is within the regulated range around

FN6482.0

February 26, 2008

11

ISL6334, ISL6334A

protection, and droop regulation. Inactive channels should

have their respective current sense inputs left open (for

example, open ISEN4+ and ISEN4- for 3-phase operation).

phase(s) and remained phase(s) as PSI# is asserted and

de-asserted. A high input signal pulls the controller back to

normal operation.

For DCR sensing, connect each ISEN- pin to the node

between the RC sense elements. Tie the ISEN+ pin to the

Operation

Multiphase Power Conversion

other end of the sense capacitor through a resistor, R

.

ISEN

The voltage across the sense capacitor is proportional to the

inductor current. Therefore, the sense current is proportional

to the inductor current and scaled by the DCR of the inductor

Microprocessor load current profiles have changed to the

point that the advantages of multiphase power conversion

are impossible to ignore. The technical challenges

and R

.

associated with producing a single-phase converter (which

are both cost-effective and thermally viable), have forced a

change to the cost-saving approach of multiphase. The

ISL6334, ISL6334A controller helps reduce the complexity of

implementation by integrating vital functions and requiring

minimal output components. The block diagrams on pages

page 5, 7, and 6 provide top level views of multiphase power

conversion using the ISL6334, ISL6334A controller.

ISEN

To match the time delay of the internal circuit, a capacitor is

needed between each ISEN+ pin and GND, as described in

“Current Sensing” on page 14.

IMON - IMON is the output pin of sensed, thermally

compensated (if internal thermal compensation is used)

average current. The voltage at IMON pin is proportional to

the load current and the resistor value, and internally clamped

to 1.11V plus the remote ground potential difference. If the

clamped voltage (1.11V) is triggered, it will initiate the

overcurrent shutdown. By choosing the proper value for the

resistor at IMON pin, the overcurrent trip level can be set to be

lower than the fixed internal overcurrent threshold. During the

dynamic VID, the OCP function of this pin is disable to avoid

falsely triggering. Tie it to GND if not used.

Interleaving

The switching of each channel in a multiphase converter is

timed to be symmetrically out-of-phase with each of the

other channels. In a 3-phase converter, each channel

switches 1/3 cycle after the previous channel and 1/3 cycle

before the following channel. As a result, the 3-phase

converter has a combined ripple frequency three times

greater than the ripple frequency of any one phase. In

addition, the peak-to-peak amplitude of the combined

inductor currents is reduced in proportion to the number of

phases (Equations 1 and 2). Increased ripple frequency and

lower ripple amplitude mean that the designer can use less

per-channel inductance and lower total output capacitance

for any performance specification.

FS - Use this pin to set up the desired switching frequency. A

resistor, placed from FS to ground/VCC will set the switching

frequency. The relationship between the value of the resistor

and the switching frequency will be approximated by

Equation 3. This pin is also used with SS and PSI# pins for

phase dropping decoding. See Table 1.

SS - Use this pin to set up the desired start-up oscillator

frequency. A resistor placed from SS to ground/VCC will set

up the soft-start ramp rate. The relationship between the

value of the resistor and the soft-start ramp up time will be

approximated by Equations 15 and 16. This pin is also used

with FS and PSI# pins for phase dropping decoding. See

Table 1.

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The DC components of the inductor currents

combine to feed the load.

VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 -

These are the inputs to the internal DAC that generates the

reference voltage for output regulation. All VID pins have no

internal pull-up current sources until after TD3. Connect

these pins either to open-drain outputs with external pull-up

resistors or to active-pull-up outputs, as high as VCC plus

0.3V.

IL1 + IL2 + IL3, 7A/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

IL2, 7A/DIV

PSI# - A low input signal indicates the low power mode

operation of the processor. The controller drops the number

of active phases to single or 2-phase operation, according to

the logic on Table 1 on page 14. The PSI# pin, SS, and FS

pins are used to program the controller in operation of

non-coupled, 2-Phase coupled, or (n-x)-Phase coupled

inductors when PSI# is asserted (active low). Different cases

yield different PWM output behavior on both dropped

PWM2, 5V/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

FN6482.0

February 26, 2008

12

ISL6334, ISL6334A

To understand the reduction of ripple current amplitude in the

multiphase circuit, examine Equation 1, which represents an

individual channel’s peak-to-peak inductor current.

an input capacitor bank with twice the RMS current capacity as

the equivalent three-phase converter.

Figures 18, 19 and 20 in the section entitled “” on page 28

can be used to determine the input capacitor RMS current

based on load current, duty cycle, and the number of

channels. They are provided as aids in determining the

optimal input capacitor solution. Figure 21 shows the single

phase input-capacitor RMS current for comparison.

(V – V

) V

OUT

IN

OUT

(EQ. 1)

I

= -----------------------------------------------------

PP

LF

V

SW

IN

In Equation 1, V and V

IN

are the input and output

OUT

voltages respectively, L is the single-channel inductor value,

and F

is the switching frequency.

SW

PWM Modulation Scheme

INPUT-CAPACITOR CURRENT, 10A/DIV

The ISL6334, ISL6334A adopts Intersil's proprietary Active

Pulse Positioning (APP) modulation scheme to improve

transient performance. APP control is a unique dual-edge

PWM modulation scheme with both PWM leading and

trailing edges being independently moved to give the best

response to transient loads. The PWM frequency, however,

is constant and set by the external resistor between the FS

pin and GND. To further improve the transient response, the

ISL6334, ISL6334A also implements Intersil's proprietary

Adaptive Phase Alignment (APA) technique. APA, with

sufficiently large load step currents, can turn on all phases

together. With both APP and APA control, ISL6334,

ISL6334A can achieve excellent transient performance and

reduce demand on the output capacitors.

CHANNEL 1

INPUT CURRENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 3

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

Under steady state conditions, the operation of the ISL6334,

ISL6334A PWM modulators appear to be that of a

conventional trailing edge modulator. Conventional analysis

and design methods can therefore be used for steady state

and small signal operation.

The output capacitors conduct the ripple component of the

inductor current. In the case of multiphase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

PWM and PSI# Operation

The timing of each channel is set by the number of active

channels. The default channel setting for the ISL6334,

ISL6334A is four. The switching cycle is defined as the time

between PWM pulse termination signals of each channel.

The cycle time of the pulse signal is the inverse of the

switching frequency set by the resistor between the FS pin

and ground. The PWM signals command the MOSFET

driver to turn on/off the channel MOSFETs.

(V – N V

) V

OUT

IN

OUT

For 4-channel operation, the channel firing order is 1-2-3-4:

PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2

output follows another 1/4 of a cycle after PWM3, and

PWM1 delays another 1/4 of a cycle after PWM2. For

3-channel operation, the channel firing order is 1-2-3.

I

= -----------------------------------------------------------

(EQ. 2)

C, PP

Lf

V

S

IN

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multiphase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

Connecting PWM4 to VCC selects three channel operation

and the pulse times are spaced in 1/3 cycle increments. If

PWM3 is connected to VCC, two channel operation is

selected and the PWM2 pulse happens 1/2 of a cycle after

PWM1 pulse. If PWM2 is connected to VCC, only Channel 1

operation is selected. In addition, tie PSI# to GND to

configure for single or 2-phase operation with diode

emulation on remaining channel(s), Channel 1 or Channels

1 and 3.

The converter depicted in Figure 2 delivers 36A to a 1.5V load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS

input capacitor current. The single-phase converter must use

FN6482.0

February 26, 2008

13

ISL6334, ISL6334A

When PSI# is asserted low, indicating the low power mode

Current Sensing

operation of the processor, the controller drops the number of

active phases according to the logic on Table 1 for highlight

load efficiency performance. SS and FS pins are used to

program the controller in operation of non-coupled, 2-phase

coupled, or (n-x)-Phase coupled inductors. Different cases yield

different PWM output behaviors on both dropped phase(s) and

remained phase(s) as PSI# is asserted and de-asserted. A high

PSI# input signal pulls the controller back to normal CCM PWM

operation to sustain an immediate heavy transient load and

high efficiency. Note that “n-x” means n-x phase coupled and x

phase(s) are uncoupled.

The ISL6334, ISL6334A senses current continuously for fast

response. The ISL6334, ISL6334A supports inductor DCR

sensing, or resistive sensing techniques. The associated

channel current sense amplifier uses the ISEN inputs to

reproduce a signal proportional to the inductor current, I .

L

The sense current, I

, is proportional to the inductor

SEN

current. The sensed current is used for current balance,

load-line regulation, and overcurrent protection.

The internal circuitry, shown in Figures 4, and 5, represents

one channel of an N-channel converter. This circuitry is

repeated for each channel in the converter, but may not be

active depending on the status of the PWM2, PWM3 and

PWM4 pins, as described in “PWM and PSI# Operation” on

page 13. The input bias current of the current sensing

amplifier is typically 60nA; less than 5kΩ input impedance is

preferred to minimized the offset error.

TABLE 1. PSI# OPERATION DECODING

PSI#

FS

0

SS

0

Non CI or (n-1) CI Drops to 1-phase

Non CI or (n-2) CI Drops to 2-phase

2-phase CI Drops to 1-phase

2-phase CI Drops to 2-phase

Normal CCM PWM Mode

0

1

0

1

0

INDUCTOR DCR SENSING

1

An inductor’s winding is characteristic of a distributed

resistance, as measured by the DCR (Direct Current

Resistance) parameter. Consider the inductor DCR as a

separate lumped quantity, as shown in Figure 4. The

x

The dropped PWM is forced low for 200ns (uncoupled case)

or until falling edge of coupled PWM (coupled case) then

pulled to VCC/2, while the remained PWM(s) sends out a

special 3-level PWM protocol that the dedicated VR11.1

drivers can decode and then enter diode emulation mode

with gate drive voltage optimization.

channel current I , flowing through the inductor, will also

L

pass through the DCR. Equation 4 shows the s-domain

equivalent voltage across the inductor V .

L

V (s) = I ⋅ (s ⋅ L + DCR)

(EQ. 4)

L

The ISL6334A only generates 2-level normal CCM PWM

except for faults. No dedicated VR11.1 driver is required.

See “Controller and Driver Recommendation” on page 3.

A simple R-C network across the inductor extracts the DCR

voltage, as shown in Figure 4.

V

IN

Switching Frequency

I

(s)

L

Switching frequency is determined by the selection of the

L

DCR

V

OUT

frequency-setting resistor, R , which is connected from FS

pin to GND or VCC. Equation 3 and Figure 3 are provided to

assist in selecting the correct resistor value.

T

ISL6596

INDUCTOR

-

C

OUT

V

L

10

2.5X10

-

(s)

V

C

R

= -------------------------

T

(EQ. 3)

F

SW

R

C

PWM(n)

where F

is the switching frequency of each phase.

SW

250

ISL6334, ISL6334A INTERNAL CIRCUIT

R

ISEN(n)

200

150

100

50

I

n

CURRENT

SENSE

ISEN-(n)

+

-

ISEN+(n)

C

T

DCR

I

-----------------

= I

SEN

L

R

0

ISEN

100k 200k 300k 400k 500k 600k 700k 800k 900k 1M

SWITCHING FREQUENCY (Hz)

FIGURE 4. DCR SENSING CONFIGURATION

FIGURE 3. SWITCHING FREQUENCY vs RT

FN6482.0

February 26, 2008

14

ISL6334, ISL6334A

The voltage on the capacitor V , can be shown to be

proportional to the channel current I . See Equation 5.

L

C

I

L

R

V

OUT

SENSE

L

⎛

⎝

⎞

-------------

s ⋅

+ 1 ⋅ (DCR ⋅ I )

L

⎠

(EQ. 5)

C

DCR

OUT

V

(s) = --------------------------------------------------------------------

C

(s ⋅ RC + 1)

ISL6334, ISL6334A INTERNAL CIRCUIT

If the R-C network components are selected such that the

RC time constant (= R*C) matches the inductor time

R

ISEN(n)

I

n

constant (= L/DCR), the voltage across the capacitor V is

equal to the voltage drop across the DCR, i.e., proportional

to the channel current.

C

CURRENT

SENSE

ISEN-(n)

ISEN+(n)

+

-

With the internal low-offset current amplifier, the capacitor

voltage V is replicated across the sense resistor R

.

C

ISEN

, is proportional

T

Therefore, the current out of ISEN+ pin, I

to the inductor current.

SEN

R

SENSE

I

= I --------------------------

SEN

L

R

ISEN

Because of the internal filter at ISEN- pin, one capacitor, C ,

T

FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS

is needed to match the time delay between the ISEN- and

ISEN+ signals. Select the proper C to keep the time

Channel-Current Balance

T

constant of R

ISEN

and C (R x C ) close to 27ns.

ISEN T

T

The sensed current I from each active channel is summed

n

together and divided by the number of active channels. The

Equation 6 shows that the ratio of the channel current to the

sensed current, I , is driven by the value of the sense

resulting average current I

provides a measure of the

AVG

SEN

total load current. Channel current balance is achieved by

comparing the sensed current of each channel to the

average current to make an appropriate adjustment to the

PWM duty cycle of each channel with Intersil’s patented

current-balance method.

resistor and the DCR of the inductor.

DCR

-----------------

I

= I

⋅

(EQ. 6)

SEN

L

R

ISEN

RESISTIVE SENSING

For accurate current sense, a dedicated current-sense resistor

in series with each output inductor can serve as the

Channel current balance is essential in achieving the

thermal advantage of multiphase operation. With good

current balance, the power loss is equally dissipated over

multiple devices and a greater area.

R

SENSE

current sense element (see Figure 5). This technique is more

accurate, but reduces overall converter efficiency due to the

additional power loss on the current sense element R

.

SENSE

Voltage Regulation

The same capacitor C is needed to match the time delay

T

The compensation network shown in Figure 6 assures that

the steady-state error in the output voltage is limited only to

the error in the reference voltage (output of the DAC) and

offset errors in the OFS current source, remote-sense and

error amplifiers. Intersil specifies the guaranteed tolerance of

the ISL6334, ISL6334A to include the combined tolerances

of each of these elements.

between ISEN- and ISEN+ signals. Select the proper C to

T

keep the time constant of R

27ns.

and C (R x C ) close to

ISEN T

ISEN

T

Equation 7 shows the ratio of the channel current to the

sensed current I

R

.

SEN

SENSE

-----------------------

I

= I

⋅

(EQ. 7)

SEN

L

R

ISEN

The sensed average current I

is tied to FB internally.

AVG

This current will develop voltage drop across the resistor

between FB and VDIFF pins for droop control. ISL6334,

ISL6334A can not be used for non-droop applications.

The inductor DCR value will increase as the temperature

increases. Therefore, the sensed current will increase as the

temperature of the current sense element increases. In order

to compensate the temperature effect on the sensed current

signal, a Positive Temperature Coefficient (PTC) resistor can

The output of the error amplifier, V

, is compared to

COMP

sawtooth waveforms to generate the PWM signals. The

PWM signals control the timing of the Intersil MOSFET

drivers and regulate the converter output to the specified

reference voltage. The internal and external circuitry, which

control voltage regulation, are illustrated in Figure 6.

be selected for the sense resistor R

, or the integrated

ISEN

temperature compensation function of ISL6334, ISL6334A

should be utilized. The integrated temperature compensation

function is described in “External Temperature Compensation”

on page 24.

FN6482.0

February 26, 2008

15

ISL6334, ISL6334A

TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

EXTERNAL CIRCUIT ISL6334, ISL6334A INTERNAL CIRCUIT

R

C

COMP

DAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

R

REF

C

REF

+

-

V

FB

COMP

ERROR AMPLIFIER

+

V

-

R

FB

DROOP

I

AVG

VDIFF

VSEN

RGND

V

+

OUT

+

-

OUT

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

The ISL6334, ISL6334A incorporates an internal differential

remote-sense amplifier in the feedback path. The amplifier

removes the voltage error encountered when measuring the

output voltage relative to the local controller ground

reference point, resulting in a more accurate means of

sensing output voltage. Connect the microprocessor sense

pins to the non-inverting input, VSEN, and inverting input,

RGND, of the remote-sense amplifier. The remote-sense

output, V

, is connected to the inverting input of the error

DIFF

amplifier through an external resistor.

A digital-to-analog converter (DAC) generates a reference

voltage based on the state of logic signals at pins VID7

through VID0. The DAC decodes the eight 6-bit logic signal

(VID) into one of the discrete voltages shown in Table 2. All

VID pins have no internal pull-up current sources after t

After t , each VID input offers a minimum 30µA pull-up to

an internal 2.5V source for use with open-drain outputs. The

pull-up current diminishes to zero above the logic threshold

to protect voltage-sensitive output devices. External pull-up

resistors can augment the pull-up current sources in case

leakage into the driving device is greater than 30µA.

.

D3

TABLE 2. VR11 VID 8 BIT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

OFF

1.60000

1.59375

1.58750

1.58125

FN6482.0

February 26, 2008

16

ISL6334, ISL6334A

TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

FN6482.0

February 26, 2008

17

ISL6334, ISL6334A

TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

Load-Line Regulation

Some microprocessor manufacturers require a precisely

controlled output resistance. This dependence of output

voltage on load current is often termed “droop” or “load line”

regulation. By adding a well controlled output impedance,

the output voltage can effectively be level shifted in a

direction, which works to achieve the load-line regulation

required by these manufacturers.

In other cases, the designer may determine that a more

cost-effective solution can be achieved by adding droop.

Droop can help to reduce the output-voltage spike that

results from fast load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL

of the output capacitors selected. By positioning the no-load

voltage level near the upper specification limit, a larger

negative spike can be sustained without crossing the lower

limit. By adding a well controlled output impedance, the

output voltage under load can effectively be level shifted

down so that a larger positive spike can be sustained without

crossing the upper specification limit.

As shown in Figure 6, a current proportional to the average

current of all active channels, I

load-line regulation resistor R . The resulting voltage drop

across R is proportional to the output current, effectively

FB

creating an output voltage droop with a steady-state value

defined as shown in Equation 8:

, flows from FB through a

AVG

FB

V

= I

R

AVG FB

(EQ. 8)

DROOP

FN6482.0

February 26, 2008

18

ISL6334, ISL6334A

The regulated output voltage is reduced by the droop voltage

. The output voltage as a function of load current is

Once the desired output offset voltage has been determined,

use Equations 11 and 12 to calculate R

V

:

DROOP

OFS

derived by combining Equation 8 with the appropriate

sample current expression defined by the current sense

method employed, as shown in Equation 9:

For Positive Offset (connect R

to VCC):

OFS

1.6 × R

REF

(EQ. 11)

(EQ. 12)

-----------------------------

R

=

OFS

V

OFFSET

I

R

X

R

ISEN

⎛

⎞

⎟

⎠

LOAD

N

V

= V

– V

– ---------------- ----------------- R

⎜

OFS FB

(EQ. 9)

OUT

REF

⎝

For Negative Offset (connect R

to GND):

OFS

0.4 × R

REF

-----------------------------

where V

REF

programmed offset voltage, I

of the converter, R

is the reference voltage, V

is the

R

=

OFS

is the total output current

OFS

V

OFFSET

LOAD

is the sense resistor connected to

ISEN

Dynamic VID

the ISEN+ pin, and R is the feedback resistor, N is the

FB

Modern microprocessors need to make changes to their

core voltage as part of normal operation. They direct the

core-voltage regulator to do this by making changes to the

VID inputs during regulator operation. The power

management solution is required to monitor the DAC inputs

and respond to on-the-fly VID changes in a controlled

manner. Supervising the safe output voltage transition within

the DAC range of the processor without discontinuity or

disruption is a necessary function of the core-voltage

regulator.

active channel number, and R is the DCR, or R

X

depending on the sensing method.

SENSE

Therefore, the equivalent loadline impedance, i.e. Droop

impedance, is equal to Equation 10:

R

X

R

ISEN

FB

R

= ------------ -----------------

(EQ. 10)

LL

N

Output-Voltage Offset Programming

The ISL6334, ISL6334A allows the designer to accurately

adjust the offset voltage. When a resistor, R , is

In order to ensure the smooth transition of output voltage

during VID change, a VID step change smoothing network,

OFS

connected between OFS to VCC, the voltage across it is

regulated to 1.6V. This causes a proportional current (I

composed of R

and C

, as shown in Figure 7, can be

is based on the desired offset

)

REF

OFS

used. The selection of R

to flow into OFS. If R

is connected to ground, the voltage

REF

voltage as detailed in “Output-Voltage Offset Programming”

on page 19. The selection of C is based on the time

OFS

across it is regulated to 0.4V, and I

resistor between DAC and REF, R

flows out of OFS. A

OFS

, is selected so that

REF

duration for 1-bit VID change and the allowable delay time.

the product (I

x R ) is equal to the desired offset

OFS

voltage. These functions are shown in Figure 7.

Assuming the microprocessor controls the VID change at

1-bit every t , the relationship between the time constant

VID

FB

of R

and C

network and t

is given by Equation 13.

REF

VID

(EQ. 13)

C

R

= t

REF REF

VID

DAC

DYNAMIC

VID D/A

During dynamic VID transition and VID steps up, the

overcurrent trip point increases by 140% to avoid falsely

triggering OCP circuits, while the overvoltage trip point is set

to its maximum VID OVP trip level. If the dynamic VID occurs

at PSI# asserted, the system should exit PSI# and complete

the transition, and then resume PSI# operation 50µs after

the transition.

R

REF

E/A

REF

C

REF

Operation Initialization

VCC

OR

Prior to converter initialization, proper conditions must exist

on the enable inputs and VCC. When the conditions are met,

the controller begins soft-start. Once the output voltage is

within the proper window of operation, VR_RDY asserts

logic high.

GND

-

R

1.6V

OFS

+

0.4V

OFS

-

ISL6334, ISL6334A

Enable and Disable

GND

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL6334,

ISL6334A is released from shutdown mode.

VCC

FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING

FN6482.0

February 26, 2008

19

ISL6334, ISL6334A

1. The bias voltage applied at VCC must reach the internal

Soft-Start

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6334, ISL6334A are guaranteed. Hysteresis

between the rising and falling thresholds assure that once

enabled, ISL6334, ISL6334A will not inadvertently turn off

unless the bias voltage drops substantially (see

ISL6334, ISL6334A based VR has 4 periods during soft-start,

as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach

their POR/enable thresholds, the controller will have a fixed

delay period t . After this delay period, the VR will begin first

D1

soft-start ramp until the output voltage reaches 1.1V Vboot

voltage. Then, the controller will regulate the VR voltage at 1.1V

“Electrical Specifications” table beginning on page 8).

for another fixed period t . At the end of t period, ISL6334,

D3 D3

2. The ISL6334, ISL6334A features an enable input

(EN_PWR) for power sequencing between the controller

bias voltage and another voltage rail. The enable

comparator holds the ISL6334, ISL6334A in shutdown

until the voltage at EN_PWR rises above 0.875V. The

enable comparator has about 130mV of hysteresis to

prevent bounce. It is important that the driver reach their

POR level before the ISL6334, ISL6334A becomes

enabled. The schematic in Figure 8 demonstrates

sequencing the ISL6334, ISL6334A with the ISL66xx

family of Intersil MOSFET drivers, which require 12V

bias.

ISL6334A reads the VID signals. If the VID code is valid,

ISL6334, ISL6334A will initiate the second soft-start ramp until

the voltage reaches the VID voltage minus offset voltage.

The soft-start time is the sum of the 4 periods as shown in

Equation 14.

t

= t + t + t + t

D1 D2 D3 D4

(EQ. 14)

SS

t

is a fixed delay with the typical value as 1.36ms. t is

D3

D1

determined by the fixed 85µs plus the time to obtain valid

VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns.

3. The voltage on EN_VTT must be higher than 0.875V to

enable the controller. This pin is typically connected to the

output of VTT VR.

Therefore, the minimum t is about 86µs.

D3

During t and t , ISL6334, ISL6334A digitally controls the

D2 D4

DAC voltage change at 6.25mV per step. The time for each

step is determined by the frequency of the soft-start

oscillator, which is defined by the resistor R from SS pin to

SS

When all conditions previously mentioned are satisfied,

ISL6334, ISL6334A begins the soft-start and ramps the

output voltage to 1.1V first. After remaining at 1.1V for some

time, ISL6334, ISL6334A reads the VID code at VID input

pins. If the VID code is valid, ISL6334, ISL6334A will

regulate the output to the final VID setting. If the VID code is

OFF code, ISL6334, ISL6334A will shut down, and cycling

VCC, EN_PWR or EN_VTT is needed to restart.

GND. The second soft-start ramp time t and t can be

D2

D4

calculated based on Equations 15 and 16:

1.1xR

SS

-----------------------

(μs)

t

=

(EQ. 15)

(EQ. 16)

D2

D4

6.25x25

(V – 1.1)xR

VID

SS

ISL6334, ISL6334A INTERNAL CIRCUIT

EXTERNAL CIRCUIT

------------------------------------------------

t

=

(μs)

6.25x25

+12V

VCC

For example, when VID is set to 1.5V and the R is set at

SS

100kΩ, the first soft-start ramp time t will be 704µs and the

second soft-start ramp time t will be 256µs.

D4

D2

100kΩ

POR

ENABLE

COMPARATOR

CIRCUIT

EN_PWR

After the DAC voltage reaches the final VID setting,

+

-

VR_RDY will be set to high with the fixed delay t . The

D5

typical value for t is 85µs. Before the VR_RDY is

D5

9.1kΩ

released, the controller disregards the PSI# input and

always operates in normal CCM PWM mode.

0.875V

EN_VTT

+

-

VOUT, 500mV/DIV

0.875V

t

D3

t

D5

D2

D1

D4

SOFT-START

AND

FAULT LOGIC

EN_VTT

FIGURE 8. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

VR_RDY

500µs/DIV

FIGURE 9. SOFT-START WAVEFORMS

FN6482.0

February 26, 2008

20

ISL6334, ISL6334A

during the soft-start intervals t , t and t , the OVP

D1 D2 D3

Current Sense Output

threshold is 1.273V. Once the controller detects valid VID

input, the OVP trip point will be changed to DAC plus

175mV.

The current flowing out of the IMON pin is equal to the

sensed average current inside ISL6334, ISL6334A. In typical

applications, a resistor is placed from the IMON pin to GND

to generate a voltage, which is proportional to the load

current and the resistor value, as shown in Equation 17:

Two actions are taken by ISL6334, ISL6334A to protect the

microprocessor load when an overvoltage condition occurs.

R

X

R

ISEN

At the inception of an overvoltage event, all PWM outputs

are commanded low instantly (less than 20ns). This causes

the Intersil drivers to turn on the lower MOSFETs and pull

the output voltage below a level to avoid damaging the load.

When the VDIFF voltage falls below the DAC plus 75mV,

PWM signals enter a high-impedance state. The Intersil

drivers respond to the high-impedance input by turning off

both upper and lower MOSFETs. If the overvoltage condition

reoccurs, ISL6334, ISL6334A will again command the lower

MOSFETs to turn on. ISL6334, ISL6334A will continue to

protect the load in this fashion as long as the overvoltage

condition occurs.

IOUT

N

(EQ. 17)

V

= ------------------ -----------------I

IOUT

LOAD

where V

is the voltage at the IMON pin, R

IMON

is the

IMON

resistor between the IMON pin and GND, I

output current of the converter, R

connected to the ISEN+ pin, N is the active channel number,

and R is the DC resistance of the current sense element,

either the DCR of the inductor or R

sensing method.

is the total

LOAD

is the sense resistor

ISEN

X

depending on the

SENSE

The resistor from the IMON pin to GND should be chosen to

ensure that the voltage at the IMON pin is less than 1.11V

under the maximum load current. If the IMON pin voltage is

higher than 1.11V, overcurrent shutdown will be triggered, as

described in “Overcurrent Protection” on page 21.

Once an overvoltage condition is detected, normal PWM

operation ceases until ISL6334, ISL6334A is reset. Cycling

the voltage on EN_PWR, EN_VTT or VCC below the

POR-falling threshold will reset the controller. Cycling the

VID codes will not reset the controller.

A small capacitor can be placed between the IMON pin and

GND to reduce the noise impact. If this pin is not used, tie it

to GND.

VR_RDY

Fault Monitoring and Protection

The ISL6334, ISL6334A actively monitors output voltage and

current to detect fault conditions. Fault monitors trigger

protective measures to prevent damage to a microprocessor

load. One common power-good indicator is provided for linking

to external system monitors. The schematic in Figure 10

outlines the interaction between the fault monitors and the

VR_RDY signal.

UV

50%

105µA

+

DAC

SOFT-START, FAULT

AND CONTROL LOGIC

OC

-

I

AVG

VR_RDY Signal

The VR_RDY pin is an open-drain logic output which

indicates that the soft-start period has completed and the

output voltage is within the regulated range. VR_RDY is

pulled low during shutdown and releases high after a

1.11V

VDIFF

+

OV

OC

IMON

-

successful soft-start and a fixed delay t . VR_RDY will be

D5

VID + 0.175V

pulled low when an undervoltage or overvoltage condition is

detected, or the controller is disabled by a reset from

EN_PWR, EN_VTT, POR, or VID OFF-code.

FIGURE 10. VR_RDY AND PROTECTION CIRCUITRY

Undervoltage Detection

Overcurrent Protection

The undervoltage threshold is set at 50% of the VID code.

When the output voltage at VSEN is below the undervoltage

threshold, VR_RDY is pulled low.

ISL6334, ISL6334A has two levels of overcurrent protection.

Each phase is protected from a sustained overcurrent

condition by limiting its peak current, while the combined

phase currents are protected on an instantaneous basis.

Overvoltage Protection

In instantaneous protection mode, ISL6334, ISL6334A

Regardless of the VR being enabled or not, the ISL6334,

ISL6334A overvoltage protection (OVP) circuit will be active

after its POR. The OVP thresholds are different under

different operation conditions. When VR is not enabled and

utilizes the sensed average current I

to detect an

AVG

overcurrent condition. See “Channel-Current Balance” on

page 15 for more details on how the average current is

FN6482.0

February 26, 2008

21

ISL6334, ISL6334A

measured. The average current is continually compared with

Thermal Monitoring (VR_HOT/VR_FAN)

a constant 105µA reference current, as shown in Figure 10.

Once the average current exceeds the reference current, a

comparator triggers the converter to shutdown.

There are two thermal signals to indicate the temperature

status of the voltage regulator: VR_HOT and VR_FAN. Both

VR_FAN and VR_HOT pins are open-drain outputs, and

external pull-up resistors are required. Those signals are

valid only after the controller is enabled.

The current out of IMON pin is equal to the sensed average

current I

. With a resistor from IMON to GND, the voltage

AVG

at IMON will be proportional to the sensed average current

and the resistor value. The ISL6334, ISL6334A continuously

monitors the voltage at IMON pin. If the voltage at IMON pin

is higher than 1.11V, a comparator triggers the overcurrent

shutdown. By increasing the resistor between IMON and

GND, the overcurrent protection threshold can be adjusted

to be less than 105µA. For example, the overcurrent

The VR_FAN signal indicates that the temperature of the

voltage regulator is high and more cooling airflow is needed.

The VR_HOT signal can be used to inform the system that

the temperature of the voltage regulator is too high and the

CPU should reduce its power consumption. The VR_HOT

signal may be tied to the CPU’s PROC_HOT signal.

The diagram of thermal monitoring function block is shown in

Figure 12. One NTC resistor should be placed close to the

power stage of the voltage regulator to sense the operational

temperature, and one pull-up resistor is needed to form the

voltage divider for the TM pin. As the temperature of the

power stage increases, the resistance of the NTC will

reduce, resulting in the reduced voltage at the TM pin.

Figure 13 shows the TM voltage over the temperature for a

typical design with a recommended 6.8kΩ NTC (P/N:

NTHS0805N02N6801 from Vishay) and 1kΩ resistor RTM1.

We recommend using those resistors for the accurate

temperature compensation.

threshold for the sensed average current I

95µA by using a 11.8kΩ resistor from IMON to GND.

can be set to

AVG

At the beginning of overcurrent shutdown, the controller

places all PWM signals in a high-impedance state within

20ns, commanding the Intersil MOSFET driver ICs to turn off

both upper and lower MOSFETs. The system remains in this

state a period of 4096 switching cycles. If the controller is still

enabled at the end of this wait period, it will attempt a

soft-start. If the fault remains, the trip-retry cycles will

continue indefinitely (as shown in Figure 11) until either

controller is disabled or the fault is cleared. Note that the

energy delivered during trip-retry cycling is much less than

during full-load operation, so there is no thermal hazard

during this kind of operation.

There are two comparators with hysteresis to compare the

TM pin voltage to the fixed thresholds for VR_FAN and

VR_HOT signals respectively. The VR_FAN signal is set to

high when the TM voltage is lower than 39.1% of VCC

voltage, and is pulled to GND when the TM voltage

increases to above 45.1% of VCC voltage. The VR_FAN

signal is set to high when the TM voltage goes below 33.3%

of VCC voltage, and is pulled to GND when the TM voltage

goes back to above 39.1% of VCC voltage. Figure 14 shows

the operation of those signals.

OUTPUT CURRENT

0A

OUTPUT VOLTAGE

VCC

VR_FAN

0V

2ms/DIV

FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE.

0.391V_CC

R_TM1

F

= 500kHz

SW

VR_HOT

TM

For the individual channel overcurrent protection, ISL6334,

ISL6334A continuously compares the sensed current signal

of each channel with the 129µA reference current. If one

channel current exceeds the reference current, ISL6334,

ISL6334A will pull PWM signal of this channel to low for the

rest of the switching cycle. This PWM signal can be turned

on next cycle if the sensed channel current is less than the

129µA reference current. The peak current limit of individual

channel will not trigger the converter to shutdown.

^oc

R_NTC

0.333V_CC

FIGURE 12. BLOCK DIAGRAM OF THERMAL MONITORING

FUNCTION

FN6482.0

February 26, 2008

22

ISL6334, ISL6334A

Since the voltage across inductor is sensed for the output

current information, the sensed current has the same

positive temperature coefficient as the inductor DCR.

100

90

80

70

60

50

40

30

20

In order to obtain the correct current information, there

should be a way to correct the temperature impact on the

current sense component. ISL6334, ISL6334A provides two

methods: integrated temperature compensation and external

temperature compensation.

Integrated Temperature Compensation

When the TCOMP voltage is equal or greater than VCC/15,

ISL6334, ISL6334A will utilize the voltage at TM and

TCOMP pins to compensate the temperature impact on the

sensed current. The block diagram of this function is shown

in Figure 15.

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

FIGURE 13. THE RATIO OF TM VOLTAGE TO NTC

TEMPERATURE WITH RECOMMENDED PARTS

TM

V_CC

I_sen4

0.451*Vcc

0.391*Vcc

0.333*Vcc

CHANNEL

CURRENT

SENSE

I_sen3

R_TM1

I_sen2

NON-LINEAR

A/D

TM

I_sen1

I₄

I₃

I₂

I₁

VR_FAN

VR_HOT

^oc

R_NTC

TEMPERATURE

k_i

D/A

V_CC

T1

T2

T3

R_TC1

FIGURE 14. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE

4-BIT

A/D

TCOMP

DROOP AND

OVERCURRENT

PROTECTION

Based on the NTC temperature characteristics and the

desired threshold of the VR_HOT signal, the pull-up resistor

RTM1 of TM pin is given by Equation 18:

R_TC2

R

= 2.75xR

NTC(T3)

(EQ. 18)

TM1

FIGURE 15. BLOCK DIAGRAM OF INTEGRATED

TEMPERATURE COMPENSATION

R

is the NTC resistance at the VR_HOT threshold

NTC(T3)

When the TM NTC is placed close to the current sense

temperature T3.

component (inductor), the temperature of the NTC will track

the temperature of the current sense component. Therefore

the TM voltage can be utilized to obtain the temperature of

the current sense component.

The NTC resistance at the set point T2 and release point T1 of

VR_FAN signal can be calculated as shown in Equations 19

and 20:

R

= 1.267xR

(EQ. 19)

NTC(T2)

NTC(T3)

Based on VCC voltage, ISL6334, ISL6334A converts the TM

pin voltage to a 6-bit TM digital signal for temperature

compensation. With the non-linear A/D converter of

ISL6334, ISL6334A, the TM digital signal is linearly

proportional to the NTC temperature. For accurate

temperature compensation, the ratio of the TM voltage to the

NTC temperature of the practical design should be similar to

that in Figure 13.

R

= 1.644xR

(EQ. 20)

NTC(T1)

NTC(T3)

With the NTC resistance value obtained from Equations 19

and 20, the temperature value T2 and T1 can be found from

the NTC datasheet.

Depending on the location of the NTC and the airflow, the

NTC may be cooler or hotter than the current sense

component. The TCOMP pin voltage can be utilized to

correct the temperature difference between NTC and the

current sense component. When a different NTC type or

Temperature Compensation

The ISL6334, ISL6334A supports inductor DCR sensing, or

resistive sensing techniques. The inductor DCR has a

positive temperature coefficient, which is about +0.385%/°C.

FN6482.0

February 26, 2008

23

ISL6334, ISL6334A

different voltage divider is used for the TM function, the

TCOMP voltage can also be used to compensate for the

difference between the recommended TM voltage curve in

Figure 14 and that of the actual design. According to the

VCC voltage, ISL6334, ISL6334A converts the TCOMP pin

voltage to a 4-bit TCOMP digital signal as TCOMP factor N.

11. If the output voltage increases over 2mV as the

temperature increases, i.e. V2 - V1 > 2mV, reduce N and

redesign R ; if the output voltage decreases over 2mV

TC2

as the temperature increases, i.e. V1 - V2 > 2mV,

increase N and redesign R

.

TC2

External Temperature Compensation

By pulling the TCOMP pin to GND, the integrated

temperature compensation function is disabled. In addition,

one external temperature compensation network, shown in

Figure 16, can be used to cancel the temperature impact on

the droop (i.e., load line).

The TCOMP factor N is an integer between 0 and 15. The

integrated temperature compensation function is disabled for

N = 0. For N = 4, the NTC temperature is equal to the

temperature of the current sense component. For N < 4, the

NTC is hotter than the current sense component. The NTC is

cooler than the current sense component for N > 4. When

N > 4, the larger TCOMP factor N, the larger the difference

between the NTC temperature and the temperature of the

current sense component.

ISL6334,

ISL6334A

INTERNAL

CO M P

CIRCUIT

ISL6334, ISL6334A multiplexes the TCOMP factor N with

the TM digital signal to obtain the adjustment gain to

compensate the temperature impact on the sensed channel

current. The compensated channel current signal is used for

droop and overcurrent protection functions.

FB

^oC

ISEN

VDIFF

Design Procedure

1. Properly choose the voltage divider for the TM pin to

match the TM voltage vs temperature curve with the

recommended curve in Figure 13.

FIGURE 16. EXTERNAL TEMPERATURE COMPENSATION

The sensed current will flow out of the FB pin and develop a

2. Run the actual board under the full load and the desired

cooling condition.

droop voltage across the resistor equivalent (R ) between

the FB and VDIFF pins. If R resistance reduces as the

FB

temperature increases, the temperature impact on the droop

can be compensated. An NTC resistor can be placed close to

FB

3. After the board reaches the thermal steady state, record

the temperature (T

) of the current sense component

CSC

(inductor or MOSFET) and the voltage at TM and VCC

pins.

the power stage and used to form R . Due to the non-linear

FB

temperature characteristics of the NTC, a resistor network is

needed to make the equivalent resistance between the FB

and VDIFF pins reverse proportional to the temperature.

4. Use Equation 21 to calculate the resistance of the TM

NTC, and find out the corresponding NTC temperature

T

from the NTC datasheet.

NTC

The external temperature compensation network can only

compensate the temperature impact on the droop, while it has

no impact to the sensed current inside ISL6334, ISL6334A.

Therefore, this network cannot compensate for the

V

xR

TM

TM1

(EQ. 21)

R

= -------------------------------

NTC(T

)

V

– V

NTC

CC

TM

5. Use Equation 22 to calculate the TCOMP factor N:

209x(T

– T

)

NTC

temperature impact on the overcurrent protection function.

CSC

(EQ. 22)

-------------------------------------------------------

N =

+ 4

3xT

+ 400

NTC

General Design Guide

6. Choose an integral number close to the above result for

the TCOMP factor. If this factor is higher than 15, use

N = 15. If it is less than 1, use N = 1.

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following. In addition to this guide, Intersil provides complete

reference designs, which include schematics, bills of

materials, and example board layouts for all common

microprocessor applications.

7. Choose the pull-up resistor R

TC1

(typical 10kΩ);

8. If N = 15, one does not need the pull-down resistor R

.

TC2

If otherwise, obtain R

using Equation 23:

TC2

NxR

TC1

15 – N

----------------------

=

(EQ. 23)

R

TC2

9. Run the actual board under full load again with the proper

resistors connected to the TCOMP pin.

Power Stages

The first step in designing a multiphase converter is to

determine the number of phases. This determination

depends heavily upon the cost analysis, which in turn

depends on system constraints that differ from one design to

10. Record the output voltage as V1 immediately after the

output voltage is stable with the full load. Record the

output voltage as V2 after the VR reaches the thermal

steady state.

FN6482.0

February 26, 2008

24

ISL6334, ISL6334A

the next. Principally, the designer will be concerned with

whether components can be mounted on both sides of the

circuit board; whether through-hole components are

permitted; and the total board space available for power

supply circuitry. Generally speaking, the most economical

solutions are those in which each phase handles between

15A and 25A. All surface-mount designs will tend toward the

lower end of this current range. If through-hole MOSFETs

and inductors can be used, higher per-phase currents are

possible. In cases where board space is the limiting

constraint, current can be pushed as high as 40A per phase,

but these designs require heat sinks and forced air to cool

the MOSFETs, inductors and heat-dissipating surfaces.

the lower-MOSFET body-diode reverse-recovery charge, Q ;

rr

and the upper MOSFET r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 26,

the required time for this commutation is t and the

1

approximated associated power loss is P

.

UP,1

t

I

⎛

⎜

⎝

⎞

⎟

⎠

1

M

PP

2

⎛

⎝

⎞

(EQ. 26)

P

≈ V

f

S

----

----- + --------

UP,1

IN

⎠

2

N

MOSFETs

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 27, the

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct; the switching

frequency; the capability of the MOSFETs to dissipate heat;

and the availability and nature of heat sinking and air flow.

2

approximate power loss is P

.

UP,2

I

t

2

⎛I

⎞ ⎛

⎞

⎟

⎠

PP

2

M

(EQ. 27)

P

≈ V

f

S

-------- ----

⎟ ⎜

⎜

⎝

----- –

UP,2

IN

N

⎠ ⎝

LOWER MOSFET POWER CALCULATION

The calculation for heat dissipated in the lower MOSFET is

simple, since virtually all of the heat loss in the lower

MOSFET is due to current conducted through the channel

A third component involves the lower MOSFET’s reverse-

recovery charge, Q . Since the inductor current has fully

rr

commutated to the upper MOSFET before the lower-

resistance (r

). In Equation 24, I is the maximum

DS(ON)

M

MOSFET’s body diode can draw all of Q , it is conducted

rr

continuous output current; I is the peak-to-peak inductor

PP

through the upper MOSFET across VIN. The power

current (see Equation 1); d is the duty cycle (V

/V ); and

OUT IN

dissipated as a result is P

Equation 28:

and is approximated in

UP,3

L is the per-channel inductance.

2

I

(1 – d)

⎛

⎜

⎝

⎞

⎟

⎠

P

= V

Q f

I

(EQ. 28)

L, PP

(EQ. 24)

UP,3

IN rr S

M

P

= r

(1 – d) + --------------------------------

-----

LOW, 1

DS(ON)

12

N

Finally, the resistive part of the upper MOSFET’s is given in

Equation 29 as P

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

.

UP,4

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 26, 27, and 28. Since the power equations

depend on MOSFET parameters, choosing the correct

MOSFETs can be an iterative process involving repetitive

solutions to the loss equations for different MOSFETs and

different switching frequencies, as shown in Equation 29.

diode forward voltage at I , V

; the switching

M

D(ON)

frequency, F ; and the length of dead times, t and t , at

sw d1 d2

the beginning and the end of the lower-MOSFET conduction

interval respectively.

⎛

⎜

⎝

⎞

⎟

⎠

I

M

N

I

(EQ. 25)

2

⎛

⎝

⎞

⎠

M

PP

2

PP

2

P

= V

F

D(ON) sw

t

d2

+

I

PP

--------

⎛

⎜

⎝

⎞

⎟

⎠

----- + --------

----- –

I

M

N

LOW, 2

d1

(EQ. 29)

N

P

≈ r

d +

d

---------

12

-----

UP,4

DS(ON)

Thus the total maximum power dissipated in each lower

MOSFET is approximated by the summation of P

Current Sensing Resistor

and

LOW,1

The resistors connected to the Isen+ pins determine the

gains in the load-line regulation loop and the channel-current

balance loop as well as setting the overcurrent trip point.

Select values for these resistors by using Equation 30:

P

.

LOW,2

Upper MOSFET Power Calculation

In addition to r losses, a large portion of the upper-

DS(ON)

MOSFET losses are due to currents conducted across the

input voltage (V ) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

Upper MOSFET losses can be divided into separate

R

I

OCP

N

X

(EQ. 30)

R

= -------------------------- -------------

–

ISEN

IN

6

105 ×10

where R

ISEN

is the sense resistor connected to the ISEN+

pin, N is the active channel number, R is the resistance of

X

components involving the upper-MOSFET switching times;

the current sense element, either the DCR of the inductor or

R

depending on the sensing method, and I

is the

OCP

SENSE

FN6482.0

February 26, 2008

25

ISL6334, ISL6334A

desired overcurrent trip point. Typically, I

OCP

can be chosen

Based on the desired loadline R , the loadline regulation

LL

to be 1.2 times the maximum load current of the specific

application.

resistor can be calculated using Equation 33:

N

R

LL

ISEN

R

X

R

= ---------------------------------

(EQ. 33)

FB

With integrated temperature compensation, the sensed

current signal is independent on the operational temperature

of the power stage, i.e. the temperature effect on the current

where N is the active channel number, R

is the sense

resistor connected to the ISEN+ pin, and R is the

ISEN

X

sense element R is cancelled by the integrated

X

resistance of the current sense element, either the DCR of

the inductor or R depending on the sensing method.

temperature compensation function. R in Equation 30

X

SENSE

should be the resistance of the current sense element at the

room temperature.

If one or more of the current sense resistors are adjusted for

thermal balance (as in Equation 31), the load-line regulation

resistor should be selected based on the average value of

the current sensing resistors, as given in Equation 34:

When the integrated temperature compensation function is

disabled by pulling the TCOMP pin to GND, the sensed

current will be dependent on the operational temperature of

the power stage, since the DC resistance of the current

sense element may be changed according to the operational

R

LL

R

= ----------

R

ISEN(n)

(EQ. 34)

∑

FB

R

X

n

temperature. R in Equation 30 should be the maximum DC

resistance of the current sense element at the all operational

temperature.

where R is the current sensing resistor connected to

ISEN(n)

the n ISEN+ pin.

X

th

Compensation

In certain circumstances, it may be necessary to adjust the

value of one or more ISEN resistors. When the components

of one or more channels are inhibited from effectively

dissipating their heat so that the affected channels run hotter

than desired, choose new, smaller values of RISEN for the

affected phases (see the section entitled “Channel-Current

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in Load-Line Regulation, there are two distinct

methods for achieving these goals.

COMPENSATING LOAD-LINE REGULATED

CONVERTER

Balance” on page 15). Choose R

in proportion to the

ISEN,2

desired decrease in temperature rise in order to cause

proportionally less current to flow in the hotter phase, as

shown in Equation 31:

The load-line regulated converter behaves in a similar

manner to a peak-current mode controller because the two

poles at the output-filter L-C resonant frequency split with

the introduction of current information into the control loop.

The final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

ΔT

2

(EQ. 31)

R

= R

----------

ISEN,2

ISEN

ΔT

1

In Equation 31, make sure that ΔT is the desired temperature

2

compensation components, R and C .

C

rise above the ambient temperature, and ΔT is the measured

1

temperature rise above the ambient temperature. While a

single adjustment according to Equation 31 is usually

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator by compensating the L-C

poles and the ESR zero of the voltage-mode approximation

yields a solution that is always stable with very close to ideal

transient performance.

sufficient, it may occasionally be necessary to adjust R

two or more times to achieve optimal thermal balance

between all channels.

ISEN

Load-Line Regulation Resistor

The load-line regulation resistor is labelled R in Figure 6.

FB

Its value depends on the desired loadline requirement of the

application.

The desired loadline can be calculated using Equation 32:

V

DROOP

R

= ------------------------

(EQ. 32)

LL

I

FL

where I is the full load current of the specific application,

FL

and VR

is the desired voltage droop under the full

DROOP

load condition.

FN6482.0

February 26, 2008

26

ISL6334, ISL6334A

The optional capacitor C , is sometimes needed to bypass

2

C

(OPTIONAL)

2

noise away from the PWM comparator. Keep a position

available for C , and be prepared to install a high-frequency

capacitor of between 10pF and 100pF in case any

leading-edge jitter problem is noted.

2

C

R

C

COMP

FB

Once selected, the compensation values in Equation 35

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

+

improved by making adjustments to R . Slowly increase the

R

FB

V

C

DROOP

value of R while observing the transient performance on an

C

-

oscilloscope until no further improvement is noted. Normally,

VDIFF

C

will not need adjustment. Keep the value of C from

C

Equation 35 unless some performance issue is noted.

FIGURE 17. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6334, ISL6334A

CIRCUIT

Output Filter Design

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter necessarily limits the

system transient response. The output capacitor must

supply or sink load current while the current in the output

inductors increases or decreases to meet the demand.

The feedback resistor, R , has already been chosen as

FB

outlined in “Load-Line Regulation Resistor” on page 26.

Select a target bandwidth for the compensated system, f .

0

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

compensation components depend on the relationships of f

0

to the L-C pole frequency and the ESR zero frequency. For

each of the three cases which follow, there is a separate set

of equations for the compensation components.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ΔI;

the load-current slew rate, di/dt; and the maximum allowable

1

------------------- > f

Case 1:

0

2π LC

2πf V

LC

PP

0

R

C

= R ------------------------------------

C

FB

0.75V

IN

0.75V

IN

output-voltage deviation under transient loading, ΔV

.

= ------------------------------------

MAX

2πV

R

f

PP FB 0

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

1

-------------------

≤ f < -----------------------------

0

2πC(ESR)

Case 2:

2π LC

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will initially

deviate by an amount approximated by the voltage drop across

the ESL. As the load current increases, the voltage drop across

the ESR increases linearly until the load current reaches its final

value. The capacitors selected must have sufficiently low ESL

and ESR so that the total output-voltage deviation is less than

the allowable maximum. Neglecting the contribution of inductor

current and regulator response, the output voltage initially

2

V

(2π)

f

LC

0

PP

R

C

= R --------------------------------------------

(EQ. 35)

C

FB

0.75 V

IN

0.75V

IN

= ------------------------------------------------------------

2

(2π)

f

V

R

LC

0

PP FB

1

Case 3:

f > -----------------------------

0

2πC(ESR)

2π f V

L

pp

deviates by an amount, as shown in Equation 36:

di

0

R

C

= R

-----------------------------------------

FB

C

0.75 V (ESR)

(EQ. 36)

ΔV ≈ (ESL) ---- + (ESR) ΔI

IN

dt

0.75V (ESR)

C

IN

= -------------------------------------------------

2πV

The filter capacitor must have sufficiently low ESL and ESR

so that ΔV < ΔV

R

f

L

PP FB 0

.

MAX

In Equation 35, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent-series resistance of

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

the bulk output-filter capacitance; and V is the sawtooth

PP

amplitude described in the “Electrical Specifications” table

beginning on page 8.

FN6482.0

February 26, 2008

27

ISL6334, ISL6334A

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

0.3

0.2

0.1

0

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see “Interleaving” on

page 12 and Equation 2), a voltage develops across the

bulk-capacitor ESR equal to I

(ESR). Thus, once the

C,PP

output capacitors are selected, the maximum allowable

ripple voltage, V , determines the lower limit on the

PP(MAX)

inductance, as shown in Equation 37.

I

= 0

L,PP

= 0.5 I

O

⎛

⎝

⎞

V

– N V

IN

OUT

⎠

= 0.75 I

0.2

O

(EQ. 37)

L

(ESR)

≥

-----------------------------------------------------------

f V

V

IN PP(MAX)

S

0

0.4

0.6

0.8

1.0

DUTY CYCLE (V /V

)

IN

O

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 2-PHASE CONVERTER

0.3

I

= 0

I

= 0.5 I

O

L,PP

ΔV

. This places an upper limit on inductance.

MAX

= 0.25 I

= 0.75 I

O

L,PP

O

L,PP

Equation 38 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 39

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

0.2

0.1

0

0.2

0.4

0.6

0.8

1.0

2NCV

O

(EQ. 38)

DUTY CYCLE (V

V

)

L ≤ --------------------- ΔV

– ΔI(ESR)

O/ IN

MAX

2

(

)

ΔI

FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 3-PHASE CONVERTER

(EQ. 39)

(

)

1.25 NC

⎛

⎝

⎞

– V

O

L ≤ ------------------------- ΔV

– ΔI(ESR)

V

For a 2-phase design, use Figure 18 to determine the input-

capacitor RMS current requirement given the duty cycle,

MAX

IN

2

⎠

(

ΔI

maximum sustained output current (I ), and the ratio of the

O

Switching Frequency Selection

per-phase peak-to-peak inductor current (I

) to I . Select

L,PP

O

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper-MOSFET loss calculation. These effects are

outlined in “MOSFETs” on page 25, and they establish the

upper limit for the switching frequency. The lower limit is

established by the requirement for fast transient response

and small output-voltage ripple as outlined in “Output Filter

Design” on page 27. Choose the lowest switching frequency

that allows the regulator to meet the transient-response

requirements.

a bulk capacitor with a ripple current rating which will

minimize the total number of input capacitors required to

support the RMS current calculated. The voltage rating of

the capacitors should also be at least 1.25 times greater

than the maximum input voltage.

Figures 19 and 20 provide the same input RMS current

information for three and four phase designs respectively.

Use the same approach to selecting the bulk capacitor type

and number as previously described.

Low capacitance, high-frequency ceramic capacitors are

needed in addition to the bulk capacitors to suppress leading

and falling edge voltage spikes. The result from the high

current slew rates produced by the upper MOSFETs turn on

and off. Select low ESL ceramic capacitors and place one as

close as possible to each upper MOSFET drain to minimize

board parasitic impedances and maximize suppression.

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

FN6482.0

February 26, 2008

28

ISL6334, ISL6334A

Layout Considerations

0.3

0.2

0.1

0

I

= 0

= 0.25 I

I

= 0.5 I

O

L,PP

= 0.75 I

O

The following layout strategies are intended to minimize the

impact of board parasitic impedances on converter

performance and to optimize the heat-dissipating capabilities

of the printed-circuit board. These sections highlight some

important practices which should not be overlooked during the

layout process.

Component Placement

Within the allotted implementation area, orient the switching

components first. The switching components are the most

critical because they carry large amounts of energy and tend

to generate high levels of noise. Switching component

placement should take into account power dissipation. Align

the output inductors and MOSFETs such that space between

the components is minimized while creating the PHASE

plane. Place the Intersil MOSFET driver IC as close as

possible to the MOSFETs they control to reduce the parasitic

impedances due to trace length between critical driver input

and output signals. If possible, duplicate the same placement

of these components for each phase.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

0.6

0.4

0.2

Next, place the input and output capacitors. Position one high-

frequency ceramic input capacitor next to each upper

MOSFET drain. Place the bulk input capacitors as close to the

upper MOSFET drains as dictated by the component size and

dimensions. Long distances between input capacitors and

MOSFET drains result in too much trace inductance and a

reduction in capacitor performance. Locate the output

capacitors between the inductors and the load, while keeping

them in close proximity to the microprocessor socket.

I

= 0

= 0.5 I

= 0.75 I

L,PP

O

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

Voltage-Regulator (VR) Design Materials

FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS

The tolerance band calculation (TOB) worksheets for VR

output regulation and IMON have been developed using the

Root-Sum-Squared (RSS) method with 3 sigma distribution

point of the related components and parameters. Note that

the “Electrical Specifications” table beginning on page 8

specifies no less than 6 sigma distribution point, not suitable

for RSS TOB calculation. Intersil also developed a set of

worksheets to support VR design and layout. Contact

Intersil’s local office or field support for the latest available

information.

CURRENT vs DUTY CYCLE FOR SINGLE-PHASE

CONVERTER

MULTIPHASE RMS IMPROVEMENT

Figure 21 is provided as a reference to demonstrate the

dramatic reductions in input-capacitor RMS current upon the

implementation of the multiphase topology. For example,

compare the input RMS current requirements of a 2-phase

converter versus that of a single phase. Assume both

converters have a duty cycle of 0.25, maximum sustained

output current of 40A, and a ratio of I

to I of 0.5. The

L,PP

single phase converter would require 17.3A

O

current

RMS

capacity while the two-phase converter would only require

10.9A . The advantages become even more pronounced

RMS

when output current is increased and additional phases are

added to keep the component cost down relative to the

single phase approach.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6482.0

February 26, 2008

29

ISL6334, ISL6334A

Package Outline Drawing

L40.6x6

40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 10/06

4X

4.5

6.00

0.50

36X

A

6

B

31

40

PIN #1 INDEX AREA

6

30

1

PIN 1

INDEX AREA

4 . 10 ± 0 . 15

21

10

(4X)

0.15

11

20

0.10 M C A B

TOP VIEW

40X 0 . 4 ± 0 . 1

4

0 . 23 +0 . 07 / -0 . 05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

0 . 90 ± 0 . 1

BASE PLANE

( 5 . 8 TYP )

(

SEATING PLANE

0.08 C

SIDE VIEW

4 . 10 )

( 36X 0 . 5 )

5

C

0 . 2 REF

( 40X 0 . 23 )

0 . 00 MIN.

0 . 05 MAX.

( 40X 0 . 6 )

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6482.0

February 26, 2008

30


型号：	ISL6622A,
厂家：	Intersil
描述：	VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring VR11.1 ， 4相PWM控制器，具有轻载效率的提高和负载电流监控监控控制器
文件：	总30页 (文件大小：560K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6622A, [INTERSIL]

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