ISL6444CA_技术文档

ISL6444

®

Data Sheet

May 2002

FN9069.1

Dual PWM Controller with DDR Memory

Option for Gateway Applications

Features

• Provides regulated output voltage in the range 0.9V–5.5V

- High efficiency over wide load range

The ISL6444 PWM controller provides high efficiency and

regulation for two output voltages adjustable in the range from

0.9V to 5.5V that are required to power I/O, chip-sets, and

memory banks in high-performance notebook computers,

PDAs, and Internet appliances.

- Synchronous buck converter with hysteretic operation at

light load

• Complete DDR memory power solution

- VTT tracks VDDQ/2

- VDDQ/2 buffered reference output

• No current-sense resistor required

Synchronous rectification and hysteretic operation at light

loads contribute to a high efficiency over a wide range of

loads. The hysteretic mode of operation can be disabled

separately on each PWM converter if continuous conduction

operation is desired for all load levels. Efficiency is even

- Uses MOSFET’s R

DS(ON)

- Optional current-sense resistor for precision overcurrent

• Undervoltage lock-out on VCC pin

• Dual mode operation

further enhanced by using MOSFET’s R

sense component.

as a current

DS(ON)

- Operates directly from battery 5.0-24V input

- Operates from 3.3V or 5V system rail

• Excellent dynamic response

Feed-forward ramp modulation, current mode control

scheme, and internal feed-back compensation provide fast

response to load transients. Out-of-phase operation with a

180^ophase shift reduces the input current ripple.

- Combined voltage feed-forward and current mode

control

• Power-good signal for each channel

• 300kHz switching frequency

The controller can be transformed in a complete DDR

memory power supply solution by activating a DDR pin. In

DDR mode of operation one of the channels tracks the

output voltage of another channel and provides output

current sink and source capability–features essential for

proper powering of DDR chips. The buffered reference

voltage required by this type of memory is also provided.

- Out-of-phase operation for reduced input ripple

- In-phase operation in DDR mode for reduced channel

interference

- Out-of-phase operation with 90^ophase shift for two-

stage conversion in DDR mode

Applications

The ISL6444 monitors the output voltages. Each PWM

controller generates a PGOOD (power good) signal when

the soft-start is completed and the output is within ±10% of

the set point.

•

Residential and Enterprise Gateways

• DSL Modems

• Routers and Switchers

A built-in overvoltage protection prevents output voltage

from going above 115% of the set point. Normal operation

automatically restores when the overvoltage conditions go

away. Undervoltage protection latches the chip off when

either output drops below 75% of its set value after the soft-

start sequence for this output is completed. An adjustable

overcurrent function monitors the output current by sensing

the voltage drop across the lower MOSFET. If precision

current-sensing is required, an external current-sense

resistor may optionally be used.

Pinout

ISL6444 (SSOP-28)

VCC

1

2

3

4

5

6

7

8

GND

LGATE1

PGND1

28

27

26

25

24

23

22

LGATE2

PGND2

PHASE2

UGATE2

PHASE1

UGATE1

BOOT1

BOOT2

ISEN2

EN2

ISEN1

EN1

The IC comes in a 28 lead SSOP package.

21

VOUT2

VSEN2

20

19

18

17

16

9

VOUT1

VSEN1

Ordering Information

10

o

PART NUMBER

TEMP. ( C)

PACKAGE

PKG. NO.

M28.15

OCSET2

SOFT2

OCSET1 11

12

ISL6444CA

-10 to 85

28 Ld SSOP

SOFT1

PG2/REF

13

14

DDR

VIN

ISL6444CA-T

-10 to 85

28 Ld SSOP

Taped and

Reeled

M28.15

15 PG1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

ISL6444

Generic Application Circuits

+V

IN

=+5V... +24V

Q1

V

OUT1

L1

(+1.8V)

PWM1

OCSET1

Q2

C1

Q3

Q4

V

OUT2

L2

OCSET2

DDR

PWM2

(+1.2V)

C2

ISL6444 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY

+5V

+V

IN

+5V...24V

Q1

V

OUT1

DDR

VDDQ

(+2.5V)

L1

OCSET1

PWM1

Q2

C1

R

OCSET2

Q3

Q4

V

VTT

(+1.25V)

V

OUT2

OUT3

L2

DDR REF

(+1.25V)

PWM2

C2

PGOOD2/REF

ISL6444 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY

2

ISL6444

Absolute Maximum Ratings

Thermal Information

o

Bias Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V

cc

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V

PHASE, BOOT, ISEN, UGATE . . . . . . . . . . . . . GND-0.3V to +33.0V

BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V

in

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

78

o

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V + 0.3V

cc

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

(SSOP - Lead Tips Only)

Recommended Operating Conditions

Bias Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V ±5%

cc

Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V to +24.0V

in

o

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -10 C to 85 C

Junction Temperature Range . . . . . . . . . . . . . . . . . -10 C to 125 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY

Bias Current

I

LGATEx, UGATEx Open, VSENx forced above

regulation point, DDR=0, VIN>5V

-

2.2

-

3.2

30

mA

CC

Shut-down Current

VCC UVLO

I

µA

CCSN

Rising Vcc Threshold

Falling Vcc Threshold

VIN

V

4.3

4.1

4.65

4.35

4.75

4.45

V

CCU

CCD

V

Input Voltage Pin Current (Sink)

Input Voltage Pin Current (Source)

Shut-down Current

OSCILLATOR

I

10

-

-15

-

30

-30

1

µA

VIN

I

VINO

I

-

VINS

PWM1 Oscillator Frequency

Ramp Amplitude, pk-pk

Ramp Offset

F

255

300

2

345

kHz

V

c

V

Vin= 16V, by design

Vin= 5V, by design

By design

-

R1

R2

1.25

0.5

125

250

V

ROFF

Ramp/V Gain

IN

G

Vin≥ 3V, by design

1 ≤ Vin ≤ 3V, by design

mV/V

RB1

RB2

Ramp/V Gain

IN

G

REFERENCE AND SOFT START

Internal Reference Voltage

Reference Voltage Accuracy

Soft-Start Current During Start-up

Soft-Start Complete Threshold

PWM CONVERTERS

V

-

-1.0

-

0.9

-

+1.0

-

V

%

µA

V

REF

I

-5

SOFT

V

By design

1.5

ST

Load Regulation

0.0mA < I

By design

< 5.0A; 5.0V < V

BATT

< 24.0V -2.0

-

+2.0

120

65

%

nA

VOUT1

VSEN pin bias current

I

50

40

80

55

VSEN

VOUT pin input impedance

I

VOUT = 5V

kOhm

VOUT

3

ISL6444

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER

Undervoltage Shut-Down Level

Overvoltage Shut-Down

SYMBOL

TEST CONDITIONS

MIN

70

TYP

MAX

85

UNITS

%

V

Fraction of the set point; ~2µs noise filter

UVL

V

110

-

130

%

OVP1

GATE DRIVERS

Upper Drive Pull-Up Resistance

Upper Drive Pull-Down Resistance

Lower Drive Pull-Up Resistance

Lower Drive Pull-Down Resistance

POWER GOOD AND CONTROL FUNCTIONS

Power Good Lower Threshold

Power Good Higher Threshold

R

V

=4.5V

-

8

15

5

Ω

2UGPUP

CC

3.2

8

2UGPDN

R

15

3

2LGPUP

1.8

2LGPDN

V

Fraction of the set point; ~3µs noise filter

-13

12

-

-7

%

PG-

V

Fraction of the set point; ~3µs noise filter.

16

PG+

Guaranteed by design.

PGOODx Leakage Current

PGOODx Voltage Low

EN - Low (Off)

I

V

= 5.5V

-

1

0.85

0.8

-

µA

V

PGLKG

PULLUP

= -4mA

PGOOD

V

I

-

0.5

PGOOD

-

V

EN - High (On)

2.5

-

V

CCM Enforced (Hysteretic Operation

Inhibited)

VOUTX pulled low

0.1

V

Automatic CCM/Hysteretic Operation Enabled

DDR - Low (Off)

VOUTX connected to the output

0.9

-

0.8

-

V

DDR - High (On)

2.5

DDR REF Output Voltage

V

DDR=1, I

=0...10mA

0.99*

V

1.01*

DDREF

REF

OC2

10

V

OC2

-

OC2

16

DDR REF Output Current

I

DDR=1. Guaranteed by design.

mΑ

DDREF

4

ISL6444

SOFT1, SOFT2 (Pin 12, 17)

Functional Pin Description

These pins provide soft-start function for their respective

controllers. When the chip is enabled, the regulated 5µA

pull-up current source charges the capacitor connected from

the pin to ground. The output voltage of the converter follows

the ramping voltage on the SOFT pin.

GND (Pin 1)

Signal ground for the IC.

LGATE1, LGATE2 (Pin 2, 27)

These are outputs of the lower MOSFET drivers.

DDR (Pin 13)

PGND1, PGND2 (Pin 3, 26)

This pin, when high, transforms dual channel chip into

complete DDR memory solution. The OCSET2 pin becomes

an input to provide the required tracking function. The

channel synchronization is changed from out-of-phase to in-

phase. The PG2/REF pin becomes the output of the

VDDQ/2 buffered voltage that is used as a reference voltage

by the second channel.

These pins provide the return connection for lower gate

drivers. These pins are connected to sources of the lower

MOSFETs of their respective converters.

PHASE1, PHASE2 (Pin 4, 25)

The PHASE1 and PHASE2 points are the junction points of

the upper MOSFET sources, output filter inductors, and

lower MOSFET drains. Connect these pins to the respective

converter’s upper MOSFET source.

VIN (Pin 14)

Provides battery voltage to the oscillator for feed-forward

rejection of the input voltage variation.

UGATE1, UGATE2 (Pin 5, 24)

These pins provide the gate drive for the upper MOSFETs.

When connected to ground via 100kΩ resistor while the

DDR pin is high, this pin commands the out-of-phase 90^o

channels synchronization for reduces inter-channel

interference.

BOOT1, BOOT2 (Pin 6, 23)

These pins power the upper MOSFET drivers of the PWM

converter. Connect this pin to the junction of the bootstrap

capacitor with the cathode of the bootstrap diode. Anode of

the bootstrap diode is connected to the VCC pin.

PG1 (Pin 15)

PGOOD1 is an open drain output used to indicate the status

of the output voltage. This pin is pulled low when the first

channel output is not within ±10% of the set value.

ISEN1, ISEN2 (Pin 7, 22)

These pins are used to monitor the voltage drop across the

lower MOSFET for current feedback and overcurrent

protection. For precise current detection these inputs can be

connected to the optional current sense resistors placed in

series with the source of the lower MOSFETs.

PG2/REF (Pin 16)

This pin has a double function depending on the mode the

chip is operating. When the chip is used as a dual channel

PWM controller (DDR=0), the pin provides a PGOOD2

function for the second channel. The pin is pulled low when

the second channel output is not within ±10% of the set value.

EN1, EN2 (Pin 8, 21)

These pins enable operation of the respective converter

when high. When both pins are low, the chip is disabled and

only low leakage current <1uA is taken from Vcc and Vin.

In DDR mode (DDR=1), this pin serves as an output of the

buffer amplifier that provides VDDQ/2 reference voltage

applied to the OCSET2 pin.

VOUT1, VOUT2 (Pin 9, 20)

OCSET2 (Pin 18)

These pins when connected to the converters’ respective

outputs provide the output voltage inside the chip to reduce

output voltage excursion during HYS/PWM transition. When

connected to ground, the se pins command forced

converters operate in continuous conduction mode at all

load levels.

In a dual channel application (DDR=0), a resistor from this

pin to ground sets the over current threshold for the second

controller.

In the DDR application (DDR=1), this pin sets the output

voltage of the buffer amplifier and the second controller and

should be connected to the center point of a divider from the

VDDQ output.

VSEN1, VSEN2 (Pin 10, 19)

These pins are connected to the resistive dividers that set

the desired output voltage. The PGOOD, UVP, and OVP

circuits use this signal to report output voltage status.

VCC (Pin 28)

This pin powers the controller.

OCSET1 (Pin 11)

A resistor from this pin to ground sets the over current

threshold for the first controller.

6

ISL6444

1.5V, the power good (PGOOD), the mode control, and the

fault functions are enabled, as depicted in Figure 1.

Description

Operation

The ISL6444 is a dual channel PWM controller intended for

use in power supplies for graphic chipset, SDRAM, DDR

DRAM or other low voltage power applications in modern

notebook and sub-notebook PCs. The IC integrates two

control circuits for two synchronous buck converters. The

output voltage of each controller can be set in the range of

0.9V to 5.5V by an external resistive divider. Out-of-phase

operation with 180 degree phase shift reduces input current

ripple.

EN

1

1.5V

0.9V

SOFT

2

VOUT

3

PGOOD

4

The synchronous buck converters can operate from either

an unregulated DC source such as a notebook battery with a

voltage ranging from 5.0V to 24V, or from a regulated

system rail of 3.3V or 5V. In either mode of operation the

controller is biased from the +5V source.

Ch1 5.0V

Ch3 1.0V

Ch2 2.0V

Ch4 5.0V

M1.00ms

FIGURE 1. START UP

The controllers operate in the current mode with input

voltage feed-forward for simplified feedback loop

compensation and reduced effect of the input voltage

variation. An integrated feedback loop compensation

dramatically reduces the number of external components.

This completes the soft start sequence. Further rise of pin

voltage does not affect the output voltage. During the soft-

start, the converter always operates in continuous

conduction mode independently of the load level or FCCM

pin potential.

Depending on the load level, converters can operate either

in a fixed-frequency mode or in a hysteretic mode. Switch-

over to the hysteretic mode operation at light loads improves

the converters' efficiency and prolongs battery run time. The

hysteretic mode of operation can be inhibited independently

for each channel if a variable frequency operation is not

desired.

The soft-start time (the time from the moment when EN

becomes high to the moment when PGOOD is reported) is

determined by the following equation.

1.5V × Csoft

T

= ----------------------------------

SOFT

5µA

The time it takes the output voltage to come into regulation

can be obtained from the following equation.

The ISL6444 has a special means to rearrange its internal

architecture into a complete DDR solution. When DDR input

is set high, the second channel can provide the capability to

track the output voltage of the first channel. The buffered

reference voltage required by DDR memory chips is also

provided.

T

= 0.6 × T

SOFT

RISE

Having such a spread between the time when the output

voltage reaches the regulation point and the moment when

PGOOD is reported allows for a fault-safe test mode by

means of an external circuit that clamps the SOFT pin

voltage on the level 0.9V<V

<1.5V.

SOFT

Initialization

Output Voltage Program

The ISL6444 initializes if at least one of the enable pins is

set high. The Power-On Reset (POR) function continually

monitors the bias supply voltage on the VCC pin and initiates

soft-start operation after the input supply voltage exceeds

4.5V. Should this voltage drop lower than 4.0V, the POR

disables the chip.

The output voltage of either channel is set by a resistive divider

from the output to ground. The center point of the divider is

connected to VSEN pin as shown in Figure 2. The output

voltage value is determined by the following equation.

0.9V • (R1 + R2)

V

= ---------------------------------------------

O

R2

Soft-Start

Where 0.9V is the value of the internal reference. The VSEN

pin voltage is also used by the controller for the power good

function and to detect undervoltage and overvoltage

conditions.

When soft start is initiated, the voltage on the SOFT pin of

the enabled channel starts to ramp gradually due to the 5µA

current sourced into the external soft-start capacitor. The

output voltage starts to follow the soft-start voltage.

Automatic Operation Mode Control

When the SOFT pin voltage reaches a level of 0.9V, the

output voltage comes into regulation while the soft-start pin

voltage continues to rise. When the SOFT voltage reaches

In nominal currents the synchronous buck converter

operates in continuous-conduction constant-frequency

mode. This mode of operation achieves higher efficiency

due to the substantially lower voltage drop across the

7

ISL6444

synchronous MOSFET compared to a Shottky diode. In

contrast, continuous-conduction operation in load currents

lower than the inductor critical value results in lower

efficiency. In this case, during a fraction of a switching cycle,

the direction of the inductor current changes to the opposite

actively discharging the output filter capacitor.

Hysteretic Operation

When the critical inductor current is detected, the converter

enters hysteretic mode. The PWM comparator and the error

amplifier that provided control in the CCM mode are inhibited

and the hysteretic comparator is now activated. A change is

also made to the gate logic. In hysteretic mode the

synchronous rectifier MOSFET is controlled in diode

emulation mode, hence conduction in the second quadrant

is prohibited.

Vin

Q1

L1

UGATE

ISEN

R

CS

VOUT

t

C1

Cz

Q2

R1

R2

LGATE

VOUT

VSEN

IIND

t

PHASE

OCSET

R

COMP

ISL6444

OC

t

1

2 3 4 5 6 7 8

Hysteretic

MODE

PWM

FIGURE 2. OUTPUT VOLTAGE PROGRAM

OF

t

OPERATION

To maintain the output voltage in regulation, the discharged

energy should be restored during the consequent cycle of

operation by the cost of increased circulating current and

losses associated with it.

FIGURE 3. CCM -- HYSTERETIC TRANSITION

VOUT

IIND

t

The critical value of the inductor current can be estimated by

the following expression.

(V – V ) • V

IN

O

I

= --------------------------------------------------

HYS

2 • F

• L • V

O IN

SW

t

1

2

3

4

5

6 7 8

PHASE

COMP

To improve converter efficiency in loads lower than critical,

the switch-over to variable frequency hysteretic operation

with diode emulation is implemented into the PWM scheme.

The switch-over is provided automatically by the mode

control circuit that constantly monitors the inductor current

and alters the way the PWM signal is generated.

t

MODE

Hysteretic

PWM

OF

OPERATION

FIGURE 4. HYSTERETIC -- CCM TRANSITION

The voltage across the synchronous MOSFET at the

moment of time just before the upper-MOSFET turns on is

monitored for purposes of mode change. When the

converter operates in currents higher than critical, this

voltage is always positive as shown in Figure 3 and 4. In

currents lower than critical, the voltage is always negative.

The mode control circuit uses a sign of voltage across the

synchronous devices to determine if the load current is

higher or lower than the critical value.

The hysteretic comparator initiates the PWM signal when the

output voltage gets below the lower threshold and

terminates the PWM signal when the output voltage rises

over the upper threshold. A spread or hysteresis between

these two thresholds determines the switching frequency

and the peak value of the inductor current. A transition to a

constant frequency CCM mode will happen when the load

current gets to a level higher than the critical:

∆V

hys

To prevent chatter between operating modes, the circuit

looks for eight sequential matching sign signals before it

makes its decision to perform a mode change. The same

algorithm is true for both CCM-hysteretic and hysteretic-

CCM transitions.

---------------------

≈

I

CCM

2 • ESR

Where, ∆V = 15mV, is a hysteretic comparator window,

hys

ESR is the equivalent series resistance of the output

capacitor.

8

ISL6444

Because of different control mechanisms, the value of the

load current where transition into CCM operation takes place

is usually higher compared to the load level at which

transition into hysteretic mode had occurred.

where: Ro -- is load resistance and Co -- is load

capacitance. For this type of modulator, a Type 2

compensation circuit is usually sufficient.

Figure 5 shows a Type 2 amplifier and its response along

with the responses of the current mode modulator and the

converter. The Type 2 amplifier, in addition to the pole at

origin, has a zero-pole pair that causes a flat gain region at

frequencies in between the zero and the pole.

VOUT pin and Forced Continuous Conduction Mode

(FCCM)

The error amplifier that provides control over the converter

during CCM mode is excluded from the regulation loop in the

hysteretic mode. Due to that, its output voltage eventually

runs away from the operation point that is normally related to

the desired output voltage. When the converter transitions

from hysteretic mode of operation into CCM, the output

voltage transient can occur as it takes some time for the

error amplifier to catch-up with regulation.

1

F

= ------------------------------ = 6kHz ;

Z

2π ⋅ R ⋅ C

2

1

F

= ------------------------------ = 600kHz ;

2π ⋅ R ⋅ C

P

1

2

This region is also associated with phase ‘bump’ or

reduced phase shift. The amount of phase shift reduction

depends on how wide the region of flat gain is and has a

maximum value of 90^o. To further simplify the converter

compensation, the modulator gain is kept independent of

the input voltage variation by providing feed-forward of V_IN

to the oscillator ramp.

To reduce undesirable effects of the error amplifier run away

during mode change, the exact value of the output voltage is

provided to the internal circuit via the VOUT pin, Figure 2.

In case the hysteretic mode of operation is not required, the

controller can be put in a forced continuous conduction

mode (FCCM) of operation. That can be accomplished by

connecting the VOUT pin to ground, which disables the

mode control circuit.

C2

C1

R2

Converter

R1

Such dual function of the VOUT pin enhances applicability of

the controller and allows for lower pin count.

EA

Type 2 EA

Feedback Loop Compensation

G

=18dB

M

To reduce the number of external components and remove

the burden of determining compensation components from a

system designer, both PWM controllers have internally

compensated error amplifiers. To make internal

compensation possible several design measures where

taken.

G

=14dB

EA

Modulator

F

Z

P

F

PO

F

C

First, the ramp signal applied to the PWM comparator is

proportional to the input voltage provided via the VIN pin.

This keeps the modulator gain constant when the input

voltage varies. The second, the load current proportional

signal is derived from the voltage drop across the lower

MOSFET during the PWM time interval and is added to the

amplified error signal on the comparator input. This

effectively creates an internal current control loop. The

resistor connected to the ISEN pin sets the gain in the

current feedback loop. The following expression estimates

the required value of the current sense resistor depending

on the maximum load current and the value of the

FIGURE 5. FEEDBACK LOOP COMPENSATION

The zero frequency, the amplifier high-frequency gain, and

the modulator gain are chosen to satisfy most typical

applications. The crossover frequency will appear at the

point where the modulator attenuation equals the amplifier

high frequency gain. The only task that the system designer

has to complete is to specify the output filter capacitors to

position the load main pole somewhere within one decade

lower than the amplifier zero frequency. With this type of

compensation plenty of phase margin is easily achieved due

to zero-pole pair phase ‘boost’.

MOSFET’s R

.

DS(ON)

Conditional stability may occur only when the main load pole

is positioned too much to the left side on the frequency axis

due to excessive output filter capacitance. In this case, the

ESR zero placed within 10kHz...50kHz range gives some

additional phase ‘boost’. Some phase boost can also be

I

⋅ R

MAX

DS(ON)

R

= ------------------------------------------- – 100Ω

CS

75µA

Due to implemented current feedback, the modulator has a

single pole response with -1 slope at a frequency

determined by the load

achieved by connecting capacitor C in parallel with the

upper resistor R1 of the divider that sets the output voltage

value, as shown in Figure 2.

1

z

F

= -------------------------------- ,

PO

2π ⋅ R ⋅ C

O

9

ISL6444

If the lower MOSFET current exceeds the overcurrent

Gate Control Logic

threshold, a pulse skipping circuit is activated. The upper

MOSFET will not be turned on as long as the sensed

current is higher then the threshold value. This limits the

current supplied by the DC voltage source. This condition

keeps on for eight clock cycles after the overcurrent

comparator was tripped for the first time. If after these first

eight clock cycles the current exceeds the overcurrent

threshold again in a time interval of another eight clock

cycles, the overcurrent protection latches and disables the

chip. If the overcurrent condition goes away during the first

eight clock cycles, normal operation is restored and the

overcurrent circuit resets itself sixteen clock cycles after the

overcurrent threshold was exceeded the first time, Figure 6.

The gate control logic translates generated PWM signals

into gate drive signals providing necessary amplification,

level shift, and shoot-trough protection. Also, it bears some

functions that help to optimize the IC performance over a

wide range of the operational conditions. As MOSFET

switching time can very dramatically from type to type and

with the input voltage, the gate control logic provides

adaptive dead time by monitoring real gate waveforms of

both the upper and the lower MOSFETs.

Dual-Step Conversion

The ISL6444 dual channel controller can be used either in

power systems with a single-stage power conversion when

the battery power is converted into the desired output

voltage in one step, or in the systems where some

intermediate voltages are initially established. The choice of

the approach may be dictated by the overall system design

criteria or simply to be a matter of voltages available to the

system designer, like in the case of PCI card applications.

PGOOD

1

8 CLK

IL

Shutdown

2

VOUT

When the power input voltage is a regulated 5V or 3.3V

system bus, the feed-forward ramp may become too

shallow, which creates the possibility of duty-factor jitter

especially in a noisy environment. The noise susceptibility

when operating from low level regulated power sources can

be improved by connecting the VIN pin to ground via a

resistor. The internal pull-up current source of ~15µA will

create a voltage drop across the resistor. If this voltage is

lower than 2.5V, the feed-forward ramp generator will be

internally reconnected from the VIN pin to the VCC pin and

the ramp slew rate will be doubled. Application circuits for

dual-step power conversion are presented in Figure 10.

3

Ch1 5.0V

Ch2 100mV

M 10.0µs

Ch3 1.0AΩ

FIGURE 6. OVERCURRENT PROTECTION WAVEFORMS

If load step is strong enough to pull output voltage lower

than the undervoltage threshold, the chip shuts down

immediately.

Because of the nature of the used current sensing

technique, and to accommodate wide range of the R

DS(ON)

variation, the value of the overcurrent threshold should

represent overload current about 150%...180% of the

nominal value. If accurate current protection is desired, a

current sense resistor placed in series with the lower

MOSFET source may be used.

Protections

The converter output is monitored and protected against

extreme overload, short circuit, overvoltage, and

undervoltage conditions.

A sustained overload on the output sets the PGOOD low and

latches-off the whole chip. The controller operation can be

restored by cycling the VCC voltage or an enable (EN) pin.

Overvoltage Protection

Should the output voltage increase over 115% of the normal

value due to the upper MOSFET failure, or other reasons,

the overvoltage protection comparator will force the

synchronous rectifier gate driver high. This action actively

pulls down the output voltage and eventually attempts to

blow the battery fuse. As soon as the output voltage drops

below the threshold, the OVP comparator is disengaged.

Overcurrent Protection

Both PWM controllers use the lower MOSFET’s

on-resistance -- R

to monitor the current for

DS(ON)

protection against shorted outputs. The sensed current

from the ISEN pin is compared with a current set by a

resistor connected from the OCSET pin to ground,.

This OVP scheme provides a ‘soft’ crowbar function which

helps to tackle severe load transients and does not invert the

output voltage when activated -- a common problem for OVP

schemes with a latch.

11.2V • (R

+ 100Ω)

CS

R

= -----------------------------------------------------------

OCSET

I

• R

OC

DS(ON)

Where, I

is a desired overcurrent protection threshold and

is the value of the current sense resistor connected to

OC

R

CS

the I

pin.

SEN

10

ISL6444

The PG2 pin function is also different in DDR mode. This pin

becomes the output of the buffer, which input is connected

via the OCSET2 pin to the center point of the R/R divider

from the VDDQ output. The buffer output voltage serves as

1.25V reference for the DDR memory chips. Current

capability of this pin is about 10mA.

Overtemperature Protection

The chip incorporates an over temperature protection circuit

that shuts the chip down when the die temperature of 150 C

o

is reached. Normal operation restores at die temperatures

o

below 125 C through the full soft-start cycle.

DDR Application

For the VTT channel some control and protective functions

can be significantly simplified as this output is derived from

the VDDQ output. For example, the overcurrent and

overvoltage protections for the second controller are

disabled when the DDR pin is set high. The hysteretic mode

of operation is also disabled on the VTT channel to allow

sinking capability to be independent from the load level. As

the VTT channel tracks the VDDQ/2 voltage, the soft-start

function is not required and the SOFT2 pin may be left open

or may be connected to VCC.

Double Data Rate (DDR) memory chips are expected to take

a place of memory of choice in many newly designed

computers including high-end notebooks due to increased

throughput. A novelty feature associated with this type of

memory is new referencing and data bus termination

techniques. These techniques employ a reference voltage,

VREF, that tracks the center point of VDDQ and VSS

voltages and an additional VTT power source to which all

terminating resistors are connected. Despite the additional

power source, the overall memory power consumption is

reduced compared to traditional termination.

Channel Synchronization in DDR

Applications

The added power source has a cluster of requirements that

should be observed and considered. Due to reduced

differential thresholds of DDR memory, the termination

power supply voltage, VTT, shall closely track VDDQ/2

voltage. Another very important feature for the termination

power supply is a capability to equally operate in sourcing

and sinking modes. The VTT supply shall regulate the output

voltage with the same degree of precision when current is

floating from the supply to the load and when the current is

diverted back from the load into the power supply. The last

mode of operation usually conflicts with the way most PWM

controllers operate.

Presence of two PWM controllers on the same die require

channel synchronization to reduce inter channel interference

that may cause the duty factor jitter and increased output

ripple. The PWM controller is mostly susceptible to noise

when an error signal on the input of the PWM comparator

approaches the decision making point. False triggering can

occur causing jitter and affecting the output regulation.

Out-of-phase operation is a common approach to

synchronize dual channel converters as it reduces an input

current ripple and provides a minimum interference for

channels that control different voltage levels. When used in

DDR application with cascaded converters (VTT generated

from VDDQ), the turn-on of the upper MOSFET in the VDDQ

channel happens to be just before the decision making point

in the VTT channel that is running with a duty-factor close to

50%, Figure 7 and Figure 8. This makes out-of-phase

channel synchronization undesirable when one of the

channels is running on a duty-factor of 50%. Inversely, the

in-phase channel arrangement does not have this drawback.

Points of decision are far from noisy moments of time in both

sourcing and sinking modes of operation for Vin=7.5V to 24V

as it is shown in Figure 7.

The ISL6444 dual channel PWM controller possesses

several important means that allow re configuration for this

particular application and provide all three voltages required

in DDR memory compliant computer.

To reconfigure the ISL6444 for a complete DDR solution, the

DDR pin shall be permanently set high. The simplest way to

do that is to connect it to the VCC rail. This activates some

functions inside the chip that are specific to the DDR

memory power needs.

In DDR application presented in Figure 12, the first controller

regulates VDDQ rail to 2.5V. The output voltage is set by an

external divider R3 and R4. The second controller regulates

the VTT rail to VDDQ/2. The OCSET2 pin function is now

different. The pin serves now as an input that brings VDDQ/2

voltage created by R5 and R6 divider inside the chip. That

effectively provides a tracking function for the VTT voltage.

11

ISL6444

In the case when power for VDDQ is taken from the +5V

system rail, as Figure 8 shows, both in-phase and out-of-

phase approaches are susceptible to noise in the sourcing

mode.

Noise immunity can be improved by operating the VTT

converter with a 90^ophase shift. As the time diagrams in

Figure 8 show, the points of concern are always about a

quarter of the period away from the noise emitting

transitions.

300kHz CLOCK

VDDQ

SOURCING

VTT

OUT-OF-PHASE

VTT

OUT-OF-PHASE

SINKING

SOURCING

VTT

SOURCING

IN-PHASE

VTT

IN-PHASE

SINKING

SOURCING

VTT

FIGURE 7. CHANNEL INTRFEARENCE Vin=7.5V...24V

o

90 PHASE SHIFT

SINKING

FIGURE 8. CHANNEL INTERFERENCE Vin=5V

Several ways of synchronization are implemented into the

chip. When the DDR pin is connected to GND, the channels

operate 180^oout-of-phase. In the DDR mode when the DDR

pin is connected to VCC, the channels operate either in-

phase when the VIN pin is connected to the input voltage

source, or with 90^ophase shift if the VIN pin is connected to

GND via the 100kOhm resistor.

12

ISL6444

ISL6444 DC-DC Converter Application Circuits

Figures 9 and 10 show application circuits of a dual channel

DC/DC converter for a notebook PC.

The power supply shown in Figure 12 generates +2.5V

VDDQ voltage from a battery. The +1.25V VTT termination

voltage tracks VDDQ/2 and is derived from +2.5V VDDQ. To

complete the DDR memory power requirements, the +1.25V

reference voltage is also provided. The PG2 pin serves as

an output for the reference voltage in this mode.

The power supply in Figure 9 provides +V2.5S and +V1.8S

voltages for memory and graphic interface chipset from

+5.0-24VDC battery voltage.

Figure 10 shows the power supply that provides +V2.5S and

+V1.8S voltages for memory and graphic interface chipset

from +5.0V system rail.

Figure 13 depicts the DDR solution in the case where the 5V

system rail is used as a primary voltage source.

For detailed information on the circuit, including a Bill-of-

Materials and circuit board description, see Application Note

AN9995. Also see Intersil’s web site (http://www.intersil.com)

for the latest information.

Figure 11 shows an application circuit for a single-output

split input power supply with current sharing for advanced

graphic card applications.

Figure 12 and 13 show application circuits of a complete

power solution for DDR memory that becomes a preferred

choice in modern computers.

+5.0-24V

GND

IN

C2

56µF

C1

1µF

+

+5.0V

cc

C3

+

C4

0.01µF

CR1

VIN

12

VCC

28

C5

10µF

CR2

0.01µF

SOFT1

SOFT2

14

17

23

BOOT1

BOOT2

6

Q1

Q3

1/2 IRF7313

C7

0.1µF

C6

0.1µF

UGATE1

PHASE1

UGATE2

PHASE2

5

4

24

25

+V1_8

(2A)

L1

10µH

+V2_5S

(3A)

L2

10µH

R1

2k

ISEN1

R2

2k

ISEN2

7

22

27

C8

+

C9

+

ISL6444

330µF

LGATE1

330µF

LGATE2

Q2

2/2 IRF7313

2

Q4

2/2 IRF7313

R3

R5

R4

PGND1

VSEN1

PGND2

VSEN2

3

26

19

10

VOUT1

EN1

R6

VOUT2

EN2

9

8

20

21

16

PG1

PG2/REF

15

11

OCSET2 R8

OCSET1

R7

18

13

1

DDR

GND

FIGURE 9. DUAL OUTPUT APPLICATION CIRCUIT FOR ONE-STEP CONVERSION

13

ISL6444

R9

100k

+5.0V

GND

cc

C1

C3

0.01µF

+

C4

0.01µF

C2

56µF

CR1

VIN

12

1µF

VCC

CR2

SOFT1

SOFT2

14

28

17

23

BOOT1

BOOT2

6

Q1

Q3

1/2 IRF7313

C7

0.1µF

C6

0.1µF

UGATE1

PHASE1

UGATE2

PHASE2

5

4

24

25

L1

+V1_8

(2A)

L2

4.7µH

+V2_5S

(3A)

4.7µH

R1

2k

ISEN1

R2

2k

ISEN2

7

22

27

C8

330µF

+

C9

330µF

+

ISL6444

LGATE1

LGATE2

Q2

2/2 IRF7313

2

Q4

2/2 IRF7313

R3

R5

R4

PGND1

VSEN1

PGND2

VSEN2

3

26

19

10

VOUT1

EN1

R6

VOUT2

EN2

9

8

20

21

16

PG1

PG2/REF

15

11

OCSET2 R8

OCSET1

R7

18

13

1

DDR

GND

FIGURE 10. DUAL OUTPUT APPLICATION CIRCUIT FOR TWO-STEP CONVERSION

14

ISL6444

+12.0V

C1

10µF

GND

+5.0V

C3

0.01µF

SOFT1

+

C4

0.01µF

CR1

VIN

12

VCC

C5

10µF

CR2

SOFT2

14

28

17

BOOT1

BOOT2

6

23

Q1

Q3

1/2 IRF7313

C7

0.1µF

C6

0.1µF

UGATE1

PHASE1

UGATE2

PHASE2

5

4

24

25

L1

10.0µH

L2

4.7µH

R1

2k

ISEN1

R2

2k

ISEN2

7

22

C8

+

C9

+

ISL6444

330µF

LGATE1

330µF

LGATE2

Q2

2

27

Q4

2/2 IRF7313

R3

2/2 IRF7313

R4

6.89k

PGND1

VSEN1

PGND2

VSEN2

3

26

19

10

VOUT1

EN1

VOUT2

EN2

R6

10K

R5

10K

9

8

20

21

16

PG1

PG2/REF

15

11

OCSET2 R8

OCSET1

R7

18

13

1

DDR

GND

R9 0.01

R10 0.01

C10

330µF

C11

330µF

+

VOUT

+1.5V

(8A)

FIGURE 11. SINGLE-OUTPUT SPLIT INPUT POWER SUPPLY

15

ISL6444

+5.6-24V

GND

IN

C1, C2

10µF

+5.0V

cc

C3

0.01µF

+

CR1

VIN

12

VCC

28

C5

10µF

CR2

SOFT1

SOFT2

BOOT2

14

17

23

BOOT1

6

Q1

Q3

1/2 IRF7313

C7

0.1µF

C6

UGATE1

PHASE1

UGATE2

PHASE2

5

4

24

25

0.1µF

VTT

+1.25V

VDDQ

+2.5V

(6A)

L1

4.7µH

L2

1.5µH

R1

680

LGATE1

ISEN1

R2

499

LGATE2

ISEN2

(3A)

7

22

27

C8

+

C9

+

ISL6444

330µF

Q2

2/2 IRF7313

2

Q4

2/2 IRF7313

R3

PGND1

VSEN1

32k4

PGND2

VSEN2

3

26

19

10

VOUT1

EN1

VOUT2

EN2

R4

9

20

VREF

18k2

1.25V

8

EN1

21

16

(10mA)

PG1

PG2/REF

15

11

OCSET1

R7

OCSET2

R5

18

13

1

18k2

DDR

VCC

GND

R6

C10

0.01µF

18k2

FIGURE 12. APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SOLUTION WITH ONE-STEP CONVERSION

16

ISL6444

R9

100k

+5.0V

GND

cc

C1, C2

C3

0.01µF

10µF

CR1

VIN

12 14

VCC

28

CR2

SOFT1

SOFT2

BOOT2

17

23

BOOT1

6

Q1

Q3

1/2 IRF7313

C7

0.1µF

C6

0.1µF

UGATE1

PHASE1

UGATE2

PHASE2

5

4

24

25

VDDQ

+2.5V

(6A)

VTT

+1.25V

L1

L2

1.5µH

4.7µH

R1

1k

ISEN1

R2

5.9k

LGATE2

ISEN2

(3A)

7

22

27

C8

330µF

+

C9

330µF

+

ISL6444

LGATE1

Q2

2/2 IRF7313

2

Q4

2/2 IRF7313

R3

PGND1

VSEN1

32k4

PGND2

VSEN2

3

26

19

10

VOUT1

EN1

VOUT2

EN2

R4

9

8

20

VREF

1.25V

18k2

EN1

21

16

(10mA)

PG1

PG2/REF

15

OCSET1

R7

OCSET2

R5

18

11

1

13

18k2

DDR

GND

R6

C10

0.01µF

VCC

18k2

FIGURE 13. APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SOLUTION WITH TWO-STEP CONVERSION

17

ISL6444

Shrink Small Outline Plastic Packages (SSOP)

M28.15

N

28 LEAD SHRINK NARROW BODY SMALL OUTLINE

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MIN

MILLIMETERS

GAUGE

PLANE

-B-

SYMBOL

MAX

0.069

0.010

0.061

0.012

0.010

0.394

0.157

MIN

1.35

0.10

-

MAX

1.75

0.25

1.54

0.30

0.25

10.00

3.98

NOTES

A

A1

A2

B

0.053

0.004

-

1

2

3

-

L

-

0.25

0.010

SEATING PLANE

A

0.008

0.007

0.386

0.150

0.20

0.18

9.81

3.81

9

-A-

o

D

h x 45

C

D

E

-

3

-C-

α

4

A2

e

A1

e

0.025 BSC

0.635 BSC

-

C

B

0.10(0.004)

H

h

0.228

0.0099

0.016

0.244

0.0196

0.050

5.80

0.26

0.41

6.19

0.49

1.27

-

0.17(0.007) M

C

A M B S

5

L

6

NOTES:

N

α

28

7

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

o

0

8

0

8

-

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Rev. 0 2/95

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch)

per side.

5. The chamfer on the body is optional. If it is not present, a visual in-

dex feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dam-

bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”

dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

18


型号：	ISL6444CA
厂家：	Intersil
描述：	Dual PWM Controller with DDR Memory Option for Gateway Applications 双PWM控制器， DDR内存选项为网关应用开关光电二极管栅双倍数据速率控制器
文件：	总18页 (文件大小：438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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