ISL6443_技术文档

ISL6443

®

Data Sheet

October 4, 2005

FN9044.1

300kHz Dual, 180° Out-of-Phase, Step-

Down PWM and Single Linear Controller

Features

• Wide Input Supply Voltage Range

- 5.6V to 24V

The ISL6443 is a high-performance, triple-output controller

optimized for converting wall adapter, battery or network

intermediate bus DC input supplies into the system supply

voltages required for a wide variety of applications. Each

output is adjustable down to 0.8V. The two PWMs are

synchronized 180° out of phase reducing the RMS input

current and ripple voltage.

- 4.5V to 5.6V

• Three Independently Programmable Output Voltages

• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .300kHz

• Out of Phase PWM Controller Operation

- Reduces Required Input Capacitance and Power

Supply Induced Loads

The ISL6443 incorporates several protection features. An

adjustable overcurrent protection circuit monitors the output

current by sensing the voltage drop across the lower

MOSFET. Hiccup mode overcurrent operation protects the

DC/DC components from damage during output

overload/short circuit conditions. Each PWM has an

independent logic-level shutdown input (SD1 and SD2).

• No External Current Sense Resistor

- Uses Lower MOSFET’s r

DS(ON)

• Bidirectional Frequency Synchronization for

Synchronizing Multiple ISL6443s

• Programmable Soft-Start

A single PGOOD signal is issued when soft-start is complete

on both PWM controllers and their outputs are within 10% of

the set point and the linear regulator output is greater than

75% of its setpoint. Thermal shutdown circuitry turns off the

device if the junction temperature exceeds +150°C.

• Extensive circuit protection functions

- PGOOD

- UVLO

- Overcurrent

- Over-temperature

- Independent Shutdown for Both PWMs

Ordering Information

• Excellent Dynamic Response

- Voltage Feed-Forward with Current Mode Control

PART

TEMP.

PKG.

NUMBER MARKING RANGE (°C) PACKAGE

DWG. #

ISL6443IR ISL6443IR

-40 to 85 28 Ld 5x5 QFN L28.5x5

• QFN Packages:

ISL6443IRZ ISL6443IRZ

(See Note)

-40 to 85 28 Ld 5x5 QFN L28.5x5

(Pb-free)

- QFN - Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

Add “-T” or “-TK” suffix for tape and reel.

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Power Supplies with Multiple Outputs

• xDSL Modems/Routers

• DSP, ASIC, and FPGA Power Supplies

• Set-Top Boxes

• Dual Output Supplies for DSP, Memory, Logic, µP Core

and I/O

• Telecom Systems

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6443

Pinouts

ISL6443 (QFN)

TOP VIEW

28 27 26 25 24 23 22

PHASE2

ISEN2

ISEN1

PGND

1

2

3

4

5

6

7

21

20

19

PGOOD

VCC_5V

SD2

SD1

18 SS1

SGND

17

SS2

16 OCSET1

15

OCSET2

FB1

8

9

10 11 12 13 14

FN9044.1

2

October 4, 2005

ISL6443

Typical Application Schematic

+12V

+

C1

56µF

C2

4.7µF

VIN

10

VCC_5V

D1

D2

SS1

SS2

BAT54HT1

C4

4

6

BAT54HT1

18

C5

0.1µF

C3

C6

BOOT1

BOOT2

24

1µF

27

1µF

C7

C8

UGATE1

PHASE1

UGATE2

PHASE2

0.1µF

23

22

0.1µF

28

1

L1

R3

L2

VOUT1

R4

VOUT2

ISEN1

ISEN2

21

2

6.4µH

1.4K

+

6.4µH

C9

330µF

+3.3V, 2A

+1.2V, 2A

1.4K

C10

+

330µF

ISL6443

26

LGATE1

PGND

LGATE2

25

20

R5

Q1

(See Note)

Q2

FDS6990S

R1

31.6K

FDS6990S

4.99k

FB2

8

FB1

SD1

SGND

15

9

14

13

R6

R2

10k

10K

19

5

GATE3

FB3

C11

0.1µF

SD2

VOUT2

+3.3V

12

OCSET1

OCSET2

7

R12

100

16

R8

17 11

3

R7

Q3

IRF7404

120K

SGND

SYNC

VOUT3

PGOOD

+2.5V, 500mA

R9

10K

R10

21.5K

C12

10µF

VCC_5V

R11

10K

FN9044.1

October 4, 2005

4

ISL6443

Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical)

Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . .-0.3V to +7V

θ

(°C/W)

36

θ

(°C/W)

5.5

JA

JC

Input Voltage (V Pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V

IN

28 Lead QFN (Note 1) . . . . . . . . . . .

BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V

PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V

BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V

UGATE1, 2. . . . . . . . . . . . (PHASE1, 2 - 0.3V) to (BOOT1, 2 +0.3V)

Maximum Junction Temperature (Plastic Package) .-55°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θ

JC

JA

the “case temp” location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, T = -40°C to 85°C (Note 2),

IN

Typical values are at T = 25°C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VIN SUPPLY

Input Voltage Range

5.6

12

24

V

VCC_5V SUPPLY (Note 3)

Input Voltage

4.5

60

5.0

-

5.6

5.5

-

V

Output Voltage

V

> 5.6V, I = 20mA

L

IN

Maximum Output Current

SUPPLY CURRENT

= 12V

mA

Shutdown Current (Note 4)

Operating Current (Note 5)

REFERENCE SECTION

Nominal Reference Voltage

Reference Voltage Tolerance

POWER-ON RESET

SD1 = SD2 = GND

-

50

375

4.0

µA

2.0

mA

-

0.8

-

V

-1.0

1.0

%

Rising VCC_5V Threshold

Falling VCC_5V Threshold

OSCILLATOR

4.25

3.95

4.45

4.2

4.5

4.4

V

Total Frequency Variation

Peak-to-Peak Sawtooth Amplitude (Note 6)

260

300

340

kHz

V

= 12V

= 5V

-

1.6

-

IN

-

0.667

-

V

Ramp Offset (Note 7)

1.0

-

10.0

5.44

-

V

SYNC Input Rise/Fall Time (Note 7)

SYNC Frequency Range

-

ns

MHz

V

4.16

3.5

-

4.8

SYNC Input HIGH Level

-

SYNC Input LOW Level

1.5

-

V

SYNC Input Minimum Pulse Width (Note 7)

SYNC Output HIGH Level

10

ns

V

- 0.6V

-

CC

SHUTDOWN1/SHUTDOWN2

HIGH Level (Converter Enabled)

LOW Level (Converter Disabled)

Internal Pull-up (3µA)

2.0

-

V

0.8

FN9044.1

October 4, 2005

5

ISL6443

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, T = -40°C to 85°C (Note 2),

IN

A

Typical values are at T = 25°C (Continued)

A

PARAMETER

PWM CONVERTERS

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage

-

0.8

-

V

nA

%

FB Pin Bias Current

-

150

Maximum Duty Cycle

C

= 1000pF, T = 25°C

93

-

OUT

A

Minimum Duty Cycle

4

%

PWM CONTROLLER ERROR AMPLIFIERS

DC Gain (Note 7)

80

5.9

-

88

-

dB

MHz

V/µs

V

Gain-Bandwidth Product (Note 7)

Slew Rate (Note 7)

-

2.0

-

Maximum Output Voltage (Note 7)

Minimum Output Voltage (Note 7)

PWM CONTROLLER GATE DRIVERS (Note 8)

Sink/Source Current

0.9

-

3.6

V

-

400

8

-

mA

Upper Drive Pull-Up Resistance

Upper Drive Pull-Down Resistance

Lower Drive Pull-Up Resistance

Lower Drive Pull-Down Resistance

Rise Time

VCC_5V = 4.5V

3.2

8

1.8

18

C

= 1000pF

ns

OUT

Fall Time

OUT

LINEAR CONTROLLER

Drive Sink Current

50

-

mA

V

FB3 Feedback Threshold

I = 21mA

0.8

75

45-

2

-

Undervoltage Threshold

V

-

150

-

%

FB

FB3 Input Leakage Current (Note 7)

Amplifier Transconductance

POWER GOOD AND CONTROL FUNCTIONS

PGOOD LOW Level Voltage

PGOOD Leakage Current

PGOOD Upper Threshold, PWM 1 and 2

PGOOD Lower Threshold, PWM 1 and 2

PGOOD for Linear Controller

ISEN and CURRENT LIMIT

Full Scale Input Current (Note 9)

Overcurrent Threshold (Note 9)

OCSET (Current Limit) Voltage

SOFT-START

-

nA

A/V

V

= 0.8V, I = 21mA

-

FB

Pull-up = 100kΩ

-

0.1

0.5

±1.0

120

95

V

µA

%

-

Fraction of set point

105

80

70

-

75

80

-

32

64

-

µA

V

ROCSET = 110kΩ

1.75

Soft-Start Current

-

5

-

µA

FN9044.1

October 4, 2005

6

ISL6443

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Schematic. V = 5.6V to 24V, or VCC_5V = 5V ±10%, T = -40°C to 85°C (Note 2),

IN

A

Typical values are at T = 25°C (Continued)

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

PROTECTION

Thermal Shutdown

Rising

-

150

20

-

°C

Hysteresis

NOTES:

2. Specifications at -40°C and 85°C are guaranteed by design, not production tested.

3. In normal operation, where the device is supplied with voltage on the V pin, the VCC_5V pin provides a 5V output capable of 60mA (min).

IN

When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the V input pin must be connected to the

IN

VCC_5V pin. (Refer to the Pin Descriptions section for more details.)

4. This is the total shutdown current with V = VCC_5V = PVCC = 5V.

IN

5. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.

6. The peak-to-peak sawtooth amplitude is production tested at 12V only; at 5V this parameter is guaranteed by design.

7. Guaranteed by design; not production tested.

8. Not production tested; guaranteed by characterization only.

9. Guaranteed by design. The full scale current of 32µA is recommended for optimum current sample and hold operation. See the Feedback Loop

Compensation Section below.

FN9044.1

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October 4, 2005

ISL6443

Typical Performance Curves

(Oscilloscope Plots are Taken Using the ISL6443EVAL Evaluation Board, VIN = 12V Unless Otherwise Noted.)

3.4

3.39

3.38

3.37

3.36

3.35

3.34

3.4

3.39

3.38

3.37

3.36

3.35

3.34

3.33

3.32

3.33

3.32

3.31

3.3

3.31

3.3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

LOAD CURRENT (A)

FIGURE 1. PWM1 LOAD REGULATION

FIGURE 2. PWM2 LOAD REGULATION

PGOOD 5V/DIV

0.85

0.84

0.83

0.82

V

2V/DIV

OUT3

OUT2

0.81

0.8

V

0.79

0.78

0.77

0.76

0.75

V

2V/DIV

OUT1

60

-40

-20

20

40

80

0

TEMPERATURE (°C)

FIGURE 3. REFERENCE VOLTAGE VARIATION OVER

TEMPERATURE

FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD

V

20mV/DIV, AC COUPLED

OUT2

V

20mV/DIV, AC COUPLED

OUT1

I

0.5A/DIV, AC COUPLED

L1

I

0.5A/DIV, AC COUPLED

L2

PHASE1 10V/DIV

PHASE2 10V/DIV

FIGURE 5. PWM1 WAVEFORMS

FIGURE 6. PWM2 WAVEFORMS

FN9044.1

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October 4, 2005

ISL6443

Typical Performance Curves (Continued)

(Oscilloscope Plots are Taken Using the ISL6443EVAL Evaluation Board, VIN = 12V Unless Otherwise Noted.)

V

200mV/DIV

OUT2

AC COUPLED

V

200mV/DIV

OUT1

AC COUPLED

I

1A/DIV

OUT2

I

1A/DIV

OUT1

FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V)

FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (3.3V)

VCC_5V 1V/DIV

V

I

2V/DIV

OUT1

2A/DIV

L1

SS1 2V/DIV

V

1V/DIV

OUT1

FIGURE 10. OVERCURRENT HICCUP MODE OPERATION

FIGURE 9. PWM SOFT-START WAVEFORM

100

90

100

90

80

70

60

70

60

0

1

2

3

4

0

1

2

3

4

LOAD CURRENT (A)

FIGURE 11. PWM1 EFFICIENCY vs LOAD (3.3V), VIN = 12V

FIGURE 12. PWM2 EFFICIENCY vs LOAD (3.3V), VIN = 12V

FN9044.1

October 4, 2005

9

ISL6443

Pin Descriptions

BOOT2, BOOT1 - These pins power the upper MOSFET

drivers of each PWM converter. Connect this pin to the

junction of the bootstrap capacitor and the cathode of the

bootstrap diode. The anode of the bootstrap diode is

connected to the VCC_5V pin.

SYNC - This pin may be used to synchronize two or more

ISL6443 controllers. This pin requires a 1K resistor to

ground if used; connect directly to VCC_5V if not used.

SS1, SS2 - These pins provide a soft-start function for their

respective PWM controllers. When the chip is enabled, the

regulated 5µA pull-up current source charges the capacitor

connected from this pin to ground. The error amplifier

reference voltage ramps from 0 to 0.8V while the voltage on

the soft-start pin ramps from 0 to 0.8V.

UGATE2, UGATE1 - These pins provide the gate drive for

the upper MOSFETs.

PHASE2, PHASE1 - These pins are connected to the junction

of the upper MOSFETs source, output filter inductor and lower

MOSFETs drain.

SD1, SD2 - These pins provide an enable/disable function

for their respective PWM output. The output is enabled when

this pin is floating or pulled HIGH, and disabled when the pin

is pulled LOW.

LGATE2, LGATE1 - These pins provide the gate drive for

the lower MOSFETs.

PGND - This pin provides the power ground connection for

the lower gate drivers for both PWM1 and PWM2. This pin

should be connected to the sources of the lower MOSFETs

and the (-) terminals of the external input capacitors.

GATE3 - This pin is the open drain output of the linear

regulator controller.

OCSET2, OCSET1 - A resistor from this pin to ground sets

the overcurrent threshold for the respective PWM.

FB3, FB2, FB1 - These pins are connected to the feedback

resistor divider and provide the voltage feedback signals for

the respective controller. They set the output voltage of the

converter. In addition, the PGOOD circuit uses these inputs

to monitor the output voltage status.

Functional Description

General Description

The ISL6443 integrates control circuits for two synchronous

buck converters and one linear controller. The two

synchronous bucks operate out of phase to substantially

reduce the input ripple and thus reduce the input filter

requirements. The chip has four control lines (SS1, SD1,

SS2, and SD2), which provide independent control for each

of the synchronous buck outputs.

ISEN2, ISEN1 - These pins are used to monitor the voltage

drop across the lower MOSFET for current loop feedback

and overcurrent protection.

PGOOD - This is an open drain logic output used to indicate

the status of the output voltages. This pin is pulled low when

either of the two PWM outputs is not within 10% of the

respective nominal voltage, or if the linear controller output is

less than 75% of it’s nominal value.

The buck PWM controllers employ a free-running frequency

of 300kHz. The current mode control scheme with an input

voltage feed-forward ramp input to the modulator provides

excellent rejection of input voltage variations and provides

simplified loop compensations.

SGND - (Pin 20 on the TSSOP; Pin 17 on the QFN)

This is the small-signal ground, common to all 3 controllers,

and must be routed separately from the high current ground

(PGND). All voltage levels are measured with respect to this

pin. Connect the additional SGND pins to this pin. If using a

5V supply, connect this pin to VCC_5V. A small ceramic

capacitor should be connected right next to this pin for noise

decoupling.

The linear controller can drive either a PNP or PFET to

provide ultra low-dropout regulation with programmable

voltages.

Internal 5V Linear Regulator (VCC_5V)

All ISL6443 functions are internally powered from an on-

chip, low dropout 5V regulator. The maximum regulator input

voltage is 24V. Bypass the regulator’s output (VCC_5V) with

a 4.7µF capacitor to ground. The dropout voltage for this

LDO is typically 600mV, so when VCC_5V is greater then

5.6V, VCC_5V is typically 5V. The ISL6443 also employs an

undervoltage lockout circuit that disables both regulators

when VCC_5V falls below 4.4V.

VIN - Use this pin to power the device with an external

supply voltage with a range of 5.6V to 24V. For 5V ±10%

operation, connect this pin to VCC_5V.

VCC_5V - This pin is the output of the internal 5V linear

regulator. This output supplies the bias for the IC, the low

side gate drivers, and the external boot circuitry for the high

side gate drivers. The IC may be powered directly from a

single 5V (±10%) supply at this pin. When used as a 5V

The internal LDO can source over 60mA to supply the IC,

power the low side gate drivers, charge the external boot

capacitor and supply small external loads. When driving

large FETs especially at 300kHz frequency, little or no

regulator current may be available for external loads.

supply input, this pin must be externally connected to V

The VCC_5V pin must be always decoupled to power

.

IN

ground with a minimum of 4.7µF ceramic capacitor, placed

very close to the pin.

FN9044.1

10

October 4, 2005

ISL6443

For example, a single large FET with 15nC total gate charge

requires 15nC x 300kHz = 4.5mA. Also, at higher input

voltages with larger FETs, the power dissipation across the

internal 5V will increase. Excessive dissipation across this

regulator must be avoided to prevent junction temperature

rise. Larger FETs can be used with 5V ±10% input

V

1V/DIV

OUT1

applications. The thermal overload protection circuit will be

triggered, if the VCC_5V output is short circuited. Connect

V

OUT2

VCC_5V to V for 5V ±10% input applications.

IN

Soft-Start Operation

When soft-start is initiated, the voltage on the SS pin of the

enabled PWM channels starts to ramp gradually, due to the

5µA current sourced into the external capacitor. The output

voltage follows the soft-start voltage.

FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING

STARTUP

When the SS pin voltage reaches 0.8V, the output voltage of

the enabled PWM channel reaches the regulation point, and

the soft-start pin voltage continues to rise. At this point the

PGOOD and fault circuitry is enabled. This completes the

soft-start sequence. Any further rise of SS pin voltage does

not affect the output voltage. By varying the values of the

soft-start capacitors, it is possible to provide sequencing of the

main outputs at start-up. The soft-start time can be obtained

from the following equation:

Output Voltage Programming

A resistive divider from the output to ground sets the output

voltage of either PWM channel. The center point of the

divider shall be connected to FBx pin. The output voltage

value is determined by the following equation.

R1 + R2









----------------------

V

= 0.8V

OUTx

R2

C

5µA

SS









-----------

T

= 0.8V

SOFT

where R1 is the top resistor of the feedback divider network

and R2 is the resistor connected from FBx to ground.

Out-of-Phase Operation

The two PWM controllers in the ISL6443 operate 180^oout-

of-phase to reduce input ripple current. This reduces the

input capacitor ripple current requirements, reduces power

supply-induced noise, and improves EMI. This effectively

helps to lower component cost, save board space and

reduce EMI.

VCC_5V 1V/DIV

V

1V/DIV

OUT1

Dual PWMs typically operate in-phase and turn on both

upper FETs at the same time. The input capacitor must then

support the instantaneous current requirements of both

controllers simultaneously, resulting in increased ripple

voltage and current. The higher RMS ripple current lowers

the efficiency due to the power loss associated with the ESR

of the input capacitor. This typically requires more low-ESR

capacitors in parallel to minimize the input voltage ripple and

ESR-related losses, or to meet the required ripple current

rating.

SS1 1V/DIV

FIGURE 13. SOFT-START OPERATION

The soft-start capacitors can be chosen to provide startup

tracking for the two PWM outputs. This can be achieved by

choosing the soft-start capacitors such that the soft-start

capacitor ration equals the respective PWM output voltage

ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V

With dual synchronized out-of-phase operation, the high-

side MOSFETs of the ISL6443 turn on 180^oout-of-phase.

The instantaneous input current peaks of both regulators no

longer overlap, resulting in reduced RMS ripple current and

input voltage ripple. This reduces the required input

capacitor ripple current rating, allowing fewer or less

expensive capacitors, and reducing the shielding

then the soft-start capacitor ration should be, C

/C =

SS1 SS1

1.2/3.3 = 0.364. Figure 14 shows that soft-start waveform

with C = 0.01µF and C = 0.027µF.

SS1

SS2

requirements for EMI. The typical operating curves show the

synchronized 180° out-of-phase operation.

FN9044.1

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October 4, 2005

ISL6443

Input Voltage Range

VIN

The ISL6443 is designed to operate from input supplies

ranging from 4.5V to 24V. However, the input voltage range

can be effectively limited by the available maximum duty

VCC_5V

BOOT

cycle (D

= 93%).

MAX

V

+ V

0.93

OUT

d1







--------------------------------

+ V – V

d2 d1



V

=

IN(min)

UGATE

PHASE

where,

Vd1 = Sum of the parasitic voltage drops in the inductor

discharge path, including the lower FET, inductor and PC

board.

ISL6443

Vd2 = Sum of the voltage drops in the charging path,

including the upper FET, inductor and PC board resistances.

FIGURE 15.

The maximum input voltage and minimum output voltage is

At start-up the low-side MOSFET turns on and forces

PHASE to ground in order to charge the BOOT capacitor to

5V. After the low-side MOSFET turns off, the high-side

MOSFET is turned on by closing an internal switch between

BOOT and UGATE. This provides the necessary gate-to-

source voltage to turn on the upper MOSFET, an action that

boosts the 5V gate drive signal above VIN. The current

required to drive the upper MOSFET is drawn from the

internal 5V regulator.

limited by the minimum on-time (t

).

ON(min)

V

OUT

---------------------------------------------------

V

≤

IN(max)

t

× 300kHz

ON(min)

where, t

= 30ns

ON(min)

Gate Control Logic

The gate control logic translates generated PWM signals

into gate drive signals providing amplification, level shifting

and shoot-through protection. The gate drivers have some

circuitry that helps optimize the ICs performance over a wide

range of operational conditions. As MOSFET switching

times can vary dramatically from type to type and with input

voltage, the gate control logic provides adaptive dead time

by monitoring real gate waveforms of both the upper and the

lower MOSFETs. Shoot-through control logic provides a

20ns deadtime to ensure that both the upper and lower

MOSFETs will not turn on simultaneously and cause a shoot-

through condition.

Protection Circuits

The converter output is monitored and protected against

overload, short circuit and undervoltage conditions. A

sustained overload on the output sets the PGOOD low and

initiates hiccup mode.

Overcurrent Protection

Both PWM controllers use the lower MOSFET’s on-

resistance, r

, to monitor the current in the converter.

DS(ON)

The sensed voltage drop is compared with a threshold set by

a resistor connected from the OCSETx pin to ground.

Gate Drivers

(7)(R

)

CS

The low-side gate driver is supplied from VCC_5V and

provides a peak sink/source current of 400mA. The high-

side gate driver is also capable of 400mA current. Gate-drive

voltages for the upper N-Channel MOSFET are generated

by the flying capacitor boot circuit. A boot capacitor

connected from the BOOT pin to the PHASE node provides

power to the high side MOSFET driver. To limit the peak

current in the IC, an external resistor may be placed

between the UGATE pin and the gate of the external

MOSFET. This small series resistor also damps any

oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board an the FET’s input

capacitance.

------------------------------------------

R

=

OCSET

(I )(R

)

OC

DS(on)

where, I

is the desired overcurrent protection threshold,

OC

and R

is a value of the current sense resistor connected

CS

to the ISENx pin. If an overcurrent is detected for 2

consecutive clock cycles then the IC enters a hiccup mode

by turning off the gate drivers and entering into soft-start.

The IC will cycle 2 times through soft-start before trying to

restart. The IC will continue to cycle through soft-start until

the overcurrent condition is removed. Hiccup mode is active

during soft-start so care must be taken to ensure that the

peak inductor current does not exceed the overcurrent

threshold during soft-start.

Because of the nature of this current sensing technique, and

to accommodate a wide range of r

variations, the

DS(ON)

value of the overcurrent threshold should represent an

overload current about 150% to 180% of the maximum

operating current. If more accurate current protection is

FN9044.1

October 4, 2005

12

ISL6443

desired place a current sense resistor in series with the

lower MOSFET source.

following expression estimates the required value of the

current sense resistor depending on the maximum operating

load current and the value of the MOSFET’s r

.

DS(ON)

Over-Temperature Protection

The IC incorporates an over-temperature protection circuit

that shuts the IC down when a die temperature of 150°C is

reached. Normal operation resumes when the die

temperatures drops below 130°C through the initiation of a

full soft-start cycle.

(I

)(R

32µA

)

MAX

DS(ON)

------------------------------------------------

≥

R

CS

Choosing R

to provide 32µA of current to the current

CS

sample and hold circuitry is recommended but values down

to 2µA and up to 100µA can be used.

Implementing Synchronization

The SYNC pin may be used to synchronize two or more

controllers. When the SYNC pins of two controllers are

connected together, one controller becomes the master and

the other controller synchronizes to the master. A pull-down

resistor is required and must be sized to provide a low

enough time constant to pass the SYNC pulse. Connect this

pin to VCC_5V if not used. Figure 16 shows the SYNC pin

waveform operating at 16 times the switching frequency.

Due to the current loop feedback, the modulator has a single

pole response with -20dB slope at a frequency determined

by the load.

1

O

--------------------------------

F

=

PO

2π ⋅ R ⋅ C

O

where R is load resistance and C is load capacitance. For

O

this type of modulator, a Type 2 compensation circuit is

usually sufficient.

Figure 17 shows a Type 2 amplifier and its response along

with the responses of the current mode modulator and the

converter. The Type 2 amplifier, in addition to the pole at

origin, has a zero-pole pair that causes a flat gain region at

frequencies in between the zero and the pole.

1

2

------------------------------

F

=

= 6kHz

Z

2π ⋅ R ⋅ C

1

------------------------------

F

=

= 600kHz

P

2π ⋅ R ⋅ C

2

C2

C1

R2

CONVERTER

R1

FIGURE 16. SYNC WAVEFORM

EA

TYPE 2 EA

Feedback Loop Compensation

G

= 17.5dB

M

G

= 18dB

To reduce the number of external components and to

simplify the process of determining compensation

components, both PWM controllers have internally

compensated error amplifiers. To make internal

compensation possible several design measures were

taken.

EA

MODULATOR

F

Z

P

F

PO

F

C

First, the ramp signal applied to the PWM comparator is

proportional to the input voltage provided via the VIN pin.

This keeps the modulator gain constant with variation in the

input voltage. Second, the load current proportional signal is

derived from the voltage drop across the lower MOSFET

during the PWM time interval and is subtracted from the

amplified error signal on the comparator input. This creates

an internal current control loop. The resistor connected to

the ISEN pin sets the gain in the current feedback loop. The

FIGURE 17. FEEDBACK LOOP COMPENSATION

The zero frequency, the amplifier high-frequency gain, and

the modulator gain are chosen to satisfy most typical

applications. The crossover frequency will appear at the

point where the modulator attenuation equals the amplifier

high frequency gain. The only task that the system designer

has to complete is to specify the output filter capacitors to

FN9044.1

13

October 4, 2005

ISL6443

position the load main pole somewhere within one decade

lower than the amplifier zero frequency. With this type of

compensation plenty of phase margin is easily achieved due

to zero-pole pair phase ‘boost’.

Figure 18 shows the linear regulator (2.5V) startup waveform

and the PWM (3.3V) startup waveform.

Conditional stability may occur only when the main load pole

is positioned too much to the left side on the frequency axis

due to excessive output filter capacitance. In this case, the

ESR zero placed within the 1.2kHz to 30kHz range gives

some additional phase ‘boost’. Some phase boost can also

V

1V/DIV

OUT2

be achieved by connecting capacitor C in parallel with the

Z

upper resistor R1 of the divider that sets the output voltage

value. Please refer to the output inductor and capacitor

selection sections for further details.

V

OUT3

Linear Regulator

The linear regulator controller is a transconductance

amplifier with a nominal gain of 2A/V. The N-channel

MOSFET output device can sink a minimum of 50mA. The

reference voltage is 0.8V. With zero volts differential at it’s

input, the controller sinks 21mA of current. An external PNP

transistor or PFET pass element can be used. The dominant

pole for the loop can be placed at the base of the PNP (or

gate of the PFET), as a capacitor from emitter to base

(source to gate of a PFET). Better load transient response is

achieved however, if the dominant pole is placed at the

output, with a capacitor to ground at the output of the

regulator.

FIGURE 18. LINEAR REGULATOR STARTUP WAVEFORM

60

50

40

30

Under no-load conditions, leakage currents from the pass

transistors supply the output capacitors, even when the

transistor is off. Generally this is not a problem since the

feedback resistor drains the excess charge. However,

20

charge may build up on the output capacitor making V

LDO

10

0

rise above its set point. Care must be taken to insure that the

feedback resistor’s current exceeds the pass transistors

leakage current over the entire temperature range.

0.84

0.79

0.8

0.82

0.83

0.85

0.81

FEEDBACK VOLTAGE (V)

The linear regulator output can be supplied by the output of

one of the PWMs. When using a PFET, the output of the

linear will track the PWM supply after the PWM output rises

to a voltage greater than the threshold of the PFET pass

device. The voltage differential between the PWM and the

FIGURE 19. LINEAR CONTROLLER GAIN

Base-Drive Noise Reduction

The high-impedance base driver is susceptible to system

noise, especially when the linear regulator is lightly loaded.

Capacitively coupled switching noise or inductively coupled

EMI onto the base drive causes fluctuations in the base

current, which appear as noise on the linear regulator’s

output. Keep the base drive traces away from the step-down

converter, and as short as possible, to minimize noise

coupling. A resistor in series with the gate drivers reduces

the switching noise generated by PWM. Additionally, a

bypass capacitor may be placed across the base-to-emitter

resistor. This bypass capacitor, in addition to the transistor’s

input capacitor, could bring in second pole that will de-

stabilize the linear regulator. Therefore, the stability

requirements determine the maximum base-to-emitter

capacitance.

linear output will be the load current times the r

.

DS(ON)

FN9044.1

14

October 4, 2005

ISL6443

9. Use copper filled polygons or wide but short trace to

connect junction of upper FET. Lower FET and output

inductor. Also keep the PHASE node connection to the IC

short. Do not unnecessary oversize the copper islands for

PHASE node. Since the phase nodes are subjected to

very high dv/dt voltages, the stray capacitor formed

between these islands and the surrounding circuitry will

tend to couple switching noise.

Layout Guidelines

Careful attention to layout requirements is necessary for

successful implementation of a ISL6443 based DC/DC

converter. The ISL6443 switches at a very high frequency

and therefore the switching times are very short. At these

switching frequencies, even the shortest trace has

significant impedance. Also the peak gate drive current rises

significantly in extremely short time. Transition speed of the

current from one device to another causes voltage spikes

across the interconnecting impedances and parasitic circuit

elements. These voltage spikes can degrade efficiency,

generate EMI, increase device overvoltage stress and

ringing. Careful component selection and proper PC board

layout minimizes the magnitude of these voltage spikes.

10. Route all high speed switching nodes away from the

control circuitry.

11. Create separate small analog ground plane near the IC.

Connect SGND pin to this plane. All small signal

grounding paths including feedback resistors, current

limit setting resistors, SYNC/SDx pull down resistors

should be connected to this SGND plane.

There are two sets of critical components in a DC/DC

converter using the ISL6443. The switching power

components and the small signal components. The

switching power components are the most critical from a

layout point of view because they switch a large amount of

energy so they tend to generate a large amount of noise.

The critical small signal components are those connected to

sensitive nodes or those supplying critical bias currents. A

multi-layer printed circuit board is recommended.

12. Ensure the feedback connection to output capacitor is

short and direct.

Component Selection Guidelines

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output

power requirements. Two N-Channel MOSFETs are used in

each of the synchronous-rectified buck converters for the

PWM1 and PWM2 outputs. These MOSFETs should be

Layout Considerations

selected based upon r

, gate supply requirements,

1. The Input capacitors, Upper FET, Lower FET, Inductor

and Output capacitor should be placed first. Isolate these

power components on the topside of the board with their

ground terminals adjacent to one another. Place the input

high frequency decoupling ceramic capacitor very close

to the MOSFETs.

DS(ON)

and thermal management considerations.

The power dissipation includes two loss components;

conduction loss and switching loss. These losses are

distributed between the upper and lower MOSFETs

according to duty cycle (see the following equations). The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper MOSFET

has significant switching losses, since the lower device turns

on and off into near zero voltage. The equations assume

linear voltage-current transitions and do not model power

loss due to the reverse-recovery of the lower MOSFET’s

body diode.

2. Use separate ground planes for power ground and small

signal ground. Connect the SGND and PGND together

close of the IC. Do not connect them together anywhere

else.

3. The loop formed by Input capacitor, the top FET and the

bottom FET must be kept as small as possible.

4. Insure the current paths from the input capacitor to the

MOSFET; to the output inductor and output capacitor are

as short as possible with maximum allowable trace

widths.

2

(I )(r

)(V

)

(I )(V )(t

)(F

SW

)

O

DS(ON)

OUT

O

IN SW

-------------------------------------------------------------- -----------------------------------------------------------

P

=

+

UPPER

V

2

IN

5. Place The PWM controller IC close to lower FET. The

LGATE connection should be short and wide. The IC can

be best placed over a quiet ground area. Avoid switching

ground loop current in this area.

2

(I )(r

)(V – V

OUT

)

O

DS(ON)

IN

------------------------------------------------------------------------------

P

=

LOWER

V

IN

A large gate-charge increases the switching time, t

,

6. Place VCC_5V bypass capacitor very close to VCC_5V

pin of the IC and connect its ground to the PGND plane.

SW

which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications.

7. Place the gate drive components BOOT diode and BOOT

capacitors together near controller IC

8. The output capacitors should be placed as close to the

load as possible. Use short wide copper regions to

connect output capacitors to load to avoid inductance and

resistances.

Output Capacitor Selection

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

FN9044.1

October 4, 2005

15

ISL6443

selected to meet the dynamic regulation requirements

including ripple voltage and load transients. Selection of

output capacitors is also dependent on the output inductor,

so some inductor analysis is required to select the output

capacitors.

30kHz. This range is set by an internal, single compensation

zero at 6kHz. The ESR zero can be a factor of five on either

side of the internal zero and still contribute to increased

phase margin of the control loop. Therefore,

1

------------------------------------

C

=

OUT

2Π(ESR)(f )

Z

One of the parameters limiting the converter’s response to a

load transient is the time required for the inductor current to

slew to it’s new level. The ISL6443 will provide either 0% or

71% duty cycle in response to a load transient.

In conclusion, the output capacitors must meet three criteria:

1. They must have sufficient bulk capacitance to sustain the

output voltage during a load transient while the output

inductor current is slewing to the value of the load

transient,

2. The ESR must be sufficiently low to meet the desired

output voltage ripple due to the output inductor current,

and

The response time is the time interval required to slew the

inductor current from an initial current value to the load

current level. During this interval the difference between the

inductor current and the transient current level must be

supplied by the output capacitor(s). Minimizing the response

time can minimize the output capacitance required. Also, if

the load transient rise time is slower than the inductor

response time, as in a hard drive or CD drive, it reduces the

requirement on the output capacitor.

3. The ESR zero should be placed, in a rather large range,

to provide additional phase margin.

The recommended output capacitor value for the ISL6443 is

between 150µF to 680µF, to meet stability criteria with

external compensation. Use of aluminum electrolytic,

POSCAP, or tantalum type capacitors is recommended. Use

of low ESR ceramic capacitors is possible but would take

more rigorous loop analysis to ensure stability.

The maximum capacitor value required to provide the full,

rising step, transient load current during the response time of

the inductor is:

2

(L )(I

)

O

TRAN

----------------------------------------------------------

=

C

OUT

2(V – V )(DV

)

Output Inductor Selection

IN

O

OUT

The PWM converters require output inductors. The output

inductor is selected to meet the output voltage ripple

requirements. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current and output capacitor(s) ESR. The ripple voltage

expression is given in the capacitor selection section and the

ripple current is approximated by the following equation:

where, C

OUT

is the output capacitor(s) required, L is the

O

output inductor, I

is the transient load current step, V

TRAN

IN

is the

is the input voltage, V is output voltage, and DV

drop in output voltage allowed during the load transient.

O

OUT

High frequency capacitors initially supply the transient

current and slow the load rate-of-change seen by the bulk

capacitors. The bulk filter capacitor values are generally

determined by the ESR (Equivalent Series Resistance) and

voltage rating requirements as well as actual capacitance

requirements.

(V – V

)(V

)

IN

OUT

---------------------------------------------------------

=

∆I

L

(f )(L)(V

)

S

IN

For the ISL6443, Inductor values between 6.4µH to 10µH is

recommended when using the Typical Application

Schematic. Other values can be used but a thorough stability

study should be done.

The output voltage ripple is due to the inductor ripple current

and the ESR of the output capacitors as defined by:

V

= ∆I (ESR)

L

RIPPLE

Input Capacitor Selection

where, I is calculated in the Inductor Selection section.

L

The important parameters for the bulk input capacitor(s) are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load

circuitry for specific decoupling requirements.

maximum input voltage and 1.5 times is a conservative

guideline. The AC RMS Input current varies with the load.

The total RMS current supplied by the input capacitance is:

Use only specialized low-ESR capacitors intended for

switching-regulator applications at 300kHz for the bulk

capacitors. In most cases, multiple small-case electrolytic

capacitors perform better than a single large-case capacitor.

2

I

=

I

+ I

RMS

RMS1

RMS2

where,

The stability requirement on the selection of the output

capacitor is that the ‘ESR zero’, f , be between 1.2kHz and

2

I

=

DC – DC

Z

RMSx

FN9044.1

16

October 4, 2005

ISL6443

DC is duty cycle of the respective PWM.

Depending on the specifics of the input power and its

impedance, most (or all) of this current is supplied by the

input capacitor(s). Figure 20 shows the advantage of having

the PWM converters operating out of phase. If the

converters were operating in phase, the combined RMS

current would be the algebraic sum, which is a much larger

value as shown. The combined out-of-phase current is the

square root of the sum of the square of the individual

reflected currents and is significantly less than the combined

in-phase current.

5

4.5

4

IN PHASE

3.5

3

2.5

OUT OF PHASE

2

1.5

5V

3.3V

1

0.5

0

1

2

3

4

5

3.3V AND 5V LOAD CURRENT

FIGURE 20. INPUT RMS CURRENT vs LOAD

Use a mix of input bypass capacitors to control the voltage

ripple across the MOSFETs. Use ceramic capacitors for the

high frequency decoupling and bulk capacitors to supply the

RMS current. Small ceramic capacitors can be placed very

close to the upper MOSFET to suppress the voltage induced

in the parasitic circuit impedances.

For board designs that allow through-hole components, the

Sanyo OS-CON® series offer low ESR and good

temperature performance. For surface mount designs, solid

tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX is

surge current tested.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9044.1

17

October 4, 2005

ISL6443

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L28.5x5

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)

2X

0.15

C A

MILLIMETERS

D

A

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

9

D/2

A

A1

A2

A3

b

0.80

0.90

-

D1

-

0.02

-

D1/2

2X

0.65

9

N

0.15 C

B

6

0.20 REF

9

INDEX

AREA

1

2

3

E1/2

E/2

9

0.18

2.95

0.25

0.30

3.25

5,8

D

5.00 BSC

-

E1

E

B

D1

D2

E

4.75 BSC

9

3.10

7,8

2X

0.15 C

B

5.00 BSC

-

2X

TOP VIEW

E1

E2

e

4.75 BSC

9

0.15 C A

3.10

7,8

0

A2

4X

0.50 BSC

-

A

/ /

0.10 C

0.08 C

C

k

0.20

0.50

-

0.60

28

7

-

L

0.75

8

SEATING PLANE

A1

A3

SIDE VIEW

9

N

2

Nd

Ne

P

3

5

NX b

0.10 M C A B

7

3

4X P

D2

8

7

-

0.60

12

9

NX k

(DATUM B)

θ

-

9

2

N

Rev. 1 11/04

4X P

1

NOTES:

(DATUM A)

2

3

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

(Ne-1)Xe

REF.

E2

6

INDEX

AREA

7

8

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

E2/2

NX L

8

N

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

e

9

(Nd-1)Xe

REF.

CORNER

OPTION 4X

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

BOTTOM VIEW

A1

NX b

5

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

SECTION "C-C"

C

L

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

C

L

10

L1

e

C

TERMINAL TIP

FOR ODD TERMINAL/SIDE

FOR EVEN TERMINAL/SIDE

FN9044.1

18

October 4, 2005


型号：	ISL6443
厂家：	Intersil
描述：	300kHz Dual, 180 Degree Out-of-Phase, Step-Down PWM and Single Linear Controller 300kHz的双路， 180 °异相，降压型，PWM和单点线性控制器控制器
文件：	总18页 (文件大小：395K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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