ISL6228IRTZ_技术文档

ISL6228

®

Data Sheet

May 7, 2008

FN9095.2

High-Performance Dual-Output Buck

Controller for Notebook Applications

Features

3

• High performance R technology

The ISL6228 IC is a dual channel synchronous-buck PWM

controller featuring Intersil's Robust Ripple Regulator (R )

• Fast transient response

3

• ±1% regulation accuracy: -40°C to +100°C

• Individual power stage input rail for each channel

• Wide input voltage range: +3.3V to +25V

• Output voltage range: +0.6V to +5V

technology that delivers truly superior dynamic response to

input voltage and output load transients. Integrated

MOSFET drivers and bootstrap diodes result in fewer

components and smaller implementation area.

3

Intersil’s R technology combines the best features of fixed-

• Diode emulation mode for increased light load efficiency

• Programmable PWM frequency: 200kHz to 600kHz

• Pre-biased output start-up capability

frequency and hysteretic PWMs while eliminating many of

3

their shortcomings. R technology employs an innovative

modulator that synthesizes an AC ripple voltage signal V ,

R

analogous to the output inductor ripple current. The AC signal

• Integrated MOSFET drivers and bootstrap diode

• Internal digital soft-start

V

enters a window comparator where the lower threshold is

R

the error amplifier output V

, and the upper threshold is a

COMP

programmable voltage reference V resulting in generation

• Power good monitor

W,

of the PWM signal. The voltage reference V sets the

W

• Fault protection

steady-state PWM frequency. Both edges of the PWM can be

modulated in response to input voltage transients and output

load transients, much faster than conventional fixed-

frequency PWM controllers. Unlike a conventional hysteretic

converter, each channel of the ISL6228 has an error amplifier

that provides ±1% voltage regulation at the FB pin.

- Undervoltage protection

- Soft crowbar overvoltage protection

- Inductor DCR overcurrent protection

- Over-temperature protection

- Fault identification by PGOOD pull-down resistance

• Pb-free (RoHS compliant)

The ISL6228 has a 1.5ms digital soft-start and can be

started into a pre-biased output voltage. A resistor divider is

used to program the output voltage setpoint. The ISL6228

operates in continuous-conduction-mode (CCM) in heavy

load, and in diode-emulation-mode (DEM) in light load to

improve light-load efficiency. In CCM, the controller always

operates as a synchronous rectifier. In DEM, the low-side

MOSFET is permitted to stay off, blocking negative current

flow into the low-side MOSFET from the output inductor.

Applications

• General purpose switching buck regulators

• PCI express graphical processing unit

• Auxiliary power rail

• VRM

• Network adaptor

Pinout

Ordering Information

ISL6228 (28 LD 4x4 TQFN)

PART NUMBER

(Note)

PART

MARKING

TEMP

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6228HRTZ

6228HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4A

28 27 26 25 24 23 22

ISL6228HRTZ-T* 6228HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4A

Tape and Reel

21

BOOT2

FSET2

VIN2

1

2

3

4

5

6

7

20 PVCC2

ISL6228IRTZ

6228IRTZ -40 to +100 28 Ld 4x4 TQFN L28.4x4A

LGATE2

PGND2

VCC2

19

18

ISL6228IRTZ-T* 6228IRTZ -40 to +100 28 Ld 4x4 TQFN L28.4x4A

Tape and Reel

VCC1

GND

17 PGND1

VIN1

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-

free material sets; molding compounds/die attach materials and 100% matte

tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet

or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

LGATE1

PVCC1

FSET1

PGOOD1

16

15

8

9

10 11 12 13 14

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6228

Typical Application

5V

R

PGOOD1

R

PVCC1

PGOOD2

PVCC2

VCC2

VCC1

VCC2

VCC1

PVCC2

PVCC1

C

VCC2

C

PVCC1

PVCC2

VCC1

PGOOD2

PGOOD1

PGOOD2

VIN2

PGOOD1

VIN1

V

IN1

IN2

3.3V TO 25V

C

Q

IN1

IN2

HIGH_SIDE1

HIGH_SIDE2

UGATE1

BOOT1

UGATE2

BOOT2

C

BOOT2

C

L

O1

BOOT1

O2

V

O2

O1

PHASE2

PHASE1

0.6V TO 5V

ISL6228

C

Q

SEN2

C

SEN1

C

LOW_SIDE1

C

LOW_SIDE2

O2

O1

R

OCSET1

OCSET2

LGATE2

PGND2

LGATE1

PGND1

OCSET2

VO2

OCSET1

VO1

R

FB2

FB1

C

R

TOP2

R

TOP1

O2

O1

C

FB1

FB2

FB1

FB2

FSET1

FSET2

R

BOTTOM1

BOTTOM2

R

C

FSET1

C

FSET1

FSET2

EN1

EN2

GND

FN9095.2

May 7, 2008

3

ISL6228

Absolute Voltage Ratings

Thermal Information

VIN

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V

to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V

Thermal Resistance (Typical, Notes 1, 2)

θ

(°C/W)

40

θ

(°C/W)

3

1,2

JA

JC

VCC, PGOOD

1,2

PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V

TQFN Package . . . . . . . . . . . . . . . . . .

Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C

Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +100°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V

1,2

VO , FB , FSET . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V

1,2

to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V

1,2

PHASE

1,2

(<100ns Pulse Width, 10µJ). . . . . . . . . . . . . . . . . . . . . . . . . -5.0V

BOOT

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V

1,2

to PHASE

. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V

1,2

Recommended Operating Conditions

UGATE

. . . . . . . . . . . .(DC) -0.3V to PHASE , BOOT

+0.3V

1,2

1,2 1,2

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C

Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . 3.3V to 25V

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%

PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%

(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V

LGATE . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, PVCC +0.3V

1,2

(<100ns Pulse Width, 4µJ). . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. Limits established by characterization and are not production tested.

Electrical Specifications These specifications apply for T = -40°C to +100°C; All typical specifications T = +25°C, VCC = 5V,

A

PVCC = 5V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN

VIN Input Bias Current

I

EN = 5V, VIN = 15V

EN = GND, VIN = 25V

-

16

-

µA

VIN

VIN Shutdown Current

I

0.1

1.0

VIN_SHDN

VCC and PVCC

VCC Input Bias Current in Single-Channel

I

EN = 5V, FB = 0.65V, VIN = 3.3V to 25V,

mA

VCC_S

1

-

1

2

-

EN = GND, FB = GND, VIN = GND

2

VCC Input Bias Current in Dual Channel

I

EN = 5V, FB = 0.65V, VIN = 3.3V to 25V,

1 1 1

VCC_D

EN = 5V, FB = 0.65V, VIN = 3.3V to 25V

2

VCC Shutdown Current

I

EN = GND, EN = GND, VCC = 5V

-

0.1

1.0

µA

VCC_SHDN

1

2

PVCC Shutdown Current

VCC POR THRESHOLD

Rising VCC POR Threshold Voltage

I

EN = GND, EN = GND, PVCC = 5V

PVCC_SHDN 1 2

V

4.33

4.35

4.08

4.10

4.45

4.20

4.55

4.30

V

VCC_THR

T

= -10°C to +100°C

A

V

Falling VCC POR Threshold Voltage

VCC_THF

T

A

REGULATION

Reference Voltage

Regulation Accuracy

PWM

V

f

-

0.6

-

V

REF

SW

Close loop

-1

-

+1

%

Frequency Range

Frequency-Set Accuracy

VO Range

200

-

600

kHz

%

f

= 300kHz

-12

+12

SW

V

0.60

-

5

-

V

VO

VO Input Leakage

I

EN = 5V, VO = 0.60V

EN = 5V, VO = 5V

EN = 0V, VO = 5V

-

1

µA

VO

7.0

0.1

-

FN9095.2

May 7, 2008

4

ISL6228

Electrical Specifications These specifications apply for T = -40°C to +100°C; All typical specifications T = +25°C, VCC = 5V,

A

PVCC = 5V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER

ERROR AMPLIFIER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FB Input Bias Current

I

FB = 0.60V

-33

-35

-

15

nA

FB

FB = 0.60V T = -10°C to +100°C

A

POWER GOOD

PGOOD Pull-Down Impedance

R

PGOOD = 5mA Sink

70

75

70

75

45

50

22

25

-

95

125

85

Ω

PG_SS

PG_UV

PG_OV

PG_OC

PGOOD

PGOOD = 5mA Sink T = -10°C to +100°C

A

PGOOD = 5mA Sink

95

Ω

PGOOD = 5mA Sink T = -10°C to +100°C

A

95

Ω

R

PGOOD = 5mA Sink

63

Ω

PGOOD = 5mA Sink T = -10°C to +100°C

A

63

85

Ω

PGOOD = 5mA Sink

32

45

Ω

PGOOD = 5mA Sink T = -10°C to +100°C

A

32

45

Ω

PGOOD Leakage Current

PGOOD Maximum Sink Current (Note 3)

PGOOD Soft-Start Delay

GATE DRIVER

I

PGOOD = 5V

0.1

5.0

2.75

1.0

-

µA

mA

ms

-

t

EN High to PGOOD High

2.20

3.50

SS

UGATE Pull-Up Resistance (Note 3)

UGATE Source Current (Note 3)

UGATE Sink Resistance (Note 3)

UGATE Sink Current (Note 3)

LGATE Pull-Up Resistance (Note 3)

LGATE Source Current (Note 3)

LGATE Sink Resistance (Note 3)

LGATE Sink Current (Note 3)

UGATE to LGATE Deadtime

LGATE to UGATE Deadtime

BOOTSTRAP DIODE

R

200mA Source Current

-

1.0

2.0

1.0

2.0

1.0

2.0

0.5

4.0

21

1.5

Ω

A

UGPU

I

UGATE - PHASE = 2.5V

250mA Sink Current

-

UGSRC

R

1.5

Ω

A

UGPD

I

UGATE - PHASE = 2.5V

250mA Source Current

-

UGSNK

R

1.5

Ω

A

LGPU

I

LGATE - PGND = 2.5V

-

LGSRC

R

250mA Sink Current

0.9

Ω

A

LGPD

I

LGATE - PGND = 2.5V

-

LGSNK

t

UGATE falling to LGATE rising, no load

LGATE falling to UGATE rising, no load

ns

UGFLGR

21

LGFUGR

Forward Voltage

V

PVCC = 5V, I = 2mA

F

-

0.58

0.2

-

V

F

Reverse Leakage

I

V

= 25V

R

µA

R

CONTROL INPUTS

EN High Threshold

V

2.0

-

V

ENTHR

EN Low Threshold

V

1.0

2.5

V

ENTHF

EN Leakage

I

EN = 0V

-

0.1

2

µA

ENL

I

EN = 5.0V

1.4

1.5

ENH

EN = 5.0V T = -10°C to +100°C

A

2

PROTECTION

OCSET-VO Threshold

OCSET 10µA Current Source

V

-1.75

8.8

9

0

1.75

10.5

-

mV

µA

kΩ

%

OCSETTHR

I

EN = 5V

10

OCSET

EN = 5V T = -10°C to +100°C

A

10

EN = 0V

-

0

OCSET 10µA Current Source Impedance R

UVP Threshold

EN = 5V, OCSET = 1.2V

-

600

86

-

OCSETIMP

V

81

113

100

87

UV

OVP Rising Threshold

V

116

102

120

106

%

OVR

OVP Falling Threshold

V

%

OVF

FN9095.2

May 7, 2008

5

ISL6228

Electrical Specifications These specifications apply for T = -40°C to +100°C; All typical specifications T = +25°C, VCC = 5V,

A

PVCC = 5V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER

OTP Rising Threshold (Note 3)

OTP Hysteresis (Note 3)

SYMBOL

TEST CONDITIONS

MIN

TYP

150

25

MAX

UNIT

°C

T

-

OTR

T

°C

OTHYS

connected across the VO1, FB1, and GND pins. Select the

resistor values such that FB1 to GND is 600mV when the

converter output voltage is at the programmed regulation

value.

Functional Pin Descriptions

GND (Bottom Pad)

Signal common of the IC. Unless otherwise stated, signals

are referenced to the GND pin.

VO1 (Pin 9)

FSET2 (Pin 1)

The VO1 pin measures the Channel 1 converter output

voltage and is used as an input to the Channel 1 R PWM

modulator. It also serves as part of Channel 1 inductor

current sensing and the OCP overcurrent fault protection

circuit.

3

The FSET2 pin programs the PWM switching frequency of

Channel 2. Program the desired PWM frequency with a

resistor and a capacitor connected across the FSET2 and

GND pins.

VIN2 (Pin 2)

OCSET1 (Pin 10)

The VIN2 pin measures the input voltage of the Channel 2

converter. It is a required input to the Channel 2 R PWM

modulator. Connect the VIN2 pin to the drain of the

Channel 2 high-side MOSFET.

The OCSET1 pin measures the Channel 1 inductor current

and programs the threshold of the OCP overcurrent fault

protection.

3

EN1 (Pin 11)

VCC2 (Pin 3)

The EN1 pin is the on/off switch of Channel 1. The soft-start

sequence begins when the EN1 pin is pulled above the

The VCC2 pin is the input bias voltage for Channel 2.

Connect +5V to the VCC2 pin. Decouple with at least 1µF of

a MLCC capacitor from the VCC2 pin to the GND pin.

rising threshold voltage V

and VCC1 is above the

ENTHR

power-on reset (POR) rising threshold voltage V

.

VCC_THR

When the EN1 pin is pulled below the falling threshold

voltage V PWM1 immediately stops.

VCC1 (Pin 4)

ENTHF

The VCC1 pin is the input bias voltage for Channel 1.

Connect +5V to the VCC1 pin. Decouple with at least 1µF of

a MLCC capacitor from the VCC1 pin to the GND pin.

PHASE1 (Pin 12)

The PHASE1 pin is the current return path for the Channel 1

high-side MOSFET gate driver. Connect the PHASE1 pin to

the node consisting of the high-side MOSFET source, the

low-side MOSFET drain, and the output inductor of the

Channel 1 converter.

VIN1 (Pin 5)

The VIN1 pin measures the input voltage of the Channel 1

converter. It is a required input to the Channel 1 R PWM

modulator. Connect the VIN1 pin to the drain of the

Channel 1 high-side MOSFET.

3

UGATE1 (Pin 13)

The UGATE1 pin is the output of the Channel 1 high-side

MOSFET gate driver. Connect the UGATE1 pin to the gate

of the Channel 1 converter high-side MOSFET.

FSET1 (Pin 6)

The FSET1 pin programs the PWM switching frequency of

Channel 1. Program the desired PWM frequency with a

resistor and a capacitor connected across the FSET1 and

GND pins.

BOOT1 (Pin 14)

The BOOT1 pin stores the input voltage for the Channel 1

high-side MOSFET gate driver. Connect an MLCC capacitor

across the BOOT1 and PHASE1 pins. The boot capacitor is

charged through an internal boot diode connected from the

PVCC1 pin to the BOOT1 pin, each time the PHASE1 pin

drops below PVCC1 minus the voltage dropped across the

internal boot diode.

PGOOD1 (Pin 7)

The PGOOD1 pin is an open-drain output that indicates

when the Channel 1 converter is able to supply regulated

voltage. Connect the PGOOD1 pin to +5V through a pull-up

resistor.

FB1 (Pin 8)

PVCC1 (Pin 15)

The FB1 pin is the inverting input of the control-loop error

amplifier for Channel 1. The Channel 1 converter output

voltage regulates to 600mV from the FB1 pin to the GND pin.

Program the desired output voltage with a resistor network

The PVCC1 pin is the input voltage bias for the Channel 1

low-side MOSFET gate drivers. Connect +5V to the PVCC1

FN9095.2

May 7, 2008

6

ISL6228

pin. Decouple with at least 1µF of an MLCC capacitor across

EN2 (Pin 24)

the PVCC1 and PGND1 pin.

The EN2 pin is the on/off switch of Channel 2. The soft-start

sequence begins when the EN2 pin is pulled above the

LGATE1 (Pin 16)

rising threshold voltage V

and VCC2 is above the

ENTHR

power-on reset (POR) rising threshold voltage V

The LGATE1 pin is the output of the Channel 1 converter

low-side MOSFET gate driver. Connect the LGATE1 pin to

the gate of the Channel 1 converter low-side MOSFET.

.

VCC_THR

When the EN2 pin is pulled below the falling threshold

voltage V , PWM2 immediately stops.

ENTHF

PGND1 (Pin 17)

OCSET2 (Pin 25)

The PGND1 pin is the current return path for the Channel 1

converter low-side MOSFET gate driver. Connect the

PGND1 pin to the source of the Channel 1 converter low-

side MOSFET through a low impedance path, preferably in

parallel with the trace connecting the LGATE1 pin to the gate

of the Channel 1 converter low-side MOSFET.

The OCSET2 pin measures the Channel 2 inductor current

and programs the threshold of the OCP overcurrent fault

protection.

VO2 (Pin 26)

The VO2 pin measures the Channel 2 converter output

3

voltage and is used as an input to the Channel 2 R PWM

PGND2 (Pin 18)

modulator. It also serves as part of Channel 2 inductor

current sensing and the OCP overcurrent fault protection

circuit.

The PGND2 pin is the current return path for the Channel 2

converter low-side MOSFET gate driver. Connect the

PGND2 pin to the source of the Channel 2 converter low-

side MOSFET through a low impedance path, preferably in

parallel with the trace connecting the LGATE2 pin to the gate

of the Channel 2 converter low-side MOSFET.

FB2 (Pin 27)

The FB2 pin is the inverting input of the control-loop error

amplifier for Channel 2. The Channel 2 converter output

voltage regulates to 600mV from the FB2 pin to the GND pin.

Program the desired output voltage with a resistor network

connected across the VO2, FB2, and GND pins. Select the

resistor values such that FB2 to GND is 600mV when the

converter output voltage is at the programmed regulation

value.

LGATE2 (Pin 19)

The LGATE2 pin is the output of the Channel 2 converter

low-side MOSFET gate driver. Connect to the gate of the

Channel 2 converter low-side MOSFET.

PVCC2 (Pin 20)

The PVCC2 pin is the input voltage bias for the Channel 2

low-side MOSFET gate drivers. Connect +5V to the PVCC2

pin. Decouple with at least 1µF of an MLCC capacitor across

the PVCC2 and PGND2 pin.

PGOOD2 (Pin 28)

The PGOOD2 pin is an open-drain output that indicates

when the Channel 2 converter is able to supply regulated

voltage. Connect the PGOOD2 pin to +5V through a pull-up

resistor.

BOOT2 (Pin 21)

The BOOT2 pin stores the input voltage for the Channel 2

high-side MOSFET gate driver. Connect an MLCC capacitor

across the BOOT2 and PHASE2 pins. The boot capacitor is

charged through an internal boot diode connected from the

PVCC2 pin to the BOOT2 pin, each time the PHASE2 pin

drops below PVCC2 minus the voltage dropped across the

internal boot diode.

Theory of Operation

Two Separate Channels

The ISL6228 is a dual channel controller. Pins 4~17 are

dedicated to Channel 1, and pins 1~3 and pins 18~28 are

dedicated to Channel 2. The two channels are identical and

almost entirely independent, with the exception of sharing

the GND pin. Unless otherwise stated, only an individual

channel is discussed, and the conclusion applies to both

channels.

UGATE2 (Pin 22)

The UGATE2 pin is the output of the Channel 2 high-side

MOSFET gate driver. Connect to the gate of the Channel 2

converter high-side MOSFET.

Modulator

3

The ISL6228 modulator features Intersil’s R technology, a

PHASE2 (Pin 23)

hybrid of fixed frequency PWM control and variable

frequency hysteretic control. Intersil’s R technology can

simultaneously affect the PWM switching frequency and

The PHASE2 pin is the current return path for the Channel 2

high-side MOSFET gate driver. Connect the PHASE2 pin to

the node consisting of the high-side MOSFET source, the

low-side MOSFET drain, and the output inductor of the

Channel 2 converter.

3

PWM duty cycle in response to input voltage and output load

3

transients. The R modulator synthesizes an AC signal V ,

R

which is an analog representation of the output inductor

ripple current. The duty-cycle of V is the result of charge

R

and discharge current through a ripple capacitor C . The

R

FN9095.2

May 7, 2008

7

ISL6228

current through C is provided by a transconductance

Soft-Start Delay t begins and the output voltage begins to

SS

R

amplifier g that measures the VIN and VO pin voltages.

rise. The FB pin ramps to 0.6V in approximately 1.5ms and

m

The positive slope of V can be written as Equation 1:

the PGOOD pin goes to high impedance approximately

1.25ms after the FB pin voltage reaches 0.6V.

R

(EQ. 1)

V

= (g ) ⋅ (V – V

) ⁄ C

OUT R

RPOS

m

IN

1.5ms

The negative slope of V can be written as Equation 2:

R

Vo

(EQ. 2)

V

= g ⋅ V

⁄ C

OUT R

RNEG

m

VCC and PVCC

Where g is the gain of the transconductance amplifier.

m

EN

FB

A window voltage V is referenced with respect to the error

W

amplifier output voltage V

, creating an envelope into

COMP

which the ripple voltage V is compared. The amplitude of

R

PGOOD

1.25ms

V

is set by a resistor connected across the FSET and GND

W

pins. The V and V signals feed into a window

V

R, COMP, W

comparator in which V

is the lower threshold voltage

and V is the higher threshold voltage. Figure 2 shows

COMP

W

FIGURE 3. SOFT-START SEQUENCE

PWM pulses being generated as V traverses the V and

R

W

V

thresholds. The PWM switching frequency is

COMP

proportional to the slew rates of the positive and negative

slopes of V it is inversely proportional to the voltage

The PGOOD pin indicates when the converter is capable of

supplying regulated voltage. The PGOOD pin is an

R;

between V and V

undefined impedance if V

has not reached the rising POR

CC

is below the falling POR threshold

W

COMP.

threshold V

, or if V

CCR CC

V

. The ISL6228 features a unique fault-identification

CCF

capability that can drastically reduce trouble-shooting time

and effort. The pull-down resistance of the PGOOD pin

corresponds to the fault status of the controller. The PGOOD

pull-down resistance is 95Ω during soft-start or if an UVP

occurs, 30Ω for an OCP, or 60Ω for OVP.

Ripple Capacitor Voltage C

Window Voltage V

R

W

TABLE 1. PGOOD PULL-DOWN RESISTANCE

CONDITION

VCC Below POR

Soft-start or Undervoltage

Overvoltage

PGOOD RESISTANCE

Error Amplifier Voltage V

COMP

Undefined

90Ω

60Ω

PWM

Overcurrent

30Ω

MOSFET Gate-Drive Outputs LGATE and UGATE

FIGURE 2. MODULATOR WAVEFORMS DURING LOAD

TRANSIENT

The ISL6228 has internal gate-drivers for the high-side and

low-side N-Channel MOSFETs. The low-side gate-drivers

are optimized for low duty-cycle applications where the low-

side MOSFET conduction losses are dominant, requiring a

Power-On Reset

The ISL6228 is disabled until the voltage at the VCC pin has

low r

MOSFET. The LGATE pull-down resistance is

DS(ON)

small in order to clamp the gate of the MOSFET below the

at turnoff. The current transient through the gate at

increased above the rising power-on reset (POR) V

CCR

threshold voltage. The controller will be disabled when the

voltage at the VCC pin decreases below the falling POR

V

GS(th)

turn-off can be considerable because the gate charge of a

low r MOSFET can be large. Adaptive shoot-through

V

threshold voltage.

CCF

DS(ON)

protection prevents a gate-driver output from turning on until

EN, Soft-Start and PGOOD

the opposite gate-driver output has fallen below

The ISL6228 uses a digital soft-start circuit to ramp the

output voltage of the converter to the programmed regulation

setpoint at a predictable slew rate. The slew rate of the

soft-start sequence has been selected to limit the in-rush

current through the output capacitors as they charge to the

desired regulation voltage. When the EN pin is pulled above

approximately 1V. The dead-time shown in Figure 4 is

extended by the additional period that the falling gate voltage

stays above the 1V threshold. The typical dead-time is 21ns.

The high-side gate-driver output voltage is measured across

the UGATE and PHASE pins while the low-side gate-driver

output voltage is measured across the LGATE and PGND

the rising EN threshold voltage V

, the PGOOD

ENTHR

FN9095.2

May 7, 2008

8

ISL6228

pins. The power for the LGATE gate-driver is sourced

directly from the PVCC pin. The power for the UGATE gate-

driver is sourced from a “boot” capacitor connected across

the BOOT and PHASE pins. The boot capacitor is charged

from a 5V bias supply through a “boot diode” each time the

low-side MOSFET turns on, pulling the PHASE pin low. The

ISL6228 has an integrated boot diode connected from the

PVCC pin to the BOOT pin.

detected positive voltage and LGATE was allowed to go high

for eight consecutive PWM switching cycles. The ISL6228

will turn off the low-side MOSFET once the phase voltage

turns positive, indicating negative inductor current. The

ISL6228 will return to CCM on the following cycle after the

PHASE pin detects negative voltage, indicating that the body

diode of the low-side MOSFET is conducting positive

inductor current.

Efficiency can be further improved with a reduction of

unnecessary switching losses by reducing the PWM

frequency. It is characteristic of the R architecture for the

t

UGFLGR

LGFUGR

3

PWM frequency to decrease while in diode emulation. The

extent of the frequency reduction is proportional to the

reduction of load current. Upon entering DEM, the PWM

frequency makes an initial step-reduction because of a 33%

50%

UGATE

LGATE

step-increase of the window voltage V .

W

Overcurrent Protection

The overcurrent protection (OCP) setpoint is programmed

50%

with resistor R

that is connected across the OCSET

OCSET

and PHASE pins.

L

DCR

V

I

O

L

_

PHASE

FIGURE 4. LGATE AND UGATE DEAD-TIME

V

+

DCR

C

SEN

R

OCSET

C

ISL6228

Diode Emulation

O

_

The ISL6228 implements forced continuous-conduction-

mode (CCM) at heavy load and diode-emulation-mode

(DEM) at light load, to optimize efficiency in the entire load

range. The transition is automatically achieved by detecting

the output load current.

10µA

V

+

ROCSET

OCSET

R

O

VO

FIGURE 5. OVERCURRENT-SET CIRCUIT

Positive-going inductor current flows from either the source

of the high-side MOSFET, or the drain of the low-side

MOSFET. Negative-going inductor current flows into the

drain of the low-side MOSFET. When the low-side MOSFET

conducts positive inductor current, the phase voltage will be

negative with respect to the GND and PGND pins.

Conversely, when the low-side MOSFET conducts negative

inductor current, the phase voltage will be positive with

respect to the GND and PGND pins. The ISL6228 monitors

the phase voltage, when the low-side MOSFET is

conducting inductor current, to determine the direction of the

inductor current.

Figure 5 shows the overcurrent-set circuit. The inductor

consists of inductance L and the DC resistance DCR. The

inductor DC current I creates a voltage drop across DCR,

L

given by Equation 3:

(EQ. 3)

V

= I

L ^{• DCR}

DCR

The ISL6228 sinks 10µA current into the OCSET pin,

creating a DC voltage drop across the resistor R

given by Equation 4:

,

OCSET

(EQ. 4)

V

= 10μA• R

OCSET

ROCSET

When the output load current is greater than or equal to ½

the inductor ripple current, the inductor current is always

positive, and the converter is always in CCM. The ISL6228

minimizes the conduction loss in this condition by forcing the

low-side MOSFET to operate as a synchronous rectifier.

Resistor R is connected between the VO pin and the actual

O

output voltage of the converter. During normal operation, the

VO pin is a high impedance path, therefore there is no

voltage drop across R . The DC voltage difference between

O

the OCSET pin and the VO pin can be established using

When the output load current is less than ½ the inductor

ripple current, negative inductor current occurs. Sinking

negative inductor through the low-side MOSFET lowers

efficiency through unnecessary conduction losses. The

ISL6228 automatically enters DEM after the PHASE pin has

Equation 5:

OCSET

VO

DCR

L ^{• DCR – 10μA• R}OCSET

(EQ. 5)

V

–V

= V

–V

= I

ROCSET

FN9095.2

May 7, 2008

9

ISL6228

The ISL6228 monitors the OCSET pin and the VO pin

voltages. Once the OCSET pin voltage is higher than the VO

pin voltage for more than 10µs, the ISL6228 declares an OCP

the output voltage transversing the V

and V

OVR OVF

thresholds. The LGATE gate-driver will turn on the low-side

MOSFET to discharge the output voltage, protecting the

load. The LGATE gate-driver will turn off the low-side

MOSFET once the FB pin voltage is lower than the falling

fault. The value of R

OCSET

is then written as Equation 6:

I

OC ^{• DCR}

10μA

---------------------------

overvoltage threshold V

for more than 2µs. The falling

is typically 106%. That means if

R

=

OVF

OCSET

(EQ. 6)

OVF

Where:

the FB pin voltage falls below 106% x 0.6V = 0.636V, for

more than 2µs, the LGATE gate-driver will turn off the low-

side MOSFET. If the output voltage rises again, the LGATE

driver will again turn on the low-side MOSFET when the FB

- R

(Ω) is the resistor used to program the

OCSET

overcurrent setpoint

- I is the output current threshold that will activate the

OC

pin voltage is above the rising overvoltage threshold V

OCP circuit

OVR

for more than 2µs. By doing so, the ISL6228 protects the

load when there is a consistent overvoltage condition.

- DCR is the inductor DC resistance

For example, if I

is 20A and DCR is 4.5mΩ, the choice of

= 20A x 4.5mΩ/10µA = 9kΩ.

OC

Undervoltage Protection

R

is R

OCSET

The UVP fault detection circuit triggers after the FB pin

Resistor R

and capacitor C

SEN

form an R-C network

OCSET

voltage is below the undervoltage threshold V

for more

UV

than 2µs. The FB pin voltage is 0.6V in normal operation.

The undervoltage threshold V is typically 86%. That

to sense the inductor current. To sense the inductor current

correctly not only in DC operation, but also during dynamic

operation, the R-C network time constant R

UV

C

OCSET SEN

means if the FB pin voltage is below 86% x 0.6V = 0.516V,

for more than 2µs, an UVP fault is declared, and the

PGOOD pin will pull down to 95Ω and latch-off the converter.

The fault will remain latched until the EN pin has been pulled

needs to match the inductor time constant L/DCR. The value

of C

is then written as Equation 7:

SEN

L

-----------------------------------------

C

=

SEN

OCSET ^{• DCR}

R

(EQ. 7)

below the falling EN threshold voltage V

or if V

has

CC

ENTHF

decayed below the falling POR threshold voltage

V

For example, if L is 1.5µH, DCR is 4.5mΩ, and R

9kΩ, the choice of C

SEN

is

= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.

OCSET

.

VCC_THF

Programming the Output Voltage

Upon converter startup, capacitor C

initial voltage is 0V.

SEN

To prevent false OCP, a 10µA current source flows out of the

VO pin during start up, generating a voltage drop on resistor

When the converter is in regulation there will be 0.6V from

the FB pin to the GND pin. Connect a two-resistor voltage

divider across the VO pin and the GND pin with the output

node connected to the FB pin. Scale the voltage-divider

network such that the FB pin is 0.6V with respect to the GND

pin when the converter is regulating at the desired output

voltage. The output voltage can be programmed from 0.6V

to 5V.

R , which has the same resistance as R

. When

O

OCSET

PGOOD pin goes high, the VO pin current source will

terminate.

When an OCP fault is declared, the PGOOD pin will pull

down to 30Ω and latch off the converter. The fault will remain

latched until the EN pin has been pulled below the falling EN

Programming the output voltage is written as Equation 8:

threshold voltage V

falling POR threshold voltage

or if V

has decayed below the

ENTHF

CC

V

R

.

VCC_THF

BOTTOM

+ R

BOTTOM

(EQ. 8)

V

= V

REF

O ^{• --------------------------------------------------}

R

TOP

Overvoltage Protection

Where:

- V is the desired output voltage of the converter

The OVP fault detection circuit triggers after the FB pin voltage

is above the rising overvoltage threshold V for more than

O

OVR

2µs. The FB pin voltage is 0.6V in normal operation. The rising

overvoltage threshold V is typically 116%. That means if

- The voltage to which the converter regulates the FB pin

is the V

REF

OVR

the FB pin voltage is above 116% x 0.6V = 0.696V, for more

- R

TOP

is the voltage-programming resistor that connects

from the FB pin to the converter output. In addition to

setting the output voltage, this resistor is part of the loop

compensation network

than 2µs, an OVP fault is declared.

When an OVP fault is declared, the PGOOD pin will pull

down to 60Ω and latch-off the converter. The OVP fault will

remain latched until the EN pin has been pulled below the

- R

is the voltage-programming resistor that

connects from the FB pin to the GND pin

BOTTOM

falling EN threshold voltage V

or if V

has decayed

ENTHF

CC

Choose R

TOP

value first, and calculate R

according

V

BOTTOM

below the falling POR threshold voltage

.

VCC_THF

to Equation 9:

Although the converter has latched-off in response to an

OVP fault, the LGATE gate-driver output will retain the ability

to toggle the low-side MOSFET on and off, in response to

V

REF ^{• R}

TOP

----------------------------------

=

(EQ. 9)

R

BOTTOM

V

– V

REF

O

FN9095.2

May 7, 2008

10

ISL6228

General Application Design Guide

Programming the PWM Switching Frequency

The ISL6228 does not use a clock signal to produce PWMs.

This design guide is intended to provide a high-level

explanation of the steps necessary to design a single-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following section. In addition to this guide, Intersil provides

complete reference designs that include schematics, bills of

materials, and example board layouts.

The PWM switching frequency f

is programmed by the

SW

that is connected from the FSET pin to the

resistor R

FSET

GND pin. The approximate PWM switching frequency is

written as Equation 10:

1

---------------------------

=

(EQ. 10)

f

SW

K ⋅ R

FSET

Estimating the value of R

1

is written as Equation 11:

FSET

Selecting the LC Output Filter

-----------------

(EQ. 11)

R

=

FSET

K^•f

SW

The duty cycle of an ideal buck converter is a function of the

input and the output voltage. This relationship is written as

Equation 13:

Where:

- f

is the PWM switching frequency

SW

V

O

---------

(EQ. 13)

D =

- R

is the f programming resistor

SW

FSET

V

IN

-10

- K = 1.5 x 10

It is recommended that whenever the control loop

compensation network is modified, f should be checked

The output inductor peak-to-peak ripple current is written as

Equation 14:

SW

V

O ^{• (1 – D)}

(EQ. 14)

for the correct frequency and if necessary, adjust R

.

-----------------------------

=

I

FSET

PP

SW ^{• L}

f

Compensation Design

A typical step-down DC/DC converter will have an I

of

P-P

20% to 40% of the maximum DC output load current. The

Figure 6 shows the recommended Type-II compensation

circuit. The FB pin is the inverting input of the error amplifier.

The COMP signal, the output of the error amplifier, is inside the

value of I is selected based upon several criteria such as

PP

MOSFET switching loss, inductor core loss, and the resistive

loss of the inductor winding. The DC copper loss of the

inductor can be estimated by Equation 15:

2

chip and unavailable to users. C

is a 100pF capacitor

INT

integrated inside the IC, connecting across the FB pin and the

COMP signal. R , R , C and C form the Type-II

TOP FB FB INT

(EQ. 15)

P

= I

• DCR

LOAD

compensator. The frequency domain transfer function is given

by Equation 12:

COPPER

Where I

is the converter output DC current.

LOAD

1 + s^•(R

+ R ) • C

FB

TOP

FB

The copper loss can be significant so attention has to be

given to the DCR selection. Another factor to consider when

choosing the inductor is its saturation characteristics at

elevated temperature. A saturated inductor could cause

destruction of circuit components, as well as nuisance OCP

faults.

-------------------------------------------------------------------------------------------

(s) =

G

(EQ. 12)

COMP

s^•R

)

TOP ^{• C}INT ^{• (1 + s• R}FB ^{• C}

FB

C

= 100pF

FB

INT

R

FB

A DC/DC buck regulator must have output capacitance C

O

R

TOP

into which ripple current I

can flow. Current I develops

PP

P-P

a corresponding ripple voltage V

VO

-

across C which is the

P-P

O,

FB

sum of the voltage drop across the capacitor ESR and of the

voltage change stemming from charge moved in and out of

the capacitor. These two voltages are written as

Equation 16:

EA

R

COMP

BOTTOM

+

REF

ISL6228

(EQ. 16)

ΔV

= I

P-P ^{• ESR}

ESR

FIGURE 6. COMPENSATION REFERENCE CIRCUIT

and Equation 17:

I

P-P

The LC output filter has a double pole at its resonant frequency

that causes rapid phase change. The R modulator used in the

-----------------------------

(EQ. 17)

ΔV

=

C

8• C

O ^{• f}

SW

3

ISL6228 makes the LC output filter resemble a first order

system in which the closed loop stability can be achieved with

the recommended Type-II compensation network. Intersil

provides a PC-based tool (example page is shown later) that

can be used to calculate compensation network component

values and help simulate the loop frequency response.

If the output of the converter has to support a load with high

pulsating current, several capacitors will need to be paralleled

to reduce the total ESR until the required V

is achieved.

P-P

The inductance of the capacitor can cause a brief voltage dip

if the load transient has an extremely high slew rate. Low

inductance capacitors should be considered. A capacitor

FN9095.2

May 7, 2008

11

ISL6228

dissipates heat as a function of RMS current and frequency.

Be sure that I is shared by a sufficient quantity of paralleled

MOSFET Selection and Considerations

P-P

capacitors so that they operate below the maximum rated

Typically, a MOSFET cannot tolerate even brief excursions

beyond their maximum drain to source voltage rating. The

MOSFETs used in the power stage of the converter should

RMS current at f . Take into account that the rated value of

SW

a capacitor can fade as much as 50% as the DC voltage

across it increases.

have a maximum V

upper voltage tolerance of the input power source and the

voltage spike that occurs when the MOSFET switches off.

rating that exceeds the sum of the

DS

Selection of the Input Capacitor

The important parameters for the bulk input capacitance are

the voltage rating and the RMS current rating. For reliable

operation, select bulk capacitors with voltage and current

ratings above the maximum input voltage and capable of

supplying the RMS current required by the switching circuit.

Their voltage rating should be at least 1.25 times greater

than the maximum input voltage, while a voltage rating of 1.5

times is a preferred rating. Figure 7 is a graph of the input

RMS ripple current, normalized relative to output load current,

as a function of duty cycle that is adjusted for converter

efficiency. The ripple current calculation is written as

Equation 18:

There are several power MOSFETs readily available that are

optimized for DC/DC converter applications. The preferred

high-side MOSFET emphasizes low gate charge so that the

device spends the least amount of time dissipating power in

the linear region. Unlike the low-side MOSFET which has the

drain-source voltage clamped by its body diode during turn

off, the high-side MOSFET turns off with V - V

, plus the

IN OUT

spike, across it. The preferred low-side MOSFET

emphasizes low r

conduction loss.

when fully saturated to minimize

DS(ON)

For the low-side (LS) MOSFET, the power loss can be

assumed to be conductive only and is written as Equation 20:

2

D

12

2

⎛

⎞

⎠

------

(I

⋅ (D – D )) + x ⋅ I

⋅

P

≈ I

⋅ r

DS(ON)_LS ^{• (1 – D)}

(EQ. 20)

MAX

CON_LS

LOAD

⎝

----------------------------------------------------------------------------------------------------

I

=

IN_RMS, NORMALIZED

I

MAX

For the high-side (HS) MOSFET, the its conduction loss is

written as Equation 21:

(EQ. 18)

2

Where:

- I

P

= I

• r

DS(ON)_HS ^{• D}

(EQ. 21)

CON_HS

LOAD

is the maximum continuous I

of the converter

LOAD

MAX

- x is a multiplier (0 to 1) corresponding to the inductor

peak-to-peak ripple amplitude expressed as a

For the high-side MOSFET, the switching loss is written as

Equation 22:

percentage of I

(0% to 100%)

MAX

- D is the duty cycle that is adjusted to take into account

the efficiency of the converter which is written as:

V

IN ^{• I}VALLEY ^{• t}ON ^{• f}

IN ^{• I}PEAK ^{• t}OFF ^{• f}

V

SW

---------------------------------------------------------------- -------------------------------------------------------------

P

=

+

SW_HS

2

V

O

(EQ. 22)

--------------------------

D =

V

⋅ EFF

(EQ. 19)

IN

Where:

In addition to the bulk capacitance, some low ESL ceramic

capacitance is recommended to decouple between the drain

of the high-side MOSFET and the source of the low-side

MOSFET.

- I

is the difference of the DC component of the

VALLEY

inductor current minus 1/2 of the inductor ripple current

- I is the sum of the DC component of the inductor

PEAK

current plus 1/2 of the inductor ripple current

- t is the time required to drive the device into

ON

saturation

0.60

0.55

0.50

0.45

0.40

0.35

- t

is the time required to drive the device into cut-off

OFF

Selecting The Bootstrap Capacitor

The selection of the bootstrap capacitor is written as

Equation 23:

0.30

Q

g

x = 1

-----------------------

(EQ. 23)

0.25

0.20

0.15

0.10

0.05

0

C

=

x = 0.75

x = 0.50

x = 0.25

x = 0

BOOT

ΔV

BOOT

Where:

- Q is the total gate charge required to turn on the

g

high-side MOSFET

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY CYCLE

1.0

- ΔV

, is the maximum allowed voltage decay across

BOOT

the boot capacitor each time the high-side MOSFET is

switched on

FIGURE 7. NORMALIZED RMS INPUT CURRENT

FN9095.2

May 7, 2008

12

ISL6228

As an example, suppose the high-side MOSFET has a total

gate charge Q , of 25nC at V = 5V, and a ΔV of

200mV. The calculated bootstrap capacitance is 0.125µF; for

a comfortable margin, select a capacitor that is double the

calculated capacitance. In this example, 0.22µF will suffice.

Use an X7R or X5R ceramic capacitor.

EN (Pins 11 and 24), and PGOOD (Pins 7 and 28)

g

GS BOOT

These are logic signals that are referenced to the GND pin.

Treat as a typical logic signal.

OCSET (Pins 10 and 25)

The current-sensing network consisting of R

and

OCSET

needs to be connected to the inductor pads for

C

SEN

Layout Considerations

accurate measurement. Connect R

to the phase-

to the

OCSET

node side pad of the inductor, and connect C

As a general rule, power should be on the bottom layer of

the PCB and weak analog or logic signals are on the top

layer of the PCB. The ground-plane layer should be adjacent

to the top layer to provide shielding. The ground plane layer

should have an island located under the IC, the

compensation components, and the FSET components. The

island should be connected to the rest of the ground plane

layer at one point.

SEN

output side pad of the inductor. Connect the OCSET pin to

the common node of node of R and C

.

OCSET

SEN

FB (Pins 8 and 27), and VO (Pins 9 and 26)

The VO pin is used to sense the inductor current for OCP.

Connect the VO pin to the output-side of C through

SEN

resistor R . The input impedance of the FB pin is high, so

O

place the voltage programming and loop compensation

components close to the VO, FB, and GND pins keeping the

high impedance trace short.

GND

VIAS TO

GROUND

PLANE

OUTPUT

CAPACITORS

FSET (Pins 1 and 6)

SCHOTTKY

DIODE

VOUT

This pin requires a quiet environment. The resistor R

FSET

PHASE

LOW-SIDE

MOSFETS

INDUCTOR

and capacitor C

should be placed directly adjacent to

NODE

FSET

this pin. Keep fast moving nodes away from this pin.

HIGH-SIDE

MOSFETS

INPUT

LGATE (Pins 16 and 19)

CAPACITORS

VIN

The signal going through this trace is both high dv/dt and

high di/dt, with high peak charging and discharging current.

Route this trace in parallel with the trace from the PGND pin.

These two traces should be short, wide, and away from

other traces. There should be no other weak signal traces in

proximity with these traces on any layer.

FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT

Signal Ground and Power Ground

The bottom of the ISL6228 TQFN package is the signal

ground (GND) terminal for analog and logic signals of the IC.

Connect the GND pad of the ISL6228 to the island of ground

plane under the top layer using several vias, for a robust

thermal and electrical conduction path. Connect the input

capacitors, the output capacitors, and the source of the

lower MOSFETs to the power ground plane.

BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and

PHASE (Pins 12 and 23)

The signals going through these traces are both high dv/dt

and high di/dt, with high peak charging and discharging

current. Route the UGATE and PHASE pins in parallel with

short and wide traces. There should be no other weak signal

traces in proximity with these traces on any layer.

PGND (Pins 17 and 18)

This is the return path for the pull-down of the LGATE

low-side MOSFET gate driver. Ideally, PGND should be

connected to the source of the low-side MOSFET with a

low-resistance, low-inductance path.

Copper Size for the Phase Node

The parasitic capacitance and parasitic inductance of the

phase node should be kept very low to minimize ringing. It is

best to limit the size of the PHASE node copper in strict

accordance with the current and thermal management of the

application. An MLCC should be connected directly across

the drain of the upper MOSFET and the source of the lower

MOSFET to suppress the turn-off voltage spike.

VIN (Pins 2 and 5)

The VIN pin should be connected close to the drain of the

high-side MOSFET, using a low resistance and low

inductance path.

VCC (Pins 3 and 4)

For best performance, place the decoupling capacitor very

close to the VCC and GND pins.

PVCC (Pins 15 and 20)

For best performance, place the decoupling capacitor very

close to the PVCC and respective PGND pins, preferably on

the same side of the PCB as the ISL6228 IC.

FN9095.2

May 7, 2008

13

ISL6228

Typical Performance

100

95

90

85

80

75

70

65

60

100

V

= 8V

IN

V

= 8V

IN

95

90

85

80

75

70

65

60

V

= 12V

IN

V

= 12V

IN

V

= 19V

IN

V

= 19V

IN

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

I

(A)

I

(A)

OUT

FIGURE 9. CHANNEL 1 EFFICIENCY AT V = 1.5V

O

FIGURE 10. CHANNEL 2 EFFICIENCY AT VO = 1.8V

V

O1

FB1

PGOOD1

PHASE1

FIGURE 11. START-UP, V = 12V, LOAD = 0.25Ω, V = 1.05V

IN

FIGURE 12. SHUT-DOWN, V = 12V, I = 10A, V = 1.05V

O

IN

O

V

O1

PHASE1

V

O2

PHASE2

FIGURE 13. CCM STEADY-STATE OPERATION,V = 12V,

IN

FIGURE 14. DCM STEADY-STATE OPERATION,V = 12V,

IN

V

= 1.5V, I = 3A, V = 1.8A, I = 4A

V

= 1.5V, I = 1A, V = 1.8V, I = 1A

O1

O1 O2 O2

O1 O1 O2 O2

FN9095.2

May 7, 2008

14

ISL6228

Typical Performance (Continued)

I

O2

O1

V

O2

O1

PHASE2

PHASE1

FIGURE 16. TRANSIENT RESPONSE, V = 12V, V = 1.8V,

FIGURE 15. TRANSIENT RESPONSE, V = 12V, V = 1.5V,

IN

O

IN

O

I

= 0.1A/8.1A @ 2.55A/µs

I

= 0.1A/8.1A @ 2.55A/µs

O

I

O1

O2

V

O1

O2

PHASE1

PHASE2

FIGURE 18. LOAD INSERTION RESPONSE, V = 12V,

IN

FIGURE 17. LOAD INSERTION RESPONSE, V = 12V,

IN

V

= 1.8V, I = 0.1A/8.1A @ 2.55A/µs

V

= 1.5V, I = 0.1A/8.1A @ 2.55A/µs

O

I

O2

O1

V

O1

V

O2

PHASE1

PHASE2

FIGURE 19. LOAD RELEASE RESPONSE, V = 12V,

IN

FIGURE 20. LOAD RELEASE RESPONSE, V = 12V,

IN

V

= 1.5V, I = 0.1A/8.1A @ 2.55A/µs

V

= 1.8V, I = 0.1A/8.1A @ 2.55A/µs

O

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9095.2

May 7, 2008

15

ISL6228

Package Outline Drawing

L28.4x4A

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 3/07

4X

2.4

4.00

0.40

24X

A

6

B

PIN #1 INDEX AREA

28

22

6

1

21

PIN 1

INDEX AREA

2 .40 ± 0 . 15

15

(4X)

0.15

8

14

0.10 M C A B

28X 0.20

4

TOP VIEW

28X 0.45 ± 0.10

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

0 . 75

( 3. 75 TYP )

BASE PLANE

( 24X 0 . 4 )

SEATING PLANE

0.08 C

(

2. 40 )

SIDE VIEW

( 28X 0 . 20 )

( 28X 0 . 65)

5

C

0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN9095.2

May 7, 2008

16


型号：	ISL6228IRTZ
厂家：	Intersil
描述：	High-Performance Dual-Output Buck Controller for Notebook Applications 高性能双输出降压型控制器，用于笔记本电脑的应用电脑控制器
文件：	总16页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6228IRTZ [INTERSIL]

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