ISL6208_07 [INTERSIL]
High Voltage Synchronous Rectified Buck MOSFET Driver; 高电压同步整流降压MOSFET驱动器
| 型号： | ISL6208_07 |
| 厂家： | 
Intersil |
| 描述： | High Voltage Synchronous Rectified Buck MOSFET Driver |
| 文件： | 总10页 (文件大小：1684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6208
®
Data Sheet
March 30, 2007
FN9115.2
High Voltage Synchronous Rectified Buck
MOSFET Driver
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adaptive Shoot-Through Protection
The ISL6208 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
• 0.5Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency up to 2MHz
- Fast output rise and fall time
- Low propagation delay
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
The ISL6208 features 4A typical sinking current for the lower
gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.
• Low Bias Supply Current (5V, 80µA)
• Diode Emulation for Enhanced Light Load Efficiency and
Pre-Biased Start-Up Applications
• VCC POR (Power-On-Reset) Feature Integrated
• Low Three-State Shutdown Holdoff Time (Typical 160ns)
• Pin-to-pin Compatible with ISL6207
The ISL6208 also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a protective Schottky diode usually
seen in a microprocessor power systems.
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208. Each driver is capable of driving a 3000pF load
with propagation delays of 8ns and transition times under
10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
Applications
• Core Voltage Supplies for Intel® and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converters
A diode emulation feature is integrated in the ISL6208 to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”
• Technical Brief TB447 “Guidelines for Preventing Boot-to-
Phase Stress on Half-Bridge MOSFET Driver ICs”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6208
Ordering Information
PART NUMBER
PART MARKING
ISL6208CB
TEMP. RANGE (°C)
-10 to +100
-10 to +100
-10 to +100
-10 to +100
-40 to +100
-40 to +100
-40 to +100
-40 to +100
PACKAGE
PKG. DWG. #
M8.15
ISL6208CB*
8 Ld SOIC
ISL6208CBZ* (Note)
ISL6208CR*
ISL6208CBZ
208C
8 Ld SOIC (Pb-free)
8 Ld 3x3 QFN
M8.15
L8.3x3
L8.3x3
M8.15
M8.15
L8.3x3
L8.3x3
ISL6208CRZ* (Note)
ISL6208IB*
208Z
8 Ld 3x3 QFN (Pb-free)
8 Ld SOIC
ISL6208IB
ISL6208IBZ
208I
ISL6208IBZ* (Note)
ISL6208IR*
8 Ld SOIC (Pb-free)
8 Ld 3x3 QFN
ISL6208IRZ* (Note)
81RZ
8 Ld 3x3 QFN (Pb-free)
* Add “-T” suffix for Tape and Reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6208CB
(8 LD SOIC)
TOP VIEW
ISL6208CR
(8 LD 3x3 QFN)
TOP VIEW
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
FCCM
VCC
8
3
7
4
BOOT
PWM
1
2
6 FCCM
GND
LGATE
5 VCC
Block Diagram
VCC
BOOT
FCCM
UGATE
PHASE
SHOOT-
THROUGH
PROTECTION
CONTROL
LOGIC
VCC
PWM
LGATE
GND
10K
THERMAL PAD (FOR QFN PACKAGE ONLY)
FIGURE 1. BLOCK DIAGRAM
ti
FN9115.2
March 30, 2007
2
ISL6208
ti
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JC
JA
Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V
, V
). . . . . . . . . . . . . -0.3V to VCC + 0.3V
). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
FCCM PWM
SOIC Package (Note 2) . . . . . . . . . . . .
QFN Package (Notes 3, 4). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
110
80
n/a
15
BOOT-GND
). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
BOOT-PHASE
PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V
GND - 8V (<20ns Pulse Width, 10μJ)
UGATE Voltage . . . . . . . . . . . . . . . . V
- 0.3V (DC) to V
PHASE
BOOT
- 5V (<20ns Pulse Width, 10μJ) to V
BOOT
V
PHASE
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY CURRENT
CC
Bias Supply Current
POR
I
PWM pin floating, V
FCCM
= 5V
-
80
-
-
μA
VCC
-
-
V
V
Rising
Falling
-
2.40
-
3.40
2.90
500
3.90
V
V
CC
CC
-
-
Hysteresis
mV
BOOTSTRAP DIODE
Forward Voltage
PWM INPUT
V
V
= 5V, forward bias current = 2mA
0.50
0.55
0.65
V
F
VCC
Input Current
I
V
V
V
V
V
= 5V
-
250
-250
1.00
3.8
-
μA
μA
V
PWM
PWM
PWM
VCC
VCC
VCC
= 0V
-
-
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Hold-off Time
FCCM INPUT
= 5V
0.70
3.5
100
1.30
4.1
250
= 5V
V
t
= 5V, temperature = +25°C
175
ns
TSSHD
FCCM LOW Threshold
0.50
-
-
-
-
V
V
FCCM HIGH Threshold
2.0
SWITCHING TIME
UGATE Rise Time (Note 5)
LGATE Rise Time (Note 5)
t
V
V
= 5V, 3nF load
= 5V, 3nF load
-
-
8.0
8.0
-
-
ns
ns
RU
VCC
t
RL
VCC
FN9115.2
March 30, 2007
3
ISL6208
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
UGATE Fall Time (Note 5)
SYMBOL
TEST CONDITIONS
= 5V, 3nF load
MIN
TYP
8.0
4.0
18
MAX
UNITS
ns
t
V
V
V
V
V
V
V
-
-
-
-
FU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LGATE Fall Time (Note 5)
t
= 5V, 3nF load
ns
FL
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UG/LG Three-State Propagation Delay
Minimum LG On TIME in DCM (Note 5)
OUTPUT
t
= 5V, outputs unloaded
= 5V, outputs unloaded
= 5V, outputs unloaded
= 5V, outputs unloaded
= 5V, outputs unloaded
-
-
ns
PDLU
t
-
25
-
ns
PDLL
t
10
10
-
20
30
30
-
ns
PDHU
t
20
ns
PDHL
t
35
ns
PTS
t
-
400
-
ns
LGMIN
Upper Drive Source Resistance
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 5)
NOTE:
R
500mA source current
-
-
-
-
-
-
-
-
1
2.5
-
Ω
A
Ω
A
Ω
A
Ω
A
U
U
I
V
= 2.5V
2.00
1
U
UGATE-PHASE
R
500mA sink current
2.5
-
I
V
= 2.5V
2.00
1
U
UGATE-PHASE
R
500mA source current
2.5
-
L
I
V
= 2.5V
2.00
0.5
4.00
L
LGATE
R
500mA sink current
1.0
-
L
I
V
= 2.5V
L
LGATE
5. Guaranteed by characterization, not 100% tested in production.
Typical Application with 2-Phase Converter
+5V
+5V
V
BAT
VCC
+V
CORE
BOOT
UGATE
+5V
FB
COMP
FCCM
PWM
VCC
VSEN
PHASE
LGATE
DRIVE
ISL6208A
PWM1
PWM2
PGOOD
THERMAL
PAD
FCCM
MAIN
CONTROL
ISEN1
VID
ISEN2
+5V
V
BAT
VCC
BOOT
FS
DACOUT
FCCM
PWM
UGATE
PHASE
GND
DRIVE
ISL6208A
LGATE
THERMAL
PAD
FN9115.2
March 30, 2007
4
ISL6208
Timing Diagram
2.5V
t
PWM
PDHU
t
t
PDLU
TSSHD
t
t
RU
RU
t
t
FU
FU
t
PTS
1V
UGATE
LGATE
t
PTS
1V
t
RL
t
FL
t
TSSHD
t
PDHL
t
PDLL
t
FL
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Functional Pin Description
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
Description
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
Theory of Operation
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
Designed for speed, the ISL6208 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
delay [t
], the lower gate begins to fall. Typical fall times
PDLL
[t ] are provided in the Electrical Specifications section.
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see the
three-state PWM Input section under DESCRIPTION for further
details). Connect this pin to the PWM output of the controller.
FL
Adaptive shoot-through circuitry monitors the LGATE voltage.
When LGATE has fallen below 1V, UGATE is allowed to turn
ON. This prevents both the lower and upper MOSFETs from
conducting simultaneously, or shoot-through.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
propagation delay [t
] is encountered before the upper gate
PDLU
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
begins to fall [t ]. The upper MOSFET gate-to-source voltage
is monitored, and the lower gate is allowed to rise after the
upper MOSFET gate-to-source voltage drops below 1V. The
FU
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
lower gate then rises [t ], turning on the lower MOSFET.
RL
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See the Diode
Emulation section under DESCRIPTION for more detail.
The 0.5Ω on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.
FN9115.2
March 30, 2007
5
ISL6208
Typical Performance Waveforms
FIGURE 2. LOAD TRANSIENT (0 - 30A, 3-PHASE)
FIGURE 3. LOAD TRANSIENT (30 - 0A, 3-PHASE)
FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD
FIGURE 7. PRE-BIASED START-UP IN DCM MODE
FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD
FIGURE 6. PRE-BIASED START-UP IN CCM MODE
FN9115.2
March 30, 2007
6
ISL6208
Diode Emulation
2.0
1.8
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6208 will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6208 will respond to the FCCM input immediately
after it changes state. Refer to the waveforms on page 6.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Q
= 100nC
GATE
NOTE: Intersil does not recommend Diode Emulation use with
r
current sensing topologies. The turn-OFF of the low side
DS(ON)
MOSFET can cause gross current measurement inaccuracies.
20nC
Three-State PWM Input
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV (V)
A unique feature of the ISL6208 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
BOOT_CAP
FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of +125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
P = f (1.5V Q + V Q ) + I V
VCC
CC
(EQ. 2)
sw
U
L
U
L
where f is the switching frequency of the PWM signal. V
sw
U
and V represent the upper and lower gate rail voltage. Q
L
U
and Q is the upper and lower gate charge determined by
L
Internal Bootstrap Diode
MOSFET selection and any external capacitance added to
the gate pins. The lV product is the quiescent power
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
V
CC CC
of the driver and is typically negligible.
1000
Q
= 50nC
= 100nC
Q
Q
=100nC
= 200nC
U
U
L
Q
Q
= 50nC
= 50nC
U
L
Q
900
800
700
600
500
400
300
200
100
0
L
Q
GATE
-----------------------
C
≥
(EQ. 1)
BOOT
ΔV
BOOT
Q
= 20nC
=50nC
U
L
Q
where Q
is the amount of gate charge required to fully
GATE
charge the gate of the upper MOSFET. The ΔV
term is
BOOT
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
GATE
, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125μF is required.
The next larger standard value capacitance is 0.15μF. A
good quality ceramic capacitor is recommended.
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 9. POWER DISSIPATION vs FREQUENCY
FN9115.2
March 30, 2007
7
ISL6208
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
2
inductance MOSFETs and drivers. D PAK and DPAK
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
• Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
• Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
FN9115.2
March 30, 2007
8
ISL6208
Package Outline Drawing
L8.3x3
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/07
4X
8
0.65
3.00
A
6
B
7
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
6
5
1
2
1 .10 ± 0 . 15
(4X)
0.15
4
3
0.10 M C A B
8X 0.28 ± 0.05
4
TOP VIEW
8X 0.60 ± 0.15
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
( 4X 0 . 65 )
BASE PLANE
SEATING PLANE
0.08
( 2. 60 TYP )
C
(
1. 10 )
SIDE VIEW
( 8X 0 . 28 )
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 8X 0 . 80)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9115.2
March 30, 2007
9
ISL6208
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9115.2
March 30, 2007
10
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