ISL33003MSOPEVAL1Z [INTERSIL]
I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability; I2C总线缓冲器与上升时间加速器和热插拔功能
| 型号： | ISL33003MSOPEVAL1Z |
| 厂家： | 
Intersil |
| 描述： | I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability |
| 文件： | 总19页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
I C Bus Buffer with Rise Time Accelerators and
Hot Swap Capability
ISL33001, ISL33002, ISL33003 Features
2
• 2 Channel I C Compatible Bi-Directional Buffer
• +2.3VDC to +5.5VDC Supply Range
• >400kHz Operation
The ISL33001, ISL33002, ISL33003 2-Channel Bus
Buffers provide the necessary buffering for extending the
bus capacitance beyond the 400pF maximum specified
2
by the I C specification. In addition, the ISL33001,
• Bus Capacitance Buffering
ISL33002, ISL33003 feature rise time accelerator
circuitry to reduce power consumption from passive bus
pull-up resistors and improve data-rate performance. All
devices also include hot swap circuitry to prevent
• Rise Time Accelerators
• Hot-Swapping Capability
• ±6kV Class 3 HBM ESD Protection On All Pins
• ±12kV HBM ESD Protection on SDA/SCL Pins
• Enable Pin (ISL33001 and ISL33003)
• Logic Level Translation (ISL33002 and ISL33003)
• READY Logic Pin (ISL33001)
2
corruption of the data and clock lines when I C devices
are plugged into a live backplane and level translation for
mixed supply voltage applications.
The ISL33001, ISL33002, ISL33003 operates at supply
voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
• Accelerator Disable Pin (ISL33002)
• Pb-Free (RoHS Compliant) 8 Ld SOIC (ISL33001
only), 8 Ld TDFN (3mmx3mm) and 8 Ld MSOP
packages
Summary of Features
PART
LEVEL
ENABLE READY ACCELERATOR
NUMBER TRANSLATION
PIN
Yes
No
PIN
Yes
No
DISABLE
• Low Quiescent Current . . . . . . . . . . . . . 2.2mA typ
• Low Shutdown Current . . . . . . . . . . . . . .0.5µA typ
ISL33001
ISL33002
ISL33003
No
Yes
Yes
No
Yes
Applications*(see page 15)
Yes
No
No
2
• I C Bus Extender and Capacitance Buffering
• Server Racks for Telecom, Datacom, and Computer
Servers
Related Literature*(see page 15)
• AN1543, “ISL33001EVAL1Z, ISL33002EVAL1Z,
ISL33003EVAL1Z Evaluation Board Manual”
• Desktop Computers
• Hot-Swap Board Insertion and Bus Isolation
Typical Operating Circuit
Bus Accelerator Performance
+3.3V
2
+5.0V
V
V
CC2
CC1
100kHz I C BUS WITH 2.7kΩ PULL-UP RESISTOR
AND 400pF BUS CAPACITANCE
WITHOUT BUFFER
BACK
PLANE
µC
SDA
SCL
2
I C
SDA
SCL
EN
ISL33003
DEVICE
A
2
I C
WITH BUFFER
DEVICE
B
GND
TIME (2µs/DIV)
September 30, 2010
FN7560.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL33001, ISL33002, ISL33003
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL33001IRTZ
3001
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld SOIC
L8.3x3A
ISL33001IRT2Z
ISL33001IBZ
01R2
L8.3x3H
M8.15
33001 IBZ
33001
3002
ISL33001IUZ
8 Ld MSOP
M8.118
L8.3x3A
L8.3x3H
M8.118
L8.3x3A
L8.3x3H
M8.118
ISL33002IRTZ
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld MSOP
ISL33002IRT2Z
ISL33002IUZ
02R2
33002
3003
ISL33003IRTZ
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld MSOP
ISL33003IRT2Z
ISL33003IUZ
03R2
33003
ISL33001MSOPEVAL1Z
ISL33002MSOPEVAL1Z
ISL33003MSOPEVAL1Z
NOTES:
ISL33001 Evaluation Board
ISL33002 Evaluation Board
ISL33003 Evaluation Board
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL33001, ISL33002, ISL33003. For more
information on MSL please see techbrief TB363.
Pin Configurations
ISL33001
ISL33001
(8 LD SOIC, MSOP)
TOP VIEW
(8 LD TDFN)
TOP VIEW
V
EN
CC1
8
1
2
3
4
V
1
EN
8
7
6
5
CC1
SDA_OUT
SDA_IN
READY
SCL_OUT
7
6
5
2
3
4
SCL_OUT
SDA_OUT
PAD
SCL_IN
GND
SCL_IN
GND
SDA_IN
READY
FN7560.2
September 30, 2010
2
ISL33001, ISL33002, ISL33003
Pin Configurations (Continued)
ISL33002
(8 LD TDFN)
TOP VIEW
ISL33002
(8 LD MSOP)
TOP VIEW
V
V
CC1
V
V
CC2
8
1
2
3
4
CC2
1
8
7
6
5
CC1
SDA_OUT
SDA_IN
ACC
SCL_OUT
SCL_IN
GND
SCL_OUT
7
6
5
SDA_OUT
SDA_IN
ACC
2
3
4
PAD
SCL_IN
GND
ISL33003
(8 LD TDFN)
TOP VIEW
ISL33003
(8 LD MSOP)
TOP VIEW
V
V
V
CC2
V
CC1
8
1
CC2
1
8
7
6
5
CC1
SCL_OUT
SCL_IN
GND
SDA_OUT
SDA_IN
EN
7
6
5
SDA_OUT
SDA_IN
EN
2
3
4
2
3
4
SCL_OUT
PAD
SCL_IN
GND
Pin Descriptions
NAME
NOTES
PIN NUMBER
FUNCTION
power supply, +2.3V to +5.5V. Decouple V
V
V
8
V
to ground with a high
to ground with a high
CC1
CC2
CC1
frequency 0.01µF to 0.1µF capacitor.
CC1
ISL33002, ISL33003
1
V
power supply, +2.3V to +5.5V. Decouple V
CC2
CC2
frequency 0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT
and SCL_OUT logic thresholds are referenced to V supply levels. Connect
CC2
pull-up resistors on these pins to V
.
CC2
GND
EN
4
1
5
5
Device Ground Pin
ISL33001
ISL33003
Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the
device. Logic threshold referenced to V
.
CC1
READY
ACC
ISL33001 only
Buffer Active ‘Ready’ Logic Output. When buffer is active, READY is high
impedance. When buffer is inactive, READY is low impedance to ground.
ISL33002 only
5
Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic
“1” enables the accelerator. Logic threshold referenced to V
.
CC1
SDA_IN
SDA_OUT
SCL_IN
SCL_OUT
PAD
6
7
3
2
Data I/O Pins
Clock I/O Pins
Thermal Pad; TDFN only
Thermal pad should be connected to ground or float.
FN7560.2
September 30, 2010
3
ISL33001, ISL33002, ISL33003
Absolute Maximum Ratings
Thermal Information
(All voltages referenced to GND)
V
, V
CC1 CC2
. . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JC
JA
SDA_IN, SCL_IN . . . . . . . . . . . . . -0.3V to +(V
SDA_OUT, SCL_OUT . . . . . . . . . . . -0.3V to +(V
ENABLE, READY, ACC . . . . . . . . . . -0.3V to +(V
Maximum Sink Current (SDA and SCL Pins). . . . . . . . . 20mA
Maximum Sink Current (READY pin) . . . . . . . . . . . . . . .7mA
Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . 85°C
ESD Ratings. . . . . . . . . . See “ESD PROTECTION” on page 5
+ 0.3)V
+ 0.3)V
+ 0.3)V
CC1
CC2
CC1
8 Ld TDFN Package (Notes 5, 6) . . .
(0.50mm Pitch)
8 Ld TDFN Package (Notes 5, 6) . . .
(0.65mm Pitch)
8 Ld MSOP Package (Notes 4, 7) . . .
8 Ld SOIC Package (Notes 4, 7). . . .
Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersi.com/pbfree/Pb-FreeReflow.asp
47
4
48
6
151
120
50
56
Operating Conditions
Temperature Range, T . . . . . . . . . . . . . . . -40°C to +85°C
A
V
and V Supply Voltage Range . . . . . +2.3V to +5.5V
CC1
CC2
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
JA
TB7379 for details.
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications
V
= V
, V
= +2.3V to +5.5V, V = +2.3V to +5.5V, unless otherwise noted (Note 8).
CC2
EN
CC1 CC1
Boldface limits apply over the operating temperature range,
-40°C to +85°C.
TEMP
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(°C) (Note 9)
TYP
(Note 9) UNITS
POWER SUPPLIES
V
V
Supply Range
Supply Range
V
V
Full
Full
Full
Full
2.3
2.3
-
-
5.5
5.5
4.0
3.0
V
CC1
CC2
CC1
CC2
CC1
ISL33002 and ISL33003
-
V
Supply Current from
V
I
V
= 5.5V; ISL33001 only (Note 11)
2.1
2.0
mA
mA
CC1
CC1
CC1
V
= V
= 5.5V; ISL33002 and
-
CC2
ISL33003 (Note 11)
Supply Current from
I
V
= V = 5.5V; ISL33002 and
Full
-
0.22
0.6
mA
CC2
CC2
CC
V
ISL33003 (Note 11)
CC2
V
Shut-down
I
I
V
V
= 5.5V, V
= GND; ISL33001 only Full
-
-
0.5
-
-
µA
µA
CC1
SHDN1
SHDN2
CC1
CC1
EN
Supply Current
= V
= 5.5V, V
= GND;
Full
0.05
CC2
EN
ISL33003 only
V
Shut-down
V
= V = 5.5V, V
= GND,
Full
-
0.06
1
-
µA
CC2
CC1
CC2
EN
Supply Current
ISL33003 only
START-UP CIRCUITRY
Precharge Circuitry
Voltage
V
SDA and SCL pins floating
Full
+25
+25
Full
0.8
1.2
V
V
PRE
EnableHighThreshold
Voltage
V
0.5*V
0.5*V
0.1
0.7*V
CC
EN_H
-
CC
CC
Enable Low Threshold
Voltage
V
0.3*V
-
V
EN_L
CC
Enable Pin Input
Current
I
Enable from 0V to V
ISL33003
ISL33001 and
CC1;
-1
1
µA
EN
FN7560.2
September 30, 2010
4
ISL33001, ISL33002, ISL33003
Electrical Specifications
V
= V
, V
= +2.3V to +5.5V, V = +2.3V to +5.5V, unless otherwise noted (Note 8).
CC2
EN
CC1 CC1
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
TEMP
MIN
MAX
PARAMETER
Enable Delay, On-Off
Enable Delay, Off-On
Bus Idle Time
SYMBOL
CONDITIONS
ISL33001 and ISL33003 (Note 10)
ISL33001 and ISL33003 (Figure 1)
(Figure 2, Note 12)
(°C) (Note 9)
TYP
10
(Note 9) UNITS
t
t
+25
+25
Full
-
-
-
-
ns
µs
µs
µA
EN-HL
86
EN-LH
t
50
-1
83
150
1
IDLE
Ready Pin OFF State
Leakage Current
I
ISL33001 only
+25
0.1
OFF
Ready Delay, On-Off
Ready Delay, Off-On
t
t
ISL33001 only (Note 10)
ISL33001 only (Note 10)
+25
+25
Full
-
-
-
10
10
-
-
-
ns
ns
V
READY-HL
READY-LH
OL_READY
Ready Output Low
Voltage
V
V
= +2.5V, I
PULLUP
= 3mA;
0.4
CC1
ISL33001 only
RISE-TIME ACCELERATORS
Transient Accelerator
Current
I
V
= 2.7V, V
= 2.7V;
for ISL33002 only)
+25
+25
-
-
5
-
mA
TRAN_ACC
CC1 CC2
(ACC = 0.7*V
(Figure 6)
CC1
Accelerator Enable
Threshold
V
ISL33002 only
ISL33002 only
ISL33002 only
0.5*V
0.5*V
0.7*V
CC1
V
V
ACC_EN
CC1
Accelerator Disable
Threshold
V
+25 0.3*V
CC1
ACC_DIS
CC1
-
Accelerator Pin Input
Current
I
+25
+25
-1
-
0.1
10
1
µA
ns
ACC
Accelerator Delay,
On-Off
t
ISL33002 only (Note 10)
-
-
PDOFF
ESD PROTECTION
SDA, SCL I/O Pins
Human Body Model, SDA and SCL pins to
ground only (JESD22-A114)
+25
-
-
±12
kV
All Pins
Machine Model (JESD22-A115)
Class 3 HBM ESD (JESD22-A114)
+25
+25
±400
±6
-
-
V
kV
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
V
V
= V
, 10kΩ to V
on SDA and
on SDA and
+25
Full
-
0.3*V
CC1
-
V
IL
CC1
SCL pins
CC2
CC1
Input-Output Offset
Voltage
V
V
= 3.3V, 10kΩ to V
0
50
-
150
0.4
-
mV
OS
CC1
SCL pins, V
CC1
= 0.2V; V
= 3.3V,
INPUT
CC2
ISL33002 and ISL33003 (Figure 3)
Output Low Voltage
V
V
= 2.7V, V = 0V, I = 3mA
Full
+25
Full
-
-
V
OL
CC1
INPUT SINK
on SDA/SCL pins; V = 2.7V,
CC2
ISL33002 and ISL33003 (Figure 4)
Buffer SDA and SCL
Pins Input
Capacitance
C
(Figure 23)
10
0.1
pF
µA
IN
Input Leakage
Current
I
SDA and SCL pins = V
V
= 5.5V;
= 5.5V, ISL33002 and ISL33003
-5
5
LEAK
CC1
CC2
FN7560.2
September 30, 2010
5
ISL33001, ISL33002, ISL33003
Electrical Specifications
V
= V
, V
= +2.3V to +5.5V, V = +2.3V to +5.5V, unless otherwise noted (Note 8).
CC2
EN
CC1 CC1
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
TEMP
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(°C) (Note 9)
TYP
(Note 9) UNITS
TIMING CHARACTERISTICS
SCL/SDA Propagation
Delay High to Low
t
C
= 100pF, 2.7kΩ to V
CC1
on SDA
= 3.3V,
+25
+25
0
0
27
100
26
ns
ns
PHL
PLH
LOAD
and SCL pins, V
= 3.3V; V
CC1
CC2
ISL33002 and ISL33003 (Figure 5)
SCL/SDA Propagation
Delay Low to High
t
C
= 100pF, 2.7kΩ to V on SDA
2
LOAD
and SCL pins, V
CC1
= 3.3V; V
= 3.3V,
CC1
CC2
ISL33002 and ISL33003 (Figure 5)
NOTES:
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
FN7560.2
September 30, 2010
6
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- V
SDA_IN
= V
= V
= V
SCL_OUT EN
= V
CC
- SDA and SCL pins connected to V
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
SDA_OUT
CC
- EN Logic High for t > Enable Delay, t
prior to SCL_IN transition
EN_LH
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance
inferred from ISL33001
V
CC
V
CC
0.5 * V
CC
V
V
0.5V
EN
CC
V
SCL_IN
0V
0V
V
CC
V
CC
0.5V
0.5 * V
CC
CC
READY
V
READY
0V
0V
t
t
IDLE
EN-LH
FIGURE 1. ENABLE DELAY TIME
FIGURE 2. BUS IDLE TIME
+3.3V
0.2V
SCL_IN OR
SDA_IN
10kΩ
10kΩ
10kΩ
V
CC1
SDA_OUT
SCL_OUT
10kΩ
SDA_IN
SCL_IN
V
O
GND
SCL_OUT OR
SDA_OUT
V
V
IN
0.2V
IN
0.2V
V
= V - 0.2V
O
OS
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
900Ω
SCL_OUT
900Ω
900Ω
V
V
CC1
V
CC1
SDA_OUT
V
OL
SDA_IN
SCL_OUT
SDA_OUT
SCL_IN
GND
CC1
0V
0V
V
OL
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. OUTPUT LOW VOLTAGE
FN7560.2
September 30, 2010
7
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms(Continued)
+3.3V
SCL_IN OR
SDA_IN
2.7kΩ
2.7kΩ
2.7kΩ
V
CC1
SDA_OUT
SCL_OUT
2.7kΩ
SCL_OUT OR
SDA_OUT
SDA_IN
SCL_IN
100pF
GND
V
V
IN
IN
*t
PLH
*t
PHL
100pF
100pF
100pF
*Propagation delay measured between 50% of V
CC1
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. PROPAGATION DELAY
I
= CΔV/Δt
ACC
*
*
V
X
V
X
V
V
V
CC1
CC1
2.7kΩ
2.7kΩ
2.7kΩ
10kΩ
10kΩ
10kΩ
10kΩ
100kΩ
V
CC1
CC1
SDA_OUT
SDA_IN
SCL_OUT
SDA_OUT
SDA_IN
SCL_OUT
SCL_IN
SCL_IN
GND
GND
2nF
*
V
< V
CC1
X
(See Figure 20)
FIGURE 6. ACCELERATOR CURRENT TEST CIRCUIT
FIGURE 7. ACCELERATOR PULSE WIDTH TEST CIRCUIT
FN7560.2
September 30, 2010
8
ISL33001, ISL33002, ISL33003
SDA_IN
SDA_OUT
U1
U2
M2
M1
READY
ISL33001 only
RISE TIME
ACCELERATOR
M5
LOGIC CONTROL
START-UP CIRCUITRY
V
V
CC1
CC2
ISL33002 and ISL33003
ACC
EN
ISL33002 only
ISL33001 and ISL33003
PRECHARGE
CIRCUIT
SCL_IN
SCL_OUT
M4
U3
M3
U4
FIGURE 8. CIRCUIT BLOCK DIAGRAM
With careful choosing of components, driving a bus with
the I C specified maximum bus capacitance of 400pF at
Application Information
2
The ISL33001, ISL33002, ISL33003 ICs are 2-Wire
Bidirectional Bus Buffers designed to drive heavy
capacitive loads in open-drain/open-collector systems.
The ISL33001, ISL33002, ISL33003 incorporate rise time
accelerator circuitry that improves the rise time for
systems that use a passive pull-up resistor for logic
HIGH. These devices also feature hot swapping circuitry
for applications that require hot insertion of boards into a
host system (i.e., servers racks and I/O card modules).
The ISL33001 features a logic output flag (READY) that
signals the status of the buffer and an EN pin to enable or
disable the buffer. The ISL33002 features two separate
supply pins for voltage level shifting on the I/O pins and
a logic input to disable the rise time accelerator circuitry.
The ISL33003 features an EN pin and the level shifting
functionality.
400kHz data rate is possible.
Start-Up Sequencing and Hot Swap Circuitry
The ISL33001, ISL33002, ISL33003 buffers contain
undervoltage lock out (UVLO) circuitry that prevents
operation of the buffer until the IC receives the proper
supply voltage. For V
and V , this voltage is
CC1
CC2
approximately 1.8V on the rising edge of the supply
voltage. Externally driven signals at the SDA/SCL pins
are ignored until the device supply voltage is above 1.8V.
This prevents communication errors on the bus until the
device is properly powered up. The UVLO circuitry is also
triggered on the falling edge when the supply voltage
drops below 1.7V.
Once the IC comes out of the UVLO state, the buffer will
remain disconnected until it detects a valid connection
state. A valid connection state is either a BUS IDLE
condition (see Figure 2) or a STOP BIT condition (a rising
edge on SDA_IN when SCL_IN is high) along with the
SCL_OUT and SDA_OUT pins being logic high.
2
I C and SMBUS Compatibility
The ISL33001, ISL33002, ISL33003 ICs are I C and
2
SMBUS compatible devices, designed to work in
open-drain/open-collector bus environments. The ICs
support both clock stretching and bus arbitration on the
SDA and SCL pins. They are designed to operate from DC
to more than 400kHz, supporting Fast Mode data rates of
Note - For the ISL33001 and ISL33003 with EN pins,
after coming out of UVLO, there will be an additional
delay from the enable circuitry if the EN pin voltage is not
rising at the same time as the supply pins (see Figure 1)
before a valid connection state can be established.
2
the I C specification.
In addition, the buffer rise time accelerators are designed
to increase the capacitive drive capability of the bus.
FN7560.2
September 30, 2010
9
ISL33001, ISL33002, ISL33003
Coming out of UVLO but prior to a valid connection state,
the SDA and SCL pins are pre-charged to 1V to allow hot
insertion. Because the bus at any time can be between
typically 40mV. Reducing the pull-up resistor values
increases the sink current and increases the output
voltage of the buffer for a given input low voltage
(Figures 15, 16, 17, 18).
0V and V , pre-charging the I/O pins to 1V reduces the
CC
maximum differential voltage from the buffer I/O pin and
the active bus. The pre-charge circuitry reduces system
disturbance when the IC is hot plugged into a live back
plane that may have the bus communicating with other
devices.
Rise Time Accelerators
The ISL33001, ISL33002, ISL33003 buffer rise time
accelerators on the SDA/SCL pins improve the transient
performance of the system. Heavy load capacitance or
weak pull-up resistors on an Open-Drain bus cause the
rise time to be excessively long, which leads to data
errors or reduced data rate performance. The rise time
accelerators are only active on the low to high transitions
and provide an active constant current source to slew the
voltage on the pin quickly (Figure 19).
Note - For ISL33001 and ISL33003 with EN pins, the
pre-charge circuitry is active only after coming out of
UVLO and having the device enabled.
Connection Circuitry
Once a valid connection condition is met, the buffer is
active and the input stage of the SDA/SCL pins is
controlled by external drivers. The output of the buffer
will follow the input of the buffer. The directionality of the
IN/OUT pins are not exclusive (bi-directional operation)
and functionally behave identical to each other. Being a
two channel buffer, the SDA and SCL pins also behave
identically. In addition, the SDA and SCL portions of the
buffer are independent from each other. The SDA pins
can be driven in one direction while the SCL pins can be
driven opposite.
The rise time accelerators are triggered immediately
after the buffer release threshold (approximately 30% of
V
) on both sides of the buffer is crossed. Once
CC
triggered, the accelerators are active for a defined pulse
width (Figure 20) with the current source turning off as it
approaches the supply voltage.
Enable Pin (ISL33001 and ISL33003)
When driven high, the enable pin puts the buffer into its
normal operating state. After power-up, EN high will
activate the bus pre-charge circuitry and wait for a valid
connection state to enable the buffer and the accelerator
circuitry.
Refer to Figure 8 for the operation of the bi-directional
buffer. When the input stage of the buffer on one side is
driven low by an external device, the output of the buffer
drives an open-drain transistor to pull the ‘output’ pin
low. The ‘output’ pin will continue to be held low by the
transistor until the external driver on the ‘input’ releases
the bus.
Driving the EN pin low disables the accelerators, disables
the buffer so that signals on one side of the buffer will be
isolated from the other side, disables the pre-charge
circuit and places the device in a low power shutdown
state.
To prevent the buffer from entering a latched condition
where both internal transistors are actively pulling the
I/O pins low, the buffer is designed to be active in only
one direction. The buffer logic circuitry senses which
input stage is being externally driven low and sets that
buffer to be the active one. For example, referring to
Figure 8, if SDA_OUT is externally driven low, buffer U2
will be active and buffer U1 is inactive. M1 is turned on to
drive SDA_IN low, effectively buffering the signal from
SDA_OUT to SDA_IN. The low signal at the input of U1
will not turn M2 on because U1 remains inactive,
preventing a latch condition.
READY Logic Pin (ISL33001 Only)
The READY pin is a digital output flag for signaling the
status of the buffer. The pin is the drain of an Open-Drain
NMOS. Connect a resistor from the READY pin to V
provide the high pull-up. The recommended value is
to
CC1
10kΩ.
When the buffer is disabled by having the EN pin low or if
the start-up sequencing is not complete, the READY pin
will be pulled low by the NMOS. When the buffer has the
EN pin high and a valid connection state is made at the
SDA/SCL pins, the READY pin will be pulled high by the
pull-up resistor. The READY pin is capable of sinking 3mA
when pulled low while maintaining a voltage of less than
0.4V.
Buffer Output Low and Offset Voltage
By design, when a logic input low voltage is forced on the
input of the buffer, the output of the buffer will have an
input to output offset voltage. The output voltage of the
buffer is determined by Equation 1:
ACC Accelerator Pin (ISL33002 Only)
The ACC logic pin controls the rise time accelerator
circuitry of the buffer. When ACC is driven high, the
accelerators are enabled and will be triggered when
crossing the buffer release threshold. When ACC is driven
low, the accelerators are disabled.
V
= V + V
+ [V
⁄ R
× R
]
ON
(EQ. 1)
OUT
IN
OS
CC
PULL-UP
Where V
OS
is the buffer internal offset voltage, R is
Pull-Up
and
is the ON resistance of the buffer’s internal NMOS
the pull up resistance on the SDA/SCL pin to V
CC
R
ON
pull-down device. The last term of the equation is the
additional voltage drop developed by sink current and
For lightly loaded buses, having the accelerators active
may cause ringing or noise on the rising edge transition.
Disabling the accelerators will have the buffers continue
the internal resistance of the transistor. The V
of the
OS
buffer can be determined by Figures 17, 18 and is
FN7560.2
September 30, 2010
10
ISL33001, ISL33002, ISL33003
to perform level shifting with the V
and provide capacitance buffering.
and V
CC2
supplies
propagation delay of the buffer, there will be additional
delay from the different capacitive loading of the buffer.
Figures 21 and 22 show how the propagation delay from
CC1
Propagation Delays
high to low, t
loading.
, is affected by V and capacitive
PHL CC
On a low to high transition, the rising edge signal is
determined by the bus pull-up resistor, load capacitance,
and the accelerator current from the ISL33001,
ISL33002, ISL33003 buffer. Prior to the accelerators
becoming active, the buffer is connected and the output
voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released
and the signal on each side of the buffer rises
The buffer’s propagation delay times for rising and falling
edge signals must be taken into consideration for the
timing requirements of the system. SETUP and HOLD
times may need to be adjusted to take into account
excessively long propagation delay times caused by
heavy bus capacitances.
independently. The accelerator current on both sides of
the buffer will be equal. If the pull-up resistance on both
sides of the buffer are also equal, then differences in the
rise time will be proportional to the difference in
capacitive loading on the two sides.
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel
buffers are designed to improve the rise time of the bus
in passive pull-up systems, proper selection of the
pull-up resistor is critical for system operation when a
buffer is used. For a bus that is operating normally
without active rise time circuitry, using the ISL33001,
ISL33002, ISL33003 buffer will allow larger pull-up
resistor values to reduce sink currents when the bus is
driving low. However, choose a pull-up resistor value of
no larger than 20kΩ regardless of the bus capacitance
seen on the SDA/SCL lines. The Bus Idle or Stop Bit
condition requires valid logic high voltages to give a valid
connection state. Pull-up resistor values 20kΩ or smaller
are recommended to overcome the typical 150kΩ
impedance of the pre-charge circuitry, delivering valid
high levels.
Because the signals on each side of the buffer rise
independently, the propagation delay can be positive or
negative. If the input side rises slowly relative to the
output (i.e., heavy capacitive loading on the input and
light load on the output) then the propagation delay t
PLH
is negative. If the output side rises slowly relative to the
input, t is positive.
PLH
For high to low transitions, there is a finite propagation
delay through the buffer from the time an external low
on the input drives the NMOS output low. This
propagation delay will always be positive because the
buffer connect threshold on the falling edge is below the
measurement points of the delay. In addition to the
Typical Performance Curves
C
= C
OUT
= 10pF, V
= V
CC2
= V , T = +25°C; Unless Otherwise
CC
IN
CC1
A
Specified.
2.4
600
550
500
2.3
T = -40°C
2.2
T = +25°C
2.1
2.0
T = +25°C
450
400
350
300
250
200
150
100
T = +85°C
T = +85°C
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.0
2.5
3.0
3.5
4.0
V (V)
CC1
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
V
CC1
FIGURE 9. I
CC1
ENABLED CURRENT vs V
(ISL33001)
FIGURE 10. I
DISABLED CURRENT vs V
CC1
CC1
CC1
(ISL33001)
FN7560.2
September 30, 2010
11
ISL33001, ISL33002, ISL33003
Typical Performance Curves
C
= C
OUT
= 10pF, V
CC1
= V
= V , T = +25°C; Unless Otherwise
CC
IN
CC2
A
Specified. (Continued)
2.4
60
V
= 5.5V
V
= 5.5V
CC2
CC2
2.3
2.2
2.1
2.0
1.9
50
40
T = -40°C
T = +25°C
T = +85°C
T = +25°C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
30
20
10
0
T = +85°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
V (V)
CC1
4.5
5.0
5.5
6.0
V
(V)
CC1
FIGURE 11. I
ENABLED CURRENT vs V
FIGURE 12. I
DISABLED CURRENT vs V
CC1
CC1
CC1
CC1
(ISL33003)
(ISL33002 AND ISL33003)
0.24
0.22
0.20
0.18
0.16
0.14
60
50
40
30
20
10
0
T = +25°C
V
= 5.5V
CC1
V
= 5.5V
CC1
T = -40°C
T = +85°C
T = +25°C
T = +85°C
0.12
0.10
2.0 2.5
3.0
3.5
4.0
(V)
4.5 5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
(V)
V
CC2
CC2
FIGURE 14. I
DISABLED CURRENT vs V
CC2
FIGURE 13. I
ENABLED CURRENT vs V
CC2
CC2
(ISL33003)
CC2
(ISL33002 AND ISL33003)
120
100
80
60
40
20
0
120
100
80
T = -40°C
V
= 2.3V
CC
T = +25°C
T = +85°C
60
V
= 2.7V
CC
40
V
= 4.5V
CC
20
0
V
V
= 3.3V
= 0V
CC
IN
V
= 0V
2
IN
0
1
2
3
4
5
6
7
8
9
10 11
0
1
3
4
5
6
7
8
9
10 11
I
(mA)
OL
I
(mA)
OL
FIGURE 16. SDA/SCL OUTPUT LOW VOLTAGE vs SINK
CURRENT vs TEMPERATURE
FIGURE 15. SDA/SCL OUTPUT LOW VOLTAGE vs SINK
CURRENT vs V
CC
FN7560.2
September 30, 2010
12
ISL33001, ISL33002, ISL33003
Typical Performance Curves
C
= C
OUT
= 10pF, V
CC1
= V
CC2
= V , T = +25°C; Unless Otherwise
CC
IN
A
Specified. (Continued)
100
90
100
90
T = -40°C
T = +25°C
V
= 5.5V
CC
80
70
60
50
40
30
20
10
0
80
T = +85°C
70
60
50
40
30
20
10
0
V
= 3.3V
CC
V
= 2.3V
CC
V
= 3.3V
CC
V
= 0.2V
IN
V
= 0.2V
IN
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
I
(mA)
I
(mA)
OL
OL
FIGURE 17. INPUT TO OUTPUT OFFSET VOLTAGE vs
FIGURE 18. INPUT TO OUTPUT OFFSET VOLTAGE vs
SINK CURRENT vs TEMPERATURE
SINK CURRENT vs V
CC
800
12
11
10
(See Figure 7)
T = -40°C
700
T = +25°C
600
500
400
T = -40°C
9
8
T = +85°C
T = +85°C
7
6
5
T = +25°C
300
200
4
3
2.0 2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0 2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
CC
V
VCC (V)
CC
FIGURE 19. ACCELERATOR PULL-UP CURRENT vs V
FIGURE 20. ACCELERATOR PULSE WIDTH vs V
CC
50
50
R
= 2.7kΩ
PULL-UP
T = +85°C
T = +25°C
T = +85°C
C
C
= 10pF
IN
= 100pF
OUT
40
30
40
30
T = +25°C
20
20
T = -40°C
T = -40°C
V
= 3.3V
CC
10
0
10
0
R
C
= 10kΩ
PULL-UP
= 50pF
IN
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
0
100 200 300 400 500 600 700 800 900
(pF)
C
V
OUT
CC
FIGURE 22. PROPAGATION DELAY H-L vs C
FIGURE 21. PROPAGATION DELAY H-L vs V
OUT
CC
FN7560.2
September 30, 2010
13
ISL33001, ISL33002, ISL33003
Typical Performance Curves
C
= C
OUT
= 10pF, V
CC1
= V
CC2
= V , T = +25°C; Unless Otherwise
CC
IN
Specified. (Continued)
A
12
V
= 2.3V
CC
11
10
V
= 5.5V
CC
V
= 3.3V
CC
9
8
7
6
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
FIGURE 23. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs V
CC
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
GND
PROCESS:
0.25µm CMOS
FN7560.2
September 30, 2010
14
ISL33001, ISL33002, ISL33003
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
FN7560.2
FN7560.1
CHANGE
9/13/10
4/30/10
Added SOIC package information to datasheet for ISL33001.
Changed typical value of “Supply Current from V
to 2.1mA.
” on page 4 for ISL33001 only from 2.2mA
CC1
Changed typical value of “Input-Output Offset Voltage” on page 5 from 100mV to 50mV.
3/18/10
FN7560.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL33001, ISL33002, ISL33003
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
FN7560.2
September 30, 2010
15
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3H
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 2/08
2.38
1.50 REF
3.00
A
PIN #1 INDEX AREA
6
6 X 0.50
6
PIN 1
INDEX AREA
B
8 X 0.40
1
4
2.20
3.00
1.64
(4X)
0.15
5
8
0.10 M C A B
8 X 0.25
TOP VIEW
BOTTOM VIEW
( 2.38 )
SEE DETAIL "X"
0 .80 MAX
C
0.10
C
BASE PLANE
SEATING PLANE
0.08
C
2 . 80
( 2 .20 )
SIDE VIEW
0.2 REF
( 1.64 )
C
8X 0.60
0 . 00 MIN.
0 . 05 MAX.
( 8X 0.25 )
DETAIL “X”
( 6X 0 . 5 )
NOTES:
1. Dimensions are in millimeters.
TYPICAL RECOMMENDED LAND PATTERN
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7560.2
September 30, 2010
16
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN7560.2
September 30, 2010
17
ISL33001, ISL33002, ISL33003
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.036
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7560.2
September 30, 2010
18
ISL33001, ISL33002, ISL33003
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
0.25(0.010)
M
L
B M
H
AREA
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7560.2
September 30, 2010
19
相关型号：
ISL33334EIAZ
3.3V, ±15kV ESD Protected, Two Port, Dual Protocol (RS-232/RS-485) Transceiver in a SSOP Package; SSOP28; Temp Range: -40° to 85°C
RENESAS
©2020 ICPDF网 联系我们和版权申明