ISL28110FBBZ [INTERSIL]
Precision Low Noise JFET Operational Amplifiers; 精密，低噪声JFET运算放大器
| 型号： | ISL28110FBBZ |
| 厂家： | 
Intersil |
| 描述： | Precision Low Noise JFET Operational Amplifiers |
| 文件： | 总25页 (文件大小：1053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Low Noise JFET Operational Amplifiers
ISL28110, ISL28210
Features
• Wide Supply Range. . . . . . . . . . . . . . . . .9V to 40V
• Low Voltage Noise . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . 2pA
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . .23V/µs
• High Bandwidth . . . . . . . . . . . . . . . . . . . .12.5MHz
• Low Input Offset . . . . . . . . . . . . . . . . .300µV, Max
• Offset Drift . . . . . . . . . . . . . . . . Grade C 10µV/°C
• Low Current Consumption . . . . . . . . . . . . . 2.55mA
• Operating Temperature Range . . . -40°C to +125°C
• Small Package Offerings in Single, and Dual
The ISL28110, ISL28210, are single and dual JFET
amplifiers featuring low noise, high slew rate, low input
bias current and offset voltage, making them the ideal
choice for high impedance applications where precision
and low noise are important. The combination of
precision, low noise, and high speed combined with a
small footprint provides the user with outstanding value
and flexibility relative to similar competitive parts.
Applications for these amplifiers include precision medical
and analytical instrumentation, sensor conditioning,
precision power supply controls, industrial controls and
photodiode amplifiers.
• Pb-Free (RoHS compliant)
The ISL28110 single amplifier is available in the 8 Ld
SOIC, TDFN, and MSOP packages. The ISL28210 dual
amplifier is available in the 8 Ld SOIC and TDFN
packages. All devices are offered in standard pin
configurations and operate over the extended
temperature range from -40°C to +125°C.
Applications*(see page 22)
• Precision Instruments
• Photodiode Amplifiers
• High Impedance Buffers
• Medical Instrumentation
• Active Filter Blocks
• Industrial Controls
Typical Application
Input Bias Current vs Common
Mode Input Voltage
R
F
10
V
= ±15V
S
8
6
C
F
4
V
+
2
0
-
PHOTO
DIODE
-2
-4
-6
-8
-10
R
C
OUTPUT
SH
T
+
V
-
-15
-10
-5
0
5
10
15
V
(V)
CM
BASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER
December 8, 2010
FN6639.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL28110, ISL28210
Pin Configurations
ISL28110
(8 LD TDFN)
TOP VIEW
ISL28110
(8 LD, SOIC, MSOP)
TOP VIEW
NC
-IN A
+IN A
1
2
3
4
8
7
6
5
NC
NC
NC
1
2
3
4
8
7
6
V
+
-IN A
V
+
-
+
- +
PAD
V
A
+IN A
V
A
OUT
OUT
V
-
5 NC
V
-
NC
ISL28210
(8 LD TDFN)
TOP VIEW
ISL28210
(8 LD SOIC)
TOP VIEW
V
A
V
V
V A
OUT
1
2
3
4
8
7
6
5
V
+
1
8
7
6
OUT
+
-IN A
+IN A
B
-IN A
V
B
2
3
4
- +
OUT
OUT
- +
-IN B
+IN A
-IN B
+IN B
-
+
+ -
PAD
V
5 +IN B
-
V
-
Pin Descriptions
ISL28110
ISL28110
(8 Ld SOIC,
ISL28210
ISL28210
PIN
NAME
EQUIVALENT
CIRCUIT
(8 Ld TDFN) 8 Ld MSOP) (8 Ld TDFN) (8 Ld SOIC)
DESCRIPTION
3
2
6
4
3
2
6
4
3
2
1
4
5
6
7
8
3
2
1
4
5
6
7
8
+IN A
-IN A
Circuit 1
Circuit 1
Circuit 2
Circuit 3
Circuit 1
Circuit 1
Circuit 2
Circuit 3
Amplifier A non-inverting input
Amplifier A inverting input
Amplifier A output
VOUT A
V-
Negative power supply
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
+IN B
-IN B
VOUT B
7
7
V+
Positive power supply
No connect
1, 5, 8
PAD
1, 5, 8
PAD
PAD
Thermal Pad is electrically
isolated from active circuitry. Pad
can float, connect to Ground or to
a potential source that is free
from signals or noise sources.
V
+
V
+
V
+
CAPACITIVELY
TRIGGERED
ESD CLAMP
OUT
IN-
IN+
V
-
V
-
V
-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN6639.1
December 8, 2010
2
ISL28110, ISL28210
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
TCVOS
(µV/°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
MARKING
28110 FBZ -C
28210 FBZ -C
ISL28110FBZ
10 (C Grade)
10 (C Grade)
8 Ld SOIC
M8.15E
ISL28210FBZ
8 Ld SOIC
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld SOIC
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
M8.15E
L8.3x3A
L8.3x3A
L8.3x3A
L8.3x3A
M8.15E
M8.15E
M8.118
M8.118
Coming Soon
ISL28110FRTZ
-C 8110
-C 8210
8110
10 (C Grade)
10 (C Grade)
4 (B Grade)
4 (B Grade)
4 (B Grade)
4 (B Grade)
4 (B Grade)
10 (C Grade)
Coming Soon
ISL28210FRTZ
Coming Soon
ISL28110FRTBZ
Coming Soon
ISL28210FRTBZ
8210
Coming Soon
ISL28110FBBZ
28110 FBZ -C
28210 FBZ
8110Z
Coming Soon
ISL28210FBBZ
Coming Soon
ISL28110FUBZ
Coming Soon
ISL28110FUZ
8110Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications..
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on
MSL please see techbrief TB363.
FN6639.1
December 8, 2010
3
ISL28110, ISL28210
Absolute Voltage Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Turn On Voltage Slew Rate . . . . . . . .1V/µs
Maximum Differential Input Voltage . . . . . . . . . . . . . . . 33V
Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . .±20mA
Output Short-Circuit Duration
(1 output at a time) . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical)
θ
JA (°C/W)
θ
JC (°C/W)
8 Ld SOIC (Notes 5, 7)
ISL28110 . . . . . . . . . . . . . . . . .
ISL28210 . . . . . . . . . . . . . . . . .
8 Ld TDFN (Notes 4, 6)
ISL28110 . . . . . . . . . . . . . . . . .
ISL28210 . . . . . . . . . . . . . . . . .
8 Ld MSOP (Notes 5, 7)
125
120
70
50
48
46
7.8
4.5
ISL28110 . . . . . . . . . . . . . . . . .
158
60
Ambient Operating Temperature Range . . . -40°C to +125°C
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VS = ±5V, VCM = 0, VOUT = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNITS
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-300
300
1300
10
µV
µV
-40°C < TA < +125°C
-40°C < TA < +125°C
-1300
TCVOS
IB
Input Offset Voltage
Temperature Coefficient
1
µV/C
Input Bias Current
ISL28110
-2
-5.3
-36
±0.3
2
5.3
36
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pF
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-235
-2
235
2
Input Bias Current
ISL28210
±0.3
±0.15
±0.15
8.3
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-4.5
-50
4.5
50
-245
-1
245
1
IOS
Input Offset Current
ISL28110
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-2.25
-30
2.25
30
-105
-1
105
1
Input Offset Current
ISL28210
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-3.5
-32
3.5
32
-245
245
CIN-DIFF
Differential Input Capacitance
FN6639.1
December 8, 2010
4
ISL28110, ISL28210
Electrical Specifications VS = ±5V, VCM = 0, VOUT = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNITS
CIN-CM
Common Mode Input
Capacitance
11.8
pF
RIN-DIFF
RIN-CM
VCMIR
Differential Input Resistance
530
560
GΩ
GΩ
Common Mode Input Resistance
Common Mode Input Voltage
Range
Guaranteed by CMRR test
V- + 1.5
V+ - 1.5
V
V- + 2.5
V+ - 2.5
V
CMRR
AVOL
Common Mode Rejection Ratio
V
V
CM = -3.5V to +3.5V
CM = -2.5V to +2.5V
90
dB
dB
dB
dB
88
104
103
100
108
Open-loop Gain
RL = 10kΩ to ground
O = -3V to +3V
V
DYNAMIC PERFORMANCE
GBWP
SR
Gain-bandwidth Product
G = 100, RL = 100kΩ, CL = 4pF
G = -1, RL = 2kΩ, 4V Step
11
12.5
20
MHz
V/µs
%
Slew Rate, VOUT 20% to 80%
THD+N
Total Harmonic Distortion +
Noise
G = 1, f = 1kHz, 4VP-P, RL = 2kΩ
G = 1, f = 1kHz, 4VP-P, RL = 600Ω
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
0.0002
0.0003
0.4
%
ts
Settling Time to 0.1%
4V Step; 10% to VOUT
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
1
µs
NOISE PERFORMANCE
enP-P Peak-to-Peak Input Voltage
0.1Hz to 10Hz
580
nVP-P
Noise
en
Input Voltage Noise Spectral
Density
f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
f = 1kHz
14
7
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
6
6
in
Input Current Noise Spectral
Density
9
OUTPUT CHARACTERISTICS
VOL
VOH
ISC
Output Voltage Low, VOUT to V- RL = 10kΩ
0.8
0.9
0.8
0.9
±50
1.0
1.1
1.1
1.2
1.0
1.1
1.1
1.2
V
V
R
L = 2kΩ
V
V
Output Voltage High, V+ to VOUT RL to GND = 10kΩ
V
V
R
L to GND = 2kΩ
V
V
Output Short Circuit Current
RL = 10Ω to V+. V-
mA
POWER SUPPLY
VSUPPLY
PSRR
Supply Voltage Range
Guaranteed by PSRR
±4.5
102
±20V
V
Power Supply Rejection Ratio
Supply Current/Amplifier
VS = ± 4.5V to ±5V
115
2.5
dB
dB
mA
mA
100
IS
2.9
3.8
FN6639.1
December 8, 2010
5
ISL28110, ISL28210
Electrical Specifications VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNITS
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-300
300
1300
10
µV
µV
-40°C < TA < +125°C
-40°C < TA < +125°C
-1300
TCVOS
IB
Input Offset Voltage Temperature
Coefficient (Grade C)
1
µV/C
Input Bias Current
ISL28110
4.5
-25
±2
4.5
25
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pF
pF
GΩ
GΩ
V
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-85
85
-950
5
950
5
IB
Input Bias Current
ISL28210
±2
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
-350
-700
-3600
-2.5
-25
350
700
3600
2.5
IOS
Input Offset Current
ISL28110
±0.5
±0.5
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
25
-85
85
-650
-2.5
-285
-445
-2000
650
2.5
IOS
Input Offset Current
ISL28210
-40°C < TA < +60°C
-40°C < TA < +85°C
-40°C < TA < +125°C
285
445
2000
CIN-DIFF
CIN-CM
RIN-DIFF
RIN-CM
VCMIR
Differential Input Capacitance
Common Mode Input Capacitance
Differential Input Resistance
Common Mode Input Resistance
8.3
11.8
530
560
Common Mode Input Voltage Range Guaranteed by CMRR test
V- + 1.5
80
V+ - 1.5
CMRR
AVOL
Common Mode Rejection Ratio
Open-loop Gain
VCM = -13.5V to +13.5V
100
dB
dB
RL = 10kΩ to ground
107
109
V
O = -12.5V to +12.5V
-40°C < TA < +125°C
106
dB
DYNAMIC PERFORMANCE
GBWP
SR
Gain-bandwidth Product
G = 100, RL = 100kΩ, CL = 4pF
G = -1, RL = 2kΩ, 10V Step
11
12.5
20
MHz
V/µs
%
Slew Rate, VOUT 20% to 80%
THD+N
Total Harmonic Distortion + Noise
G = 1, f = 1kHz,
0.00025
10VP-P, RL = 2kΩ
G = 1, f = 1kHz,
10VP-P, RL = 600Ω
0.0003
1.3
%
µs
µs
ts
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2k
to VCM
Ω
Ω
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2k
to VCM
1.6
FN6639.1
December 8, 2010
6
ISL28110, ISL28210
Electrical Specifications VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNITS
NOISE PERFORMANCE
enP-P
en
Peak-to-Peak Input Voltage Noise
0.1Hz to 10Hz
600
18
7.8
6
nVP-P
Input Voltage Noise Spectral Density f = 10Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
f = 100Hz
f = 1kHz
f = 10kHz
6
in
Input Current Noise Spectral Density f = 1kHz
9
OUTPUT CHARACTERISTICS
VOL
VOH
ISC
Output Voltage Low,
OUT to V-
RL = 10kΩ
0.8
0.9
1.0
1.1
1.1
1.2
1.0
1.1
1.1
1.2
V
V
V
RL = 2kΩ
V
V
Output Voltage High,
+ to VOUT
RL to GND = 10kΩ
RL to GND = 2kΩ
RL = 10Ω to V+. V-
0.8
V
V
V
0.9
V
V
Output Short Circuit Current
±50
115
2.55
mA
POWER SUPPLY
PSRR
IS
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
102
dB
100
dB
Supply Current/Amplifier
3.1
mA
mA
3.9
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6639.1
December 8, 2010
7
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified.
25
20
15
10
5
250
200
150
100
50
V
= ±15V
T
= -40°C TO +125°C
S
V
= ±15V
A
S
0
0
-10 -8
-6
-4
-2
0
2
4
6
8
10
-150 -100 -50
0
50
(µV)
100
150
200
250
TCV (µV/C)
V
OS
OS
FIGURE 1. INPUT OFFSET VOLTAGE (VOS
DISTRIBUTION
)
FIGURE 2. TCVOS DISTRIBUTION, -40°C to +125°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
0
-10
-20
V
= ±5V
S
-30
-40
-50
-60
-70
-80
V
= ±15V
S
5
6
7
8
9
10
11
12
13
14
15
-40
-20
0
20
40
60
80
100 120 140
±V
(±V)
TEMPERATURE (°C)
SUPPLY
FIGURE 3. INPUT BIAS CURRENT (IB) vs SUPPLY
VOLTAGE
FIGURE 4. ISL28110 INPUT BIAS CURRENT (IB) vs
TEMPERATURE
100
0
20
-100
-200
10
0
V
= ±5V
S
V
= ±5V
S
-300
-400
-500
-600
-700
-800
-900
-1000
-1100
V
= ±15V
S
-10
-20
V
= ±15V
40
S
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. ISL28210 INPUT BIAS CURRENT (IB) vs
TEMPERATURE
FIGURE 6. ISL28110 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE
FN6639.1
December 8, 2010
8
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
20
10
0
300
250
200
150
100
50
V
= ±15V
S
V
= ±5V
S
I
CHA
CHB
OS
I
CHA
OS
S
I
O
OS
-10
I
CHB
OS
0
-20
-40
-50
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ±5V
FIGURE 8. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ±15V
10
4.0
V
= ±5V
V = ±15V
S
S
8
6
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
2
0
-2
-4
-6
-8
-10
-0.5
-1.0
-5
-4
-3
-2
-1
0
1
2
3
4
5
-15
-10
-5
0
5
10
15
V
(V)
V
(V)
CM
CM
FIGURE 9. NORMALIZED INPUT BIAS CURRENT (IB) vs
INPUT COMMON MODE VOLTAGE (VCM),
VS = ±5V
FIGURE 10. NORMALIZED INPUT BIAS CURRENT (IB)
vs INPUT COMMON MODE VOLTAGE (VCM),
VS = ±15V
500
500
V
= ±5V
V
= ±15V
S
S
400
300
200
100
0
400
300
200
100
0
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-5
-4
-3
-2
-1
0
1
2
3
4
5
-15
-10
-5
0
CM
5
10
15
V
(V)
V
(V)
CM
FIGURE 11. NORMALIZED INPUT OFFSET VOLTAGE
FIGURE 12. NORMALIZED INPUT OFFSET VOLTAGE
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ±5V
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ±15V
FN6639.1
December 8, 2010
9
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
1000
100
10
1000
100
10
1000
100
10
1000
100
10
V
= ±5V
V
= ±18V
S
S
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
1
0.1
1
1
0.1
1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±5V
FIGURE 14. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±18V
1000
1000
V
= ±5V
= 10k
V
A
= ±18V
= 10k
S
S
800
600
800
600
A
V
V
400
400
200
200
0
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
TIME (s)
FIGURE 15. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS =±5V
FIGURE 16. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS = ±18V
0.1
0.1
V
= ±15V
= 4pF
= 600
= 10V
C-WEIGHTED
22Hz to 500kHz
C-WEIGHTED
22Hz to 500kHz
V
= ±15V
= 4pF
= 2k
S
S
C
R
V
C
R
V
L
L
L
L
= 10V
OUT
P-P
OUT
P-P
0.01
0.001
0.01
0.001
-40°C
-40°C
+125°C
+125°C
+125°C
+125°C
+25°C
+25°C
+25°C
+25°C
A
= 10
V
A
= 10
V
-40°C
100
-40°C
A
= 1
V
A
= 1
V
0.0001
0.0001
10
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 17. THD+N vs FREQUENCY vs TEMPERATURE,
FIGURE 18. THD+N vs FREQUENCY vs TEMPERATURE,
AV = 1, 10, VOUT = 10VP-P, RL = 600Ω
VOUT = 10VP-P, RL = 2kΩ
FN6639.1
December 8, 2010
10
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
1
0.1
1
A
= 1
V
C
R
= ±15V
= 4pF
= 600
V = ±15V
S
A
= 1
V
S
V
C = 4pF
L
L
L
R = 2k
L
f = 1kHz
f = 1kHz
0.1
C-WEIGHTED
22Hz to 22kHz
C-WEIGHTED
22Hz to 22kHz
0.01
0.01
+25°C
+25°C
0.001
0.0001
0.001
0.0001
+125°C
20
+125°C
20
-40°C
30
-40°C
0
5
10
15
(V
25
0
5
10
15
(V
25
30
V
)
V
)
P-P
OUT
P-P
OUT
FIGURE 19. THD+N vs OUTPUT VOLTAGE (VOUT) vs
FIGURE 20. THD+N vs OUTPUT VOLTAGE (VOUT) vs
TEMPERATURE, AV = 1 f = 1kHz, RL = 600Ω
TEMPERATURE, AV = 1 f =1kHz, RL = 2kΩ
60
50
40
30
20
10
0
0
-20
V
V
= ±15V
V
C
V
= ±15V
= 4pF
S
S
= 100mV
OUT
P-P
L
= 1V
R -
= 2k
CM
P-P
L TRANSMIT
R _
= 10k
RECEIVE
-40
L
A
= 10
V
-60
A
= -1
V
-80
R -
= ∞
L TRANSMIT
A
= 1
V
R _
= ∞
RECEIVE
L
-100
-120
-140
0.001
0.01
0.1
1
10
100
1
10
100
1k
10k
100k 1M
10M 100M
FREQUENCY (Hz)
LOAD CAPACITANCE (nF)
FIGURE 21. CROSSTALK vs FREQUENCY
FIGURE 22. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE (CL)
200
70
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
A
= 1000
R
= 100kΩ, R = 100Ω
G
CL
F
60
50
40
30
20
10
0
PHASE
R
= 100kΩ, R = 1kΩ
G
F
A
A
= 100
= 10
CL
V
= ±5V & ±15V
= 4pF
= OPEN
S
C
R
V
L
L
= 100mV
CL
OUT
P-P
GAIN
R
A
= 100kΩ, R = 10kΩ
G
F
= 1
CL
V
= ±15V
S
R =1MΩ
L
R
= 0, R = ∞
F
G
-10
0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 23. OPEN LOOP GAIN-PHASE vs FREQUENCY
FIGURE 24. CLOSED LOOP GAIN vs FREQUENCY
FN6639.1
December 8, 2010
11
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
120
110
100
90
80
70
60
50
40
30
20
10
0
130
120
110
100
90
PSRR-
80
70
60
50
V
A
C
R
V
= ±15V
= 1
S
40
V
PSRR+
30
= 4pF
= 10k
= 1V
L
L
V
= ±15V
20
S
SIMULATION
CM
P-P
10
0
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. POWER SUPPLY REJECTION RATIO (PSRR)
vs FREQUENCY
FIGURE 26. COMMON-MODE REJECTION RATIO (CMRR)
vs FREQUENCY
5
4
15
14
13
12
11
-40°C
-40°C
3
125°C
= ±15V
25°C
+125°C
2
+25°C
V
S
V
A
R
V
= ±5V
= 2
= R = 100k
S
1
-1
A = 2
10
-10
V
R
V
V
= R = 100k
F
G
F
G
= 7.5V
-11
-12
-13
IN
P-P
= 2.5V
P-P
-2
-3
-4
-5
IN
+85°C
85°C
0°C
60
-14
-15
0°C
60
0
10
20
30
40
50
70
0
10
20
30
40
50
70
I-FORCE (mA)
I-FORCE (mA)
FIGURE 27. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±5V
FIGURE 28. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±15V
0
200
20
0
V
= ±15V
S
INPUT
INPUT
A
R
= 100
= 10k
= 100mV
V
-4
160
120
80
40
0
16
12
8
-40
L
V
IN
P-P
OVERDRIVE = 1V
-8
-80
OUTPUT
A
= 1
-12
-16
-20
V
-120
V
A
R
V
= ±15V
= 100
= 10k
OUTPUT
S
V
4
-160
-200
L
= 100mV
IN
P-P
OVERDRIVE = 1V
0
0
2
4
6
8
10
12
14 16 18 20
0
2
4
6
8
10
TIME (µs)
12
14
16
18
20
TIME (µs)
FIGURE 29. POSITIVE OUTPUT OVERLOAD RECOVERY
TIME
FIGURE 30. NEGATIVE OUTPUT OVERLOAD RECOVERY
TIME
FN6639.1
December 8, 2010
12
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
30
25
20
15
10
5
30
25
20
15
10
5
-SR
-SR
+SR
+SR
V
V
R
C
= ±5V
V
= ±15V
S
S
= 4V
V
= 10V
OUT-PP
OUT-PP
= 2k
= 4pF
R
C
= 2k
= 4pF
L
L
L
L
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
GAIN
GAIN
FIGURE 31. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±5V
FIGURE 32. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±15V
30
25
30
-SR
25
20
-SR
20
+SR
15
15
+SR
10
10
V
V
= ±5V
V
= ±15V
S
S
= 4V
V
= 10V
OUT-PP
OUT-PP
5
0
5
0
R
C
= 2k
= 4pF
R
C
= 2k
= 4pF
L
L
L
L
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
GAIN
GAIN
FIGURE 33. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±5V
FIGURE 34. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±15V
6
0.15
V
A
R
C
= ±15V
= 1
= 2k
S
V
= ±15V
A = 1
V
S
V
4
2
0.10
0.05
0
R
C
= 2k
L
L
L
L
= 4pF
= 4pF
0
-2
-4
-6
-0.05
-0.10
-0.15
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
TIME (µs)
1.0
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
FIGURE 35. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 36. LARGE SIGNAL UNITY GAIN TRANSIENT
RESPONSE
FN6639.1
December 8, 2010
13
ISL28110, ISL28210
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
6
4
6
4
V
= ±15V
= +10
= 2k
V
= ±15V
= -1
= 2k
S
S
A
A
V
V
R
C
R
C
L
L
L
L
= 4pF
= 4pF
2
2
0
0
-2
-4
-6
-2
-4
-6
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (µs)
FIGURE 37. LARGE SIGNAL 10V STEP RESPONSE AV = -1
FIGURE 38. LARGE SIGNAL 10V STEP RESPONSE
AV = +10
100
1000
V
= ±15V
V
V
= ±15V
S
S
= 10V
OUT
P-P
100
10
R
= 2kΩ
L
G = 10
0.01%
10
1
G = 100
0.1%
1
0.1
G = 1
1M
0.1
0.01
1
10
CLOSED LOOP GAIN (V/V)
100
10
100
1k
10k
100k
10M
100M
FREQUENCY (Hz)
FIGURE 39. SETTLING TIME (tS) vs CLOSED LOOP GAIN
FIGURE 40. ZOUT vs FREQUENCY
voltage range of ±33V. Internal ESD protection diodes
clamp the non-inverting and inverting inputs to one diode
drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5
MHz precision JFET input op amps. These devices are
fabricated in the PR40 Advanced Silicon-on-Insulator
(SOI) bipolar-JFET process to ensure latch-free
operation. The precision JFET input stage provides low
input offset voltage (300µV max @ +25°C), low input
voltage noise (6nV/√Hz), and input current noise that is
very low with virtually no 1/f component. A high current
complementary NPN/PNP emitter-follower output stage
provides high slew rate and maintains excellent THD+N
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V
reverse breakdown voltage which enables the device to
function reliably in large signal pulse applications without
the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. No
special input signal restrictions are needed for power
supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate
conditions are avoided. For power supply operation
greater than ±16V (>32V), the internal ESD clamp
diodes alone cannot clamp the maximum input
performance into heavy loads (0.0003% @ 10VP-P
1kHz into 600Ω).
@
Operating Voltage Range
differential signal to the power supply rails without the
risk of exceeding the 33V breakdown of the JFET gate.
Under these conditions, differential input voltage limiting
is necessary to prevent damage to the JFET input stage.
The devices are designed to operate over the 9V (±4.5V)
to 40V (±20V) range and are fully characterized at 10V
(±5V) and 30V (±15V). The JFET input stage maintains
high impedance over a maximum input differential
FN6639.1
December 8, 2010
14
ISL28110, ISL28210
In applications where one or both amplifier input
Output Drive Capability
terminals are at risk of exposure to voltages beyond the
supply rails, current limiting resistors may be needed at
each input terminal (see Figure 41 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
The complementary bipolar emitter follower output
stage features low output impedance (Figure 40) and is
capable of substantial current drive over the full
temperature range (Figures 27, 28) while driving the
output voltage close to the supply rails. The output
current is internally limited to approximately ±50mA at
+25°C. The amplifiers can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability.
V+
R
-
IN
-
V
-
IN
R
IN
+
V
+
R
IN
L
Output Phase Reversal
V-
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28110 and ISL28210
are immune to output phase reversal, out to 0.5V
beyond the rail (VABS MAX) limit. Beyond these limits,
the device is still immune to reversal to 1V beyond the
rails but damage to the internal ESD protection diodes
can result unless these input currents are limited.
FIGURE 41. INPUT ESD DIODE CURRENT LIMITING
JFET Input Stage Performance
The ISL28110, ISL28210 JFET input stage has the linear
gain characteristics of the MOSFET but can operate at
high frequency with much lower noise. The reversed-
biased gate PN gate junction has significantly lower gate
capacitance than the MOSFET, enabling input slew rates
that rival op amps using bipolar input stages. The added
advantage for high impedance, precision amplifiers is
the lack of a significant 1/f component of current noise
(Figures 13, 14) as there is virtually no gate current.
Maximizing Dynamic Signal Range
The amplifiers maximum undistorted output swing is a
figure of merit for precision, low distortion applications.
Audio amplifiers are a good example of amplifiers that
require low noise and low signal distortion over a wide
output dynamic range. When these applications operate
from batteries, raising the amplifier supply voltage to
overcome poor output voltage swing has the penalty of
increased power consumption and shorter battery life.
Amplifiers whose input and output stages can swing
closest to the power supply rails while providing low
noise and undistorted performance, will provide
maximum useful dynamic signal range and longer
battery life.
The input stage JFETs are bootstrapped to maintain a
constant JFET drain to source voltage which keeps the
JFET gate currents and input stage frequency response
nearly constant over the common mode input range of
the device. These enhancements provide excellent
CMRR, AC performance and very low input distortion
over a wide temperature range. The common mode
input performance for offset voltage and bias current is
shown in Figure 42. Note that the input bias current
remains low even after the maximum input stage
common mode voltage is exceeded (as indicated by the
abrupt change in input offset voltage).
Rail-to-rail input and output (RRIO) amplifiers have the
highest dynamic signal range but their added complexity
degrades input noise and amplifier distortion. Many
contain two input pairs, one pair operating to each supply
rail. The trade-offs for these are increased input noise
and distortion caused by non-linear input bias current
and capacitance when amplifying high impedance
sources. Their rail-to-rail output stages swing to within a
few millivolts of the rail, but output impedances are high
so that their output swing decreases and distortion
increases rapidly with increasing load current. At heavy
load currents the maximum output voltage swing of RRO
op amps can be lower than a good emitter follower
output stage.
10
8
500
400
300
200
100
0
V
= ±15V
S
INPUT OFFSET VOLTAGE (V
)
OS
T = +25°C
6
4
2
0
-2
-4
-6
-8
-10
-100
-200
-300
-400
-500
INPUT BIAS (I )
B
The ISL28110 and ISL28210 low noise input stage and
high performance output stage are optimized for low
THD+N into moderate loads over the full -40°C to
+125°C temperature range. Figures 19 and 20 show the
1kHz THD+N unity gain performance vs output voltage
swing at load resistances of 2kΩ and 600Ω. Figure 43
shows the unity-gain THD+N performance driving
600Ω from ±5V supplies.
-15
-10
-5
0
5
10
15
V
(V)
CM
FIGURE 42. INPUT OFFSET VOLTAGE AND BIAS
CURRENT vs COMMON MODE INPUT
VOLTAGE
FN6639.1
December 8, 2010
15
ISL28110, ISL28210
ISL28110 and ISL28210 SPICE Model
1
0.1
V
= ±5V
= 600Ω
= 1
S
Figure 44 shows the SPICE model schematic and
Figure 45 shows the net list for the SPICE model. The
model is a simplified version of the actual device and
simulates important AC and DC parameters. AC
parameters incorporated into the model are: 1/f and
flatband noise voltage, Slew Rate, CMRR, Gain and
Phase. The DC parameters are IOS, total supply current
and output voltage swing. The model uses typical
parameters given in the “Electrical Specifications” Table
beginning on page 4. The AVOL is adjusted for 125dB
with the dominant pole at 7Hz. The CMRR is set 120dB,
f = 280kHz. The input stage models the actual device to
present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
R
L
A
V
+125°C
+85°C
0.01
+25°C
0.001
0.0001
0°C
-40°C
0
1
2
3
4
5
6
7
8
9
10
V
(V)
P-P
FIGURE 43. UNITY-GAIN THD+N vs OUTPUT VOLTAGE
vs TEMPERATURE AT VS = ±5V FOR 600Ω
LOAD
Figures 46 through 59 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Small Signal 0.1V Step, Large Signal
5V Step Response, Open Loop Gain Phase, CMRR and
Output Voltage Swing for ±5V and ±15V supplies.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
T
= T
+ θ xPD
MAX JA MAXTOTAL
(EQ. 1)
JMAX
where:
• PDMAXTOTAL is the sum of the maximum power
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
dissipation of each amplifier in the package (PDMAX
)
• PDMAX for each amplifier can be calculated using
Equation 2:
V
OUTMAX
R
L
----------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
(EQ. 2)
MAX
S
qMAX
S
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
• IqMAX = Maximum quiescent supply current of 1
amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
FN6639.1
December 8, 2010
16
C3
6e-12
V++
V++
V++
V2
V3
D9
0.7Vdc
I1
240E-6
0.7Vdc
D5
10
R5
5.5k
21
R6
5.5k
G1
26
+
-
G3
+
C4
2.5e-12
C1
R9
R13
200k
-
G
1
D7
4e-12
G
22
9
20
R12
GAIN = 33
Vmid
V4
1e10
GAIN = 181.819E-6
PNP_MIRROR
Q7
PNP_MIRROR
11
1.18
Vin-
Q6
V6
buffer1
buffer2
1.18
R11
1k
+
+
-
+
Vg
+
23
25
Vg
Vmid
VC
-
-
-
D2 DBREAK
0.4
E
E
12
Vmid
Vc
19
EOS
8
C2
4e-12
+
-
+
-
1
V1
D3 DBREAK
NPN_CASCODE
Q5
R2
5e11
Vmid
13
E
R8
NPN_CASCODE
100
GAIN = 1
D1
3
Q2
NPN_CASCODE
Q1
NPN_CASCODE
D8
V7
E2
+
0
CinDif
5.87E-40
V5
R4
Q4
18
D4
1.18
+
-
IOS
0.3E-12
1.18
DBREAK
250
-
110
R1
R3
5e11
2
E
J2
R7
GAIN = 0.5
16
17
Vmid
G4
5
J1
6
14
C5
E
En
0
24
27
G2
5-
+
R10
250
-
pj110_input
PJ110_INPUT
1
R14
200k
2.5e-12
Vin+
4
+
7
15
J3
GAIN = 33
D6
G
J4
GAIN = 1
PJ110_CASCODE
GAIN = 181.819E-6
PJ110_CASCODE
D10
Cin2
Cin1
7.27e-40
7.27e-40
V--
V--
V--
VCM
MID SUPPLY REF V
INPUT STAGE
GAIN STAGE
V+
E3
+
-
+
-
E
V++
0
V++
V++
GAIN = 1
R19
R21
318.319274232055
L1
L3
D14
D15
G
-
318.319274232055
+
+
5.30532e-10
5.30532e-10
VCM
G9
+
G11
R23
50
+
-
G5
G7
G15
GAIN = 20e-3
Vout
+
-
G
+
-
28
R15
0.001
31
R17
0.001
-
G
G
G
Vout
V8
GAIN = 0.0031415
Vout
D11
GAIN = 0.0031415
DX
GAIN = 1
GAIN = 1
35
36
C6
C8
.523
29
VOUT
10e-12
10e-12
Vc
33
34
Vg
Vmid
37
38
ISY
VC
2.5E-3
D12
D X
V9
Vout
.523
R16
R18
0.001
0.001
Vmid
C7
C9
G10
-
G12
-
30
G8
-
10e-12
10e-12
Vout
Vout
32
+
+
G13
+
G14
+
G6
-
D16
+
GAIN = 0.0031415
R20
GAIN = 0.0031415
R22
R24
50
L4
G
-
+
-
-
GAIN = 1
D13
V--
+
L2
G
G
5.30532e-10
5.30532e-10
GAIN = 1
GAIN = 1.11e-2 GAIN = 1.11e-2
G16
318.319274232055
318.319274232055
GAIN = 20e-3
V--
V--
V--
V-
E4
+
VCM
+
-
COMMON MODE
GAIN STAGE
WITH ZERO
CORRECTION CURRENT OUTPUT STAGE
SOURCES
-
E
GAIN = 1
0
FIGURE 44. SPICE NET LIST
ISL28110, ISL28210
* source ISL28110_210_presubckt_0
* Revision A, LaFontaine Nov 4th 2010
* Model for Noise 200nV/rtHz@0.1Hx
*11nV/rtHz base band, supply current 2.5mA,
*CMRR 120dB fcm=281kHz ,AVOL 125dB
*fd=7Hz
* SR = 20V/us, GBWP 12.6MHz, Output
*voltage clamp
*Copyright 2010 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
G_G1
V++ 23 19 8 33
V-- 23 19 8 33
23 V++ 1
V-- 23 1
25 23 1k
25 VMID DX
VMID 25 DX
25 VMID 1e10
V++ VG 25 VMID 181.819E-6
V-- VG 25 VMID 181.819E-6
26 V++ DX
V-- 27 DX
26 VG 1.18
VG 27 1.18
VG V++ 200k
V-- VG 200k
8 VG 6e-12
VG V++ 2.5e-12
V-- VG 2.5e-12
V_V9
R_R23
R_R24
*
*
.model pj110_input pjf
+ vto=-1.4
+ beta=0.0025
+ lambda=0.03
+ is=2.68e-015
+ pb=0.73
+ cgd=8.6e-012
+ cgs=9.05e-012
+ fc=0.5 kf=0
+ af=1
VOUT 36 -.384
VOUT V++ 50
V-- VOUT 50
G_G2
R_R9
R_R10
R_R11
D_D7
D_D8
R_R12
G_G3
G_G4
D_D9
D_D10
V_V6
V_V7
R_R13
R_R14
C_C3
C_C4
C_C5
*
* Connections:
*
*
*
*
*
*
+input
|
|
|
|
|
-input
| +Vsupply
|
|
|
+ tnom=35
*
.model NPN_CASCODE npn
+ is=5.02e-016
+ bf=150
|
|
|
-Vsupply
| output
|
|
.subckt ISL28110subckt Vin+ Vin- V+ V- VOUT
* source ISL28110_210_PRESUBCKT_0
*
* Mid Supply Reference
*
+ va=300
+ ik=0.017
*Voltage Noise
*
E_E2
E_E3
E_E4
I_ISY
*
VMID V-- V++ V-- 0.5
V++ 0 V+ 0 1
V-- 0 V- 0 1
+ rb=0.01
+ re=0.011
+ rc=900
+ cje=2e-013
+ cjc=1.6e-028
+ kf=0
E_En
V_V1
D_D1
R_R1
*
VIN+ 4 2 0 1
1 0 0.4
1 2 DN
V+ V- DC 2.5E-3
2 0 110
*Common Mode Gain Stage 40dB/dec
*
+ af=1
*Input Stage
*
G_G5
G_G6
G_G7
G_G8
L_L1
L_L2
L_L3
L_L4
R_R15
R_R16
R_R17
R_R18
*
V++ 29 3 VMID 1
V-- 29 3 VMID 1
V++ VC 29 VMID 1
V-- VC 29 VMID 1
28 V++ 5.30532e-11
30 V-- 5.30532e-11
31 V++ 5.30532e-11
32 V-- 5.30532e-11
29 28 0.001
*
.model PJ110_CASCODE pjf
+ vto=-1.4
+ beta=0.000617
+ lambda=0.03
+ is=3.96e-016
+ pb=0.73
+ cgd=2.2e-012
+ cgs=3e-012
+ fc=0.5
+ kf=0
+ af=1
+ tnom=35
*
R_R2
R_R3
C_CinDif
C_Cin1
C_Cin2
I_IOS
R_R4
J_J1
VIN- 3 5e11
3 4 5e11
4 VIN- 5.87E-40
V-- VIN- 7.27e-40
V-- 4 7.27e-40
4 VIN- DC 0.3E-12
5 VIN- 250
7 5 6 pj110_input
30 29 0.001
VC 31 0.001
32 VC 0.001
J_J2
J_J3
J_J4
Q_Q1
Q_Q2
Q_Q4
Q_Q5
Q_Q6
Q_Q7
V_V2
15 16 14 pj110_input
V-- 14 15 PJ110_CASCODE
V-- 6 7 PJ110_CASCODE
19 13 14 NPN_CASCODE
12 13 6 NPN_CASCODE
8 13 6 NPN_CASCODE
12 13 14 NPN_CASCODE
19 11 20 PNP_MIRROR
8 11 9 PNP_MIRROR
V++ 10 0.7Vdc
*Second Pole Stage 40dB/dec
*
.model DBREAK d
+ bv=43
+ rs=1
G_G9
G_G10
G_G11
G_G12
R_R19
R_R20
R_R21
R_R22
C_C6
C_C7
C_C8
C_C9
*
V++ 33 VG VMID 0.0031415
V-- 33 VG VMID 0.0031415
V++ 34 33 VMID 0.0031415
V-- 34 33 VMID 0.0031415
33 V++ 318.319274232055
V-- 33 318.319274232055
34 V++ 318.319274232055
V-- 34 318.319274232055
33 V++ 10e-12
*
.model PNP_MIRROR pnp
+ is=4e-015
+ bf=150
+ va=50
+ ik=0.138
+ rb=0.01
+ re=0.101
+ rc=180
+ cje=1.34e-012
+ cjc=4.4e-013
+ kf=0
+ af=1
*
.model DN D(KF=6.69e-12 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28110subckt
V_V3
V++ 21 0.7Vdc
R_R5
R_R6
E_buffer1
E_buffer2
D_D2
D_D3
9 10 5.5k
20 21 5.5k
11 V++ 8 V++ 1
13 V-- 12 V-- 1
V-- 33 10e-12
34 V++ 10e-12
V-- 34 10e-12
8 19 DBREAK
19 8 DBREAK
I_I1
V++ 12 DC 240E-6
19 V++ 4e-12
V-- 19 4e-12
C_C1
C_C2
R_R7
E_EOS
*
* Output Stage
*
16 17 250
D_D11
D_D12
D_D13
D_D14
D_D15
D_D16
G_G13
G_G14
G_G15
G_G16
V_V8
34 35 DX
36 34 DX
V-- 37 DY
V++ 37 DX
V++ 38 DX
V-- 38 DY
37 V-- VOUT 34 1.11e-2
38 V-- 34 VOUT 1.11e-2
VOUT V++ V++ 34 20e-3
V-- VOUT 34 V-- 20e-3
35 VOUT -.384
17 4 VC VMID 1
*1st Gain Stage
*
R_R8
D_D4
D_D5
D_D6
V_V4
V_V5
18 V++ 100
V-- 18 DBREAK
22 V++ DX
V-- 24 DX
22 23 1.18
23 24 1.18
FIGURE 45. SPICE NET LIST
FN6639.1
December 8, 2010
18
ISL28110, ISL28210
Characterization vs Simulation Results
1000
100
10
1000
100
10
1000
V
= ±18V
S
V
= ±18V
S
INPUT NOISE VOLTAGE
INPUT NOISE VOLTAGE
100
1
0.1
1
10
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 46. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 47. SIMULATED INPUT NOISE VOLTAGE
70
70
A
= 1000
A
= 1000
R = 100kΩ, R = 100Ω
F G
R
= 100kΩ, R = 100Ω
CL
CL
F
G
60
50
40
30
20
10
0
60
50
40
30
20
10
0
R
= 100kΩ, R = 1kΩ
G
R
= 100kΩ, R = 1kΩ
G
F
F
A
A
= 100
= 10
A
A
= 100
= 10
CL
CL
V
= ±5V & ±15V
= 4pF
= OPEN
V
= ±5V & ±15V
S
S
C
R
V
C
R
V
= 4pF
= OPEN
L
L
L
L
CL
R
= 100mV
CL
= 100mV
OUT
P-P
OUT
P-P
= 100kΩ, R = 10kΩ
R
A
= 100kΩ, R = 10kΩ
F
G
F
G
A
= 1
= 1
CL
CL
R
= 0, R = ∞
R
= 0, R = ∞
F
G
F
G
-10
1k
-10
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 48. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 49. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
0.15
0.15
V
= ±15V
= 1
= 2k
V
A
R
C
= ±15V
= 1
= 2k
S
S
A
V
V
0.10
0.05
0
0.10
0.05
0
R
C
L
L
L
L
= 4pF
= 4pF
-0.05
-0.10
-0.15
-0.05
-0.10
-0.15
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
TIME (µs)
1.0
0
0.2
0.4
0.6
0.8
1.0
TIME (µs)
FIGURE 50. CHARACTERIZED SMALL SIGNAL
FIGURE 51. SIMULATED SMALL SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
TRANSIENT RESPONSE vs RL, VS = ±0.9V,
±2.5V
FN6639.1
December 8, 2010
19
ISL28110, ISL28210
Characterization vs Simulation Results(Continued)
6
6
V
= ±15V
= 1
V
= ±15V
= 1
S
S
A
A
4
4
V
V
R
C
= 2k
= 4pF
R
C
= 2k
= 4pF
L
L
L
L
2
2
0
0
-2
-4
-6
-2
-4
-6
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
TIME (µs)
TIME (µs)
FIGURE 52. CHARACTERIZED LARGE SIGNAL
FIGURE 53. SIMULATED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
TRANSIENT RESPONSE vs RL, VS = ±0.9V,
±2.5V
200
180
160
140
120
100
80
60
40
20
0
200
180
160
PHASE
PHASE
140
120
100
80
60
40
20
0
GAIN
GAIN
-20
-40
-60
-80
-100
-20
-40
-60
-80
V
= ±15V
S
V
= ±15V
S
R =1MΩ
L
R =1MΩ
L
-100
0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
FIGURE 54. SIMULATED (DESIGN) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
FIGURE 55. SIMULATED (SPICE) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
130
120
110
100
90
130
120
110
100
90
80
80
70
70
60
60
50
50
40
40
30
30
V
= ±15V
V = ±15V
S
SIMULATION
20
10
0
20
10
0
S
SIMULATION
0.1
1
10
100
1k
10k 100k 1M 10M 100M
0.1
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 56. SIMULATED (DESIGN) CMRR
FIGURE 57. SIMULATED (SPICE) CMRR
FN6639.1
December 8, 2010
20
ISL28110, ISL28210
Characterization vs Simulation Results(Continued)
15V
10V
5V
5.0
0V
0
-5V
-10V
-15V
V
= ±5V
S
-5.0
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
0
0
TIME (m s)
TIME (m s)
FIGURE 58. SIMULATED OUTPUT VOLTAGE SWING ±5V
FIGURE 59. SIMULATED OUTPUT VOLTAGE SWING ±15V
FN6639.1
December 8, 2010
21
ISL28110, ISL28210
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
11/29/10
11/23/10
FN6639.1
Removed label on right side of characterization curve, Figure 46 (Input Noise Current).
Page 1 Updated Trademark statement
Page 3 Ordering Information: Removed "coming soon" from ISL28110FBZ
Page 4 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS=±5V.
Page 5 Electrical Specifications: Changed AVOL limits fro V/mV to dB
Page 5 Electrical Specifications, Dynamic Performance, Slew Rate: Added "4V Step" to
conditions; changed TYP limit from 23V/µs to 20V/µs
Page 6 Electrical Specifications, Dynamic Performance, Slew Rate:
Added "10V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs
Page 6 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS= ±15V.
Changed AVOL limits from V/mV to dB. Changed ts, settling time to 0.1% from 0.9µs to 1.3µs
and changed ts, settling time to 0.01% from 1.2µs to 1.6µs.
Page 7 Replaced Elect Spec table Notes 8 & 9 (Note 8 "Parameters with MIN and/or MAX limits
are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested./Note 9 Limits established by characterization
and are not production tested.)" With: "Compliance to datasheet limits is assured by one or
more methods: production test, characterization and/or design."
Page 8 Characteristic Curves: Added ISL28110 IB vs Temperature (Fig 4)
Page 8 Characteristic Curves: Added ISL28110 IOS vs Temperature (Fig 6)
Pages 17-21: Added PSPICE model section
9/13/10
FN6639.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28110, ISL28210
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6639.1
December 8, 2010
22
ISL28110, ISL28210
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN6639.1
December 8, 2010
23
ISL28110, ISL28210
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.25 - 0.036
0.10 C
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN6639.1
December 8, 2010
24
ISL28110, ISL28210
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6639.1
December 8, 2010
25
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