ISL26314_技术文档

12-bit, 125kSPS Low-power ADCs with Single-ended

and Differential Inputs and Multiple Input Channels

ISL26310, ISL26311, ISL26312,

ISL26313, ISL26314, ISL26315,

ISL26319

Features

• Pin-compatible Family Allows Easy Design Upgrades

• Excellent Differential Non-Linearity (0.7LSB max)

• Low THD: -86dB (typ)

The ISL26310/11/12/13/14/15/19 family of sampling

SAR-type ADCs feature excellent linearity over supply and

temperature variations, and offer versions with 1-, 2-, 4- and

8-channel single-ended inputs, and 1-, 2- and 4-channel

differential inputs.

• Simple SPI-compatible Serial Digital Interface

• Low 2.2mA Operating Current

• Power-down Current between Conversions 8µA (typ)

• +5.25V to +2.7V Supply

A proprietary input multiplexer and combination buffer amplifier

reduces the input drive requirements, resulting in lower cost and

reduced board space. Specified measurement accuracy is

maintained with input signals up to VDD.

• Excellent ESD Survivability: 5kV HBM, 350V MM, 2kV CDM

Applications

• Industrial Process Control

• Energy Measurement

• Multichannel Data Acquisition Systems

• Pressure Sensors

Members of the ISL26310/11/12/13/14/15/19 family of

Low-Power ADCs offer pinout intercompatibility, differing only in

the analog inputs, to support quick replication of proven layouts

across multiple design platforms.

The serial digital interface is SPI compatible and is easily

interfaced to popular FPGAs and microcontrollers. Power

consumption is limited to 11mW at a sampling rate of 125kSPS,

and an operating current of just 8µA typical between

conversions, when configured for Auto Powerdown mode.

• Flow Controllers

The ISL26310/11/12/13/14/15/19 feature up to 5kV Human

Body Model ESD survivability and are available in the popular

SOIC and TSSOP packages. Performance is specified for

operation over the full industrial temperature range (-40°C to

+125°C).

VDD

VREF

BUFFER

CNV

ANALOG INPUTS

DIFFERENTIAL/

SINGLE-ENDED

SCLK

MUX

ADC

OSC

SPI

SDO

SDI

POR

GND

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

July 3, 2012

FN7549.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners

1

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Application Block Diagram

ANALOG SIGNAL INPUT MODULES

Pressure/Strain Gage Sensor

V-REF

DCP

RS-485

RTC

Precision

Amp

M

U

X

µC

ADC

Gain

Amplifier

+V

Active

Filter

+V

Precision

Amp

Precision

Amp

POWER

MUX and ADC

-V

Voltage

Monitors &

Watchdog

V-REF

Temperature Sensor

Gain

Amplifier

+V

Active

Filter

+V

DCP

Core &

I/O Power

LDOs

Precision

Amp

Precision

Amp

System

Power

RTD

-V

SW

Controller

ISO-Thermal

Block

Switching

Regulators

Thermal

Couple

Isolated

Power

Flow Sensor

Loop Supply

Gain

Amplifier

+V

Active

Filter

+V

Differential

Pressure

Transducer

W/ sqrt

Precision

Amp

Precision

Amp

Vin

Iout

4-20mA

Extractor

-V

Pin-Compatible Family

RESOLUTION

SPEED

(kHz)

ANALOG

INPUT

CHANNELS

MODEL

(Bits)

ISL26310

ISL26311

ISL26312

ISL26313

ISL26314

ISL26315

ISL26319

ISL26320

ISL26321

ISL26322

ISL26323

ISL26324

ISL26325

ISL26329

12

125

250

Differential

Single-Ended

Differential

Single-Ended

Differential

Single-Ended

Differential

Single-Ended

Differential

Single-Ended

Differential

Single-Ended

1

2

4

8

1

2

4

8

FN7549.1

July 3, 2012

2

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Ordering Information

DESCRIPTION

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

RESOLUTION

(Bits)

SPEED

(kHz)

INPUT

(SE/DIFF)

INPUT

CHANNELS

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG

DWG #

ISL26310FBZ

26310 FBZ

12

125

Diff

SE

1

2

4

8

-40 to +125

8 Ld SOIC

M8.15

ISL26311FBZ

ISL26312FVZ

ISL26313FBZ

ISL26314FVZ

ISL26315FVZ

ISL26319FVZ

NOTES:

26311 FBZ

26312 FVZ

26313 FBZ

26314 FVZ

26315 FVZ

26319 FVZ

8 Ld SOIC

M8.15

Diff

SE

16 Ld TSSOP

8 Ld SOIC

M16.173

M8.15

Diff

SE

16 Ld TSSOP

M16.173

SE

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315,

ISL26319. For more information on MSL please see techbrief TB363.

FN7549.1

July 3, 2012

3

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Pin Configurations

ISL26310

(8 LD SOIC)

TOP VIEW

ISL26311

(8 LD SOIC)

TOP VIEW

CNV

SCLK

SDO

SDI

CNV

SCLK

SDO

SDI

1

2

3

4

1

2

3

4

VDD

GND

8

7

6

5

VDD

GND

AIN+

AIN-

8

7

6

5

VREF

AIN0

ISL26313

(8 LD SOIC)

TOP VIEW

CNV

SCLK

SDO

SDI

1

2

3

4

VDD

GND

AIN0

AIN1

8

7

6

5

ISL26312

(16 LD TSSOP)

TOP VIEW

ISL26314

(16 LD TSSOP)

TOP VIEW

CNV

1

2

3

4

5

6

7

CNV

1

2

3

4

5

6

7

VDD

16

15

VDD

GND

16

15

SCLK

GND

VREF

GND

VREF

14 SDO

13

SDI

GND

AIN0+

AIN0-

AIN1+

AIN3+

12

11

10

9

12 NC

11 NC

10 NC

AIN0+

AIN0-

AIN1+

AIN1-

AIN3-

AIN2+

AIN2-

AIN1-

9

NC

8

ISL26315

(16 LD TSSOP)

TOP VIEW

ISL26319

(16 LD TSSOP)

TOP VIEW

CNV

SCLK

1

2

3

4

5

6

7

1

VDD

GND

16

15

VDD

16

15

SCLK

2

3

4

5

6

7

GND

VREF

14 SDO

13

SDI

GND

AIN0

AIN1

AIN2

GND

AIN0

AIN3

NC

12 AIN7

12

11

AIN6

11

NC

AIN1

NC

AIN5

10

AIN2

NC

10

9

AIN4

9

AIN3

8

FN7549.1

July 3, 2012

4

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Pin Descriptions

PIN NUMBER

PIN NAME ISL26310 ISL26311 ISL26312

ISL26313 ISL26314 ISL26315 ISL26319

DESCRIPTION

Positive Supply Voltage

VDD

GND

1

2

-

1

2

3

-

1

2

-

1

2, 4

Ground

VREF

AIN0+

AIN0-

AIN1+

AIN1-

AIN2+

AIN2-

AIN3+

AIN3-

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

SDI

3

Reference Voltage Input

-

5

-

5

-

Differential Analog Input, Positive

Differential Analog Input, Negative

Differential Analog Input, Positive

Differential Analog Input, Negative

Differential Analog Input, Positive

Differential Analog Input, Negative

Differential Analog Input, Positive

Differential Analog Input, Negative

Single-Ended Analog Input

Serial Interface Data Input

Serial Interface Data Output

Serial Interface Clock Input

Conversion Control Input

-

6

-

6

-

7

-

7

-

8

-

8

-

10

-

9

-

12

-

11

-

4

-

3

4

-

5

6

7

8

9

10

11

12

13

14

15

16

-

7

-

10

-

12

-

5

6

7

8

-

5

6

7

8

-

13

5

6

7

8

-

13

14

15

16

-

13

SDO

14

SCLK

CNV

15

16

NC

9, 10, 11, 12

6, 8, 9, 11

No Connect

AIN+

AIN-

3

4

-

Differential Analog Input, Positive

Differential Analog Input, Negative

-

FN7549.1

July 3, 2012

5

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Absolute Maximum Ratings

Thermal Information

AIN+, AIN-, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3 to V +0.3V

Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3 to V +0.3V

DD

Thermal Resistance (Typical)

8 Ld SOIC (Notes 4, 5) . . . . . . . . . . . . . . . . .

16 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

_JA(°C/W)

98

θ

_JC(°C/W)

DD

48

29

VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3 to +0.3V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . .5000V

Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . . 350V

Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . 2000V

Latch-up (Tested per JESD-78B; Class 2, Level A). . . . . . . . . . . . . . . . . . . . . . . 100mA

92

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to +5.25V

DD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, V = VDD/2, SCLK = 20MHz and T = -40°C to +125°C (typical performance

CM

A

at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

MAX

SYMBOL

PARAMETER

TEST LEVEL OR NOTES

(Note 6)

TYP

(Note 6)

UNITS

ANALOG INPUTS

Number of Input Channels

ISL26310, ISL26311

1

2

4

8

ISL26312, ISL26313

ISL26314, ISL26315

ISL26319

Input Voltage Range

Differential Inputs (AINX+ - AINX-) is

0

V

REF

-V

(Min) and +V

(Max)

REF

AINX, Single-Ended Inputs

Differential Inputs

V

Common Mode Input Voltage Range

Average Input Current

V

/2 – 0.2

REF

V

/2 + 0.2

REF

REF/2

2.5

µA

pF

dB

C

Input Capacitance

4

IN

f

= 100kHz

-86

IN

Channel-Channel Crosstalk

V

= FS, other channels = 0V

IN

VOLTAGE REFERENCE

V

External Reference Input Voltage Range

Average Input Current

2

2.5

100

10

V

REFEX

DD

I

120

µA

pF

REFIN

C

Effective Input Capacitance

REFIN

DC ACCURACY

Resolution (No Missing Codes)

12

-0.7

-6

Bits

LSB

DNL

INL

Differential Nonlinearity Error

Integral Nonlinearity Error

Gain Error

+0.7

6

Gain Error Matching

Offset Error

-2

2

-6

6

Offset Error Matching

-2

2

FN7549.1

July 3, 2012

6

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, V = VDD/2, SCLK = 20MHz and T = -40°C to +125°C (typical performance

CM

A

at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

SYMBOL

PSRR

PARAMETER

TEST LEVEL OR NOTES

(Note 6)

TYP

70

(Note 6)

UNITS

dB

Power Supply Rejection Ratio

DYNAMIC PERFORMANCE

Differential Inputs

73.4

73.1

-86

dB

Signal-to-Noise

SNR

Notes: V = FS-0.1dB, f = 10kHz

IN

Single-Ended Inputs

Differential Inputs

Single-Ended Inputs

Differential Inputs

Single-Ended Inputs

Signal-to-Noise + Distortion

SINAD

THD

Notes: V = FS-0.1dB, f = 10kHz

IN IN

Total Harmonic Distortion

Notes: V = FS-0.1dB, f = 10kHz

IN IN

-86

Spurious-free Dynamic Range

f

= 20kHz

96

IN

SFDR

BW

Notes: V = FS-0.1dB

IN

-3dB Input Bandwidth

Sampling Aperture Delay

Sampling Aperture Jitter

2.5

12

25

MHz

ns

t

AD

t

ps

jit

POWER SUPPLY REQUIREMENTS

V

Supply Voltage

2.7

5.25

3

V

DD

I

Supply Current

2.2

11

8

mA

mW

µA

DD

PD

IPD

Power Consumption

Power-down Current

Standby Mode Current

Normal Operation

Auto Power-Down Mode

Auto Sleep Mode

15

50

Istby

0.4

mA

DIGITAL INPUTS

V

0.7 VDD

VDD-0.4

-100

V

IH

V

0.2 V

IL

DD

V

I

= -1mA

= 1mA

V

OH

OL

V

OL

I

, I

Input Leakage Current

Serial Clock Frequency

100

20

nA

MHz

IH IL

TIMING SPECIFICATIONS (Note 7)

t

SCLK Period (in RAC Mode)

50

ns

µs

SCLK

SCLK Period (in RSC, RDC Modes)

200

3.2

t

Safe Data Transfer Time After Conversion

State Begins

DATA

t

CSB Falling Low to SCLK Rising Edge

40

10

ns

CSB_SCLK

t

SDI Setup Time with Respect to Positive

Edge of SCLK

SDI_SU

t

SDI Hold Time with Respect to Positive

Edge of SCLK

10

ns

SDI_H

t

SDOUT Valid Time with Respect to

Negative Edge of SCLK

25

SDO_V

t

SDOUT to High Impedance State After CNV Note 8

Rising Edge (or last SCLK falling edge)

85

SDOZ_D

t

Acquisition Time when Fully Powered Up

Acquisition Time in Auto Sleep Mode

800

2.1

ns

µs

ACQ

FN7549.1

July 3, 2012

7

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, V = VDD/2, SCLK = 20MHz and T = -40°C to +125°C (typical performance

CM

A

at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

(Note 6)

SYMBOL

PARAMETER

TEST LEVEL OR NOTES

(Note 6)

150

TYP

UNITS

µs

t

Acquisition time in Auto Power Down

Mode

ACQ

t

SCLK High Time

SCLK Low Time

CNV Pulse Width

20

ns

SCLKH

t

SCLKL

t

100

CNV

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. The device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a power cycle to restore

normal operation.

8. Transition time to high impedance state is dominated by RC loading on the SDOUT pin. Specified value is measured using equivalent loading shown

in Figure 2.

VDD

R_L

2k

OUTPUT PIN

C_L

10pF

FIGURE 2. EQUIVALENT LOAD CIRCUIT FOR DIGITAL OUTPUT TESTING

FN7549.1

July 3, 2012

8

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Typical Performance Characteristics T = +25°C, V = 5V, V = 5V, f

= 125kHz, f = 20MHz,

SCLK

A

DD

REF

SAMPLE

unless otherwise specified.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

-2000

-1000

0

1000

2000

-2000

-1000

0

1000

2000

CODE

FIGURE 3. DIFFERENTIAL NONLINEARITY (DNL) vs CODE

FIGURE 4. INTEGRAL NONLINEARITY (INL) vs CODE

1.0

0.8

1.0

0.8

POSITIVE DNL

POSITIVE INL

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

NEGATIVE INL

NEGATIVE DNL

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 5. DNL DISTRIBUTION vs TEMPERATURE

FIGURE 6. INL DISTRIBUTION vs TEMPERATURE

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

2.0

1.5

2.7V

1.0

3.3V

5.0V

0.5

5.25V

2.7V

3.3V

0.0

-0.5

-1.0

-1.5

-2.0

5.0V

5.25V

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 7. GAIN ERROR vs SUPPLY VOLTAGE AND TEMPERATURE

FIGURE 8. OFFSET ERROR vs SUPPLY VOLTAGE AND TEMPERATURE

FN7549.1

July 3, 2012

9

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Typical Performance Characteristics T = +25°C, V = 5V, V = 5V, f

= 125kHz, f

= 20MHz,

SCLK

A

DD

REF

SAMPLE

unless otherwise specified. (Continued)

25

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

20

15

10

5

5.25V

5.0V

3.3V

2.7V

0

2.7

3.2

3.7

4.2

4.7

5.2

-40

-20

0

20

40

60

80

100

120

SUPPLY VOLTAGE

TEMPERATURE (°C)

FIGURE 9. APERTURE DELAY vs SUPPLY VOLTAGE

FIGURE 10. SUPPLY CURRENT vs VOLTAGE AND TEMPERATURE

2.5

50

45

40

2.0

1.5

1.0

35

5.25V

30

25

NORMAL MODE

AUTO POWER DOWN MODE

5.0V

AUTO SLEEP MODE

20

15

3.3V

0.5

0.0

10

5

2.7V

100

0

100

1k

10k

100k

-40

-20

0

20

40

60

80

120

SAMPLE RATE (Sps)

TEMPERATURE (°C)

FIGURE 11. SUPPLY CURRENT vs SAMPLING RATE (V = 5V)

DD

FIGURE 12. SHUTDOWN CURRENTS vs VOLTAGE AND TEMPERATURE

-80

-82

75

5.25V

5.0V

74

73

72

-84

-86

5.25V

5.0V

3.3V

2.7V

-88

-90

71

70

3.3V

2.7V

100

-40

-20

0

20

40

60

80

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 13. SNR AND SINAD vs SUPPLY VOLTAGE AND TEMPERATURE

FIGURE 14. THD vs SUPPLY VOLTAGE AND TEMPERATURE

FN7549.1

July 3, 2012

10

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Typical Performance Characteristics T = +25°C, V = 5V, V = 5V, f

= 125kHz, f

= 20MHz,

A

DD

REF

SAMPLE

SCLK

unless otherwise specified. (Continued)

75

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

SNR

70

SINAD

65

60

55

100

1k

10k

100k

1M

100

1k

10k

100k

1M

INPUT FREQUENCY (Hz)

FIGURE 15. SNR AND SINAD vs INPUT FREQUENCY

FIGURE 16. THD vs INPUT FREQUENCY

70,000

60,000

50,000

40,000

30,000

20,000

10,000

0

-20

SNR: 72.93dB

SINAD: 72.71dB

THD: -85.84dB

65,536

CODES

SFDR: 96.16dBc

ENOB: 11.79

-40

-60

-80

-100

-120

-140

-160

0

CODES

0

10

20

30

40

50

60

70

-3

-2

-1

0

1

2

3

FREQUENCY (kHz)

CODE

FIGURE 17. SINGLE-TONE FFT

FIGURE 18. SHORTED INPUT HISTOGRAM

FN7549.1

July 3, 2012

11

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Figures 19 and 20 illustrate simplified representations of the

Circuit Description

converter analog section for differential and single-ended inputs,

The ISL26310/11/12/13/14/15/19 family of 12-bit ADCs are

low-power Successive Approximation-type (SAR) ADCs with 1-,

2-, 4-, or 8-channels and a choice of single-ended or differential

inputs. The high-impedance buffered input simplifies interfacing

to sensors and external circuitry.

respectively. During the acquisition phase (CNV = 0) the input

signal is presented to the Cs samples capacitors. To properly

sample the signal, the CNV signal must remain low for the

specified time. When CNV is taken high (CNV = 1), the switches

that connect the sampling capacitors to the input are opened

and the control logic begins the successive approximation

sequence to convert the captured signal into a digital word. The

conversion sequence timing is determined by the on-chip

oscillator.

The entire ISL26310/11/12/13/14/15/19 family follows the

same base pinout and differs only in the analog input pins,

allowing the user to replicate the basic board layout across

multiple platforms with a minimum redesign effort.

The simple serial digital interface is compatible with popular

FPGAs and microcontrollers and allows direct conversion control

by the CNV pin.

ADC Transfer Function

The ISL26310, the ISL26312, and the ISL26314 feature

differential inputs with output data coding in two's complement

format (see Table 1). The size of one LSB in these devices is

(2*VREF)/4096. Figure 21 on page 13 illustrates the ideal

transfer function for these devices.

Functional Description

The ISL26310/11/12/13/14/15/19 devices are SAR

(Successive Approximation Register) analog-to-digital converters

that use capacitor-based charge redistribution as their

conversion method.

The ISL26311, ISL26313, ISL26315, and ISL26319 feature

single-ended inputs with output coding in binary format (see

Table 2). The size of one LSB in these devices is VREF/4096.

Figure 22 on page 13 illustrates the ideal transfer function for

these devices.

These devices include an on-chip power-on reset (POR) circuit to

initialize the internal digital logic when power is applied. An

on-chip oscillator provides the master clock for the conversion

logic. The CNV signal controls when the converter enters into its

signal acquisition time (CNV = 0), and when it begins the

conversion sequence after the signal has been captured

(CNV = 1). The converters include a configuration register that

can be accessed via the serial port. The configuration register

has various bits to indicate which channel (where applicable) is

selected, to activate the auto-power-down feature where the ADC

is shut down between conversions, or to output the configuration

register contents along with the data conversion word whenever

a conversion word is read from the serial port. The serial port

supports three different modes of reading the conversion data.

These will be discussed later in this data sheet.

VREF

CNV

C_S

ACQ

C

S

ACQ

CNV

AIN

ACQ

CNV

AIN+

SAR

LOGIC

SAR

LOGIC

COMPARATOR

Buffer

VCM

ACQ

COMPARATOR

Buffer

VCM

ACQ

AIN–

ACQ

C_S

ACQ

CNV

C

S

CNV

VREF

FIGURE 19. ARCHITECTURAL BLOCK DIAGRAM, DIFFERENTIAL INPUT

FIGURE 20. ARCHITECTURAL BLOCK DIAGRAM, SINGLE-ENDED

FN7549.1

July 3, 2012

12

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

1LSB = 2•VREF/4096

011...111

011...110

111...111

111...110

000...001

000...000

111...111

100...001

100...000

011...111

100...010

100...001

100...000

000...010

000...001

000...000

–VREF

+ ½LSB

+VREF +VREF

– 1½LSB – 1LSB

–VREF

+ ½LSB

+VREF +VREF

– 1½LSB – 1LSB

0V

ANALOG INPUT

AIN+ – (AIN–)

ANALOG INPUT

FIGURE 21. IDEAL TRANSFER CHARACTERISTICS, DIFFERENTIAL INPUT

FIGURE 22. IDEAL TRANSFER CHARACTERISTICS, SINGLE-ENDED INPUT

Analog Inputs

V

Some members of the ISL26310/11/12/13/14/15/19 family

feature a fully differential input with a nominal full-scale range

equal to twice the applied VREF voltage. Those devices with

differential inputs have a nominal full scale range equal to twice

the applied VREF voltage. Each input swings VREF volts (peak-to-

peak), 180° out of phase from one another for a total differential

input of 2*VREF (refer to Figures 23 and 24).

5.0

4.0

AIN–

3.0

2.0

1.0

AIN+

2.5Vpp

Allowable VCM Range

t

V_{REF PP}

AIN+

ISL2631X/32X

VREF = 2.5V

AIN+

V

AIN–

V_CM

AIN-

V_{REF PP}

5Vpp

5.0

4.0

3.0

2.0

1.0

FIGURE 23. DIFFERENTIAL INPUT SIGNALING

VCM

Allowable VCM Range

Differential signaling offers several benefits over a single-ended

input, such as:

• Doubling of the full-scale input range (and therefore the

dynamic range)

• Improved even order harmonic distortion

t

VREF = 5V

• Better noise immunity due to common mode rejection

FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE

RANGE FOR DIFFERENTIAL INPUTS

Figure 24 shows the relationship between the reference voltage

and the full-scale differential input range for two different values

of VREF. Note that the common-mode input voltage must be

maintained within ±200mV of VREF/2 for differential inputs.

Those devices with singled-ended inputs have a ground-

referenced peak-to-peak input voltage span equal to the

reference voltage.

FN7549.1

July 3, 2012

13

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Voltage Reference Input

V

An external reference voltage must be supplied to the VREF pin

to set the full-scale input range of the converter. The VREF input

5.0

on these devices can accept voltages ranging from 2V (nominal)

4.0

to VDD, however, they are specified with VREF at a voltage of 5V

with VDD at 5V. Note that exceeding VDD by more than 100mV

3.0

2.0

1.0

AIN

2.5Vpp

can forward bias the ESD protection diodes and degrade

measurement accuracy due to leakage current. A lower value

voltage reference must be used if the device is operated with

VDD at voltages lower than 5V. If the VREF pin is tied to the VDD

pin, the VREF pin should be decoupled with a local 1µF ceramic

capacitor as described in a later paragraph.

t

VREF = 2.5V

AIN

V

Figures 27 and 28 illustrate possible voltage reference options

for these ADCs. Figure 27 uses the precision ISL21090 voltage

reference, which exhibits exceptionally low drift and low noise.

The ISL21090 must be powered from a supply greater than 4.7V.

5Vpp

5.0

4.0

3.0

2.0

1.0

Figure 28 illustrates the ISL21010 voltage reference used with

these ADCs. The ISL21010 series voltage references have higher

noise and drift than the ISL21090 devices, but operate at lower

supply voltages. Therefore, these devices can readily be used

when these SAR ADCs operate with VDD at voltages less than 5V.

The outputs of ISL21090 or the ISL21010 devices should be

decoupled with a 1µF ceramic capacitor. A 1µF, 6.3 V, X7R, 0603

(1608 metric) MLCC type capacitor is recommended for its high

frequency performance. The trace length from the VREF pin to

this capacitor and the voltage reference output should be as

short as possible.

t

VREF = 5V

FIGURE 25. RELATIONSHIP BETWEEN VREF AND FULL-SCALE

RANGE FOR SINGLE-ENDED INPUTS

Input Multiplexer

The ISL26310 and ISL26313 devices (packaged in 8 pin SOIC

packages) derive their voltage reference from the VDD pin. To

achieve best performance, the VDD pin of these devices should

be bypassed with the 1µF ceramic capacitor mentioned above.

The input of the multiplexer connects the selected analog input

pins to the ADC input. A proprietary sampling circuit significantly

reduces the input drive requirements, resulting in lower overall

cost and board space in addition to improved performance. Note

that the input capacitance is only 2-3pF during the Sampling

phase, changing to 40pF during the Settling phase, resulting in

an average input current of 2.5µA and an effective input

capacitance of only 4pF. See Figure 26.

Power-Down/Standby Modes

In order to reduce power consumption between conversions, a

number of user-selectable modes can be utilized by setting the

appropriate bits in the Configuration Register.

TOTAL

ERROR ERROR

DC

AC

ERROR

INPUT VOLTAGE

Auto Power-down (PD0 = 0) reduces power consumption by

shutting down all portions of the device except the oscillator and

digital interface after completion of a conversion. There is a short

recovery period after CNV is asserted Low (150µs with external

reference).

OFFSET ERROR

SETTLING ERROR AND NOISE

In Auto Sleep mode (PD1 = 1), the device will automatically enter

the low-power Sleep mode at the end of the current conversion.

Recovery from this mode involves only 2.1µs and may offer an

alternative to Power-down mode in some applications.

SAMPLING PHASE

Output Data Format

The converter output word is delivered in two’s complement

format in differential input mode, and straight binary in

SETTLING PHASE

single-ended input mode of operation respectively, all MSB-first.

Input exceeding the specified full-scale voltage results in a clipped

output which will not return to in-range values until after the input

signal has returned to the specified allowable voltage range.

FIGURE 26. INPUT SAMPLING OPERATION

Data must be read prior to the completion of the current

conversion to avoid conflict and loss of data, due to overwriting of

the new conversion data into the output register.

FN7549.1

July 3, 2012

14

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

5V

BULK

+

0.1µF

DNC

VIN

DNC

1

8

7

6

5

VDD

ISL2631X

ISL2632X

2

3

4

VREF

2.5V

COMP VOUT

GND TRIM

0.1µF

1µF (see text)

ISL21090

FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY

+2.7V TO +3.6V

OR +5V

+

BULK

0.1µF

VIN

1

2

0.1µF

GND

3

VDD

ISL2631X

ISL2632X

VREF

VOUT

1.25, 2.048 OR 2.5V

ISL21010

1µF (see text)

FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY

+2.7V TO +5V

BULK

1µF (see text)

VDD

ISL26310

ISL26313

FIGURE 29. VOLTAGE REFERENCE FOR ISL26310/313 IS DERIVED FROM VDD

TABLE 1. OUTPUT CODES - DIFFERENTIAL

INPUT VOLTAGE TWO’S COMPLEMENT (12-bit)

TABLE 2. OUTPUT CODES - SINGLE-ENDED

INPUT VOLTAGE BINARY (12-bit)

>(VFS - 1.5 LSB)

7FF

>AIN - 1.5 LSB

AIN - 1.5 LSB

0.5 LSB

FFF

7FF

...

7FE

VFS - 1.5 LSB

FFF

…

FFE

000

…

FFF

-0.5 LSB

001

…

000

801

…

-VFS +0.5 LSB

800

<0.5 LSB

000

NOTE: VFS in the table above equals the voltage between AIN+ and AIN-.

Differential full scale is equal to 2* VREF.

NOTE: Single-ended full scale is equal to VREF.

FN7549.1

July 3, 2012

15

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Reading During Conversion Mode

Without EOC

Serial Digital Interface

The ISL26310/11/12/13/14/15/19 family utilizes an SPI-

compatible interface to set the device configuration and read

conversion data. This flexible interface provides 3 modes of

operation: Reading After Conversion (RAC), Reading During

Conversion (RDC), and Reading Spanning Conversions (RSC),

with an additional option providing an End of Conversion (EOC)

indication on the SDO output in all 3 modes. The choice of

operating mode is determined by the timing of the signals on the

serial interface.

From Idle, the user initiates the input signal Acquisition mode by

taking CNV Low, and then initiates a conversion after t by

pulsing CNV High. After the conversion starts, data is exchanged

on the serial interface while CNV is held Low (as shown in

ACQ

Figure 31). CNV must also be asserted High before t

to avoid

DATA

enabling EOC. This method is ideal for hosts with high SCLK

communication rates to operate the device at the highest

conversion rates.

The interface consists of the data clock (SCLK), serial digital

input (SDI), serial digital output (SDO), and the conversion control

input (CNV). From the Idle state (after completion of a prior

conversion), a High-to-Low transition on CNV indicates the

beginning of input signal acquisition, with the Conversion then

initiated by a subsequent Low-to-High transition. When CNV is

Low, input data presented to SDI is latched on the rising edge of

SCLK. Output data will be present at SDO on the falling edge of

SCLK. SDO is in the high-impedance state whenever CNV is High,

and activity on SCLK should be avoided during this time to avoid

corruption of the conversion process. SCLK should be Low when

CNV is High.

At the end of conversion the device enters the Idle state. After the

host is certain that the conversion is completed (7.2µs after

conversion is initiated at 125kSPS) a new acquisition can be

initiated by pulling CNV Low which will initiate the Acquisition state.

Reading Spanning Conversion Mode

Without EOC

In applications desiring slower interface data rates and while still

maintaining maximum possible throughput, RSC mode can be

used to transfer data during both the Acquisition and Conversion

phases, as shown in Figure 32.

Data exchange begins during the Acquisition phase until CNV is

asserted High to initiate a conversion and SDO returns to the

high-impedance state, interrupting the exchange. After CNV is

returned Low, SDO will return to the state prior to the CNV pulse

in order to avoid data loss. Once again data exchange occurs

During the Nth conversion, output data indicates the conversion

data and configuration settings for the N-1th conversion, while

the current configuration settings apply to the N+1th conversion.

In order to minimize errors due to digital noise coupling, there

should be no activity on the serial interface after the specified

when CNV is Low. CNV must be asserted High before t

order to avoid enabling EOC.

in

DATA

t

period. Data should be read before the conversion is

DATA

completed to avoid the newer results being overwritten resulting

in a permanent loss of data.

At the end of conversion the device enters the Idle state. After

the host is certain that the conversion is completed (7.2µs after

conversion is initiated at 125kSPS) a new acquisition can be

initiated by pulling CNV Low, which will take the device back to

Acquisition state from Idle state.

Reading After Conversion Mode Without EOC

In this mode, data transfer always occurs during the Acquisition

phase, supporting the widest variety of interface data rates.

Figure 30 depicts a timing waveform in this mode. From Idle, the

device enters the Acquisition phase when CNV is taken Low. SDO

emerges High from a high-impedance state, waiting for an SCLK

to present the MSB of the current output data word. The

configuration settings can be updated using SDI and at the same

time previous conversion results can be read from SDO. After the

communication is completed or the required acquisition time

(t

) has elapsed – whichever is later – CNV transitions High

ACQ

indicating the start of conversion. CNV must be held High

continuously for a minimum of 7.2µs (at 125kSPS) so that the

conversion is completed without enabling EOC. Subsequently

CNV may be asserted Low at any time so that the next

Acquisition phase can begin. This method is suitable for hosts

which operate with lower frequency SCLK.

Note that when using slower SPI rates the data transfer time can

exceed the minimum acquisition time, which will limit the

conversion throughput to less than the maximum specified rate.

For example, a 12-bit data transfer takes 12µs with a 1MHz SPI

clock. This adds to the 7.2µs conversion time for an effective

throughput of 52ksps.

FN7549.1

July 3, 2012

16

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

ADC STATE

Conversion N

Acquisition

Conversion N+1

Acquisition

Power-Up Idle

CNV

Conversion

Idle

Conversion

Idle

Acq.

t_ACQ

t_SCLK

t_SCLKH

t_{SDOZ_D}

t_{CNV_SCLK}

SCLK

SDI

t_SCLKL

D5

t_{SDI_H}

t_{SDI_SU}

D15

D14

D4

D1

D15

D14

D5

D4

. . .

Configuration N+1

Configuration N+2

Hi-Z State

t_{SDO_V}

LSB

MSB MSB-1

LSB

MSB MSB-1

SDO

. . .

Conversion Result N-1

Conversion Result N

FIGURE 30. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE, WITHOUT EOC

ADC STATE

Conversion N

Conversion

Conversion N+1

t_CNV

Power-Up Idle Acquisition

Idle

Acquisition

Conversion

Idle

t_ACQ

t_DATA

CNV

t_SCLK

t_SCLKH

t_{CNV_CLK}

SCLK

SDI

t_SCLKL

D5

t_{SDI_H}

t_{SDI_SU}

D4

D1

D5

D4

D1

D15

D14

. . .

Configuration N+1

Configuration N+2

Hi-Z State

t_{SDO_V}

MSB MSB-1

LSB

MSB MSB-1

SDO

. . .

Conversion Result N-1

Conversion Result N

FIGURE 31. TIMING DIAGRAM FOR READING DURING CONVERSION MODE, WITHOUT EOC

ADC STATE

Conversion N

t_CNV

Conversion N+1

Conversion

Power-Up Idle

CNV

Acquisition

t_ACQ

Conversion

Idle

Acquisition

Idle

t_DATA

t_SCLKH

t_{CNV_SCLK}

SCLK

SDI

t_SCLK

t_SCLKL

t_{SDI_H}

D12

D15

D14

D13

D12

D4

D15

D14

D13

D4

. . .

t_{SDI_SU}

Configuration N+1

Configuration N+2

Hi-Z State

LSB

t_{SDO_V}

MSB

MSB-1

MSB-1 MSB-2

D1

MSB

MSB-1

MSB-1 MSB-2

D1

SDO

. . .

Conversion Result N-1

Conversion Result N

Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum t_ACQis satisfied).

FIGURE 32. TIMING DIAGRAM FOR READING SPANNING CONVERSION MODE, WITHOUT EOC

FN7549.1

July 3, 2012

17

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Reading After Conversion Mode, with EOC

Reading Spanning Conversion Mode, with EOC

In this mode (Figure 33), after CNV is asserted Low to start input

acquisition, a data exchange is executed by SCLK during the

Acquisition period. CNV is asserted High briefly to initiate a

Conversion, forcing SDO to a high-impedance state. SDO returns

HIGH when CNV is asserted Low during the entire conversion period.

After initiating an Acquisition by bringing CNV Low, the user

begins exchanging data as previously mentioned, until CNV is

asserted High to initiate a conversion and SDO returns to a

high-impedance state, interrupting the exchange. And, after CNV

is returned Low, SDO will return to the state prior to the CNV

pulse in order to avoid losing data interrupted by the conversion

pulse. See Figure 35. The user should take care to observe the

At the end of conversion, the device asserts SDO Low to indicate

that the conversion is complete. This may be used as an interrupt

to start the Acquisition phase. It should be noted (as indicated in

Figure 33) that an additional pulse on CNV is required at the end

of conversion to take the part back to Acquisition from Idle state.

t

period in order to minimize the effects of digital noise on

DATA

sensitive portions of conversion. After completion of the data

exchange, an additional pulse on SCLK forces SDO to a

high-impedance state. At the end of conversion, the device

asserts SDO Low indicating the end of conversion. The device

then returns to Idle, waiting for a pulse on CNV to initiate a new

Acquisition cycle.

As discussed in the “Reading After Conversion Mode Without

EOC” section, the acquisition time (t

) may limit the

ACQ

conversion throughput at slower SPI clock rates.

Accessing the Configuration Register During

Data Readback

Reading During Conversion Mode, with EOC

From Idle, a falling edge on CNV initiates the Acquisition mode,

and then a rising edge initiates a Conversion. After the

conversion is initiated, CNV is asserted Low once again. Data

exchange across SDI and SDO can proceed while CNV is Low,

The Configuration Register contains the channel address of the

current conversion data. The contents can be accessed during a

normal data output sequence by continuing to clock data from

SDO if the register readback mode is enabled. Both 12-bit output

data words and the 16-bit configuration word are output in 28

SCLK periods, as shown in Figure 36, which demonstrates an

example sequence. Note that SDO goes into the high-impedance

state when CNV is High. The Configuration Register can be read

during any Read Sequence by generating the additional SCLKs,

with the restriction that the sequence must be completed prior to

the end of the current conversion. This will prevent loss of data

due to overwriting of the new conversion data into the output and

configuration registers.

again observing the requirements of the t

period in order to

DATA

minimize the effects of digital noise on sensitive portions of the

conversion. In this mode, an additional pulse is required on SCLK

after the completion of the data exchange, to transition SDO to

the high-impedance state. Later, SDO is asserted low by the

device indicating end of conversion. The device then returns to

Idle. The falling edge of SDO may be used as an interrupt to start

the Acquisition phase. See Figure 34.

ADC STATE

Conversion N

Conversion N+1

Power-Up Idle

CNV

Acquisition

Conversion

Idle

Acquisition

Conversion

Idle

Acq.

t_CNV

t_ACQ

t_SCLK

t_SCLKH

t_{CNV_SCLK}

SCLK

SDI

t_SCLKL

t_{SDI_H}

D15

D14

D5

D4

D15

D14

D5

D4

. . .

t_{SDI_SU}

Configuration N+1

Configuration N+2

Hi-Z State

D1 LSB

t_{SDO_V}

LSB

MSB MSB-1

SDO

. . .

Conversion Result N-1

Conversion Result N

FIGURE 33. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE WITH EOC ON SDO OUTPUT

FN7549.1

July 3, 2012

18

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

ADC STATE

Conversion N

Conversion

Conversion N+1

t_CNV

Power-Up Idle Acquisition

Idle

Acquisition

Conversion

Idle

t_ACQ

t_DATA

CNV

t_SCLK

t_SCLKH

t_{CNV_CLK}

SCLK

SDI

t_SCLKL

D5

t_{SDI_H}

t_{SDI_SU}

D4

D1

D5

D4

D1

D15

D14

. . .

Configuration N+1

Configuration N+2

Hi-Z State

t_{SDO_V}

MSB MSB-1

LSB

MSB MSB-1

SDO

. . .

Conversion Result N-1

Conversion Result N

FIGURE 34. TIMING DIAGRAM FOR READING DURING CONVERSION MODE WITH EOC ON SDO OUTPUT

ADC STATE

Conversion N

t_CNV

Conversion N+1

Power-Up Idle

CNV

Acquisition

t_ACQ

Conversion

Idle

Acquisition

Conversion

Idle

t_DATA

t_SCLKH

t_{CNV_SCLK}

SCLK

SDI

t_SCLK

t_SCLKL

t_{SDI_H}

D12

D15

D14

D13

D12

D4

D15

D14

D13

D4

. . .

t_{SDI_SU}

Configuration N+1

Configuration N+2

Hi-Z State

MSB

t_{SDO_V}

MSB-1

MSB-1 MSB-2

D1

LSB

MSB

MSB-1

MSB-1 MSB-2

D1

SDO

. . .

Conversion Result N-1

Conversion Result N

Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum t_ACQis satisfied).

FIGURE 35. TIMING DIAGRAM FOR READING SPANNING CONVERSIONS MODE WITH EOC ON SDO OUTPUT

ADC STATE

Conversion N

Power-Up Idle

CNV

Acquisition

Conversion

Idle

SCLK

SDI

D15

D14

D5

D4

D1

. . .

Configuration N+1

Hi-Z State

MSB MSB-1

LSB

Cfg15 Cfg14

Cfg1

Cfg0

SDO

. . .

Conversion Result N-1

Configuration settings of N-1 Result

FIGURE 36. TIMING DIAGRAM FOR READING AFTER CONVERSION WITH REGISTER READBACK, WITHOUT EOC

FN7549.1

July 3, 2012

19

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Device Configuration Registers

Power Management Modes

The Input Multiplexer Channel Select and power management

features are controlled by loading the appropriate bits into the

16-bit Configuration Register through the serial port, MSB-first,

as shown below. The first two Load bits LD1-LD0 must be set to

“11” in order to perform a Register update: any other setting will

leave the Register unchanged. Changes to the Configuration

Register will be implemented internally immediately following

the completion of the current conversion, or require a dummy

conversion in order to take effect. Also, in the case of all power

management features, a recovery time will be incurred when

returning to normal operation, as indicated.

In all SPI interface modes (RAC, RDC, etc.) the device has three

states of operation: Acquisition, Conversion and Idle. Power

management modes decide the state of the ADC in Idle mode

and are selected by the PM bits in the Configuration Register as

shown in Table 3 and Table 4.

In the default mode (Continuous Operation) the ADC is fully

powered in the Idle state and can be taken back to the

Acquisition state instantaneously. In this mode the ADC can be

operated with maximum throughput and hence is ideally suitable

for applications where the ADC is operated continuously.

In Auto Sleep Mode the ISL263XX will be in a sleep state

consuming less than 0.4mA. However, it should be noted that the

TABLE 3. CONFIGURATION REGISTER

BIT 15

requirements on t

are more stringent in Auto Sleep mode

ACQ

(MSB)

14

13

12

11

10

9

8

since the device must wake up and then perform the Acquisition.

LD1

LD0 ADDR2 ADDR1 ADDR0 PM1 PM0 Unused

In Auto Power Down Mode (as selected by PM bits) the ADC will be in

power-down condition during the Idle period, consuming less than

5µA of current. Wake-up time takes 150µs. The acquisition time

BIT 0

BIT 2 BIT 1 (LSB)

(t

) must be increased to account for this delay.

BIT 7 BIT 6

RGRD

BIT 5

BIT 4

BIT 3

ACQ

Unused

The power management modes provide a high degree of

flexibility in trading average power consumption versus the

required throughput. Significant power savings can be achieved

by operating in either Auto Sleep Mode or Auto Power-Down

mode depending on the throughput requirements.

TABLE 4. CONFIGURATION REGISTER 2

DESCRIPTION

BIT(S)

15:14 Register Load word, set to “11” to update registers,

otherwise previous settings are retained.

13:11 Multiplexer Channel Select word ADDR2:0.

000H: Channel AIN0 (single-ended input devices) or AIN0+/AIN0-

(differential input devices)

001H: Channel AIN1 or AIN1+/AIN1-

010H: Channel AIN2 or AIN2+/AIN2-

011H: Channel AIN3 or AIN3+/AIN3-

100H: Channel AIN4

101H: Channel AIN5

110H: Channel AIN6

111H: Channel AIN7

10:9 Power Management Configuration Control

00H: Auto Power-Down mode. Device will go into Power-down

mode automatically at the end of the next conversion cycle.

01H: Continuous Operation mode (default). Device remains fully

powered at all times.

1xH: Auto Sleep Mode. Device will enter reduced-power Sleep

mode automatically at the end of the next conversion cycle. A "1"

in PM1 overrides the setting in PM0.

8

7

Unused

Register readback mode. "1" means register readback is enabled

resulting in configuration settings to be output along with

conversion results. "0" (default) mode of operation register

settings are not output.

6:0 Unused

FN7549.1

July 3, 2012

20

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

CHANGE

June 22, 2012

FN7549.1 Added Part Numbers ISL26310, ISL26311, ISL26313 throughout document

Added SOIC Package throughout document

Updated Features List by Removing following bullets:

o 125kSPS Conversion Rate

o Pin-Compatible 2/4-Channel Differential or 4/8-Channel Single-Ended Inputs

o Internal 2.5V Reference

o Available in Popular TSSOP Package

o Pb-Free (RoHS Compliant)

Updated Functional Block Diagram on page 1 by removing voltage reference

Updated Pin Compatible Family by removing ISL264XX PARTS

Updated Pin Description Table to include all parts

Updated conditions in Electrical Spec Table from:

Electrical Specifications VREF+ = VDD(External) V, VDD = 3.3V to 5V, VCM = VDD/2, SCLK = 20MHz...

To:

Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz...

Removed VREFIN specs from Voltage Reference Section

Removed Test Level from tACQ in Auto Power Down Mode

Replaced Figures 3 and 4 DNL and INL

Replaced Figure 17 by changing from single line curve to frequency mode

Rewrote Functional Description Section

January 11, 2012 FN7549.0 Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7549.1

July 3, 2012

21

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Package Outline Drawing

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 5/10

A

1

3

5.00 ±0.10

SEE DETAIL "X"

9

16

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

0.20 C B A

1

8

B

0.09-0.20

0.65

TOP VIEW

END VIEW

1.00 REF

-

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

SEATING

PLANE

GAUGE

PLANE

0.25 +0.05/-0.06

0.25

5

0.10

C B A

M

0.10 C

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

(5.65)

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

(0.65 TYP)

(0.35 TYP)

6. Dimension in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153.

FN7549.1

July 3, 2012

22

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

DETAIL "A"

1.27 (0.050)

0.40 (0.016)

INDEX

AREA

6.20 (0.244)

5.80 (0.228)

0.50 (0.20)

0.25 (0.01)

x 45°

4.00 (0.157)

3.80 (0.150)

8°

0°

1

2

3

0.25 (0.010)

0.19 (0.008)

SIDE VIEW “B”

TOP VIEW

2.20 (0.087)

1

8

SEATING PLANE

0.60 (0.023)

1.27 (0.050)

1.75 (0.069)

5.00 (0.197)

4.80 (0.189)

2

3

7

6

1.35 (0.053)

-C-

4

5

0.25(0.010)

0.10(0.004)

1.27 (0.050)

0.51(0.020)

0.33(0.013)

5.20(0.205)

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the

seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN7549.1

July 3, 2012

23


型号：	ISL26314
厂家：	Intersil
描述：	12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels 12位， 125ksps采样率的低功耗ADC，具有单端和差分输入和多输入通道
文件：	总23页 (文件大小：818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL26314 [INTERSIL]

相关型号：

ISL26314FVZ

ISL26314FVZ

ISL26314FVZ-T7A

ISL26315

ISL26315FVZ

ISL26315FVZ

ISL26315FVZ-T7A

ISL26319

ISL26319FVZ

ISL26319FVZ

ISL26319FVZ-T7A

ISL26320