ISL22424UFR16Z [INTERSIL]
Dual Digitally Controlled Potentiometer (XDCP?); 双数控电位器（ XDCP ™ ）
| 型号： | ISL22424UFR16Z |
| 厂家： | 
Intersil |
| 描述： | Dual Digitally Controlled Potentiometer (XDCP?) |
| 文件： | 总18页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL22424
®
Dual Digitally Controlled Potentiometer (XDCP™)
Data Sheet
®
May 31, 2007
FN6425.0
Low Noise, Low Power, SPI Bus,
256 Taps
Features
• Two potentiometers in one package
• 256 resistor taps
The ISL22424 integrates two digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
• SPI serial interface with write/read capability
• Daisy Chain Configuration
• Shutdown mode
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. Each potentiometer has an associated
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVRi to the corresponding WRi.
• Non-volatile EEPROM storage of wiper position
• 13 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55°C
• Wiper resistance: 70Ω typical @ 1mA
• Standby current <4µA max
The ISL22424 also has 13 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
• Shutdown current <4µA max
The ISL22424 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
• Dual power supply
between V- and V
.
- V = 2.25V to 5.5V
CC
CC
- V- = -2.25V to -5.5V
Each DCP can be used as three-terminal potentiometer or
as two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40ºC to +125ºC
• 14 Ld TSSOP or 16 Ld QFN
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
(NOTES 1, 2)
RESISTANCE
OPTION (kΩ)
TEMPERATURE
RANGE (°C)
PACKAGE
(Pb-Free)
PART MARKING
22424TFVZ
PKG. DWG. #
M14.173
ISL22424TFV14Z
ISL22424TFR16Z
ISL22424UFV14Z
ISL22424UFR16Z
ISL22424WFV14Z
ISL22424WFR16Z
NOTES:
100
100
50
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
14 Ld TSSOP
22424TFRZ
16 Ld QFN
L16.4x4A
M14.173
L16.4x4A
M14.173
L16.4x4A
22424UFVZ
14 Ld TSSOP
16 Ld QFN
22424UFRZ
22424WFVZ
22424WFRZ
50
10
14 Ld TSSOP
16 Ld QFN
10
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22424
Block Diagram
RH0
RH1
V-
VCC
SCK
SDI
POWER UP,
CONTROL
AND
STATUS
LOGIC
SPI
INTERFACE
SDO
CS
WR0
WR0
VOLATILE
REGISTER
AND
VOLATILE
REGISTER
AND
WIPER
WIPER
CONTROL
CIRCUITRY
CONTROL
CIRCUITRY
NON-VOLATILE
REGISTERS
RW0
RL0
RW1
RL1
GND
Pinouts
ISL22424
(14 LD TSSOP)
TOP VIEW
ISL22424
(16 LD QFN)
TOP VIEW
RH0
RL0
1
2
3
4
5
6
7
14
VCC
CS
16 15 14 13
13
12
11
10
9
RW0
RH1
RL1
RW1
NC
1
2
3
4
12
11
10
9
SDI
GND
SCK
SDO
V-
NC
NC
NC
V-
RL0
RH0
V
CC
CS
8
5
6
7
8
FN6425.0
May 31, 2007
2
ISL22424
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
RH0
RL0
DESCRIPTION
1
2
11
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
“High” terminal of DCP1
“Low” terminal of DCP1
“Wiper” terminal of DCP1
No connection
12
3
13
RW0
RH1
RL1
4
14
5
15
6
16
RW1
NC
7
1, 2, 3
8
4
V-
Negative power supply pin
9
5
SDO
SCK
GND
SDI
Data Output of the SPI serial interface
SPI interface clock input
10
11
12
13
14
6
7
Device ground pin
8
9
Data Input of the SPI serial interface
Chip Select active low input
CS
10
VCC
Positive power supply pin
EPAD*
Exposed Die Pad internally connected to V-
* Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
FN6425.0
May 31, 2007
3
ISL22424
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
JA
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
16 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V
+0.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to V
CC
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C
ESD
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Analog Specifications Over recommended operating conditions unless otherwise stated.
TYP
SYMBOL
PARAMETER
RHi to RLi resistance
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
kΩ
R
W option
U option
T option
10
TOTAL
50
kΩ
100
kΩ
RHi to RLi resistance tolerance
-20
V-
+20
%
End-to-End Temperature Coefficient
W option
±85
±45
ppm/°C
ppm/°C
V
U, T option
V
, V
RH RL
DCP terminal voltage
Wiper resistance
V
and V
to GND
V
CC
RHi
RLi
R
RH - floating, V = V-, force Iw current to the
70
10/10/25
0.1
250
Ω
W
RL
wiper, I = (V
- V )/R
W
CC RL TOTAL
C /C /C
W
Potentiometer capacitance
Leakage on DCP pins
See Macro Model below.
pF
µA
H
L
(Note 20)
I
Voltage at pin from V- to V
1
LkgDCP
CC
VOLTAGE DIVIDER MODE (V- @ RLi; V
@ RHi; measured at RWi, unloaded)
W option
CC
INL
Integral non-linearity
-1.5
-1.0
-1.0
-0.5
±0.5
±0.2
1.5
1.0
1.0
0.5
LSB
(Note 5)
(Note 9)
U, T option
W option
LSB
(Note 5)
DNL
(Note 8)
Differential non-linearity
Monotonic over all tap positions
±0.4
LSB
(Note 5)
U, T option
±0.15
LSB
(Note 5)
ZSerror
(Note 6)
Zero-scale error
W option
0
0
1
0.5
-1
5
2
0
0
2
LSB
(Note 5)
U, T option
W option
FSerror
(Note 7)
Full-scale error
-5
-2
-2
LSB
(Note 5)
U, T option
-1
V
DCP to DCP matching
Wipers at the same tap position, the same
voltage at all RH terminals and the same
voltage at all RL terminals
LSB
(Note 5)
MATCH
(Note 10)
TC
Ratiometric temperature coefficient
DCP register set to 80 hex
±4
ppm/°C
V
(Note 11, 20)
FN6425.0
May 31, 2007
4
ISL22424
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
TYP
SYMBOL
PARAMETER
-3dB cut off frequency
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
kHz
kHz
kHz
f
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
Wiper at midpoint (80hex) T option (100k)
1000
250
cutoff
(Note 20)
120
RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)
W
L
H
W
H
L
RINL
(Note 15)
Integral non-linearity
Differential non-linearity
Offset
W option
-3
±1.5
±0.4
±0.5
±0.15
1
3
1
MI
(Note 12)
U, T option
W option
-1
MI
(Note 12)
RDNL
(Note 14)
-1.5
-0.5
0
1.5
0.5
5
MI
(Note 12)
U, T option
W option
MI
(Note 12)
Roffset
MI
(Note 13)
(Note 12)
U, T option
0
0.5
2
MI
(Note 12)
R
DCP to DCP matching
Wipers at the same tap position with the
same terminal voltages
-2
2
MI
(Note 12)
MATCH
(Note 16)
TC
Resistance temperature coefficient
DCP register set between 32hex and FF hex
±40
ppm/°C
R
(Note 17, 20)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
= 5.5V, V- = 5.5V, f = 5MHz; (for SPI
MIN
(NOTE 4)
MAX
UNIT
I
V
Supply Current (volatile
V
0.6
1.0
mA
CC1
CC
CC
SCK
write/read)
Active, Read and Volatile Write states only)
V
= 2.25V, V- = -2.25V, f
= 5MHz; (for SPI
0.25
-0.3
-0.1
1.0
0.5
mA
mA
mA
mA
mA
mA
mA
µA
CC
SCK
Active, Read and Volatile Write states only)
I
V- Supply Current (volatile
write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
Active, Read and Volatile Write states only)
-1.0
-0.5
V-1
CC
SCK
V- = -2.25V, V = 2.25V, f
Active, Read and Volatile Write states only)
= 5MHz; (for SPI
CC SCK
I
V
Supply Current
V
= 5.5V, V- = 5.5V, f = 5MHz; (for SPI
2.0
1.0
CC2
CC
CC
SCK
(non-volatile write/read)
Active, Read and Non-volatile Write states only)
V
= 2.25V, V- = -2.25V, f
= 5MHz; (for SPI
0.3
CC
SCK
Active, Read and Non-volatile Write states only)
I
V- Supply Current (non-volatile
write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
-2.0
-1.0
-1.2
-0.4
0.5
V-2
CC
SCK
V- Supply Current (non-volatile
write/read)
V- = -2.25V, V = 2.25V, f
Active, Read and Non-volatile Write states only)
= 5MHz; (for SPI
CC SCK
I
V
Current (standby)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
2.0
4.0
1.0
2.0
SB
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
1.0
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.2
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
0.5
µA
CC
interface in standby state
FN6425.0
May 31, 2007
5
ISL22424
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
TYP
SYMBOL
PARAMETER
V- Current (standby)
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
I
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
-3.0
-0.7
µA
V-SB
in standby state
V- = -5.5V, V
= +5.5V @ +125°C, SPI
-5.0
-2.0
-3.0
-1.5
-0.3
-0.4
0.5
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +125°C, SPI
CC
interface in standby state
I
V
Current (shutdown)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
2.0
4.0
1.0
2.0
SD
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
1.0
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.2
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
0.5
CC
interface in standby state
I
V- Current (shutdown)
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
in standby state
-3.0
-5.0
-2.0
-3.0
-1
-0.7
-1.5
-0.3
-0.4
V-SD
V- = -5.5V, V
= +5.5V @ +125°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +125°C, SPI
interface in standby state
CC
I
Leakage current, at pins SCK,
SDI, SDO and CS
Voltage at pin from GND to V
1
LkgDig
CC
t
DCP wiper response time
CS rising edge to wiper new position
1.5
1.5
WRT
(Note 20)
t
DCP recall time from shutdown
CS rising edge to wiper stored position and RH
connection
µs
ShdnRec
(Note 20) mode
Vpor
Power-on recall voltage
ramp rate
Minimum Vcc at which memory recall occurs
1.9
0.2
2.1
5
V
VccRamp
V
V/ms
ms
CC
t
Power-up delay
V
above Vpor, to DCP Initial Value Register
CC
D
recall completed, and SPI Interface in standby
state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T ≤ +55ºC
t
Non-volatile Write Cycle time
12
20
WC
(Note 18)
SERIAL INTERFACE SPECIFICATIONS
V
SCK, SDI, and CS input buffer
LOW voltage
0.3 * V
V
V
IL
CC
V
SCK, SDI, and CS input buffer
HIGH voltage
0.7 * V
CC
IH
Hysteresis SCK, SDI, and CS input buffer
hysteresis
0.05 * V
0
V
CC
V
SDO output buffer LOW voltage
I
= 4mA for Open Drain output, pull-up
0.4
2
V
OL
OL
voltage Vpu = Vcc
R
SDO pull-up resistor off-chip
Maximum is determined by t
maximum bus load Cb = 30pF, f
and t
with
kΩ
pu
(Note 19)
RO
FO
= 5MHz
SCK
FN6425.0
May 31, 2007
6
ISL22424
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
Cpin
SCK, SDI, SDO and CS pin
10
pF
(Note 20) capacitance
f
SPI frequency
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCK
t
SPI clock cycle time
SPI clock high time
200
100
100
250
250
50
CYC
t
WH
t
SPI clock low time
WL
t
Lead time
LEAD
t
Lag time
LAG
t
SDI, SCK and CS input setup time
SDI, SCK and CS input hold time
SDI, SCK and CS input rise time
SDI, SCK and CS input fall time
SDO output Disable time
SDO output setup time
SDO output valid time
SDO output hold time
SDO output rise time
SDO output fall time
CS deselect time
SU
t
50
H
t
10
RI
t
10
20
FI
t
0
100
DIS
t
50
SO
t
150
0
V
t
HO
RO
t
R
= 2k, Cbus = 30pF
60
60
pu
t
t
R
= 2k, Cbus = 30pF
FO
CS
pu
2
NOTES:
4. Typical values are for T = +25°C and 3.3V supply voltage.
A
5. LSB: [V(RW)
255
– V(RW) ]/255. V(RW)
and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
255 0
0
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW) /LSB.
0
7. FS error = [V(RW)
255
– V ]/LSB.
CC
8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
9. INL = [V(RW) – i • LSB – V(RW)]/LSB for i = 1 to 255.
i
10. V
11.
= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
MATCH
Max(V(RW) ) – Min(V(RW) )
6
10
i
i
for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
--------------------------------------------------------------------------------------------- ----------------
TC
=
×
V
+
i
i
12. MI = |RW
– RW |/255. MI is a minimum increment. RW and RW are the measured resistances for the DCP register set to FF hex and
255 0
255
0
00 hex respectively.
13. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
255
14. RDNL = (RW – RW )/MI -1, for i = 1 to 255.
i-1
i
15. RINL = [RW – (MI • i) – RW ]/MI, for i = 1 to 255.
i
0
16. R
17.
= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
6
MATCH
[Max(Ri) – Min(Ri)]
10
for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
the minimum value of the resistance over the temperature range.
--------------------------------------------------------------- ----------------
TC
=
×
R
165°C
[Max(Ri) + Min(Ri)] ⁄ 2
+
18. t
is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
WC
19. R is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
pu
20. This parameter is not 100% tested.
FN6425.0
May 31, 2007
7
ISL22424
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
10pF
10pF
25pF
RW
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
RI
FI
t
t
WH
t
WL
SU
H
...
MSB
LSB
SDI
HIGH IMPEDANCE
SDO
Output Timing
CS
SCK
SDO
SDI
...
...
t
t
t
DIS
SO
HO
MSB
LSB
t
V
ADDR
XDCP Timing (for All Load Instructions)
CS
t
WRT
SCK
...
...
MSB
LSB
SDI
V
W
HIGH IMPEDANCE
SDO
FN6425.0
May 31, 2007
8
ISL22424
Typical Performance Curves
80
2.0
1.5
1.0
0.5
0
T = +125ºC
70
60
50
40
30
20
10
0
T = +25ºC
T = -40ºC
I
CC
-0.5
-1.0
-1.5
-2.0
I
V-
0
50
100
150
200
250
-40
0
40
TEMPERATURE (°C)
80
120
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY I
and I vs TEMPERATURE
V-
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10kΩ (W)
CC
CC TOTAL
0.50
0.50
0.25
0
V
= 5.5V
CC
T = +25ºC
T = +25ºC
V
= 2.25V
CC
0.25
0
-0.25
-0.50
-0.25
-0.50
V
= 5.5V
V
= 2.25V
100
CC
100
TAP POSITION (DECIMAL)
CC
0
50
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
MODE FOR 10kΩ (W)
2.0
0
10k
1.6
1.2
-1
V
= 2.25V
CC
50k
V
= 5.5V
CC
-2
0.8
-3
-4
50k
10k
V
= 2.25V
V
= 5.5V
CC
CC
0.4
0
-5
-40
0
40
80
120
-40
0
40
TEMPERATURE (ºC)
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FIGURE 5. ZS ERROR vs TEMPERATURE
FN6425.0
May 31, 2007
9
ISL22424
Typical Performance Curves (Continued)
0.5
2.0
T = +25ºC
T = +25ºC
V
= 5.5V
1.5
1.0
CC
V
= 2.25V
0.25
0
CC
0.5
0
-0.25
-0.50
V
= 2.25V
100
CC
V
= 5.5V
CC
-0.5
0
50
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10kΩ (W)
10kΩ (W)
200
1.60
10k
160
1.20
10k
120
80
0.80
5.5V
0.40
0.00
50k
40
50k
2.25V
0
-0.40
16
66
116
166
216
266
-40
0
40
80
120
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
500
400
300
INPUT
OUTPUT
10k
200
100
50k
WIPER AT MID POINT (POSITION 80h)
R
= 10kΩ
TOTAL
0
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (1MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FN6425.0
May 31, 2007
10
ISL22424
Typical Performance Curves (Continued)
CS
SCL
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
WIPER
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Pin Description
Potentiometer Pins
CHIP SELECT (CS)
RHI AND RLI
CS LOW enables the ISL22424, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22424 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
The high (RHi) and low (RLi) terminals of the ISL22424 are
equivalent to the fixed terminals of a mechanical potentiometer.
RHi and RLi are referenced to the relative position of the wiper
and not the voltage potential on the terminals. With WRi set to
255 decimal, the wiper will be closest to RHi, and with the WRi
set to 0, the wiper is closest to RLi.
Principles of Operation
RWI
The ISL22424 is an integrated circuit incorporating two
DCPs with their associated registers, non-volatile memory
and the SPI serial interface providing direct communication
between host, potentiometers and memory. The resistor
arrays are comprised of individual resistors connected in a
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following
rising edge of SCK.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the content of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial position.
The output type is configured through ACR[1] bit for Push -
Pull or Open Drain operation. Default setting for this pin is
Push - Pull. An external pull up resistor is required for Open
Drain output operation. Note: the external pull up voltage not
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
allowed beyond V
.
CC
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are
FN6425.0
May 31, 2007
11
ISL22424
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is
The register at address 0Fh is a read-only reserved register.
Information read from this register should be ignored.
closest to its “Low” terminal (RLi). When the WRi register of a
DCP contains all ones (WRi[7:0]= FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the
WRi increases from all zeroes (0) to all ones (255 decimal),
the wiper moves monotonically from the position closest to
RLi to the closest to RHi. At the same time, the resistance
between RWi and RLi increases monotonically, while the
resistance between RHi and RWi decreases monotonically.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
While the ISL22424 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WRi will be reloaded with the value stored in a
corresponding non-volatile Initial Value Register (IVRi).
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
BIT
VOL SHDN WIP
SDO
NAME
If VOL bit is 0, the non-volatile IVRi and General Purpose
registers are accessible. If VOL bit is 1, only the volatile WRi
are accessible. Note: value that is written to IVRi register
also is written to the corresponding WRi. The default value of
this bit is 0.
The WRi and IVRi can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The ISL22424 contains two non-volatile 8-bit Initial Value
Registers (IVRi), thirteen non-volatile 8-bit General Purpose
(GP) registers, two volatile 8-bit Wiper Registers (WRi), and
volatile 8-bit Access Control Register (ACR). The memory
map of ISL22424 is in Table 1.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. When this bit is 0, DCP is in Shutdown mode, i.e.
each DCP is forced to end-to-end open circuit and RWi is
shorted to RLi as shown on Figure 15. Default value of
SHDN bit is 1.
TABLE 1. MEMORY MAP
RHi
ADDRESS
(hex)
10
F
NON-VOLATILE
VOLATILE
N/A
ACR
RWi
Reserved
E
D
C
B
A
9
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
IVR1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WR1
WR0
RLi
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Setting SHDN bit to 1 is returned wipers to prior to Shutdown
Mode position.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write or read to
the WRi or ACR while WIP bit is 1.
8
7
6
5
The SDO bit (ACR[1]) configures type of SDO output pin.
The default value of SDO bit is 0 for Push - Pull output. SDO
pin can be configured as Open Drain output for some
application. In this case, an external pull up resistor is
required. See “Applications Information” on page 14.
4
3
2
1
SPI Serial Interface
0
IVR0
The ISL22424 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22424. SCK and CS lines are
The non-volatile registers (IVRi) at address 0 and 1, contain
initial wiper position and volatile registers (WRi) contain
current wiper position.
FN6425.0
May 31, 2007
12
ISL22424
controlled by the host or master. The ISL22424 operates
only as a slave device.
Write Operation
A Write operation to the ISL22424 is a two or more bytes
operation. First, It requires, the CS transition from HIGH to
LOW. Then host must send a valid Instruction Byte followed
by one or more Data Bytes to SDI pin. The host terminates
the write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write-to
address 0 or 1, the MSB of the byte at address 10h (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16. Note: the internal non-volatile
write cycle starts with the rising edge of CS and requires up
to 20ms. During non-volatile write cycle the read operation to
ACR register is allowed to check WIP bit.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).
The next byte sent to the ISL22424 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
BIT #
7
6
5
4
3
2
1
0
Read Operation
A Read operation to the ISL22424 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then the
host must send a valid Instruction Byte followed by “dummy”
Data Byte, a NOP Instruction Byte and another “dummy”
Data Byte to SDI pin. The SPI host receives the Instruction
Byte (instruction code + register address) and requested
Data Byte from SDO pin on rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS pin from LOW to HIGH (see
Figure 17). Reading from the IVRi will not change the WRi, if
its contents are different.
I2
I1
I0
R4
R3
R2
R1
R0
Table 4 contains a valid instruction set for ISL22424.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are 00000 or 00001, then the read or
write is to either the IVRi or the WRi registers (depends of
VOL bit at ACR). If the [R4:R0] are 10000, then the
operation is on the ACR.
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
0
I1
0
I0
0
R4
X
R3
X
R2
X
R1
X
R0
X
OPERATION
NOP
0
0
1
X
X
X
X
X
ACR READ
ACR WRITE
0
1
1
X
X
X
X
X
1
0
0
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
WR, IVR, GP or ACR READ
WR, IVR, GP or ACR WRITE
1
1
0
where X means “do not care”.
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
DATA BYTE
WR INSTRUCTION
ADDR
SDI
SDO
FIGURE 16. TWO BYTE WRITE SEQUENCE
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May 31, 2007
13
ISL22424
1
8
16
24
32
CS
SCK
NOP
RD
ADDR
SDI
RD
ADDR
READ DATA
SDO
FIGURE 17. FOUR BYTE READ SEQUENCE
to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... -->
DCP(N-1). The write instruction is executed on the rising
edge of CS for all N DCPs simultaneously.
Applications Information
Communicating with ISL22424
Communication with ISL22424 proceeds using SPI interface
through the ACR (address 10000b), IVRi (address 00000b,
00001b), WRi (addresses 00000b, 00001b) and General
Purpose registers (addresses from 00010b to 01110b).
Daisy Chain Read Operation
The read operation consists of two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20
and Figure 21.
The wiper position of each potentiometer is controlled by the
corresponding WRi register. Writes and reads can be made
directly to these registers to control and monitor the wiper
position without any non-volatile memory changes. This is
done by setting MSB bit at address 10000b to 1
(ACR[7] = 1).
The first part starts by HIGH to LOW transition on CS line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS
line, followed by N two bytes NOP instructions on SDI line
and LOW to HIGH transition of CS. The data is read on
every even byte during second part of read sequence while
every odd byte contains instruction code + address from
which the data is being read.
The non-volatile IVRi stores the power up position of the
wiper. IVRi is accessible when MSB bit at address 10000b is
set to 0 (ACR[7] = 0). Writing a new value to the IVRi register
will set a new power up position for the wiper. Also, writing to
this registers will load the same value into the corresponding
WRi as the IVRi. Reading from the IVRi will not change the
WRi, if its contents are different.
Daisy Chain Configuration
When application needs more then one ISL22424, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown on Figure 18. In Daisy
Chain configuration the SDO pin of previous chip is connected
to SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note, the number of daisy chained DCPs is
limited only by the driving capabilities of SCK and CS pins of
microcontroller; for larger number of SPI devices buffering of
SCK and CS lines is required.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note, that all switching transients will
settle well within the settling time as stated on the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus may not be a
good solution for some applications. It may be a good idea,
in that case, to use fast amplifiers in a signal chain for fast
recovery.
Daisy Chain Write Operation
The write operation starts by HIGH to LOW transition on CS
line, followed by N two bytes write instructions on SDI line
with reversed chain access sequence: the instruction byte +
data byte for the last DCP in chain is going first, as shown on
Figure 19. The serial data is going through DCPs from DCP0
FN6425.0
May 31, 2007
14
ISL22424
DCP1 programs the gain of the EL8173 from 90 to 110 with
Application Example
5V output for 10A current through current sense resistor.
Figure 22 shows an example of using ISL22424 for gain
setting and offset correction in high side current
measurement application. DCP0 applies a programmable
offset voltage of ±25mV to the FB+ pin of the Instrumentation
Amplifier EL8173 to adjust output offset to zero voltages.
More application examples can be found at
http://www.intersil.com/data/an/AN1145.pdf
N DCP IN A CHAIN
CS
SCK
DCP0
DCP1
DCP2
DCP(N-1)
CS
MOSI
MISO
CS
CS
CS
SCK
SDI
SCK
SCK
SDI
SCK
SDI
µC
SDO
SDI
SDO
SDO
SDO
FIGURE 18. DAISY CHAIN CONFIGURATION
CS
SCK
16 CLKS
C P0
16 CLKLS
P2
16 CLKS
WR
D C
WR
D
D
C
P1
P2
WR
WR
D
SDI
D
C P1
SDO 0
WR
C
WR
D
C P2
SDO 1
SDO 2
FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 20. TWO BYTE OPERATION
FN6425.0
May 31, 2007
15
ISL22424
CS
SCK
SDI
16 CLKS
RD DCP2
16 CLKS
RD DCP1
16 CLKS
RD DCP0
16 CLKS
NOP
16 CLKS
NOP
16 CLKS
NOP
DCP0 OUT
DCP2 OUT
DCP1 OUT
SDO
FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
1.2V
PROCESSOR LOAD
10A, MAX
DC/DC CONVERTER
OUTPUT
0.005Ω
+5V
8
10k
10k
0.1µF
EL8173IS
1
V +
S
3
2
7
5
IN+
IN-
EN
6
V
V
= 0V to + 5V to ADC
OUT
OUT
FB+
+5V
R
4
FB-
V -
S
150k, 1%
R
1
4
50k, 1%
RH1
RL1
RH0
RW1
R
5
309, 1%
R
2
1k, 1%
RW0
RL0
50k
50k
DCP0 (1/2 ISL22424U)
PROGRAMMABLE OFFSET ±25mV
DCP1 (1/2 ISL22424U)
PROGRAMMABLE GAIN 90 TO 110
R
6
R
3
1.37k, 1%
50k, 1%
-5V
ISL22424UFV14Z
14
1
2
3
+5V
Vcc
RH0
RL0
RW0
DCP0
DCP1
10
9
12
13
7
SCL
SDO
SDI
CS
SPI bus
4
5
6
RH1
RL1
RW1
NC
11
8
GND
-5V
V-
FIGURE 22. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
FN6425.0
May 31, 2007
16
ISL22424
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGD-10)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
2.30
2.30
0.25
0.30
2.55
2.55
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.40
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.40
7, 8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 2 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present.
L minus L1 to be equal to or greater than 0.3mm.
FN6425.0
May 31, 2007
17
ISL22424
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6425.0
May 31, 2007
18
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