ISL1561 [INTERSIL]
3 pin serial port interface;
| 型号： | ISL1561 |
| 厂家： | 
Intersil |
| 描述： | 3 pin serial port interface |
| 文件： | 总13页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fixed Gain Dual Port Class-G Differential xDSL Line
Driver
ISL1561
Features
The ISL1561 is a fixed gain dual port class-G differential
amplifier designed for driving full rate ADSL2+ and VDSL2
signals at very low power dissipation. The driver runs on a
single +14V power supply and internally generates higher
supply voltages when needed to enable power efficient
operation for high peak-to-average ratio (PAR) ADSL2+ and
VDSL2 signals.
• Internal fixed gain of 11.6V/V to transformer (see Figure 3)
• 360mA output drive capability
• 41.8V
P-P
differential output drive into 100Ω in class G mode
• VDSL2 8b profile MTPR of -64dBc
• VDSL2 17a profile MTPR of -60dBc
• ADSL2+, VDSL2 8b and 17a power consumption of 520mW,
610mW and 411mW respectively
In ADSL2+ mode of operation with full 19.8dBm transmit
signal power across 100Ω line load, each port consumes only
520mW of power, while with 19.5dBm VDSL2 8b profile a port
consumes 610mW of power. In VDSL2 17a mode of operation
with 14.5dBm transmit power, a port will consume 411mW of
power. These typical power consumption figures account for
receiver hybrid loading effects and transformer losses.
• 8-bit programmable register to set supply current on each
port
• 3 pin serial port interface
Applications
• Dual port ADSL2+ and VDSL2 DSLAM
The ISL1561 provides two ports of wideband, current feedback
amplifiers optimized for low power consumption in xDSL
systems. The drivers achieve an average upstream missing
band power ratio (MBPR) distortion of better than -64dBc
under 19.8dBm transmit signal power into 100Ω load. A three
pin serial interface is used to program an 8-bit internal register
to set each port’s supply current with 0.5mA step size. This
flexibility allows the DSP to optimize each port separately
during modem training.
Alternate Part
• ISL1591 Class AB VDSL Driver
The device is supplied in a thermally-enhanced small footprint
(4mmx4mm) 24 lead QFN package. The ISL1561 is specified
for operation over the full -40°C to +85°C industrial
temperature range and is Pb-free RoHS compliant.
+14V
900
SCLK
8b CLASS AB
800
CPP
SERIAL
BIAS
SDATA
CS
INTERFACE
CURRENT
SETTING
CPSW
CMM
700
POWER MANAGEMENT
17a CLASS AB
600
CMSW
500
400
SWITCH SIGNAL
BOTH PORTS
BOOST
SUPPLY
RAILS OF
LINE DRIVERS
8b CLASS G
300
200
100
0
AFE
OUTPUT OF
DRIVER
ANALOG
INPUT
CLASS
AB
DRIVER
17a CLASS G
INP
OUT
1 OF 2
PORTS
2
4
6
8
10
12
14
16
18
20
Tx POWER (dBm)
FIGURE 1. BLOCK DIAGRAM
FIGURE 2. CLASS G+ vs CLASS AB DRIVER TOTAL POWER
February 26, 2013
FN7941.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL1561
Pin Configuration
ISL1561
(24 LD QFN)
TOP VIEW
INPA
INPB
1
2
3
4
5
6
VSP
18
17
CPSW
VCMAB
VCMCD
INPC
16 CPP
THERMAL
PAD
CMM
CMSW
GND
15
14
13
INPD
THERMAL PAD CONNECTS TO GROUND
Pin Descriptions
ISL1561
PIN
(24 Ld QFN)
NAME
FUNCTION
1
2
INPA
INPB
VCMAB
VCMCD
INPC
INPD
CS
Amplifier A non-inverting input
Amplifier B non-inverting input
3
Input common mode bias for port AB
Input common mode bias for port CD
Amplifier C non-inverting input
Amplifier D non-inverting input
Chip select, low enables data input to logic
Serial clock input
4
5
6
7
8
SCLK
FBD
9
Feedback pin for amplifier D
Amplifier D output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OUTD
OUTC
FBC
Amplifier C output
Feedback pin for amplifier C
Ground
GND
CMSW
CMM
CPP
Internal negative boost supply
Internal negative supply
Internal positive supply
Internal positive boost supply
Positive supply voltage
CPSW
VSP
FBB
Feedback pin for amplifier B
Amplifier B output
OUTB
OUTA
FBA
Amplifier A output
Feedback pin for amplifier A
Serial data write
SDATA
BOOST
Class G control input
FN7941.1
February 26, 2013
2
ISL1561
VSP
1µF
CPP
CPSW
POWER
CONTROL
INP
0.1µF
+
OUTPUT
POSITIVE
SUPPLY
3.5kΩ
OUT
5.1Ω
¼
ISL1561
-
+VSP
1:1.4
Rf
1.33kΩ
Rc
100kΩ
Rp
1.78kΩ
VCM
AFE
FB
FB
Rg
733Ω
100Ω
LINE
Rc
100kΩ
0.1µF
Rp
1.78kΩ
Rf
1.33kΩ
-
OUT
¼
5.1Ω
ISL1561
3.5kΩ
OUTPUT
NEGATIVE
SUPPLY
INP
0.1µF
+
BOOST
CONTROL
CLASS G
CONTROL
ISP
ADJUST
LOGIC
ISP PORT
CONTROL
POWER
CONTROL
SPI
CMM
CMSW
GND
1µF
TYPICAL DIFFERENTIAL I/O LINE DRIVER (1 OF 2 PORTS)
FIGURE 3. CONNECTION DIAGRAM
Ordering Information
OPERATING AMBIENT
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL1561IRZ
15 61IRZ
15 61IRZ
-40 to +85
-40 to +85
24 Ld QFN
24 Ld QFN
L24.4x4H
L24.4x4H
ISL1561IRZ-T13 (Note 1)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1561. For more information on MSL please see tech brief TB363.
FN7941.1
February 26, 2013
3
ISL1561
Thermal Information
Absolute Maximum Ratings (TA = +25°C)
V + Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Thermal Resistance (Typical)
24 Ld QFN Package (Notes 4, 5)
θ
JA (°C/W)
44
θ
JC (°C/W)
S
Driver V + Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V +
5
IN
S
SPI and Boost Pin Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Performance Curve
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
V
Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V +
CM
S
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8mA
Continuous Output Current for Long Term Reliability. . . . . . . . . . . . . . . . .50mA
ESD Rating
Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . .1.5kV
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications V = +14V, R
= 51Ω differential (emulating transformer input load), Refer to Figure 3, T = +25°C. Ports
A
SP
L-DIFF
tested separately unless otherwise indicated.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 6) TYP (Note 6)
UNIT
AC PERFORMANCE
AV
Gain Across the Load, R = 5.1Ω
11.6
110
70
V/V
MHz
MHz
dB
B
BW
-3dB Bandwidth
I
I
= 14mA/port, V < 2V
O
S
S
PP-DIFF
PP-DIFF
= 10mA/port, V = 5V
O
Gain Flatness
Small Signal Gain Flatness
I
= 14mA/port, 17.6MHz
= 14mA/port, 30MHz
0.3
0.9
S
I
dB
S
SR
Slew Rate
2nd Harmonic
3rd Harmonic
THD
V
= 16V
(20% to 80%)
P-P-DIFF
560
1000
-95
-83
-83
-80
-75
-74
V/µs
dBc
dBc
dBc
dBc
dBc
dBc
dBc
OUT
200kHz Harmonic
Distortion
10mA/port, V
10mA/port, V
10mA/port, V
10mA/port, V
10mA/port, V
10mA/port, V
= 10V
OUT
OUT
OUT
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
= 10V
= 10V
= 10V
= 10V
= 10V
4MHz Harmonic
Distortion
2nd Harmonic
3rd Harmonic
THD
MBPR
Average Missing-Band Power Ratio
26kHz to 8MHz, 5kHz Tone Spacing,
= 19.5dBm, VDSL2+ 8b, US1
-64
P
LINE
e
Output Voltage Noise
f = 1MHz, differential each port
f = 1MHz
110
190
nV/ Hz
√
O
e
Common Mode Output Noise at each
Port Pair
nV/ Hz
√
O-CM
CONTROL FEATURES
V
V
Input High Voltage
Input Low Voltage
SCLK, SDATA, CS, BOOST inputs
SCLK, SDATA, CS, BOOST inputs
2.3
V
V
HIGH
LOW
0.8
-18
I
Input High Current for Pull-up Pins CS,
BOOST
V
= 3.3V
-28
40
-23
50
µA
HIGH
IN
I
Input High Current for Pull-down Pins
SCLK, SDATA
V
= 3.3V
60
µA
HIGH
IN
FN7941.1
February 26, 2013
4
ISL1561
Electrical Specifications V = +14V, R
= 51Ω differential (emulating transformer input load), Refer to Figure 3, T = +25°C. Ports
SP
L-DIFF
A
tested separately unless otherwise indicated.(Continued)
MIN
MAX
PARAMETER
LOW
DESCRIPTION
CONDITIONS
(Note 6) TYP (Note 6)
UNIT
µA
I
I
Input Low Current for Pull-up Pins CS,
BOOST
V
V
= 0V
= 0V
-88
-73
0
-58
IN
IN
Input Low Current for Pull-down Pins
SCLK, SDATA
-0.2
+0.2
µA
LOW
SUPPLY CHARACTERISTICS
V
V
V
V
V
Operating Supply Voltage
+10
+14
7
+14.7
V
V
S
Voltage on the CPP Pin
BOOST = 0V (Class AB)
BOOST = 0V (Class AB)
BOOST = 0V (Class AB)
BOOST = 0V (Class AB)
CPP
Maximum Voltage on the CPSW Pin
Voltage on the CMM Pin
14
7
V
CPSW
CMM
CMSW
V
Minimum Voltage on the CMSW Pin
Positive Supply Current per Port
0
V
I
All outputs at 0V, BOOST = 0V, SDATA = 8’h7F
for Registers 3 and 7
17.5
9.8
6.8
2.0
19.5
21.5
10.8
7.6
mA
SP
All outputs at 0V, BOOST = 0V, SDATA = 8’h1C
for Registers 3 and 7
10.3
7.2
mA
mA
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h0F
for Registers 3 and 7
I
(Power-down)
Supply Current per Port
All outputs at 0V, BOOST = 0V, SDATA = 8’h80
for Registers 3 and 7
2.5
3.0
SP
OUTPUT CHARACTERISTICS
V
Loaded Output Swing High
(Single-ended to GND)
R = 51Ω, Class AB (see Figure 3)
11.9
12.4
1.6
V
V
OUT
L
Loaded Output Swing High
(Single-ended to GND)
R = 51Ω, Class AB (see Figure 3)
2.1
L
I
Linear Output Current
R = 10Ω, f = 100kHz, THD = -60dBc (5Ω
differential)
±360
18
mA
OL
L
V
V
Differential Output Offset Voltage
SDATA = 8’h1C
-125
6.85
+125
7.09
mV
mV
OS-DM
Common Mode Output Offset Voltage
SDATA = 8’h1C (Offset from input VCM)
OS-CM
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range at each of Class AB
+4.5
+9.5
V
the 4 Non-inverting Input Pins
CMRR
DC Common Mode Rejections for each
V
to Differential Mode Output (Input
66
40
74
dB
dB
dB
CM
Referred) I = 10mA/port
Port. V = +4.5V to +9.5V
CM
SP
V
to Common Mode Output (Output
CM
Referred) I = 10mA/port
SP
PSRR
DC Power Supply Rejections for each
Port to Differential Output (Input
Referred)
+V = +7V to +14V, GND = 0V, I = 10mA/port
S
SP
DC Power Supply Rejections for each
Port to Common Mode Output (Output
Referred)
+V = +7V to +14V, GND = 0V, I = 10mA/port
55
dB
S
SP
RIN
Input Resistance
Differential
5.0
6.0
0.1
7.1
10
kΩ
DIGITAL
f
Clock Frequency
MHz
CLK
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7941.1
February 26, 2013
5
ISL1561
Typical Performance Curves
V
= +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), R
= 51Ω,
CC
LOAD
T = +25°C, Unless otherwise noted.
A
9
9
V
= 0.5V
P-P
10mA/PORT
O
V
= 1V
P-P
O
V
= 2V
P-P
6
3
6
3
O
8mA/PORT
14mA/PORT
10mA/PORT
12mA/PORT
0
0
V
= 5V
P-P
O
-3
-6
-9
-3
-6
-9
V
= 10V
O
P-P
10M
10M
FREQUENCY (Hz)
1M
100M
1G
1M
100M
1G
FREQUENCY (Hz)
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE vs BIAS CURRENT
FIGURE 5. LARGE SIGNAL FREQUENCY RESPONSE
9
9
6
3
0
10mA/PORT
V
= 0.5V
P-P
O
C
= 5.6pF
L
6
3
C
= 39pF
L
8mA/PORT
C
= 15pF
L
14mA/PORT
C
= 27pF
L
0
-3
-3
-6
-6
-9
10mA/PORT
12mA/PORT
10M
FREQUENCY (Hz)
1M
100M
1G
1M
100k
10M
FREQUENCY (Hz)
100M
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs C
FIGURE 7. COMMON MODE SMALL SIGNAL RESPONSE vs BIAS
CURRENT
LOAD
700
-50
700
CF = 6.56V/V
600
500
400
300
200
100
0
-55
-60
-65
-70
-75
-80
600
8MHz PROFILE (10mA/PORT)
Pd (mW)
500
17MHz (12mA/PORT)
400
MBPR (dBc)
300
ADSL2 SMARTG (8mA/PORT)
200
8
10
12
14
16
18
20
10
11
12
13
14
15
16
17
18
19
20
LINE POWER (dBm)
LINE POWER (dBm)
FIGURE 8. POWER CONSUMPTION vs LINE POWER
FIGURE 9. VDSL2+ 8b Avg. MBPR US1 vs LINE POWER
FN7941.1
February 26, 2013
6
ISL1561
Typical Performance Curves
V
= +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), R
= 51Ω,
CC
LOAD
T = +25°C, Unless otherwise noted. (Continued)
A
-30
-40
fc = 4MHz
10mA/PORT
V
= 2V
V
= 2V
O
P-P
O
P-P
-40
-50
-50
-60
3RD HD
-60
3RD HD
-70
-70
-80
-80
-90
-90
2ND HD
14
2ND HD
-100
-100
1M
100k
10M
8
10
12
16
18
20
FREQUENCY (Hz)
BIAS CURRENT(mA)
FIGURE 10. HARMONIC DISTORTION vs FREQUENCY
FIGURE 11. HARMONIC DISTORTION vs BIAS CURRENT
-50
-60
-65
-70
-75
-80
-85
-90
10mA/PORT
fc = 4MHz
10mA/PORT
fc = 4MHz
-55
-60
-65
-70
-75
-80
-85
-90
V
= 2V
O
P-P
3RD HD
3RD HD
2ND HD
9
2ND HD
1
3
5
7
11
13
15
25
50
75
100
125
DIFFERENTIAL OUTPUT VOLTAGE (V
)
P-P
R
(Ω)
LOAD
FIGURE 13. HARMONIC DISTORTION vs OUTPUT AMPLITUDE
FIGURE 12. HARMONIC vs R
LOAD
1000
1000
100
10
100
10
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 14. DIFFERENTIAL OUTPUT VOLTAGE NOISE
FIGURE 15. COMMON MODE OUTPUT VOLTAGE NOISE
FN7941.1
February 26, 2013
7
ISL1561
Typical Performance Curves
V
= +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), R
= 51Ω,
CC
LOAD
T = +25°C, Unless otherwise noted. (Continued)
A
-20
-60
10mA/PORT
10mA/PORT
-30
-40
-70
-80
CHANNEL AB -> CD
-50
-60
-90
CHANNEL CD -> AB
-70
-80
-100
-110
-120
-90
-100
1M
1M
100k
10M
FREQUENCY (Hz)
100M
100k
10M
FREQUENCY (Hz)
100M
FIGURE 16. CHANNEL-TO-CHANNEL CROSSTALK
FIGURE 17. OFF-ISOLATION
SDATA
OUTA
SDATA
OUTA
t
= 600ns
t
= 1.6µs
EN
DIS
FIGURE 19. DISABLE RESPONSE
FIGURE 18. ENABLE RESPONSE
25
20
15
10
5
0
0
20
40
60
80
100
120
140
Iq CODE
FIGURE 20. QUIESCENT CURRENT PER PORT vs CODES
FN7941.1
February 26, 2013
8
ISL1561
Typical Performance Curves
V
= +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), R
= 51Ω,
CC
LOAD
T = +25°C, Unless otherwise noted. (Continued)
A
45
40
11.70
11.65
I
= ‘7F’
35
30
25
20
15
10
5
q
11.60
GAIN
11.55
11.50
11.45
11.40
I
= ‘1C’
q
0
-40
-40
-20
0
20
40
60
80
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. QUIESCENT CURRENT vs TEMPERATURE
FIGURE 22. GAIN AT LOAD vs TEMPERATURE
1100
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
10V
P-P
1080
1060
1040
1020
1000
980
3RD HD
SR
960
940
2ND HD
920
900
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 24. 4MHz HARMONIC DISTORTION vs TEMPERATURE
FIGURE 23. SLEW RATE vs TEMPERATURE
14
12
10
8
8
7
HIGH SWING
CM
6
5
4
3
6
DM
4
2
LOW SWING
2
1
0
0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. OUTPUT SWING vs TEMPERATURE
FIGURE 26. OUTPUT OFFSET CM AND DM vs TEMPERATURE
FN7941.1
February 26, 2013
9
ISL1561
General Description
Digital Interface
The ISL1561 is a class G amplifier designed to reduce power
consumption in ADSL2+ and VDSL2 applications compared to
class AB. With the high PAR used for xDSL signals, a supply
voltage of +14V can be used for the majority of the small
amplitude cycles while boosting to a supply voltage of +28V can
be used for the few high amplitude cycles.
A 12-bit serial port interface is used to program ISL1561. The
first bit defines the write (1’b1) and read (1’b0) operation to the
register. The following 3-bit calls the registers. The last 8-bit
programs the registers. Default start-up for ISL1561 is in disable
mode with boost and CS pins having internal pull ups and SCLK
and SDATA pins having internal pull downs. ISL1561 can only be
programmed through the SPI when CS is set low.
Register Listing
ADDRESS
FUNCTION
BIT
[7]
DESCRIPTION
3’h3
Setting of quiescent current of port AB
Boost disable
[6:0]
[7]
Program quiescent current of port AB.
Boost disable
3’h7
Setting of quiescent current of port CD
[6:0]
Program quiescent current of port CD.
0
1
2
3
SCLK
Z-HI
Z-HI
ADDR[0:2]
W/R
D[0] D[1] D[2]
D[5]
D[3] D[4]
D[6] D[7]
SDATA
CS
CURRENT SETTING VALUE
FIGURE 27. 12 BITS SERIAL ADDRESSING DIAGRAM
t
HC
CS
t
SC
t
t
t
f
r
t
SC
SCLK
t
t
HD
t
w
SD
SDATA
BN
B(N-1)
B(N-2)
B1
B0
MSB
t
LSB
LOAD LSB FIRST, MSB LAST
FIGURE 28. 12 BITS SERIAL ADDRESSING DIAGRAM
FN7941.1
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ISL1561
TABLE 1. SERIAL TIMING DIAGRAM
PARAMETER
t
RECOMMENDED OPERATING RANGE
DESCRIPTION
Clock Period
≥100ns
0.05*t
≥7ns
t /t
Clock Rise/Clock Fall
Data Hold Time
Data Setup Time
CS Hold Time
r
f
t
t
t
HC
≥10ns
≥2.8ns
≥0.5ns
0.50*t
SD
HC
t
CS Setup Time
SC
t
Clock Pulse Width
W
Boost Control
Table 2 summarizes the logic of register MSB on boost operations followed by Figure 29 with the recommended look ahead timing for
the boost signal.
TABLE 2. REGISTER MSB ON BOOST OPERATION
Reg3 8’h[7]
Reg7 8’h[7]
BOOST PIN
BOOST OPERATION
0
X
0
1
X
1
1
X
0
1
1
0
0
X
1
X
NOTE: X = do not care
SIGNAL
t
d
BOOST
FIGURE 29. SERIAL TIMING DIAGRAM
TABLE 3. EXTERNAL BOOST SIGNAL TIMING PARAMETERS
RECOMMENDED OPERATING RANGE
100ns
PARAMETER
DESCRIPTION
t
Look ahead boost
d
FN7941.1
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ISL1561
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7941.1
CHANGE
January 24, 2013
November 21, 2012
Changed MIN/MAX specs for “Differential Output Offset Voltage” on page 5 from -75/75mV to -125/125mV.
Added resistor values to Figure 3 on page 3.
Edited table heading for columns 1 and 2 in Table 2 on page 11.
October 5, 2012
FN7941.0
Initial Release.
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FN7941.1
February 26, 2013
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ISL1561
Package Outline Drawing
L24.4x4H
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 09/11
2.50
4.00
A
0.50
20X
1
B
6
24
19
PIN #1 INDEX AREA
6
18
PIN 1
INDEX AREA
Exp. DAP
2.50 ±0.05 Sq.
2.50
6
13
0.15
(4X)
C A B
0.10 M
7
12
4
24X 0.25 +0.07
-0.05
TOP VIEW
24X 0.40 ±0.10
0.25 min (4 sides)
BOTTOM VIEW
SEE DETAIL "X"
5
C
0 . 2 REF
C
0.10
C
0.90 ±0.10
SEATING PLANE
0.08 C
0 . 00 MIN.
0 . 05 MAX.
SIDE VIEW
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
( 20X 0.50)
( 3.80 )
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
( 2.50 )
Tiebar shown (if present) is a non-functional feature.
5.
6.
(24X .25)
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
( 24 X 0.60)
7. Compliant to JEDEC MO-220 VGGD-8
TYPICAL RECOMMENDED LAND PATTERN
FN7941.1
February 26, 2013
13
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