ISL12058IBZ [INTERSIL]
Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar; 低成本和低功耗的I2C总线™实时时钟/日历
| 型号： | ISL12058IBZ |
| 厂家： | 
Intersil |
| 描述： | Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar |
| 文件： | 总19页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL12058
®
2
Low Cost and Low Power I C-Bus™ Real Time Clock/Calendar
Data Sheet
June 15, 2009
FN6756.0
Low Power and Low Cost RTC with Alarm
Function
Features
• Real Time Clock/Calendar
The ISL12058 device is a low power real time clock with
clock/calendar, and alarm function.
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Date, Month, and Year
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
• 4 Selectable Frequency Outputs
• 2 Alarms
- Settable to the Second, Minute, Hour, Day of the Week,
Date, or Month
2
• I C Interface
- 400kHz Data Transfer Rate
• Small Package Options
Pinouts
- 8 Ld 2mmx2mm µTDFN Package
- 8 Ld 3mmx3mm TDFN Package
- 8 Ld MSOP Package
ISL12058
(8 LD SOIC, MSOP)
TOP VIEW
- 8 Ld SOIC Package
X1
X2
1
2
3
4
8
7
6
5
V
DD
- Pb-Free (RoHS Compliant)
IRQ/F
SCL
OUT
• Low Cost 3V Alternative to ISL1208 and ISL12082
NC
Applications
GND
SDA
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
ISL12058
(8 LD 2x2 µTDFN, 8 LD 3x3 TDFN)
TOP VIEW
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
X1
V
DD
1
2
3
4
8
7
6
5
X2
NC
IRQ/F
SCL
OUT
GND
SDA
• Point Of Sale Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
2
I C-bus™ All other trademarks mentioned are the property of their respective owners.
ISL12058
.
Ordering Information
PART
NUMBER
PART
MARKING
V
RANGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
DD
ISL12058IBZ (Note 1)
12058 IBZ
1.4 to 3.6
1.4 to 3.6
-40 to +85
-40 to +85
8 Ld SOIC
M8.15
ISL12058IBZ-T* (Note 1) 12058 IBZ
8 Ld SOIC (Tape and Reel)
M8.15
ISL12058IUZ (Note 1)
12058
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Ld MSOP
M8.118
M8.118
L8.3x3I
L8.3x3I
L8.2x2
ISL12058IUZ-T* (Note 1) 12058
ISL12058IRTZ (Note 1) 2058
ISL12058IRTZ-T* (Note 1) 2058
ISL12058IRUZ-T* (Note 2) 058
8 Ld MSOP (Tape and Reel)
8 Ld TDFN
8 Ld TDFN (Tape and Reel)
8 Ld µTDFN (Tape and Reel)
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
SDA
SECONDS
MINUTES
HOURS
SDA
SCL
BUFFER
2
I C
RTC
CONTROL
LOGIC
INTERFACE
SCL
BUFFER
DAY OF WEEK
DATE
X1
X2
CRYSTAL
OSCILLATOR
RTC
DIVIDER
MONTH
YEAR
V
DD
POR
FREQUENCY
OUT
ALARM1
ALARM2
CONTROL
REGISTERS
F
/
OUT
IRQ
INTERNAL
SUPPLY
FN6756.0
June 15, 2009
2
ISL12058
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
2
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
3
4
5
NC
No Connection. Can be connected to GND or left floating.
Ground
GND
SDA
Serial Data (SDA) is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
6
7
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device.
IRQ/F
OUT
Interrupt Output /Frequency Output is a multi-functional pin that can be used as alarm interrupt or frequency output
pin. The function is set via the configuration register. This pin is open drain and requires an external pull-up resistor. It
has a default output of 32.768kHz at power-up.
8
V
Power supply
DD
FN6756.0
June 15, 2009
3
ISL12058
Absolute Maximum Ratings
Thermal Information
Voltage on V
DD
Pin (respect to GND) . . . . . . . . . . . . . . . -0.2V to 4V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JC
JA
8 Lead SOIC (Note 3) . . . . . . . . . . . . .
8 Lead MSOP (Note 3). . . . . . . . . . . . .
8 Lead µTDFN (Note 3) . . . . . . . . . . . .
8 Lead TDFN (Notes 4, 5) . . . . . . . . . .
120
169
160
52
N/A
N/A
N/A
7
Voltage on IRQ/F
OUT ,
SCL and SDA Pins
(respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 6V
Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . -0.2V to 4V
ESD Rating ((Per MIL-STD-883 Method 3014)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
DC Operating Characteristics – RTC Temperature = -40°C to +85°C unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
Main Power Supply
CONDITIONS
(Note 8) (Note 7) (Note 8) UNITS
NOTES
V
1.8
1.4
3.6
1.8
950
V
DD
V
Timekeeping Power Supply
Standby Supply Current
V
DDT
I
I
I
V
V
V
V
V
= 3.6V
600
500
400
350
15
nA
nA
nA
nA
µA
6, 12
6, 12
6
DD1
DD
DD
DD
DD
DD
= 3.0V
= 1.8V
= 1.4V
= 3.6V
Timekeeping Current
650
40
DD2
DD3
2
Supply Current With I C Active at
Clock Speed of 400kHz
I
Input Leakage Current on SCL
I/O Leakage Current on SDA
-100
-100
100
100
nA
nA
LI
I
LO
IRQ/F
OUT
V
Output Low Voltage
V
= 1.8V, I = 3mA
OL
0.4
V
OL
DD
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.
MIN
(Note 8)
MAX
TYP (Note 7) (Note 8) UNITS NOTES
SYMBOL
PARAMETER
TEST CONDITIONS
SERIAL INTERFACE SPECS
V
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x V
5.5
V
V
IL
DD
V
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V
DD
IH
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.04 x V
V
DD
V
Maximum Pull-up Voltage on SDA
during I C Communication
V
+ 2
DD
V
11
PULLUP
2
V
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
> 1.8V, V
DD PULLUP
= 5.0V
0
0.4
V
OL
Cpin
SDA and SCL Pin Capacitance
T
V
= +25°C, f = 1MHz, V
= 5V,
DD
10
pF
kHz
9, 10
A
= 0V, V = 0V
OUT
IN
f
SCL Frequency
400
SCL
FN6756.0
June 15, 2009
4
ISL12058
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
MAX
SYMBOL
PARAMETER
Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs spec is suppressed
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of
Data Valid , until SDA exits the 30% to
TEST CONDITIONS
(Note 8)
TYP (Note 7) (Note 8) UNITS NOTES
t
50
ns
IN
t
900
ns
11
AA
V
DD
70% of V
window
DD
t
Time the Bus Must be Free Before SDA crossing 70% of V during a
the Start of a New Transmission
1300
ns
BUF
DD
STOP condition, to SDA crossing
70% of V during the following
DD
START condition
t
Clock LOW Time
Measured at the 30% of V
crossing
1300
600
600
600
ns
ns
ns
ns
LOW
DD
DD
t
Clock HIGH Time
Measured at the 70% of V
crossing
HIGH
t
START Condition Setup Time
START Condition Hold Time
SCL rising edge to SDA falling
edge. Both crossing 70% of V
SU:STA
HD:STA
DD
From SDA falling edge crossing
30% of V to SCL falling edge
t
DD
crossing 70% of V
DD
From SDA exiting the 30% to 70%
of V window, to SCL rising edge
t
Input Data Setup Time
Input Data Hold Time
100
0
ns
ns
ns
ns
ns
SU:DAT
HD:DAT
SU:STO
HD:STO
DD
crossing 30% of V
DD
From SCL falling edge crossing
30% of V to SDA entering the
t
900
DD
30% to 70% of V
window
DD
From SCL rising edge crossing
70% of V , to SDA rising edge
t
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
600
600
0
DD
crossing 30% of V
DD
t
From SDA rising edge to SCL
falling edge. Both crossing 70% of
V
DD
From SCL falling edge crossing
30% of V , until SDA enters the
t
DH
DD
30% to 70% of V
window
DD
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
From 70% to 30% of V
20 + 0.1 x Cb
300
300
400
ns
ns
pF
kΩ
9, 10
9, 10, 11
9, 10
R
DD
DD
t
20 + 0.1 x Cb
F
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
1
Rpu
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by t and
9, 10
R
t .
F
For Cb = 400pF, max is about
2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ
to ~20kΩ
NOTES:
6. IRQ/F
inactive.
OUT
7. Typical values are for T = +25°C and 3.3V supply voltage.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9. Limits should be considered typical and are not production tested.
2
10. These are I C specific parameters and are not production tested, however, they are used to set conditions for testing devices to
validate specification.
2
limit but the t and t in the I C parameters are not guaranteed.
11. Parts will work with SDA pull-up voltage above the V
12. Specified at +25°C.
PULLUP
AA
F
FN6756.0
June 15, 2009
5
ISL12058
SDA vs SCL Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
HD:DAT
t
SU:STA
SU:STO
t
HD:STA
SDA
(INPUT TIMING)
t
t
BUF
DH
t
AA
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
5.0V
= 3.0V
DD
FOR V = 0.4V
OL
1533Ω
AND I
OL
= 3mA
SDA,
IRQ/F
OUT
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
= 3.0V, V
= 5.0V
DD
PULLUP
FN6756.0
June 15, 2009
6
ISL12058
Typical Performance Curves Temperature is +25°C unless otherwise specified
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.8
0.6
0.4
0.2
3.6
3.0
1.8
1.4
1.4
1.9
2.4
V
2.9
3.4
-40
-20
0
20
40
60
80
(V)
TEMPERATURE (°C)
DD
FIGURE 2. I
DD1
vs V
DD
FIGURE 3. I
vs TEMPERATURE
DD1
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
32769.0
32768.8
32768.6
32768.4
32768.2
32768.0
32767.8
32767.6
32767.4
32767.2
32767.0
32768Hz
8192Hz
4096Hz
1Hz
1.4
1.9
2.4
V
2.9
3.4
1.4
1.9
2.4
V
2.9
3.4
(V)
(V)
DD
DD
FIGURE 4. I
DD
vs V
vs F
FIGURE 5. F
OUT
vs V
WITH A TYPICAL 32.768kHZ CRYSTAL
DD
DD
OUT
Pin Descriptions
General Description
The ISL12058 device is a low power real time clock with
clock/calendar, and alarm.
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the ISL12058 to supply a timebase for the real
time clock. Refer to Figure 6.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The device can also be driven directly from a 32.768kHz
square wave source with peak to peak voltage from 0V to
VDD at X1 pin with X2 pin floating.
The ISL12058's flexible alarm can be set to any
clock/calendar value for a match. For example, every
minute, every Tuesday or at 5:23 AM on March 21. The
alarm status is available by checking the Status Register, or
the device can be configured to provide a hardware interrupt
X1
X2
via the IRQ/F
OUT
pin.
FIGURE 6. RECOMMENDED CRYSTAL CONNECTION
FN6756.0
June 15, 2009
7
ISL12058
IRQ/F
(Interrupt Output/Frequency Output)
Accuracy of the Real Time Clock
OUT
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/F mode is selected via
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer.
OUT
the IRQE bit of the control register (address 08h). The
IRQ/F is an open drain output and requires the use of a
OUT
pull-up resistor, and it can accept a pull-up voltage up to
5.5V.
This pin has a default output of 32.768kHz at power-up.
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action.
Alarm Interrupt
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I C bus.
The alarm interrupt mode is enabled by setting IRQE bit to
‘1’ with Alarm1 enables by setting ALM1E to ‘1’.
2
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs, the
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the
device. The input buffer on this pin is always active (not gated).
The SCL pin can accept a logic high voltage up to 5.5V.
IRQ/F
pin will be pulled low and the alarm interrupt bit
OUT
(A1F) will be set to “1”.
NOTE: The A1F bit can be reset by the user or cleared automatically
using the Auto Reset mode (see ARST bit, address 07h). Alarm2
does not have hardware interrupt function.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
Frequency Output Mode
The ISL12058 has the option to provide a frequency output
signal using the IRQ/F
pin. The frequency output mode
OUT
An open drain output requires the use of a pull-up resistor,
and it can accept a pull-up voltage up to 5.5V. The output
circuitry controls the fall time of the output signal with the use
of a slope controlled pull-down. The circuit is designed for
is set by using the FO bits to select 4 possible output
frequency values from 1Hz to 32.768kHz. The IRQE bit must
be set to ‘0’ for frequency output.
2
I C Serial Interface
2
400kHz I C interface speeds.
2
The ISL12058 has an I C serial bus interface that provides
NOTE: Parts will work with SDA pull-up voltage above the V
PULLUP
access to the real time clock registers, control and status
2
limit but the t and t in the I C parameters are not guaranteed.
AA
F
2
registers and the alarm registers. The I C serial interface is
2
V
, GND
DD
compatible with other industry I C serial bus protocols using
a bi-directional data signal (SDA) and a clock signal (SCL).
Chip power supply and ground pins. The device will have full
operation with a power supply from 1.8V to 3.6V, and
timekeeping function with a power supply from 1.4V to 3.6V.
Register Descriptions
The registers are accessible following a slave byte of
“1101111x” and reads or writes to addresses [00h:1Fh]. The
defined addresses and default values are described in
Table 1. Address 15h to 1Fh are not used. Reads or writes to
15h to 1Fh will not affect operation of the device but should
be avoided. For Page Write and Page Read operation, the
address will wrap around from address 1Fh to 00h.
A 0.1µF decoupling capacitor is recommended on the V
DD
pin to ground.
NC (No Connection)
The NC pin is not connected to the die. The pin can be
connected to GND or left floating.
REGISTER ACCESS
Functional Description
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz
crystal to maintain an accurate internal representation of
second, minute, hour, day of week, date, month, and year. The
RTC also has leap-year correction. The RTC also corrects for
months having fewer than 31 days and has a bit that controls
24 hour or AM/PM format. When the ISL12058 powers up after
The registers are divided into 3 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (2 bytes): Address 07h to 08h.
3. Alarm1 and Alarm2 (9 bytes): Address 0Ch to 14h.
There are no addresses above 1Fh.
the loss of V , the clock will not begin incrementing until at
DD
least one byte is written to the clock register.
FN6756.0
June 15, 2009
8
ISL12058
TABLE 1. REGISTER MEMORY MAP
BIT
REG
REG
ADDR. SECTION
NAME
7
0
6
5
SC21
MN21
HR21
DT21
0
4
SC20
MN20
HR20
DT20
MO20
YR20
0
3
SC13
MN13
HR13
DT13
MO13
YR13
0
2
1
0
RANGE DEFAULT
00h
01h
02h
SC
MN
SC22
SC12
MN12
HR12
DT12
MO12
YR12
DW12
A1F
IRQE
0
SC11
MN11
HR11
DT11
MO11
YR11
DW11
A2F
0
SC10
MN10
HR10
DT10
MO10
YR10
DW10
PF
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 99
0 to 6
N/A
00h
00h
00h
01h
01h
00h
00h
09h
18h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0
MN22
HR
MIL
0
0
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
RTC
DT
0
MO
0
0
YR
YR23
0
YR22
YR21
0
DW
0
Status
SR
ARST
0
XSTOP
0
WRTC
FO1
0
OSF
FO0
0
Control
INT
ALM1E
ALM2E
0
A1E
0
N/A
Not Used
Not Used
Not Used
A1SC
A1MN
A1HR
A1DT
A1MO
A1DW
A2MN
A2HR
A2DW/DT
0
0
0
0
0
N/A
0
0
0
0
0
0
0
N/A
0
0
0
0
0
0
0
N/A
A1M1
A1M2
A1M3
A1M4
A1M5
A1M6
A2M2
A2M3
A2M4
A1SC22 A1SC21 A1SC20 A1SC13 A1SC12 A1SC11 A1SC10 00 to 59
A1MN22 A1MN21 A1MN20 A1MN13 A1MN12 A1MN11 A1MN10 00 to 59
A1MIL
A1HR21 A1HR20 A1HR13 A1HR12 A1HR11 A1HR10 0 to 23
A1DT21 A1DT20 A1DT13 A1DT12 A1DT11 A1DT10 1 to 31
Alarm1
Alarm2
0
0
0
0
0
A1MO20 A1MO13 A1MO12 A1MO11 A1MO10 1 to 12
A1DW12 A1DW11 A1DW10 0 to 6
0
0
A2MN22 A2MN21 A2MN20 A2MN13 A2MN12 A2MN11 A2MN10 00 to 59
A2MIL A2HR21 A2HR20 A2HR13 A2HR12 A2HR11 A2HR10 0 to 23
A2DW/DT A2DT21 A2DT20 A2DT13 A2DT12 A2DT11 A2DT10 1 to 31
A2DW12 A2DW11 A2DW10
0 to 6
Address 09h to 0Bh and 15h to 1Fh are not used. Reads or
writes to these registers will not affect operation of the
device but should be avoided.
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR,DW, DT, MO, YR)
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC registers, the read instruction
latches all clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read will not result in the output of data from the memory
array. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read
or write instruction, the address remains at the previous
address +1 so the user can execute a current address read
and continue reading the next register.
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h)
can either be a 12-hour or 24-hour mode, DT (Date, address
03h) is 1 to 31, MO (Month, address 04h) is 1 to 12, YR
(Year, address 06h) is 0 to 99, and DW (Day of the Week,
address 06h) is 0 to 6.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
.
FN6756.0
June 15, 2009
9
ISL12058
24 HOUR TIME
ALARM2 INTERRUPT BIT (A2F)
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
These bits announce if the Alarm2 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
OSCILLATOR FAIL BIT (OSF)
If the A1HR and/or A2HR registers are used for alarm
interrupt, the A1HR and/or A2HR registers must set to the
same hour format as the HR register. For example, if the HR
register is set to 24-hour format by setting the MIL bit to “1”,
then the AxHR register must be set to 24-hour format with
AxMIL bit set to “1”. If the hour format does not match
between the HR register and the AxHR register, then the
alarm interrupt will not trigger.
Oscillator Fail Indicator bit (OSF). This bit is set to a “1” when
there is no oscillation on X1 pin. The OSF bit can only be
reset by having an oscillation on X1 and manually reset to
“0” to reset it.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
CRYSTAL OSCILLATOR ENABLE BIT (XSTOP)
ISL12058 does not correct for the leap year in the year 2100.
This bit enables/disables the internal crystal oscillator. When
the XSTOP is set to “1”, the oscillator is disabled. The
XSTOP bit is set to “0” on power-up for normal operation.
Control and Status Registers
Addresses [07h to 0Bh]
AUTO RESET ENABLE BIT (ARST)
The Control and Status Registers consist of the Status
Register, Interrupt Register, and Alarm Registers.
This bit enables/disables the automatic reset of the A1F and
A2F status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
A1F and A2F bits.
Status Register (SR) [Address 07h]
The Status Register is located in the memory map at
address 0Bh. This is a volatile register that provides either
control or status of alarm interrupt and crystal oscillator
enable. Refer to Table 2.
Interrupt Control Register (INT) [Address 08h]
TABLE 2. STATUS REGISTER (SR)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
07h
7
6
5
0
0
4
3
2
1
0
ADDR
08h
Default
7
0
0
6
ALM1E
0
5
4
3
2
1
0
0
0
A1E
0
ARST XSTOP
WRTC OSF A1F A2F PF
ALM2E FO1 FO0 IRQE
Default
0
0
0
1
0
0
1
0
1
1
0
NOTE: read operation will remain set after the read operation is
complete.
ALARM1 INTERRUPT ENABLE BIT (A1E)
This bit enables the hardware interrupt function of ALARM1
to IRQ/F pin. When A1E set to ‘1’, IRQE set to ‘1’ and
POWER FAILURE BIT (PF)
OUT
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12058 internally) when
the device powers up after having lost power to the device.
On power-up after a total power failure, all registers are set
to their default states. The first valid write to the RTC section
after a complete power failure resets the PF bit to “0” (writing
one RTC register is sufficient).
ALM1E set to ‘1’, the IRQ/F
pin will pull low when the
OUT
A1F bit is set by the ALARM1 interrupt.
IRQ/F FUNCTION SELECTION BIT (IRQE)
OUT
This bit selects the function of the IRQ/F
Table 4 for function selection of IRQ/F
OUT
pin. Refer to
OUT
PIN.
TABLE 4. FUNCTION SELECTION OF IRQ/F
A1E AND IRQE BITS
PIN WITH
OUT
ALARM1 INTERRUPT BIT (A1F)
These bits announce if the Alarm1 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
A1E
0
IRQE
IRQ/F FUNCTION
OUT
0
1
F
OUT
0
High Impedance
FN6756.0
June 15, 2009
10
ISL12058
TABLE 4. FUNCTION SELECTION OF IRQ/F
A1E AND IRQE BITS (Continued)
PIN WITH
OUT
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS SELECTION
ALARM1
Interrupt
A1E
1
IRQE
IRQ/F
FUNCTION
A1M1 A1M2 A1M3 A1M4 A1M5 A1M6
OUT
0
1
F
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
Every Second
Match Second
Match Minute
Match Hour
Match Date
OUT
1
Alarm 1 Interrupt
FREQUENCY OUT CONTROL BITS (FO <1:0>)
These bits select the output frequency at the IRQ/F
IRQE must be set to “0” for frequency output at the
pin.
OUT
IRQ/F
OUT
pin. Refer to Table 5 for frequency selection.
Match Month
Match Day
TABLE 5. FREQUENCY SELECTION OF IRQ/F
OUT
PIN WITH
FO1 AND FO0 BITS
Match Second
and Minute
FREQUENCY,
FO1
FO0
F
(Hz)
COMMENT
OUT
1
1
0
1
1
1
0
0
0
0
0
0
Match Second
and Hour
1
1
0
0
1
0
1
0
32768
8192
4096
1
Free running crystal clock
Free running crystal clock
Free running crystal clock
Sync. at RTC write
Match Second,
Minute, and Hour
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
ALARM ENABLE BITS (ALM1E, ALM2E)
0
0
0
1
1
1
Match Date,
Month, and Day
This bit enables/disables the Alarm1 and Alarm2 function.
1
0
0
1
1
1
Match Second,
Date, Month, and
Day
When the ALM1E bit is set to “1”, the Alarm1 function is
enabled. When the ALM1E is cleared to “0”, the alarm function
is disabled. ALM1E bit is set to “0” at power-up.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
When the ALM2E bit is set to “1”, the Alarm2 function is
enabled. When the ALM2E is cleared to “0”, the alarm function
is disabled. ALM2E bit is set to “0” at power-up.
0
1
1
1
1
1
1
Match MInute,
Hour, Date,
Month, and Day
NOTE: The Alarm1 has hardware function via the IRQ/F
Alarm2 does not have hardware interrupt function.
pin.
OUT
1
1
1
1
1
Match Second,
MInute, Hour,
Date, Month, and
Day
Alarm1 Registers
Addresses [Address 0Ch to 11h]
The Alarm1 register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc) are used to make the
comparison. Note that there is no alarm byte for year. When
all the enable bits are set to “0” with ALM1E set to “1”, the
Alarm 1 will triggered once a second.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on January 1 at
11:30am.
A. Set Alarm1 registers as follows:
The Alarm1 function works as a comparison between the
Alarm1 registers and the RTC registers. As the RTC
advances, the Alarm1 will be triggered once a match occurs
between the Alarm1 registers and the RTC registers. Any
one Alarm1 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm1, the A1F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
FN6756.0
June 15, 2009
11
ISL12058
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
BIT
ALARM1
REGISTER 7
6
0
0
5
0
1
4
0
1
3
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
A2DW/DT A2M2 A2M3 A2M4
ALARM2 Interrupt
Every Minute (Second=00)
Match Minute
A1SC
A1MN
0
1
0
0
00h Seconds disabled
0
0
0
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
0
0
1
1
0
1
1
1
0
1
1
1
B0h Minutes set to 30,
enabled
A1HR
A1DT
A1MO
A1DW
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
91h Hours set to 11,
enabled
Match Hour
Match Date
81h Date set to 1,
enabled
Match Day
81h Month set to 1,
enabled
Match Minute and Hour
Match Minute and Date
Match Hour and Date
Match Minute, Hour, and Date
Match Minute and Hour
Match Minute and Day
Match Hour and Day
Match Minute, Hour, and Day
00h Day of week
disabled
B. Also the ALME bit must be set as follows:
BIT
CONTROL
REGISTER
7
6
5
4
3
2
1
0
HEX DESCRIPTION
INT
0
1
x
x
x
1
0
1
45h Enable Alarm1,
and Alarm1
Interrupt to
IRQ/F
OUT
Following is example of Alarm2 Interrupt.
xx indicate other control bits and these bit can be set to 0 or
1.
Example – A single alarm will occur on every Monday at
20:00 military time (Monday is when DW = 1).
After these registers are set, the Alarm1 interrupt will be
generated when the RTC advances to exactly 11:30am on
January 1 (after seconds changes from 59 to 00) by setting
the A1F bit in the status register to “1” and also bringing the
A. Set Alarm registers as follows:
BIT
ALARM2
REGISTER 7
6
0
1
5
0
1
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
IRQ/F
OUT
output low.
A2MN
A2HR
0
1
00h Minutes disabled
Alarm2 Registers
E0h Hours set to 20,
enabled
Addresses [Address 12h to 14h]
A2DW/DT
1
1
0
0
0
0
0
1
C1h DaysettoMonday,
enabled
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. Note that there are no alarm bytes for
second, month and year. When all the enable bits are set to
“0” with ALM2E set to “1”, the Alarm2 will triggered once a
minute when second hits “00”.
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
2
I C Serial Interface
The ISL12058 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12058 operates as a slave device in all applications.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
2
All communication over the I C interface is conducted by
sending the MSB of each byte of data first.
FN6756.0
June 15, 2009
12
ISL12058
operation or at the end of a write operation to memory only
Protocol Conventions
places the device in its standby mode.
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 7). On
power-up of the ISL12058, the SDA pin is in the input mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
8 bits. During the ninth clock cycle, the receiver pulls the SDA
line LOW to acknowledge the reception of the 8 bits of data
(see Figure 8).
2
All I C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH.
The ISL12058 continuously monitors the SDA and SCL lines
for the START condition and does not respond to any
command until this condition is met (see Figure 7). A START
condition is ignored during the power-up sequence.
The ISL12058 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12058 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (see Figure 7). A STOP condition at the end of a read
SCL
SDA
DATA
STABLE
DATA
CHANGE STABLE
DATA
START
STOP
FIGURE 7. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN6756.0
June 15, 2009
13
ISL12058
R/W BIT = “0”
SIGNALS FROM
THE MASTER
S
T
A
R
T
S
T
O
P
LAST DATA
BYTE
IDENTIFICATION
BYTE
ADDRESS
BYTE
FIRST DATA
BYTE
SIGNAL AT SDA
1 1 0 1 1 1 1 0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE ISL12058
A
C
K
A
C
K
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
Device Addressing
Write Operation
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs of the Slave Address Byte are
the device identifier bits, and the device identifier bits are
“1101111”.
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
2
ISL12058 responds with an ACK. At this time, the I C
interface enters a standby state.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 10).
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 11). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL12058 responds with an ACK. Then
the ISL12058 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 11).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12058 compares the device identifier bits with
“1101111”. Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Address Byte is a 1 byte register
address. The register address is supplied by the master
device. On power-up, the internal address counter is set to
address 0h, so a current address read of the RTC array
starts at address 0h. When required, as part of a random
read, the master must supply the 1 Word Address Bytes as
shown in Figure 11.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 1Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101111x” in both places.
SLAVE
ADDRESS BYTE
1
1
1
R/W
1
1
0
1
REGISTER
ADDRESS
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
DATA BYTE
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
FN6756.0
June 15, 2009
14
ISL12058
Application Section
R/W BIT = “1”
R/W BIT =“0”
S
T
A
R
S
SIGNALS
FROM THE
MASTER
S
T
O
P
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
A
C
K
A
C
K
ADDRESS
BYTE
R/W = 1
T
SIGNAL AT
SDA
1 1 0 1 1 1 1 0
1 1 0 1 1 1 1
1
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 11. MULTIPLE BYTES READ SEQUENCE
Figure 12 shows a suggested layout for the ISL12058 device
using a surface mount crystal. Two main precautions should
be followed:
Oscillator Crystal Requirements
The ISL12058 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used. Table 8
lists some recommended surface mount crystals and the
parameters of each. This list is not exhaustive and other
surface mount devices can be used with the ISL12058 if
their specifications are very similar to the devices listed.
The crystal should have a required parallel load capacitance
of 12.5pF and an equivalent series resistance of less than
50k. The crystal’s temperature range specification should
match the application. Many crystals are rated for -10°C to
+60°C (especially through-hole and tuning fork types), so an
appropriate crystal should be selected if extended
1. Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
2. Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide
termination for emitted noise in the vicinity of the RTC
device.
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
temperature range is required.
circuit. If the IRQ/F
pin is used as a clock, it should be
.
OUT
routed away from the RTC device as well. The traces for the
pins can be treated as a ground, and should be routed
TABLE 8. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER
Citizen
PART NUMBER
CM200S
V
DD
around the crystal.
MicroCrystal
Raltron
MS3V
RSM-200S
32S12
SaRonix
Ecliptek
ECPSM29T-32.768K
ECX-306
ECS
Fox
FSM-327
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies (such as
32.768kHz) are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
RTC circuit will avoid noise pickup and insure accurate
clocking.
FIGURE 12. SUGGESTED LAYOUT FOR ISL12058 AND
FN6756.0
June 15, 2009
15
ISL12058
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN6756.0
June 15, 2009
16
ISL12058
Package Outline Drawing
L8.2x2
8 Lead Ultra Thin Dual Flat No-Lead COL Plastic Package (UTDFN COL)
Rev 3, 11/07
2X
1.5
2.00
A
PIN #1 INDEX AREA
6
6
6X 0.50
PIN 1
INDEX AREA
B
1
4
7X 0.4 ± 0.1
1X 0.5 ±0.1
2.00
(4X)
0.15
8
5
0.10 M C A B
0.25 +0.05 / -0.07
TOP VIEW
4
BOTTOM VIEW
( 8X 0 . 25 )
SEE DETAIL "X"
( 1X 0 .70 )
0 . 55 MAX
C
0.10
BASE PLANE
SEATING PLANE
C
0.08
C
( 1 . 8 )
SIDE VIEW
0 . 2 REF
C
( 7X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
( 6X 0 . 5 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6756.0
June 15, 2009
17
ISL12058
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 6/09
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
C
0.10
C
Max 0.80
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
C
0 . 2 REF
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6756.0
June 15, 2009
18
ISL12058
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6756.0
June 15, 2009
19
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