ISL12030IBZ [INTERSIL]
Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction; 低功耗RTC与50/60周期的AC输入，报警和夏令修正
| 型号： | ISL12030IBZ |
| 厂家： | 
Intersil |
| 描述： | Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction |
| 文件： | 总18页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL12030
®
Real Time Clock with 50/60 Hz Clock and Alarms
Data Sheet
December 14, 2007
FN6617.0
Low Power RTC with 50/60 Cycle AC
Input, Alarms and Daylight Savings
Correction
Features
• 50/60 Cycle AC as a Primary Clock Input for RTC Timing
• Real Time Clock/Calendar
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
- Tracks Time in Hours, Minutes, Seconds and tenths of a
Second
- Day of the Week, Day, Month and Year
• Auto Daylight Saving Time Correction
The oscillator uses a 50/60 cycle sine wave input. The real
time clock tracks time with separate registers for hours,
minutes, and seconds. The calendar registers contain the
date, month, year, and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
- Programmable Forward and Backward Dates
• Dual Alarms with Hardware and Register Indicators
- Hardware Single Event or Pulse Interrupt Mode
• 128 Bytes of User SRAM
2
• I C Interface
- 400kHz Data Transfer Rate
Pinout
• Pb-free (RoHS compliant)
ISL12030
(8 LD SOIC)
TOP VIEW
Applications
• Utility Meters
NC
GND
AC
1
2
3
4
8
7
6
5
V
DD
• Control Applications
• Vending Machines
• White Goods
IRQ
SCL
SDA
NC
• Consumer Electronics
Ordering Information
PART NUMBER
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
(Note)
PART MARKING
12030 IBZ
V
RANGE
PKG DWG #
M8.15
DD
ISL12030IBZ*
2.7V to 5.5V
-40 to +85
8 Ld SOIC
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL12030
Block Diagram
SDA
SDA
SECONDS
MINUTES
HOURS
BUFFER
2
I C
INTERFACE
CONTROL
LOGIC
REGISTERS
SCL
SCL
BUFFER
DAY OF WEEK
DATE
RTC
DIVIDER
MONTH
V
INTERNAL
SUPPLY
DD
YEAR
ALARM
CONTROL
REGISTERS
USER
SRAM
IRQ
AC INPUT
BUFFER
AC
GND
Functional Pin Descriptions
PIN
NUMBER
SYMBOL
GND
DESCRIPTION
2
3
5
Ground.
AC Input. The AC input pin accepts either 50Hz of 60Hz AC 2.5V
AC
sine wave signal.
P-P
SDA
Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
6
7
SCL
IRQ
Serial Clock. The SCL input is used to clock all serial data into and out of the device.
Interrupt Output. Open Drain active low output. Interrupt output pin to indicate alarm is triggered.
Power supply.
8
V
DD
1, 4
NC
No Connection. Do not connect to any electrical circuit, power or ground.
FN6617.0
December 14, 2007
2
ISL12030
Absolute Maximum Ratings
Thermal Information
Voltage on V , SCL, SDA, AC, IRQ pins
DD
(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>2kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
120
JA
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
A
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Operating Specifications Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated.
DD
A
MIN
TYP
MAX
SYMBOL
PARAMETER
Main Power Supply
Supply Current
CONDITIONS
(Note 8) (Note 3) (Note 8)
UNITS
V
NOTES
V
2.7
5.5
60
45
75
DD
I
V
V
V
= 5V, SCL, SDA = V
= 3V, SCL, SDA = V
= 5V
27
16
43
µA
4
4
DD1
DD
DD
DD
DD
µA
DD
2
I
I
Supply Current (I C communications
active)
µA
2, 4
DD2
DD3
Supply Current for Timekeeping
at AC Input
V
= 5.5V at T = +25°C
9.0
18.0
µA
2, 4
DD
A
I
Input Leakage Current on SCL
I/O Leakage Current on SDA
1
1
µA
µA
LI
I
LO
IRQ (OPEN DRAIN OUTPUT)
Output Low Voltage
V
V
V
= 5V, I = 3mA
OL
0.4
0.4
V
V
OL
DD
DD
= 2.7V, I = 1mA
OL
Power-Down Timing Specifications apply for: V = 2.7 to 5.5V, T = -40°C to +85°C, unless otherwise stated.
DD
A
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 8) (Note 3) (Note 8)
UNITS
NOTES
V
V
Negative Slew Rate
DD
10
V/ms
6
DD SR-
2
I C Interface Specifications Specifications apply for: V = 2.7 to 5.5V, T = -40°C to +85°C,
DD
A
unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
(Note 3) (Note 8) UNITS NOTES
V
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x V
V
V
V
V
IL
DD
V
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V
V
+ 0.3
IH
DD
DD
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x V
DD
V
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
= 5V, I = 3mA
DD OL
0.4
OL
FN6617.0
December 14, 2007
3
ISL12030
2
I C Interface Specifications Specifications apply for: V = 2.7 to 5.5V, T = -40°C to +85°C,
DD
A
unless otherwise stated. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
= +25°C, f = 1MHz,
A
(Note 8)
(Note 3) (Note 8) UNITS NOTES
C
SDA and SCL Pin Capacitance
T
10
pF
PIN
V
= 5V, V = 0V,
DD
IN
V
= 0V
OUT
f
SCL Frequency
400
50
kHz
ns
SCL
t
Pulse Width Suppression Time at Any pulse narrower than the
IN
SDA and SCL Inputs
max spec is suppressed.
t
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of V , until SDA exits
DD
900
ns
AA
the 30% to 70% of V
DD
window.
t
Time the Bus Must be Free Before SDA crossing 70% of V
the Start of a New Transmission
1300
ns
BUF
DD
during a STOP condition, to
SDA crossing 70% of V
DD
during the following START
condition.
t
Clock LOW Time
Measured at the 30% of V
crossing.
1300
600
ns
ns
ns
LOW
DD
DD
t
Clock HIGH Time
Measured at the 70% of V
crossing.
HIGH
t
START Condition Setup Time
SCL rising edge to SDA
600
SU:STA
falling edge. Both crossing
70% of V
.
DD
t
t
START Condition Hold Time
Input Data Setup Time
From SDA falling edge
crossing 30% of V to SCL
600
100
0
ns
ns
ns
ns
HD:STA
DD
falling edge crossing 70% of
V
.
DD
From SDA exiting the 30% to
70% of V window, to SCL
SU:DAT
HD:DAT
SU:STO
HD:STO
DD
rising edge crossing 30% of
V
DD.
t
Input Data Hold Time
From SCL falling edge
crossing 30% of V to SDA
900
DD
entering the 30% to 70% of
window.
V
DD
t
STOP Condition Setup Time
From SCL rising edge
600
crossing 70% of V , to SDA
DD
rising edge crossing 30% of
V
.
DD
t
STOP Condition Hold Time
Output Data Hold Time
From SDA rising edge to
SCL falling edge. Both
600
0
ns
ns
crossing 70% of V
.
DD
t
From SCL falling edge
DH
crossing 30% of V , until
DD
SDA enters the 30% to 70%
of V
window.
DD
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
From 70% to 30% of V
20 + 0.1 x Cb
20 + 0.1 x Cb
10
300
300
400
ns
ns
pF
7
7
7
R
DD.
DD.
t
F
Cb
Capacitive loading of SDA or SCL Total on-chip and off-chip
FN6617.0
December 14, 2007
4
ISL12030
2
I C Interface Specifications Specifications apply for: V = 2.7 to 5.5V, T = -40°C to +85°C,
DD
A
unless otherwise stated. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
(Note 3) (Note 8) UNITS NOTES
R
SDA and SCL Bus Pull-up Resistor Maximum is determined by
Off-chip and t .
1
kΩ
7
PU
t
R
F
For Cb = 400pF, max is about
2kΩ.
For Cb = 40pF, max is about
15kΩ
NOTES:
2. IRQ Inactive.
3. Specified at T =+25°C.
A
4. F
= 400kHz.
SCL
5. In order to ensure proper timekeeping, the V
specification must be followed.
DD SR-
6. Parameter is not 100% tested.
2
7. These are I C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
FN6617.0
December 14, 2007
5
ISL12030
SDA vs SCL Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
HD:DAT
t
SU:STA
SU:STO
t
HD:STA
SDA
(INPUT TIMING)
t
t
BUF
DH
t
AA
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
5.0V
= 5V
DD
FOR V = 0.4V
OL
1533Ω
AND I
= 3mA
OL
SDA
AND
IRQ
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
= 5.0V
DD
FN6617.0
December 14, 2007
6
ISL12030
Functional Description
General Description
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
Power Supply Operation
The ISL12030 will function with inputs from V
= 2.7V to
DD
5.5VDC. If the V
supply should drop below this, operation
DD
to the specifications may be compromised, although the
SRAM memory will hold its values until V = 1.8V. Below
that, the entire device is not guaranteed to operate or retain
SRAM memory.
The oscillator uses a 50/60 cycle sine wave input. The real
time clock tracks time with separate registers for hours,
minutes and seconds. The calendar registers contain the
date, month, year and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
DD
Power Failure Detection
The ISL12030 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
The ISL12030’s alarm can be set to any clock/calendar
value for a match. Each alarm’s status is available by
checking the Status Register. The device also can be
configured to provide a hardware interrupt via the IRQ pin.
There is a repeat mode for the alarms allowing a periodic
interrupt every minute, every hour, every day, etc.
power to the device (V
very near 0.0VDC).
DD
Real Time Clock Operation
The Real Time Clock (RTC) maintains an accurate internal
representation of tenths of a second, second, minute, hour,
day of week, date, month and year. The RTC also has
leap-year correction. The clock also corrects for months
having fewer than 31 days and has a bit that controls 24
hour or AM/PM format. When the ISL12030 powers up after
The ISL12030 devices are specified for V
= 2.7V to 5.5V
DD
Pin Descriptions
AC (AC Input)
the loss of V , the clock will not begin incrementing until at
DD
The AC input is the main clock input for the real time clock. It
can be either 50Hz or 60Hz, sine wave. The preferred
least one byte is written to the clock register.
amplitude is 2.5V , although amplitudes >0.2 x V
are
P-P DD
Alarm Operation
acceptable. An AC coupled (series capacitor) sine wave
clock waveform is desired as the AC clock input provides DC
biasing.
The alarm mode is enabled via the MSB bit. Single event or
interrupt alarm mode is selected via the IM bit. The standard
alarm allows for alarms of time, date, day of the week,
month and year. When a time alarm occurs in single event
mode, the IRQ pin will be pulled low and the corresponding
alarm status bit (ALM0 or ALM1) will be set to “1”. The
status bits can be written with a “0” to clear, or if the ARST
bit is set, a single read of the SRDC status register will
clear them.
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active LOW output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
The pulsed interrupt mode (setting the IM bit to “1”) activates
a repetitive or recurring alarm. Hence, once the alarm is set,
the device will continue to output a pulse for each occurring
match of the alarm and present time. The Alarm pulse will
occur as often as every minute (if only the nth second is set)
or as infrequently as once a year (if at least the nth month is
set). During pulsed interrupt mode, the IRQ pin will be pulled
LOW for 250ms and the alarm status bit (ALM0 or ALM1) will
be set to “1”.
gated). It is disabled when the V
supply drops below 2.7V.
DD
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be OR’ed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
General Purpose User SRAM
The ISL12030 provides 128 bytes of user SRAM. The SRAM
is volatile and will be lost or corrupted if V
2
designed for 400kHz I C interface speeds.
drops below
DD
1.8V.
V
, GND
DD
2
Chip power supply and ground pins. The device will operate
with a power supply from V = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the V
I C Serial Interface
2
DD
The ISL12030 has an I C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I C serial interface is compatible with other
pin to ground.
DD
2
FN6617.0
December 14, 2007
7
ISL12030
2
industry I C serial bus protocols using a bi-directional data
Write capability is allowable into the RTC registers (00h to
signal (SDA) and a clock signal (SCL).
07h) only when the WRTC bit (bit 6 of address 0Ch) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
Register Descriptions
The registers are accessible following an I C slave byte of
“1101 111x” and reads or writes to addresses [00h:47h]. The
defined addresses and default values are described in the
Table 1. The general purpose SRAM has a different slave
address (1010 111x), so it is not possible to read/write that
section of memory while accessing the registers.
2
A register can be read by performing a random read at any
address at any time. This returns the contents of that
register’s location. Additional registers are read by
performing a sequential read. For the RTC and Alarm
registers, the read instruction latches all clock registers into
a buffer, so an update of the clock does not change the time
being read. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read,
the address remains at the previous address +1 so the user
can execute a current address read and continue reading
the next register.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 5 sections. They are:
1. Real Time Clock (8 bytes): Address 00h to 07h.
2. Status (1 bytes): Address 08h.
It is only necessary to set the WRTC bit prior to writing into
the RTC registers. All other registers are completely
accessible without setting the WRTC bit.
3. Control (2 bytes): 0Ch and 13h.
4. Day Light Saving Time (8 bytes): 15h to 1Ch
5. Alarm 0/1 (12 bytes):1Dh to 28h
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device)
BIT
REG
ADDR SECTION NAME
7
6
5
SC21
MN21
HR21
DT21
0
4
3
2
1
0
RANGE DEFAULT
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Ch
13h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
SC
MN
0
SC22
SC20
MN20
HR20
DT20
SC13
MN13
HR13
DT13
MO13
YR13
0
SC12
SC11
SC10
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 99
0 to 6
00h
00h
00h
01h
01h
00h
00h
00h
01h
01h
00h
04h
00h
01h
02h
10h
00h
01h
02h
00h
00h
00h
01h
01h
00h
0
MN22
MN12
HR12
MN11
MN10
HR
MIL
0
HR11
HR10
DT
0
0
0
DT12
DT11
DT10
RTC
MO
0
MO20
YR20
0
MO12
YR12
MO11
YR11
MO10
YR
YR23
0
YR22
YR21
0
YR10
DW
0
DW2
DW1
DW0
SS
0
0
0
0
SS3
SS2
SS1
SS0
0 to 9
Status
SRDC
INT
0
DSTADJ
ALM1
IM
ALM0
X
0
0
0
RTCF
N/A
ARST
AC5060
DSTE
0
WRTC
X
X
ALE1
ALE0
N/A
Control
AC
ACENB
X
X
X
X
X
X
N/A
DstMoFd
DstDwFd
DstDtFd
DstHrFd
DstMoRv
DstDwRv
DstDtRv
DstHrRv
SCA0
MNA0
HRA0
DTA0
MOA0
DWA0
0
0
MoFd20
WkFd11
DtFd20
HrFd20
MoRv20
WkRv11
DtRv20
HrRv20
SCA020
MNA013
HRA020
DTA020
MOA020
0
MoFd13
WkFd10
DtFd13
HrFd13
MoRv13
WkRv10
DtRv13
HrRv13
SCA013
MNA012
HRA013
DTA013
MOA013
0
MoFd12
DwFd12
DtFd12
HrFd12
MoRv12
DwRv12
DtRv12
HrRv12
SCA012
MNA011
HRA012
DTA012
MOA012
DWA02
MoFd11
DwFd11
DtFd11
HrFd11
MoRv11
DwRv11
DtRv11
HrRv11
SCA011
MNA011
HRA011
DTA011
MOA011
DWA01
MoFd10
DwFd10
DtFd10
HrFd10
MoRv10
DwRv10
DtRv10
HrRv10
SCA010
MNA010
HRA010
DTA010
MOA010
DWA00
1 to 12
0 to 6
DwFdE
WkFd12
DtFd21
HrFd21
0
0
0
1 to 31
0 to 23
1 to 12
0 to 6
HrFdMIL
0
0
DSTCR
0
0
DwRvE
WkRv12
DtRv21
HrRv21
SCA021
MNA020
HRA021
DTA021
0
0
0
1 to 31
0 to 23
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 6
HrRvMIL
ESCA0
EMNA0
EHRA0
EDTA0
EMOA0
EDWA0
0
SCA022
MNA021
0
0
0
0
Alarm0
0
FN6617.0
December 14, 2007
8
ISL12030
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device) (Continued)
BIT
REG
ADDR SECTION NAME
7
6
5
4
3
2
1
0
RANGE DEFAULT
23h
24h
25h
26h
27h
28h
SCA1
MNA1
HRA1
DTA1
MOA1
DWA1
ESCA1
EMNA1
EHRA1
EDTA1
EMOA1
EDWA1
SCA122
SCA121
MNA121
HRA121
DTA121
0
SCA120
MNA120
HRA120
DTA120
MOA120
0
SCA113
MNA113
HRA113
DTA113
MOA113
0
SCA112
MNA112
HRA112
DTA112
MOA112
DWA12
SCA111
MNA111
HRA111
DTA111
MOA111
DWA11
SCA110
MNA110
HRA110
DTA110
MOA110
DWA10
0 to 59
0 to 59
0 to 23
1 to 31
1 to12
0 to 6
00h
00h
00h
01h
01h
00h
MNA122
0
0
0
0
Alarm1
0
FN6617.0
December 14, 2007
9
ISL12030
can be forced to “1” with a write to the Status Register. The
default value for DSTADJ is “0”.
Real Time Clock Registers
Addresses [00h to 07h]
ALARM BITS (ALM0 AND ALM1)
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW, SS)
These bits announce if an alarm matches the real time clock.
If there is a match, the respective bit is set to “1”. This bit can
be manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”. An alarm bit that is set by
an alarm occurring during an SR read operation will remain
set after the read operation is complete.
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR
(Hour) can be either 12-hour or 24-hour mode, DT (Date) is 1
to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, DW (Day of
the Week) is 0 to 6, and SS (Sub-Second) is 0 to 9. The
Sub-Second register is read-only and will clear to “0” count
each time there is a write to a register in the RTC section.
REAL TIME CLOCK FAIL BIT (RTCF)
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2.... The assignment of a numerical value to a specific day of
the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (internally) when the device
powers up after having lost all power (defined as V
= 0V).
DD
is applied to the device. The
The bit is set as soon as V
DD
first valid write to the RTC section after a complete power
failure resets the RTCF bit to “0” (writing one byte is
sufficient).
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
Control Registers
Addresses [0Ch to 13h]
The control registers (INT, AC) contain all the bits necessary
to control the parametric functions on the ISL12030.
LEAP YEARS
Interrupt Control Register (INT)
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year and the year 2100 is not. The
ISL12030 does not correct for the leap year in the year 2100.
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3
2
1
0
0Ch
ARST WRTC IM
X
X
X
ALE1 ALE0
AUTOMATIC RESET BIT (ARST)
Status Register (SR)
This bit enables/disables the automatic reset of the ALM0
and ALM1 status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the SRDC
Register (with a valid STOP condition). When the ARST is
cleared to “0”, the user must manually reset the ALM0 and
ALM1 bits.
Address [08h]
The Status Registers consist of the DC and AC status
registers (see Tables 2 and 3).
Status Register DC (SRDC)
The Status Register DC is located in the memory map at
address 08h. This is a volatile register that provides status of
RTC failure (RTCF), Alarm0 or Alarm1 trigger, and Daylight
Saving Time adjustment.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Register section. The factory default setting of this bit is
“0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle. This bit will remain set until reset to “0” or a
TABLE 2. STATUS REGISTER DC (SRDC)
ADDR
7
6
5
4
3
2
1
0
08h
X
DSTADJ ALM1 ALM0
X
X
X
RTCF
complete power-down occurs (V
= 0.0V).
DD
DAYLIGHT SAVING TIME ADJUSTMENT BIT (DSTADJ)
ALARM INTERRUPT MODE BIT (IM)
DSTADJ is the Daylight Saving Time Adjustment Bit. It
indicates that daylight saving time adjustment has
happened. The bit will be set to “1” when the Forward DST
event has occurred. The bit will stay set until the Reverse
DST event has happened. The bit will also reset to “0” when
the DSTE bit is set to “0” (DST function disabled). The bit
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarms will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ pin when the RTC is triggered
by either alarm as defined by the Alarm0 section (1Dh to
22h) or the Alarm1 section (23h to 28h). When the IM bit is
FN6617.0
December 14, 2007
10
ISL12030
cleared to “0”, the alarm will operate in standard mode,
where the IRQ pin will be set LOW until both the
ALM0/ALM1 status bits are cleared to “0”.
WkFd controls the week of the month that the DST starts.
When the day of week option is selected, the WkFd entry set
the week in the month and the DwFd selects the day of the
week. The range for WdFd is 1 to 5 and 7 with 7 being the
last week. Default is 0 (OFF).
ALARM 1 (ALE 1)
This bit enables the Alarm1 function. When ALE1 = “1”, a
match of the RTC section with the Alarm1 section will result
is setting the ALM1 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm1 function is disabled.
DstDtfd controls which Date DST begins. The default value
for DST forward date is on the first date of the month (01h).
DstDtFd is only effective if DwFdE = 0.
DstHrFd controls the hour that DST begins. It includes the
MIL bit, which is in the corresponding RTC register. The RTC
hour and DstHrFd registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value for DST hour is 2:00AM (02h). The time is advanced
from 2:00:00AM to 3:00:00AM for this setting.
ALARM 0 (ALE 0)
This bit enables the Alarm0 function. When ALE0 = 1, a
match of the RTC section with the Alarm1 section will result
is setting the ALM0 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm0 function is disabled.
AC Register (AC)
DST REVERSE REGISTERS (19H TO 1CH)
Address [13h]
DST end (reverse) is controlled by the following DST
Registers:
This register sets the parameters for the AC input.
TABLE 4. AC REGISTER
DstMoRv sets the Month that DST ends. The default value
for the DST end month is October (10h).
ADDR
7
6
5
4
3
2
1
0
13h
AC5060
X
X
X
X
X
X
X
DstDwRv controls the Week and the Day of the Week that
DST should end. The DwRvE bit sets the priority of the Day of
the Week over the Date. For DwRvE = 1, Day of the week is
the priority. Note that Day of the week counts from 0 to 6, like
the RTC registers. The default for DST DwRv end is Sunday
(00h).
AC 50/60HZ INPUT SELECT (AC5060)
This bit selects either 50Hz or 60Hz powerline AC clock
input frequency. Setting this bit to “0” selects a 60Hz input
(default). Setting this bit to “1” selects a 50Hz input.
DST Control Registers (DSTCR)
WkRv controls the week of the month that the DST starts.
When the day of week option is selected, the WkRv entry set
the week in the month and the DwRv selects the day of the
week. The range for WdRv is 1 to 5 and 7 with 7 being the
last week. Default is 0 (OFF)
Address [15h to 1Ch]
8 bytes of control registers have been assigned for the
Daylight Savings Time (DST) functions. DST beginning (set
Forward) time is controlled by the registers DstMoFd,
DstDwFd, DstDtFd, and DstHrFd. DST ending time (set
Backward or Reverse) is controlled by DstMoRv, DstDwRv,
DstDtRv and DstHrRv.
DstDtRv controls which Date DST ends. The default value
for DST Date Reverse is on the first date of the month. The
DstDtRv is only effective if the DwRvE = 0.
DstHrRv controls the hour that DST ends. It includes the MIL
bit, which is in the corresponding RTC register. The RTC
hour and DstHrRv registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value sets the DST end at 2:00AM. The time is set back from
2:00:00AM to 1:00:00AM for this setting.
Tables 5 and 6 describe the structure and functions of the
DSTCR.
DST FORWARD REGISTERS (15H TO 18H)
DSTE is the DST Enabling Bit located in bit 7 of register 15h
(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.
Upon powering up for the first time, the DSTE bit defaults to
“0”.
DST forward is controlled by the following DST Registers:
DstMoFd sets the Month that DST starts. The default value
for the DST begin month is April (04h).
DstDwFd sets the Week and the Day of the Week that DST
starts. DstDwFdE sets the priority of the Day of the Week
over the Date. For DstDwFdE=1, Day of the week is the
priority. Note that Day of the week counts from 0 to 6, like the
RTC registers. The default for the DST Forward Day of the
Week is Sunday (00h).
FN6617.0
December 14, 2007
11
ISL12030
TABLE 5. DST FORWARD REGISTERS
ADDRESS
15h
FUNCTION
Month Forward
Day Forward
Date Forward
Hour Forward
7
DSTE
0
6
5
4
3
2
1
0
0
0
MoFd20
WkFd11
DtFd20
HrFd20
MoFd13
WkFd10
DtFd13
HrFd13
MoFd12
DwFd12
DtFd12
HrFd12
MoFd11
DwFd11
DtFd11
HrFd11
MoFd10
DwFd10
DtFd10
HrFd10
16h
DwFdE
WkFd12
DtFd21
HrFd21
17h
0
0
0
18h
HrFdMIL
TABLE 6. DST REVERSE REGISTERS
ADDRESS
19h
NAME
7
6
5
4
3
2
1
0
Month Reverse
Day Reverse
Date Reverse
Hour Reverse
0
0
0
MoRv20
WkRv11
DtRv20
HrRv20
MoRv13
WkRv10
DtRv13
HrRv13
MoRv12
DwRv12
DtRv12
HrRv12
MoRv11
DwRv11
DtRv11
HrRv11
MoRv10
DwRv10
DtRv10
HrRv10
1Ah
0
0
DwRvE
WkRv12
DtRv21
HrRv21
1Bh
0
0
1Ch
HrRvMIL
ALM0 and ALM1 bits will automatically be cleared when the
status register is read.
ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The IRQ output will be set by an alarm match for either
ALM0 or ALM1.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30am.
• Set Alarm registers as follows:
There are two alarm operation modes: Single Event and
periodic Interrupt Mode.
BIT
ALARM
REGISTER 7
6
0
0
5
0
1
4
0
1
3
0
0
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
Single Event Mode is enabled by setting either ALE0 or
ALE1 to 1, then setting bit 7 on any of the Alarm registers
(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This
mode permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM bit
is set to “1” and the IRQ output will be pulled LOW and will
remain LOW until the ALM bit is reset. This can be done
manually or by using the auto-reset feature. Since the IRQ
output is shared by both alarms, they both need to be reset
in order for the IRQ output to go HIGH.
SCA0
MNA0
0
1
00h Seconds disabled
B0h Minutes set to 30,
enabled
HRA0
DTA0
MOA0
DWA0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
91h Hours set to 11,
enabled
81h Date set to 1,
enabled
81h Month set to 1,
enabled
00h Day of week
disabled
Interrupt Mode is enabled by setting either ALE0 or ALE1 to
1, then setting bit 7 on any of the Alarm registers (ESCA...
EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit
to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ
output will now be pulsed each time an alarm occurs (either
AL0 or AL1). This means that once the interrupt mode alarm
is set, it will continue to alarm until it is reset.
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
To clear a single event alarm, the corresponding ALM0 or
ALM1 bit in the SRDC register must be set to “0” with a write.
Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the
FN6617.0
December 14, 2007
12
ISL12030
2
Example 2
I C Serial Interface
• Pulsed interrupt once per minute (IM = ”1”)
The ISL12030 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12030 operates as a slave device in all applications.
• Interrupts at one minute intervals when the seconds
register is at 30 seconds.
• Set Alarm registers as follows:
BIT
ALARM
REGISTER 7
6
5
4
3
2
1
0 HEX
DESCRIPTION
SCA0
1
0
1
1
0
0
0
0
B0h Seconds set to 30,
enabled
2
All communication over the I C interface is conducted by
sending the MSB of each byte of data first.
MNA0
HRA0
DTA0
MOA0
DWA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h Minutes disabled
00h Hours disabled
00h Date disabled
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 3). On power-up of the ISL12030, the SDA pin is in
the input mode.
00h Month disabled
00h Day of week disabled
Once the registers are set, the following waveform will be
seen at IRQ as shown in Figure 2:
2
All I C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12030 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 3). A START condition is ignored during the power-up
sequence.
RTC AND ALARM REGISTERS ARE BOTH “30s”
60s
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 3). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
FIGURE 2. IRQ WAVEFORM
Note that the status register ALM0 bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 4).
User Memory Registers (accessed by
using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of user SRAM. Writes to this
section do not need to be proceeded by setting the WRTC
bit. Note that this memory, like the status and control
registers, is volatile and will be lost or corrupted when V
drops below 1.8V.
The ISL12030 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12030 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
DD
FN6617.0
December 14, 2007
13
ISL12030
SCL
SDA
DATA
STABLE
DATA
CHANGE STABLE
DATA
START
STOP
FIGURE 3. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT SDA
1 1 0 1 1 1 1 0
0 0 0 0
SIGNALS FROM
THE ISL12030
A
C
K
A
C
K
A
C
K
FIGURE 5. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
counter is set to address 00h, so a current address read starts
Device Addressing
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Byte as shown in
Figure 6.
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111b” for the RTC registers and “1010111b” for the
User SRAM.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation (see
Figure 6).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12030 compares the device identifier and device select
bits with “1101111b” or “1010111b”. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up the internal address
FN6617.0
December 14, 2007
14
ISL12030
.
Read Operation
SLAVE
ADDRESS BYTE
1
1
1
1
0
1
1
R/W
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 7). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the RW bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the RW bit set to “1”. After each of the
three bytes, the ISL12030 responds with an ACK. Then the
ISL12030 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 7).
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0 WORD ADDRESS
DATA BYTE
D0
FIGURE 6. SLAVE ADDRESS, WORD ADDRESS AND DATA
BYTES
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12030 responds with an ACK. At this time, the I C
interface enters a standby state.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the last memory location in a section or page,
the master should issue a STOP. Bytes that are read at
addresses higher than the last address in a section may be
erroneous.
2
A multiple byte operation within a page is permitted. The
Address Byte must have the start address, and the data
bytes are sent in sequence after the address byte, with the
ISL12030 sending an ACK after each byte. The page write is
terminated with a STOP condition from the master. The
pages within the ISL12030 do not support wrapping around
for page read or write operations.
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
IDENTIFICATION
BYTE WITH
R/W=0
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
A
C
K
T
O
P
ADDRESS
BYTE
SIGNAL AT
SDA
1 1 0 1 1 1 1 0
1 1 0 1 1 1 1
1
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 7. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
FN6617.0
December 14, 2007
15
ISL12030
The AC input to the ISL12030 can be damaged if subjected
to a normal AC waveform when V is powered down. This
can happen in circuits where there is a local LDO or power
switch for placing circuitry in standby, while the AC main is
still switched ON. Figure 8 shows a modified version of the
Figure 9 circuit, which uses an emitter follower to essentially
Application Section
DD
AC Input Circuits
The AC input ideally will have a 2.5V
input, so this is the target for any signal conditioning circuitry
for the 50/60Hz waveform. Note that the peak-to-peak
sine wave at the
P-P
amplitude can range from 1V
up to V , although it is
turn off the AC input waveform if the V
DD
supply goes down.
P-P
DD
best to keep the max signal level just below V . The AC
input provides DC offset so AC coupling with a series
capacitor is advised.
DD
Adding a Super Capacitor Backup
Since any loss of V power will reset the SRAM memory
DD
including control and RTC register sections, then having
some form of V backup is a good idea. Figure 10 shows
If the AC power supply has a transformer, the secondary
output can be used for clocking with a resistor divider and
series AC coupling capacitor. A sample circuit is shown in
DD
connections for a super capacitor backup using V
for the
DD
normal source and a signal diode for charging. Be careful
not to use a normal Schottky diode as the leakage will
greatly reduce the backup life of the super capacitor.
Figure 8. Values for R /R are chosen depending on the
1
2
peak-to-peak range on the secondary voltage in order to
match the input of the ISL12030. C can be sized to pass
IN
This form of backup should yield at least one full day of
backup time, assuming the SCL/SDA pins and their pull-ups
are pulled to ground on powerdown.
up to 300Hz or so, and in most cases, 0.47µF should be the
selected value for a ±20% tolerance device.
VIN (AC) = 1.5V
TO 5V
P-P
P-P
CIN
R1
120VAC
50/60Hz
ISL12030
R2
FIGURE 8. AC INPUT USING A TRANSFORMER SECONDARY
VIN (AC) = 1.5V
TO VDD (MAX)
P-P
VDD
R1
C1
CIN
120VAC
50/60Hz
ISL12030
R2
FIGURE 9. USING THE V
SUPPLY TO GATE THE AC INPUT
DD
FN6617.0
December 14, 2007
16
ISL12030
.
1N4148
REGULATED
SUPPLY
VOLTAGE
V
DD
SUPER
CAPACITOR,
>0.22F
+
ISL12030
FIGURE 10. ADDING A SUPER CAPACITOR TO PROVIDE BACKUP FOR SRAM
FN6617.0
December 14, 2007
17
ISL12030
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6617.0
December 14, 2007
18
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