ISL12029AIV27Z [INTERSIL]
Real Time Clock/Calendar with I2C Bus™ and EEPROM; 实时时钟/日历与I2C总线?和EEPROM型号: | ISL12029AIV27Z |
厂家: | Intersil |
描述: | Real Time Clock/Calendar with I2C Bus™ and EEPROM |
文件: | 总30页 (文件大小:577K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL12029, ISL12029A
®
Data Sheet
August 12, 2010
FN6206.9
Real Time Clock/Calendar with I2C Bus™
and EEPROM
Features
• Real Time Clock/Calendar
The ISL12029 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (open drain
output), intelligent battery backup switching, CPU
Supervisor, integrated 512x8-bit EEPROM configured in 16
bytes per page.
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation:
- Internal Feedback Resistor and Compensation
Capacitors
The ISL12029 and ISL12029A Power Control Settings are
different. The ISL12029 uses the Legacy Mode Setting, and
the ISL12029A uses the Standard Mode Setting.
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
Applications that have V
> V
will require only the
BAT
DD
ISL12029A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup” on page 24 for
important details.
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
Pinout
- Endurance: >2,000,000 Cycles Per Byte
ISL12029, ISL12029A
(14 LD TSSOP, SOIC)
TOP VIEW
• CPU Supervisor Functions
- Power-On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s, 1.5s)
X1
X2
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
DD
• I2C Interface
BAT
NC
IRQ/F
NC
OUT
- 400kHz Data Transfer Rate
NC
NC
NC
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
RESET
GND
SCL
SDA
8
Applications
NC = No internal connection
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/AutomotivePAR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
1
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2010.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL12029, ISL12029A
Block Diagram
OSC COMPENSATION
X1
X2
TIMER
CALENDAR
LOGIC
BATTERY
SWITCH
CIRCUITRY
TIME
V
V
FREQUENCY
DIVIDER
DD
1Hz
32.768kHZ
KEEPING
REGISTERS
(SRAM)
OSCILLATOR
BACK
IRQ/F
SELECT
OUT
STATUS
CONTROL/
REGISTERS
(EEPROM)
CONTROL
DECODE
LOGIC
COMPARE
SCL
SDA
SERIAL
INTERFACE
DECODER
REGISTERS
ALARM
(SRAM)
ALARM REGS
(EEPROM)
8
4k
EEPROM
ARRAY
WATCHDOG LOW VOLTAGE
TIMER
RESET
RESET
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
2
6
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
RESET
RESET. This is a reset signal output. This signal notifies a host processor that the “Watchdog” time period has
expired or that the voltage has dropped below a fixed V
threshold. It is an open drain active LOW output.
TRIP
Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground.
7
8
GND
SDA
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
9
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is
always active (not gated).
12
13
14
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. It
is an open drain output. The function is set via the configuration register.
IRQ/F
OUT
V
This input provides a backup supply voltage to the device. V
supplies power to the device in the event that the
BAT
BAT
V
supply fails. This pin should be tied to ground if not used.
DD
V
Power Supply.
DD
3, 4, 5, 10,
11
NC
No Internal Connection.
FN6206.9
August 12, 2010
2
ISL12029, ISL12029A
Ordering Information
BSW BIT
V
RESET
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
V
TRIP POINT DEFAULT
VOLTAGE
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
BAT
(V)
< V
< V
< V
< V
< V
< V
< V
< V
< V
< V
2.2
2.2
SETTING
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 0
BSW = 0
(V)
PKG. DWG. #
M14.15
ISL12029IB27Z
ISL12029IB27AZ
ISL12029IB30AZ
ISL12029IBZ
12029IB27Z
12029IB27 AZ
12029IB30 AZ
12029IBZ
V
V
V
V
V
V
V
V
V
V
2.63
2.92
3.09
4.38
4.64
2.63
2.92
3.09
4.38
4.64
2.63
2.63
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
M14.15
M14.15
M14.15
ISL12029IBAZ
ISL12029IV27Z
ISL12029IV27AZ
ISL12029IV30AZ
ISL12029IVZ
12029IBAZ
M14.15
12029 IV27Z
12029 27AZ
12029 30AZ
12029 IVZ
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
ISL12029IVAZ
ISL12029AIB27Z
ISL12029AIV27Z
NOTES:
12029 IVAZ
12029AIB 27Z
12029A IV27Z
14 Ld SOIC
M14.15
14 Ld TSSOP M14.173
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12029, ISL12029A. For more information on MSL please
see techbrief TB363.
FN6206.9
August 12, 2010
3
ISL12029, ISL12029A
Absolute Maximum Ratings
Thermal Information
Voltage on V , V , SCL, SDA, and IRQ/F
Pins
Thermal Resistance (Typical)
θ
(°C/W)
θ (°C/W)
JC
DD BAT
OUT
JA
(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
14 Ld SOIC Package (Notes 5, 6) . . . .
14 Ld TSSOP Package (Note 5, 6) . . .
90
110
40
35
(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model (MIL-STD-883, Method 3014) . . . . . . .>±2kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. For θ , the “case temp” location is taken at the package top center.
JC
DC Electrical Specifications Unless otherwise noted, V = +2.7V to +5.5V, T = -40°C to +85°C, Typical values are at T = +25°C
DD
A
A
and V = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
DD
MIN
MAX
SYMBOL
PARAMETER
Main Power Supply
Backup Power Supply
CONDITIONS
(Note 16)
TYP
(Note 16)
UNIT
V
NOTES
V
2.7
1.8
5.5
5.5
DD
V
V
BAT
Electrical Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
= 2.7V
(Note 16)
TYP
(Note 16)
UNIT
µA
NOTES
I
Supply Current with I2C Active
V
V
V
V
V
V
500
7, 8, 9
DD1
DD
DD
DD
DD
DD
DD
BAT
= 5.5V
= 2.7V
= 5.5V
800
µA
I
I
Supply Current for Non-Volatile
Programming
2.5
mA
mA
µA
7, 8, 9
9
DD2
DD3
,
3.5
Supply Current for Main
Timekeeping (Low Power Mode)
= V
= V
= V
= V
= 2.7V
= 5.5V
10
SDA
SDA
SCL
SCL
20
µA
I
Battery Supply Current
V
V
= 1.8V,
SDA
800
850
1000
nA
7, 10, 11
BAT
= V
= V
= V
= V
RESET
= 0V
= 0V
DD
SCL
V
V
= 3.0V,
1200
nA
BAT
DD
= V
= V
RESET
SDA
SCL
I
Battery Input Leakage
V
= 5.5V, V = 1.8V
BAT
-100
1.8
100
2.6
nA
V
BATLKG
DD
V
V
V
V
V
Mode Threshold
Hysteresis
2.2
30
50
11
TRIP
BAT
TRIP
BAT
V
mV
mV
V/ms
11, 13
11, 13
12
TRIPHYS
V
Hysteresis
BATHYS
V
Negative Slew Rate
DD
10
DD SR-
IRQ/F
RESET OUTPUTS
OUT,
V
Output Low Voltage
V
= 5.5V
DD
= 3mA
0.4
0.4
V
V
OL
I
OL
V
= 2.7V
DD
I
= 1mA
OL
I
Output Leakage Current
V
V
= 5.5V
100
400
nA
LO
DD
= 5.5V
OUT
FN6206.9
August 12, 2010
4
ISL12029, ISL12029A
Watchdog Timer/Low Voltage Reset Parameters
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 16) (Note 11) (Note 16)
UNITS
ns
NOTES
t
V
Detect to RESET LOW
DD
500
13
RPD
t
Power-Up Reset Time-Out Delay
100
1.0
250
400
ms
PURST
V
Minimum VDD for Valid RESET
Output
V
RVALID
V
ISL12029-4.5A Reset Voltage Level
ISL12029 Reset Voltage Level
ISL12029-3 Reset Voltage Level
ISL12029-2.7A Reset Voltage Level
ISL12029-2.7 Reset Voltage Level
Watchdog Timer Period
4.59
4.33
3.04
2.87
2.58
1.70
725
4.64
4.38
3.09
2.92
2.63
1.75
750
4.69
4.43
3.14
2.97
2.68
1.801
775
V
V
RESET
V
V
V
t
32.768kHz crystal between X1
and X2
s
WDO
ms
ms
ms
225
250
275
t
Watchdog Timer Reset Time-Out
Delay
32.768kHz crystal between X1
and X2
225
250
275
RST
t
I2C Interface Minimum Restart Time
1.2
µs
RSP
EEPROM SPECIFICATIONS
EEPROM Endurance
>2,000,000
50
Cycles
Years
EEPROM Retention
Temperature ≤ +75°C
Serial Interface (I2C) Specifications - DC/AC Characteristics
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 16)
TYP
(Note 16)
UNITS
NOTES
V
SDA, and SCL Input Buffer LOW
Voltage
SBIB = 1 (Under V
mode)
-0.3
0.3 x V
DD
V
IL
DD
DD
DD
V
SDA, and SCL Input Buffer HIGH SBIB = 1 (Under V
Voltage
mode)
mode)
0.7 x V
V + 0.3
DD
V
V
IH
DD
Hysteresis SDA and SCL Input Buffer
Hysteresis
SBIB = 1 (Under V
0.05 x V
0
DD
V
I
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
I
= 4mA
= 5.5V
= 5.5V
0.4
V
OL
LI
OL
V
V
0.1
0.1
10
10
µA
µA
IN
IN
I
LO
TIMING CHARACTERISTICS
SCL Frequency
Pulse Width Suppression Time at Any pulse narrower than the max
f
400
50
kHz
ns
SCL
t
IN
SDA and SCL Inputs
spec is suppressed.
t
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
900
ns
ns
AA
V
, until SDA exits the 30% to
DD
70% of V
window.
DD
t
Time the Bus Must be Free Before SDA crossing 70% of V during
1300
1300
BUF
DD
the Start of a New Transmission
Clock LOW Time
a STOP condition, to SDA
crossing 70% of V during the
DD
following START condition.
t
Measured at the 30% of V
crossing.
ns
LOW
DD
FN6206.9
August 12, 2010
5
ISL12029, ISL12029A
Serial Interface (I2C) Specifications - DC/AC Characteristics (Continued)
MIN
MAX
SYMBOL
PARAMETER
Clock HIGH Time
CONDITIONS
(Note 16)
TYP
(Note 16)
UNITS
NOTES
t
Measured at the 70% of V
crossing.
600
ns
HIGH
DD
t
START Condition Setup Time
START Condition Hold Time
SCL rising edge to SDA falling
edge. Both crossing 70% of V
600
600
ns
ns
SU:STA
HD:STA
.
DD
t
From SDA falling edge crossing
30% of V to SCL falling edge
DD
crossing 70% of V
.
DD
t
Input Data Setup Time
Input Data Hold Time
From SDA exiting the 30% to
70% of V window, to SCL rising
100
0
ns
ns
ns
ns
ns
SU:DAT
HD:DAT
SU:STO
HD:STO
DD
edge crossing 30% of V
DD
t
From SCL falling edge crossing
70% of V to SDA entering the
DD
30% to 70% of V
window.
DD
t
STOP Condition Setup Time
From SCL rising edge crossing
70% of V , to SDA rising edge
600
600
0
DD
crossing 30% of V
.
DD
t
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL
falling edge. Both crossing 70%
of V
.
DD
t
Output Data Hold Time
From SCL falling edge crossing
30% of V , until SDA enters the
DH
DD
30% to 70% of V
window.
DD
Cpin
SDA, and SCL Pin Capacitance
Non-Volatile Write Cycle Time
SDA and SCL Rise Time
10
20
pF
ms
ns
t
12
14
15
WC
t
From 30% to 70% of V
From 70% to 30% of V
20 +
0.1 x Cb
250
R
DD
DD
t
SDA and SCL Fall Time
20 +
0.1 x Cb
250
400
ns
15
F
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-up Resistor Maximum is determined by t and
10
1
pF
15
15
Rpu
kΩ
R
Off-chip
t .
F
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
NOTES:
7. IRQ/F
Inactive (no frequency output and no alarms).
OUT
8. V = V
x 0.1, V = V
x 0.9, f
= 400kHz.
SCL
IL
DD
IH
DD
9. V
= 2.63V (VDD must be greater than V
), VBAT = 0V.
RESET
RESET
10. Bit BSW = 0 (Standard Mode), ATR = 00h, V
11. Specified at +25°C.
≥ 1.8V.
BAT
12. In order to ensure proper timekeeping, the V
13. Parameter is not 100% tested.
specification must be followed.
DD SR-
14. t
is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
WC
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
FN6206.9
August 12, 2010
6
ISL12029, ISL12029A
Timing Diagrams
t
t
t
t
R
F
HIGH
LOW
t
HD:STO
SCL
t
SU:DAT
t
t
HD:DAT
t
SU:STA
SU:STO
t
HD:STA
SDA
(INPUT TIMING)
t
t
BUF
DH
t
AA
SDA
(OUTPUT TIMING)
FIGURE 1. BUS TIMING
SCL
8TH BIT OF LAST BYTE
ACK
SDA
t
WC
STOP
START
CONDITION
CONDITION
FIGURE 2. WRITE CYCLE TIMING
t
t
>t
RSP
RSP WDO
t
t
>t
t
RST
t
<t
RST
RSP WDO
RSP WDO
SCL
SDA
RESET
STOP
START
START
Note: All inputs are ignored during the active reset period (t
).
RST
FIGURE 3. WATCHDOG TIMING
V
RESET
V
DD
t
t
PURST
PURST
t
RPD
t
F
t
R
RESET
V
RVALID
FIGURE 4. RESET TIMING
FN6206.9
August 12, 2010
7
ISL12029, ISL12029A
Typical Performance Curves Temperature is +25°C unless otherwise specified
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
BSW = 0 OR 1
SCL, SDA PULL-UPS = 0V
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
SCL, SDA PULL-UPS = V
BSW = 0 OR 1
BAT
1.8
2.3
2.8
3.3
3.8
4.3
4.8
5.3
1.8
2.3
2.8
3.3
3.8
(V)
4.3
4.8
5.3
V
(V)
BAT
V
BAT
FIGURE 5. I
vs V
SBIB = 0
FIGURE 6. I
vs V
SBIB = 1
BAT
BAT,
BAT
BAT,
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
= 5.5V
DD
V
= 3.0V
BAT
V
= 3.3V
DD
-45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85
-45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. I
vs TEMPERATURE
FIGURE 8. I
vs TEMPERATURE
BAT
DD3
4.5
80
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
60
40
20
0
-20
-40
1.8
2.3
2.8
3.3
3.8
(V)
4.3
4.8
5.3
-32 -28 -24 -20 -16 -12 -8 -4
0
4
8
12 16 20 24 28
V
ATR SETTING
DD
FIGURE 9. I
vs V
FIGURE 10. ΔF
vs ATR SETTING
OUT
DD3
DD
FN6206.9
August 12, 2010
8
ISL12029, ISL12029A
Serial Data (SDA)
Description
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
The ISL12029 device is a Real Time Clock with clock/calendar,
two polled alarms with integrated 512x8 EEPROM, oscillator
compensation, CPU Supervisor (Power-on Reset, Low Voltage
Sensing and Watchdog Timer) and battery backup switch.
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as V . The output circuitry controls the fall time of the
DD
output signal with the use of a slope controlled pull-down. The
circuit is designed for 400kHz I2C interface speed.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
V
BAT
This input provides a backup supply voltage to the device.
V
supplies power to the device in the event the V
DD
BAT
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
The Dual Alarms can be set to any Clock/Calendar value for a
match. For instance, every minute, every Tuesday, or 5:23 AM
on March 21. The alarms can be polled in the Status Register
Note that the device is not guaranteed to operate with
VBAT < 1.8V. If the battery voltage is expected to drop lower
or can provide a hardware interrupt (IRQ/F
Pin). There is a
than this minimum, correct operation of the device,
OUT
repeat mode for the alarms allowing a periodic interrupt.
(especially after a V power-down cycle) is not
DD
guaranteed.
The IRQ/F pin may be software selected to provide a
OUT
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
IRQ/F
(Interrupt Output/Frequency Output)
OUT
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/F mode is selected via
The ISL12029 device integrates CPU Supervisory functions
(POR, WDT) and Battery Switch. There is Power-On-Reset
(RESET) output with 250ms delay from power-on when the
OUT
the frequency out control bits of the control/status register.
V
supply crosses the V
threshold for the device. It will
DD
RESET
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
also assert RESET when V goes below the specified
DD
V
threshold for the device. The V
threshold is
RESET
RESET
selectable via VTS2/VTS1/VTS0 registers to five (5)
preselected levels. There is Watchdog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s and 1.75s) and
disabled setting. The WatchDog Timer activates the RESET pin
when it expires. Normally, the I2C Interface is disabled when the
RESET output is active, but this can be changed by using a
register bit to enable I2C operation in battery backup mode.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is
an open drain output.
The IRQ/F
pin is an open drain output requiring a pull-up
OUT
resistor which was intended to be used for clocking
The device offers a backup power input pin. This V
pin
applications for micro controllers. Choose the pull-up resistor
with care, since low values will cause high currents to flow in
the V and ground traces around the device which can
DD
contribute to faulty oscillator function. For a 32kHz output,
values up to 10kΩ can be used with some degradation of the
square waveform.
BAT
allows the device to be backed up by battery or SuperCap. The
entire ISL12029 device is fully operational from 2.7 to 5.5V and
the clock/calendar portion of the ISL12029 device remains fully
operational down to 1.8V (Standby Mode).
The ISL12029 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a safe,
secure memory for critical user and configuration data, while
allowing a large user storage area.
RESET
The RESET signal output can be used to notify a host
processor that the Watchdog timer has expired or the VDD
voltage supply has dipped below the V
an open drain, active LOW output. Recommended value for
threshold. It is
RESET
Pin Descriptions
the pull-up resistor is 5kΩ. If unused, it can be tied to ground.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
gated). The pull-up resistor on this pin must use the same
In battery mode, the Watchdog timer function is disabled.
The RESET signal output is asserted LOW when the V
DD
voltage supply has dipped below the V
threshold but
RESET
voltage source as V
.
DD
the RESET signal output will not return HIGH until the device
FN6206.9
August 12, 2010
9
ISL12029, ISL12029A
is back to V
mode (out of Battery Backup mode) even if
during the Acknowledge. This new RTC value is loaded into
the RTC Register by a stop bit at the end of a valid write
sequence. An invalid write operation aborts the time update
procedure and the contents of the buffer are discarded. After
a valid write operation the RTC will reflect the newly loaded
data beginning with the next “one second” clock cycle after
the stop bit is written. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any non-volatile write sequences.
DD
the V
voltage is above V
threshold.
RESET
DD
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal is
used with the ISL12029 to supply a timebase for the real time
clock. Internal compensation circuitry provides high accuracy
over the operating temperature range from -40°C to +85°C.
This oscillator compensation network can be used to calibrate
the crystal timing accuracy over-temperature either during
manufacturing or with an external temperature sensor and
microcontroller for active compensation. X2 is intended to
drive a crystal only, and should not drive any external circuit.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
accuracy of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover-temperature of the
crystal from the crystal’s nominal frequency. For example, a
>20ppm frequency deviation translates into an accuracy of
>1 minute per month. These parameters are available from
the crystal manufacturer. Intersil’s RTC family provides
on-chip crystal compensation networks to adjust
No external compensation resistors or capacitors are
needed or are recommended to be connected to the X1 and
X2 pins.
X1
X2
load-capacitance to tune oscillator frequency from -34ppm to
+80ppm when using a 12.5pF load crystal. For more detailed
information, see “Application Section” on page 23.
FIGURE 11. RECOMMENDED CRYSTAL CONNECTION
Real Time Clock Operation
Clock/Control Registers (CCR)
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of the second, minute, hour, day, date, month, and year. The
RTC has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24 hour or AM/PM format. When the ISL12029 powers up
The Control/Clock Registers are located in an area separate
from the EEPROM array and are only accessible following a
slave byte of “1101111x” and reads or writes to addresses
[0000h:003Fh]. The clock/control memory map has memory
addresses from 0000h to 003Fh. The defined addresses are
described in Table 2. Writing to and reading from the
undefined addresses are not recommended.
after the loss of both V
and V , the clock will not
BAT
DD
operate until at least one byte is written to the clock register.
CCR Access
Reading the Real Time Clock
The contents of the CCR can be modified by performing a
byte or a page write operation directly to any address in the
CCR. Prior to writing to the CCR (except the status register),
however, the WEL and RWEL bits must be set using a three
step process (See “Writing to the Clock/Control Registers”
on page 15.)
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of the
Real Time Clock. The RTC Registers can then be read in a
Sequential Read Mode. Since the clock runs continuously
and read takes a finite amount of time, there is a possibility
that the clock could change during the course of a read
operation. In this device, the time is latched by the read
command (falling edge of the clock on the ACK bit prior to
RTC data output) into a separate latch to avoid time changes
during the read operation. The clock continues to run.
Alarms occurring during a read are unaffected by the read
operation.
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Writing to the Real Time Clock
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another section
The time and date may be set by writing to the RTC
registers. RTC Register should be written ONLY with Page
Write. To avoid changing the current time by an uncompleted
write operation, write to the all 8 bytes in one write operation.
When writing the RTC registers, the new time value is
loaded into a separate buffer at the falling edge of the clock
FN6206.9
August 12, 2010
10
ISL12029, ISL12029A
requires a new operation. A read or write can begin at any
address in the CCR.
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
ADDR
003Fh BAT AL1 AL0 OSCF
Default
7
6
5
4
3
0
0
2
1
0
RWEL WEL RTCF
0
0
0
0
0
0
1
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are
read by performing a sequential read. The read instruction
latches all Clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read of the CCR will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read of the CCR, the address remains at the previous
address +1 so the user can execute a current address read
of the CCR and continue reading the next Register.
BAT: Battery Supply
This bit set to “1” indicates that the device is operating from
, not V . It is a read-only bit and is set/reset by
hardware (ISL12029 internally). Once the device begins
operating from V , the device sets this bit to “0”.
DD
V
BAT
DD
AL1, AL0: Alarm Bits
These bits announce if either alarm 0 or alarm 1 match the
real time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the flags. Note: Only the AL bits that are set
when an SR read starts will be reset. An alarm bit that is set
by an alarm occurring during an SR read operation will
remain set after the read operation is complete.
Real Time Clock Registers (Volatile)
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21-bit) or
0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is
1 to 12, YR (Year) is 0 to 99.
OSCF: Oscillator Fail Indicator
This bit is set to "1" if the oscillator is not operating or is
operating but has clock jitter, which does not affect the
accuracy of RTC counting. The bit is set to "0" if the oscillator
is functioning and does not have clock jitter. This bit is read
only, and is set/reset by hardware.
DW: Day of the Week Register
This register provides a Day of the Week status and uses
three bits DY2 to DY0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as ‘0’.
RWEL: Register Write Enable Latch
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a non-volatile write cycle, so the device is ready
for the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specific sequence.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of
this device, there would be no real use for the value 19 in a
true real time clock, however.
WEL: Write Enable Latch
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the
LOW (disabled) state. While the WEL bit is LOW, writes to
the CCR address will be ignored, although acknowledgment
is still issued. The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register. Once
set, WEL remains set until either reset to 0 (by writing a “0”
to the WEL bit and zeroes to the other bits of the Status
Register) or until the part powers up again. Writes to WEL bit
do not cause a non-volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
24-Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21-bit functions as an AM/PM indicator with a ‘1’,
representing PM. The clock defaults to standard time with
H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4.
Status Register (SR) (Volatile)
RTCF: Real Time Clock Fail Bit
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
This bit is set to a “1” after a total power failure. This is a
read only bit that is set by hardware (ISL12029 internally)
when the device powers up after having lost all power to
FN6206.9
August 12, 2010
11
ISL12029, ISL12029A
the device (both V
regardless of whether V or V
of only one of the supplies does not set the RTCF bit to “1”.
On power-up after a total power failure, all registers are set
and V
go to 0V). The bit is set
BAT
to their default states and the clock will not increment until
at least one byte is written to the clock register. The first
valid write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is sufficient).
DD
is applied first. The loss
BAT
DD
TABLE 2. CLOCK/CONTROL MEMORY MAP
BIT
REG
ADDR.
TYPE
NAME
7
6
5
4
3
2
1
0
RANGE
003F
0037
0036
0035
0034
0033
0032
0031
0030
0014
0013
0012
0011
0010
Status
SR
Y2K
DW
YR
BAT
0
AL1
0
AL0
Y2K21
0
OSCF
Y2K20
0
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
01h
20h
00h
00h
00h
01h
00h
00h
00h
4Xh
00h
00h
00h
18h
01h
20h
00h
00h
00h
01h
00h
00h
00h
0Xh
00h
00h
00h
18h
RTC
(SRAM)
Y2K13
0
19/20
0-6
0
0
DY2
Y12
G12
D12
H12
M12
S12
VTS2
DTR2
ATR2
0
DY1
Y11
G11
D11
H11
M11
S11
VTS1
DTR1
ATR1
0
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
DT
G10
D10
H10
M10
S10
0
0
D21
H21
M21
S21
0
HR
MIL
0
0
MN
SC
M22
S22
BSW
0
0
Control
(EEPROM)
PWR
DTR
ATR
INT
BL
SBIB
0
VTS0
DTR0
ATR0
0
0
0
0
0
0
ATR5
AL0E
BP0
ATR4
FO1
WD1
ATR3
FO0
WD0
IM
BP2
AL1E
BP1
0
0
0
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Alarm1
(EEPROM)
Y2K1
0
0
0
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20
20h
00h
20h
00h
DWA1 EDW1
YRA1
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA1 EMO1
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
20h
00h
DTA1
EDT1
0
A1D21
A1H21
A1M21
A1S21
HRA1 EHR1
MNA1 EMN1
SCA1 ESC1
0
A1M22
A1S22
0
Alarm0
(EEPROM)
Y2K0
0
A0Y2K21 A0Y2K20 A0Y2K13
A0Y2K10 19/20
DWA0 EDW0
YRA0
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA0 EMO0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
DTA0
EDT0
A0D21
A0H21
A0M21
A0S21
HRA0 EHR0
MNA0 EMN0
SCA0 ESC0
0
A0M22
A0S22
NOTE: Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device
“Ordering Information on “” on page 3.
FN6206.9
August 12, 2010
12
ISL12029, ISL12029A
both bits are set to ‘1’ and both the FO1 and FO0 bits are set to
0 (F disabled).
Unused Bits:
OUT
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit location.
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
Alarm Registers (Non-Volatile)
“1”. The IRQ/F
output will now be pulsed each time an
OUT
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
In the case that both Alarm 0 and Alarm 1 are enabled, the
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
IRQ/F
pin will be pulsed each time either alarm matches
OUT
the RTC (both alarms can provide hardware interrupt). If the
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 15
and “Application Section” on page 23 for more information.
IM bit is also set to "1", the IRQ/F
of the alarms as well.
will be pulsed for each
OUT
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
BL Register
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
BP2, BP1, BP0 - Block Protect Bits
FO1
FO0
OUTPUT FREQUENCY
Alarm output (F disabled)
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
0
0
1
1
0
1
0
1
OUT
32.768kHz
4096Hz
1Hz
TABLE 3. BLOCK PROTECT BITS PARTITIONS
Oscillator Compensation Registers
PROTECTED ADDRESSES
There are two trimming options.
ISL12029
ARRAY LOCK
None
- ATR - Analog Trimming Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (Default)
- DTR - Digital Trimming Register
180 – 1FF
Upper 1/4
h
h
h
h
h
h
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110 ppm of
total adjustment.
100 – 1FF
Upper 1/2
h
000 – 1FF
Full Array
h
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
000 – 03F
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
h
000 – 07F
h
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
000 – 0FF
h
h
000 – 1FF
h
h
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
The effective on-chip series load capacitance, C
,
LOAD
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C is changed via two digitally
LOAD
enable or disable the alarm interrupt signal output (IRQ/F
).
OUT
controlled capacitors, C and C , connected from the X1
X1
X2
The interrupts are enabled when either the AL1E or AL0E or
FN6206.9
August 12, 2010
13
ISL12029, ISL12029A
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED FREQUENCY
PPM
DTR2
DTR1
DTR0
X1
X2
0
1
1
1
1
1
0
1
0
1
1
0
0
1
1
+30
0
C
C
X1
X2
CRYSTAL
OSCILLATOR
-10
-20
-30
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
FIGURE 12. DIAGRAM OF ATR
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
“RESET” on page 9 and “Power Control Operation” on
page 16.
and X2 pins to ground (see Figure 11). The value of C and
X1
C
is given by Equation 1:
X2
C
= (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
X
(EQ. 1)
The effective series load capacitance is the combination of
BSW: Power Control Bit
C
and C given in Equation 2:
X2
X1
The Power Control bit, BSW, determines the conditions for
1
switching between V
options.
and Back Up Battery. There are two
DD
----------------------------------
C
=
LOAD
1
1
⎛
⎞
---------- ----------
+
⎝
⎠
C
C
X2
X1
Option 1 Standard Mode: Set “BSW = 0” (default for
ISL12029A)
16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9
⎛
⎝
⎞
⎠
-----------------------------------------------------------------------------------------------------------------------------
C
=
pF
LOAD
2
(EQ. 2)
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
ISL12029)
For example, CLOAD(ATR = 00000) = 12.5pF,
(ATR = 100000) = 4.5pF, and C (ATR = 011111) =
C
LOAD
LOAD
See “Power Control Operation” on page 16 for more details.
Also see “I2C Communications During Battery Backup and
LVR Operation” on page 25 for important details.
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note
that these are typical values.
VTS2, VTS1, VTS0: V
Select Bits
RESET
The ISL12029 is shipped with a default V
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
threshold
DD
(V
) per the ordering information table. This register is
RESET
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12029 has four (4) additional
selectable levels to fit the customers application. Levels are:
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The V
selection is via 3 bits (VTS2, VTS1 and VTS0) (see Table 6).
RESET
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
Care should be taken when changing the V select bits.
RESET
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
If the V
voltage selected is higher than V , then the
DD
RESET
device will go into RESET and unless V
is increased, the
DD
device will no longer be able to communicate using the I2C
bus.
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED FREQUENCY
TABLE 6. V
SELECT BITS
RESET
DTR2
DTR1
DTR0
PPM
VTS2
VTS1
VTS0
V
(V)
RESET
4.64
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
+10
+20
4.38
FN6206.9
August 12, 2010
14
ISL12029, ISL12029A
TABLE 6. V
SELECT BITS
register are reset by the falling edge of the eighth clock of
RESET
status register read.
VTS2
VTS1
VTS0
V
(V)
RESET
3.09
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
0
0
1
1
1
0
0
1
0
2.92
1. Single Event Mode is enabled by setting the AL0E or
AL1E bit to “1”, the IM bit to “0”, and disabling the
2.63
frequency output. This mode permits a one-time match
between the alarm registers and the RTC registers. Once
this match occurs, the AL0 or AL1 bit is set to “1” and the
In battery mode, the RESET signal output is asserted LOW
when the V voltage supply has dipped below the V
threshold, but the RESET signal output will not return HIGH
DD
RESET
IRQ/F
output will be pulled low and will remain low
OUT
until the device is back to V mode even the V voltage is
DD
DD
until the AL0 or AL1 bit is read, which will automatically
resets it. Both Alarm registers can be set at the same time
above V
threshold.
RESET
to trigger alarms. The IRQ/F
output will be set by
OUT
Device Operation
either alarm, and will need to be cleared to enable
triggering by a subsequent alarm. Polling the SR will
reveal which alarm has been set.
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is
enabled by setting the AL0E or AL1E bit to “1” the IM bit
to “1”, and disabling the frequency output. If both AL0E
and AL1E bits are set to "1", then both AL0E and AL1E
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
PIM alarms will function. The IRQ/F
output will now
OUT
be pulsed each time each of the alarms occurs. This
means that once the interrupt mode alarm is set, it will
continue to alarm for each occurring match of the alarm
and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications
such as security cameras or utility meter reading.
Interrupt Mode CANNOT be used for general periodic
alarms, however, since a specific time period cannot be
programmed for interrupt, only matches to a specific time
of day. The interrupt mode is only stopped by disabling
the IM bit or the Alarm Enable bits.
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
Writing to the Alarm Registers
The Alarm Registers are non-volatile but require special
attention to insure a proper non-volatile write takes place.
Specifically, byte writes to individual registers are good for all
but registers 0006h and 0000Eh, which are the DWA0 and
DWA1 registers, respectively. Those registers will require a
special page write for non-volatile storage. The
much shorter cycle time (t = t
). Writes to undefined areas
BUF
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
recommended page write sequences are as follows:
1. 16-byte page writes: The best way to write or update the
Alarm Registers is to perform a 16-byte write beginning at
address 0001h (MNA0) and wrapping around and ending
at address 0000h (SCA0). This will insure that
non-volatile storage takes place. This means that the
code must be designed so that the Alarm0 data is written
starting with Minutes register, and then all the Alarm1
data, with the last byte being the Alarm0 Seconds (the
page ends at the Alarm1 Y2k register and then wraps
around to address 0000h).
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by either a hardware
interrupt (the IRQ/F
pin) or by polling the Status Register
Alternatively, the 16-byte page write could start with
address 0009h, wrap around and finish with address
0008h. Note that any page write ending at address
0007h or 000Fh (the highest byte in each Alarm) will not
trigger a non-volatile write, so wrapping around or
OUT
(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and
AL0 for Alarm 0), indicate if an alarm has happened. The bits
are set on an alarm condition regardless of whether the IRQ/
F
interrupt is enabled. The AL1 and AL0 bits in the status
OUT
FN6206.9
August 12, 2010
15
ISL12029, ISL12029A
overlapping to the following Alarm's Seconds register is
advised.
prevented since the battery backup input will only be used
when the V supply is shut off.
DD
2. Other non-volatile writes: It is possible to do writes of
less than an entire page, but the final byte must always
be addresses 0000h through 0004h or 0008h though
000Ch to trigger a non-volatile write. Writing to those
blocks of 5 bytes sequentially, or individually, will trigger a
non-volatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to
overlap with the other Alarm register and trigger the
non-volatile write. For Example, if the DWA0 register is
being set, then the code can start with a multiple byte
write beginning at address 0006h, and then write 3 bytes
ending with the SCA1 register as follows:
To select Option 1, BSW bit in the Power Register must be
set to “BSW = 0”. A description of power switchover follows.
Standard Mode Power Switchover
• Normal Operating Mode (V ) to Battery Backup Mode
DD
(V
)
BAT
To transition from the V
to V
mode, both of the
DD
BAT
following conditions must be met:
- Condition 1:
V
< V
- V
DD
BAT BATHYS
where V
≈ 50mV
BATHYS
Addr Name
0006h DWA0
0007h Y2K0
0008h SCA1
- Condition 2:
V
< V
DD
TRIP
TRIP
where V
≈ 2.2V
• Battery Backup Mode (V
) to Normal Mode (V
)
BAT
DD
If the Alarm1 is used, SCA1 would need to have the correct
data written.
The ISL12029 device will switch from the V
to V mode
DD
BAT
when one of the following conditions occurs:
Power Control Operation
- Condition 1:
The power control circuit accepts a V
and a V
input.
BAT
DD
V
> V
+ V
DD
BAT BATHYS
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
where V
≈ 50mV
BATHYS
- Condition 2:
V
> V
+ V
DD
TRIP TRIPHYS
where V
≈ 30mV
TRIPHYS
to use a SuperCap for applications where V
is interrupted
DD
for up to a month. See “Application Section” on page 23 for
more information.
There are two discrete situations that are possible when using
Standard Mode: V < V and V > V . These two
BAT
TRIP
BAT
TRIP
power control situations are illustrated in Figures 13 and 14.
There are two options for setting the change-over conditions
from V to Battery back-up mode. The BSW bit in the PWR
DD
register controls this operation.
BATTERY
BACKUP
MODE
Option 1 - Standard Mode (Default for ISL12029A)
Option 2 - Legacy Mode (Default for ISL12029)
V
DD
V
TABLE 7. V
TRIP POINT WITH DIFFERENT BSW SETTING
TRIP
BAT
2.2V
1.8V
V
BAT
V
TRIP POINT
(V)
BAT
BSW BIT
POWER CONTROL SETTING
V
+ V
BATHYS
BAT
V
- V
BATHYS
BAT
0
1
2.2
Standard Mode (ISL12029A)
Legacy Mode (ISL12029)
V
< V
BAT
DD
FIGURE 13. BATTERY SWITCHOVER WHEN V
< V
TRIP
BAT
Note that applications that have V
> V
will require the
BAT
DD
ISL12029A (standard mode) for proper startup. Note that the
I2C bus may or may not be operational during battery
backup, that function is controlled by the SBIB bit. That
operation is covered after the power control section.
OPTION 1 - STANDARD POWER CONTROL MODE
(DEFAULT FOR ISL12029A)
In the Standard mode, the supply will switch over to the
battery when V
drops below VTRIP or VBAT, whichever is
DD
lower. In this mode, accidental operation from the battery is
FN6206.9
August 12, 2010
16
ISL12029, ISL12029A
Power-on Reset
Application of power to the ISL12029 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
BATTERY BACKUP
MODE
V
DD
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
V
BAT
3.0V
2.2V
V
TRIP
- It prevents the processor from operating prior to
stabilization of the oscillator.
V
V
+ V
TRIP
TRIP
TRIPHYS
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
FIGURE 14. BATTERY SWITCHOVER WHEN V
> V
TRIP
BAT
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT FOR ISL12029)
When V
exceeds the device V
threshold value for
DD
RESET
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V to V is simply done by
comparing the voltages and the device operates from
DD
BAT
whichever is the higher voltage. Care should be taken when
NOTE: If the V
voltage drops below the data sheet
BAT
changing from Normal to Legacy Mode. If the V
voltage is
minimum of 1.8V and the V
power cycles to 0V then back
BAT
DD
higher than V , then the device will enter battery backup and
DD
unless the battery is disconnected or the voltage decreases,
to V voltage, then the RESET output may stay low and the
DD
I2C communications will not operate. The V
and V
DD
BAT
the device will no longer operate from V . If that is the
DD
power will need to be cycled to 0V together to allow normal
operation again.
situation on initial power-up, then I2C communication may not
be possible. For these applications, the ISL12029A should be
used.
Watchdog Timer Operation
The Watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set to
3 different time-out periods or off. When the Watchdog timer
is set to off, the Watchdog circuit is configured for low power
operation (see Table 8).
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1.”
• Normal Mode (V ) to Battery Backup Mode (V
)
BAT
DD
To transition from the V
to V mode, the following
BAT
DD
TABLE 8. WATCHDOG TIMER OPERATION
conditions must be met:
WD1
WD0
DURATION
disabled
250ms
V
< V - V
DD
BAT
BATHYS
1
1
0
0
1
0
1
0
• Battery Backup Mode (V
) to Normal Mode (V
)
BAT
DD
The device will switch from the V
following condition occurs:
to V
mode when the
DD
BAT
750ms
1.75s
V
> V
+V
DD
BAT BATHYS
Watchdog Timer Restart
The Legacy Mode power control conditions are illustrated in
Figure 15.
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
V
DD
VOLTAGE
ON
V
BAT
IN
OFF
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
In battery mode, the Watchdog timer function is disabled.
FN6206.9
August 12, 2010
17
ISL12029, ISL12029A
START CONDITION
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
compares the level of the V line versus a preset threshold
DD
voltage (V
), then generates a RESET pulse if it is
RESET
below V
. The reset pulse will time-out 250ms after the
RESET
V
V
line rises above V
. If the V remains below
RESET DD
DD
, then the RESET output will remain asserted low.
RESET
STOP CONDITION
Power-up and power-down waveforms are shown in
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 17).
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V = 1.0V.
DD
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I2C Communications During Battery
Backup and LVR Operation” on page 25.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data
(refer to Figure 18).
In battery mode, the RESET signal output is asserted LOW
when the V
voltage supply has dipped below the V
RESET
DD
The device will respond with an acknowledge after recognition
of a start condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent 8-bit word.
The device will not acknowledge if the slave address byte is
incorrect.
threshold. The RESET signal output will not return HIGH
until the device is back to V mode even the V voltage is
DD
DD
above V
threshold.
RESET
Serial Communication
The device supports the I2C bidirectional serial bus protocol.
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
STOP
START
FIGURE 17. VALID START AND STOP CONDITIONS
FN6206.9
August 12, 2010
18
ISL12029, ISL12029A
SCL FROM
MASTER
8
9
1
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
In the read mode, the device will transmit 8 bits of data,
release the SDA line, then monitor the line for an
operation is selected. A zero selects a write operation (refer
to Figure 19).
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
After loading the entire Slave Address Byte from the SDA
bus, the ISL12029 compares the device identifier and device
select bits with ‘1010111’ or ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the SDA
line.
Following the Slave Byte is a two byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up the internal
address counter is set to address 0h, so a current address
read of the EEPROM array starts at address 0. When
required, as part of a random read, the master must supply
the 2 Word Address Bytes as shown in Figure 19.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4 bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
DEVICE IDENTIFIER
SLAVE ADDRESS BYTE
ARRAY
CCR
1
1
0
1
1
0
0
1
1
0
1
1
0
R/W
A8
BYTE 0
WORD ADDRESS 1
BYTE 1
0
0
0
0
0
WORD ADDRESS 0
BYTE 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
DATA BYTE
BYTE 3
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
FN6206.9
August 12, 2010
19
ISL12029, ISL12029A
RTC registers require a page write (8 bytes), individual register
Write Operations
writes are not allowed. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation. See
“Writing to the Clock/Control Registers” on page 15.)
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/Control
Registers” on page 15. Upon receipt of each address byte,
the ISL12029 responds with an acknowledge. After receiving
both address bytes the ISL12029 awaits the eight bits of
data. After receiving the 8 data bits, the ISL12029 again
responds with an acknowledge. The master then terminates
the transfer by generating a stop condition. The ISL12029
then begins an internal write cycle of the data to the
non-volatile memory. During the internal write cycle, the
device inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance (see Figure 20).
After the receipt of each byte, the ISL12029 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time (refer to Figure 21).The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12029 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 22 for the address,
acknowledge and data transfer sequence.
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12029 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 15 for more information.
Stops and Write Modes
Stop conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12029 resets itself without performing the write. The
contents of the array are not affected.
Page Write
The ISL12029 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is transferred,
the master can transmit up to 15 more bytes to the memory
array and up to 7 more bytes to the clock/control registers. The
S
T
A
R
T
SIGNALS FROM
THE MASTER
S
T
O
P
WORD
ADDRESS 1
WORD
ADDRESS 0
SLAVE
ADDRESS
DATA
SDA BUS
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIGURE 20. BYTE WRITE SEQUENCE
FN6206.9
August 12, 2010
20
ISL12029, ISL12029A
6 BYTES
6 BYTES
ADDRESS
10
ADDRESS = 5
ADDRESS
15
ADDRESS POINTER ENDS
AT ADDR = 5
FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
.
1 ≤ n ≤ 16 FOR EEPROM ARRAY
1 ≤ n ≤ 8 FOR CCR
S
T
SIGNALS FROM
THE MASTER
S
T
O
P
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS 1
WORD
ADDRESS 0
DATA
(1)
DATA
(n)
SDA BUS
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIGURE 22. PAGE WRITE SEQUENCE
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. Refer to Figure 23 for the address, acknowledge,
and data transfer sequence.
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12029 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12029 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12029 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
S
S
T
O
P
T
A
R
T
SIGNALS FROM
THE MASTER
SLAVE
ADDRESS
SDA BUS
1
1 1 1 1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12029 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power-up, the 16-bit address is initialized to 0h. In this way, a
current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12029 issues an
acknowledge, then transmits 8 data bits. The master
FN6206.9
August 12, 2010
21
ISL12029, ISL12029A
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 25 for the address,
acknowledge, and data transfer sequence.
ISSUE START
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
ISSUE STOP
NO
NO
ACK
RETURNED?
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 25. The ISL12029 then goes
into standby mode after the stop and all bus activity will be
ignored until a start is detected. This operation loads the new
address into the address counter. The next Current Address
Read operation will read from the newly loaded address.
This operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
YES
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
ISSUE STOP
YES
Sequential Read
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
PROCEED
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space the counter “rolls over” to the start of the
address space and the ISL12029 continues to output data
for each acknowledge received. Refer to Figure 26 for the
acknowledge and data transfer sequence.
It should be noted, that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
Random read operations allow the master to access any
location in the ISL12029. Prior to issuing the Slave Address
FN6206.9
August 12, 2010
22
ISL12029, ISL12029A
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SIGNALS FROM
THE MASTER
SLAVE
ADDRESS
WORD
ADDRESS 0
SLAVE
ADDRESS
WORD
ADDRESS 1
SDA BUS
1
1 1 1 1
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 25. RANDOM ADDRESS READ SEQUENCE
S
T
O
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE MASTER
SDA BUS
1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
(2)
DATA
(n - 1)
DATA
(1)
DATA
(n)
(n IS ANY INTEGER GREATER THAN 1)
FIGURE 26. SEQUENTIAL READ SEQUENCE
devices include on-chip load capacitor trimming. This control
is handled by the Analog Trimming Register, or ATR, which
has 6 bits of control. The load capacitance range covered by
the ATR circuit is approximately 3.25pF to 18.75pF, in
0.25pF increments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-circuit
tests with commercially available crystals demonstrate that
this range of capacitance allows frequency control from
+116ppm to -37ppm, using a 12.5pF load crystal.
Application Section
Crystal Oscillator and Temperature Compensation
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over-temperature and
enable very high accuracy time keeping (<5ppm drift).
The Intersil RTC family uses an oscillator circuit with on-chip
crystal compensation network, including adjustable
load-capacitance. The only external component required is
the crystal. The compensation network is optimized for
operation with certain crystal parameters, which are
common in many of the surface mount or tuning-fork crystals
available today. Table 9 summarizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature
is available for the Intersil RTC family. There are 3 bits
known as the Digital Trimming Register or DTR, and they
operate by adding or skipping pulses in the clock signal. The
range provided is ±30ppm in increments of 10ppm. The
default setting is 0ppm. The DTR control can be used for
coarse adjustments of frequency drift over-temperature or
for crystal initial accuracy correction.
Table 10 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil RTC
products.
The turnover-temperature in Table 9 describes the
temperature where the apex of the of the drift vs temperature
curve occurs. This curve is parabolic with the drift increasing
as (T-T0)2. For an Epson MC-405 device, for example, the
turnover-temperature is typically +25°C, and a peak drift of
>110ppm occurs at the temperature extremes of -40 and
+85°C. It is possible to address this variable drift by adjusting
the load capacitance of the crystal, which will result in
predictable change to the crystal frequency. The Intersil RTC
family allows this adjustment over-temperature since the
FN6206.9
August 12, 2010
23
ISL12029, ISL12029A
TABLE 9. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs
PARAMETER
MIN
TYP
MAX
UNITS
kHz
ppm
°C
NOTES
Frequency
32.768
Frequency Tolerance
±100
30
Down to 20ppm if desired
Turnover-Temperature
20
25
Typically the value used for most crystals
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
°C
12.5
pF
50
kΩ
For best oscillator performance
TABLE 10. CRYSTAL MANUFACTURERS
PART NUMBER
+25°C FREQUENCY
TEMP RANGE
TOLERANCE
(ppm)
MANUFACTURER
(°C)
Citizen
Epson
Raltron
SaRonix
Ecliptek
ECS
CM201, CM202, CM200S
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-10 to +60
-10 to +60
-40 to +85
±20
±20
±20
±20
±20
±20
±20
MC-405, MC-406
RSM-200S-A or B
32S12A or B
ECPSM29T-32.768K
ECX-306/ECX-306I
FSM-327
Fox
A final application for the ATR control is in-circuit calibration
for high accuracy applications, along with a temperature
sensor chip. Once the RTC circuit is powered up with battery
C1
0.1µF
backup, the IRQ/F
output is set at 32.768kHz and
OUT
frequency drift is measured. The ATR control is then
adjusted to a setting which minimizes drift. Once adjusted at
a particular temperature, it is possible to adjust at other
discrete temperatures for minimal overall drift, and store the
resulting settings in the EEPROM. Extremely low overall
temperature drift is possible with this method. The Intersil
evaluation board contains the circuitry necessary to
implement this control.
R1 10k
U1
XTAL
32.768kGz
ISL12029
FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN
SO-14
Layout Considerations
The X1 and X2 connections to the crystal are to be kept as
short as possible. A thick ground trace around the crystal is
advised to minimize noise intrusion, but ground near the X1
and X2 pins should be avoided as it will add to the load
capacitance at those pins. Keep in mind these guidelines for
other PCB layers in the vicinity of the RTC device. A small
The crystal input at X1 has a very high impedance and will
pick up high frequency signals from other circuits on the
board. Since the X2 pin is tied to the other side of the crystal,
it is also a sensitive node. These signals can couple into the
oscillator circuit and produce double clocking or misclocking,
seriously affecting the accuracy of the RTC. Care needs to
be taken in layout of the RTC circuit to avoid noise pickup.
Figure 27 shows a suggested layout for the ISL12029
device.
decoupling capacitor at the V pin of the chip is mandatory,
DD
with a solid connection to ground.
For other RTC products, the same rules stated above should
be observed, but adjusted slightly since the packages and
pinouts are slightly different.
FN6206.9
August 12, 2010
24
ISL12029, ISL12029A
V
. This makes it possible to generate alarms and
Oscillator Measurements
TRIP
communicate with the device under battery backup, but the
supply current drain is much higher than the Standard mode
and backup time is reduced. In this case if alarms are used
When a proper crystal is selected and the layout guidelines
above are observed, the oscillator should start-up in most
circuits in less than one second. Some circuits may take slightly
longer, but start-up should definitely occur in less than 5s.
When testing RTC circuits, the most common impulse is to
apply a scope probe to the circuit at the X2 pin (oscillator
output) and observe the waveform. DO NOT DO THIS!
Although in some cases you may see a usable waveform, due
to the parasitics (usually 10pF to ground) applied with the
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillating. The
X2 output is sensitive to capacitive impedance so the voltage
levels and the frequency will be affected by the parasitic
elements in the scope probe. Applying a scope probe can
possibly cause a faulty oscillator to start-up, hiding other issues
(although in the Intersil RTCs, the internal circuitry assures
start-up when using the proper crystal and layout).
in backup mode, the IRQ/F
pull-up resistor must be
OUT
connected to V
voltage source. During initial power-up
BAT
the default mode is the Standard mode.
V
V
BAT
2.7V TO 5.5V
DD
SUPERCAPACITOR
V
SS
FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT
I2C Communications During Battery Backup and
LVR Operation
The best way to analyze the RTC circuit is to power it up and
read the real time clock as time advances, or if the chip has
Operation in Battery Backup mode and LVR is affected by
the BSW and SBIB bits as described earlier. These bits allow
flexible operation of the serial bus and EEPROM in battery
backup mode, but certain operational details need to be
clear before utilizing the different modes. The most
significant detail is that once VDD goes below VRESET, then
I2C communications cease regardless of whether the device
is programmed for I2C operation in battery backup mode.
the IRQ/F
output, look at the output of that pin on an
OUT
oscilloscope (after enabling it with the control register, and
using a pull-up resistor for the open-drain output).
Alternatively, the ISL12029 IRQ/F
- output can be
OUT
checked by setting an alarm for each minute. Using the
pulse interrupt mode setting, the once-per-minute interrupt
functions are an indication of proper oscillation.
Table 11 describes 4 different modes possible with using the
BSW and SBIB bits, and how they are affect LVR and battery
backup operation.
Backup Battery Operation
Many types of batteries can be used with the Intersil RTC
products. 3.0V or 3.6V Lithium batteries are appropriate, and
sizes are available that can power a Intersil RTC device for up
to 10 years. Another option is to use a supercapacitor for
• Mode A - In this mode, selection bits indicate a low VDD
switchover combined with I2C operation in battery backup
mode. In actuality the VDD will go below V
before
RESET
switching to battery backup, which will disable I2C
applications where V may disappear intermittently for short
DD
ANYTIME the device goes into battery backup mode.
Regardless of the battery voltage, the I2C will work down
periods of time. Depending on the value of supercapacitor
used, backup time can last from a few days to two weeks (with
>1F). A simple silicon or Schottky barrier diode can be used in
to the V
voltage (see Figure 29).
RESET
• Mode B - In this mode, the selection bits indicate
series with V to charge the supercapacitor, which is
DD
switchover to battery backup at V <V , and I2C
DD BAT
connected to the V
pin. Try to use Schottky diodes with
BAT
communications in battery backup. In order to
very low leakages, <1µA desirable. Do not use the diode to
charge a battery (especially lithium batteries!).
communicate in battery backup mode, the V
must be less than the VBAT voltage AND V
voltage
must be
. Also, pull-ups on the I2C bus pins
RESET
DD
greater than V
Note that whether a battery or supercap is used, if the V
RESET
BAT
must go to V
to communicate. This mode is the same
BAT
voltage drops below the data sheet minimum of 1.8V and the
power cycles to 0V then back to V voltage, then the
as the normal operating mode of the X1228 device
V
DD
DD
RESET output may stay low and the I2C communications will
not operate. The V and V power will need to be cycled
• Mode C - In this mode, the selection bits indicate a low
VDD switchover combined with no communications in
battery backup. Operation is actually identical to Mode A
BAT
DD
to 0V together to allow normal operation again.
with I2C communications down to V = V
, then no
DD
RESET
communications (see Figure 29).
There are two possible modes for battery backup operation,
Standard and Legacy mode. In Standard mode, there are no
operational concerns when switching over to battery backup
since all other devices functions are disabled. Battery drain
• Mode D - In this mode, the selection bits indicate
switchover to battery backup at V <V , and no I2C
communications in battery backup. This mode is unique in
that there is I2C communication as long as VDD is higher
DD BAT
is minimal in Standard mode, and return to Normal V
DD
than V
or V , whichever is greater. This mode is
powered operation is predictable. In Legacy modes the V
RESET
BAT
BAT
the safest for guaranteeing I2C communications only when
there is a Valid V (see Figure 30).
pin can power the chip if the voltage is above V and
DD
DD
FN6206.9
August 12, 2010
25
ISL12029, ISL12029A
TABLE 11. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (SHADED ROW IS SAME AS X1228 OPERATION)
V
I2C ACTIVE IN EE PROM WRITE/
BAT
SBIB
BIT
BSW
BIT
SWITCHOVER
VOLTAGE
BATTERY
BACKUP?
READ IN BATTERY
BACKUP?
FREQ/IRQ
ACTIVE?
MODE
NOTES
A
0
0
Standard Mode,
NO
NO
YES
Operation of I2C bus down to
V
= 2.2V typ
V
= V
, then below that no
TRIP
DD
RESET
Default for
ISL12029A
communications. Battery switchover
at V
.
TRIP
B
0
1
Legacy Mode,
< V
Default for
YES, only if
> V
BAT RESET
YES
YES
Operation of I2C bus into battery
backup mode, but only for
(X1228
mode)
V
V
DD
BAT
V
> V > V
.
BAT
DD
RESET
ISL12029
Bus must have pull-ups to V . No
BAT
nonvolatile writes with V
>V
BAT DD
C
D
1
1
0
1
Standard Mode,
NO
NO
NO
NO
YES
YES
Operation of I2C bus down to
V = V , then below that no
DD
V
= 2.2V typ
TRIP
RESET
communications. Battery switchover
at V
.
TRIP
Legacy Mode,
Operation of I2C bus down to V
RESET
V
< V
or V , whichever is higher.
BAT
DD
BAT
V
(3.0V)
BAT
V
DD
V
(2.63V)
RESET
V
TRIP
(2.2V)
tPURST
RESET
I2C BUS ACTIVE
I
(BATTERY BACKUP MODE)
BAT
(V
POWER, V
NOT CONNECTED)
BAT
DD
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
FN6206.9
August 12, 2010
26
ISL12029, ISL12029A
V
(3.0V)
BAT
V
DD
V
(2.63V)
RESET
V
TRIP
(2.2V)
t
PURST
RESET
I2C BUS ACTIVE
I
(BATTERY BACKUP MODE)
BAT
FIGURE 30. RESET OPERATION IN MODE D
Alarm Operation Examples
BIT
ALARM0
REGISTER 7
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
6
5
4
3
2
1
0
HEX
DESCRIPTION
MOA0
1
0
0
0
0
0
0
1
81h Month set to 1,
enabled
EXAMPLE 1
Alarm 0 set with single interrupt (IM = ”0”)
DWA0
0
0
0
0
0
0
0
0
00h Day of week
disabled
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
B. Also the AL0E bit must be set as follows:
BIT
BIT
ALARM0
REGISTER 7
CONTROL
REGISTER
6
0
0
5
0
1
4
0
1
3
0
0
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
7
6
5
4
3
2
1
0
HEX DESCRIPTION
SCA0
MNA0
0
1
00h Seconds disabled
INT
0
0
1
0
0
0
0
0
x0h Enable Alarm
B0h Minutes set to 30,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/F
low.
HRA0
DTA0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
91h Hours set to 11,
enabled
output
OUT
81h Date set to 1,
enabled
FN6206.9
August 12, 2010
27
ISL12029, ISL12029A
EXAMPLE 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm 0 registers as follows:
BIT
ALARM0
REGISTER 7
6
5
4
3
2
1
0 HEX
DESCRIPTION
SCA0
1
0
1
1
0
0
0
0
B0h Seconds set to 30,
enabled
MNA0
HRA0
DTA0
MOA0
DWA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h Minutes disabled
00h Hours disabled
00h Date disabled
00h Month disabled
00h Day of week disabled
B. Set the Interrupt register as follows:
BIT
CONTROL
REGISTER 7
6
5
4
3
2
1
0 HEX
DESCRIPTION
INT
1
0
1
x
x
0
0
0
x0h Enable Alarm and Int
Mode
XX indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ/F
:
OUT
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
FN6206.9
August 12, 2010
28
ISL12029, ISL12029A
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A
3
6
DETAIL"A"
0.22±0.03
D
14
8
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
(0.35) x 45°
4° ± 4°
5
0.31-0.51
0.25M C A-B D
B
3
6
TOP VIEW
0.10 C
H
1.75 MAX
1.25 MIN
0.25
GAUGE PLANE
SEATING PLANE
C
0.10-0.25
1.27
0.10 C
SIDE VIEW
DETAIL "A"
(1.27)
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
(1.50)
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6206.9
August 12, 2010
29
ISL12029, ISL12029A
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN6206.9
August 12, 2010
30
相关型号:
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