ISL12025IVZ_技术文档

ISL12025

®

New Features

October 18, 2006

Data Sheet

FN6371.1

Real-Time Clock/Calendar with EEPROM

Features

The ISL12025 device is a low power real-time clock with

timing and crystal compensation, clock/calender, 64-bit

unique ID, power-fail indicator, two periodic or polled alarms,

intelligent battery backup switching, CPU Supervisor and

integrated 512 x 8-bit EEPROM, in a 16 Bytes per page

format.

• Real-Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• 64-bit Unique ID

• Two Non-Volatile Alarms

- Settable on the Second, Minute, Hour, Day of the Week,

Day, or Month

The oscillator uses an external, low-cost 32.768kHz crystal.

The real-time clock tracks time with separate registers for

hours, minutes, and seconds. The device has calendar

registers for date, month, year and day of the week. The

calendar is accurate through 2099, with automatic leap year

correction.

- Repeat Mode (periodic interrupts)

• Automatic Backup to Battery or SuperCap

• On-Chip Oscillator Compensation

- Internal Feedback Resistor and Compensation

Capacitors

Ordering Information

- 64 Position Digitally Controlled Trim Capacitor

PART

NUMBER

(Note)

TEMP.

RANGE PACKAGE DWG.

(°C) (Pb-Free)

PKG.

- 6 Digital Frequency Adjustment Settings to ±30ppm

PART

MARKING VOLTAGE

V

RESET

• 512 x 8 Bits of EEPROM

#

- 16-Bytes Page Write Mode (32 total pages)

- 8 Modes of Block Lock™ Protection

- Single Byte Write Capability

ISL12025IBZ 12025IBZ

ISL12025IVZ 2025IVZ

2.63V

-40 to +85 8 Ld SOIC M8.15

-40 to +85 8 Ld TSSOP M8.173

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

• High Reliability

- Data Retention: 50 years

- Endurance: 2,000,000 Cycles Per Byte

2

• I C* Interface

- 400kHz Data Transfer Rate

Add “-T” suffix for tape and reel.

• 800nA Battery Supply Current

Pinouts

• Package Options

- 8 Ld SOIC and 8 Ld TSSOP Packages

ISL12025

(8 LD SOIC)

TOP VIEW

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

V

X1

X2

DD

1

2

8

7

6

5

BAT

• Utility Meters

SCL

SDA

RESET

GND

• Audio/Video Components

• Modems

3

4

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

ISL12025

(8 LD TSSOP)

TOP VIEW

V

BAT

SCL

1

2

8

7

6

5

• POS Equipment

V

SDA

DD

X1

X2

• Test Meters/Fixtures

GND

3

4

RESET

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/Automotive

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

2

All other trademarks mentioned are the property of their respective owners.

ISL12025

Block Diagram

OSC Compensation

Frequency

X1

X2

Timer

Calendar

Logic

Battery

Switch

Circuitry

Time

V

DD

1Hz

Oscillator

32.768kHz

Keeping

Registers

(SRAM)

Divider

BAT

Status

Control/

Registers

(EEPROM)

Control

Decode

Logic

Compare

Serial

Interface

Decoder

Registers

SCL

SDA

Alarm

(SRAM)

Alarm Regs

(EEPROM)

8

4k

EEPROM

ARRAY

Watchdog

Timer

Low Voltage

Reset

RESET

Pin Descriptions

PIN NUMBER

SOIC

TSSOP

SYMBOL

BRIEF DESCRIPTION

1

3

X1

The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

2

3

4

5

X2

The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal.

RESET

RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period

has expired or that the voltage has dropped below a fixed V

threshold. It is an open drain active LOW

TRIP

output. Recommended value for the pull-up resistor is 5kΩ, If unused, connect to ground.

4

5

6

7

GND

SDA

Ground.

Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an

open drain output and may be wire OR’ed with other open drain or open collector outputs.

6

7

8

1

2

SCL

The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on

this pin is always active (not gated).

V

This input provides a backup supply voltage to the device. V

supplies power to the device in the event

BAT

that the V

supply fails. This pin should be tied to ground if not used.

DD

V

Power Supply.

DD

FN6371.1

October 18, 2006

2

ISL12025

Absolute Maximum Ratings

Thermal Information

Voltage on V , V

, SCL, SDA, and RESET pins

Thermal Resistance (Note 2)

θ

(°C/W)

DD BAT

JA

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on X1 and X2 pins

8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .

8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . .

120

140

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C

ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV

ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C

*CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and

X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.

2. θJ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

A

DC Electrical Specifications Unless otherwise noted, V = +2.7V to +5.5V, T = -40°C to +85°C, Typical values are at T = +25°C

DD

A

and V

= 3.3V

DD

SYMBOL

PARAMETER

Main Power Supply

Backup Power Supply

CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

DD

V

1.8

5.5

V

BAT

Electrical Specifications

SYMBOL

PARAMETER

CONDITIONS

= 2.7V

MIN

TYP

MAX

UNIT

NOTES

2

I

Supply Current with I C Active

V

500

800

2.5

µA

mA

µA

nA

3, 4, 5

DD1

DD2

DD3

DD

BAT

V

= 5.5V

Supply Current for Non-Volatile

Programming

V

= 2.7V

= 5.5V

3, 4, 5

, 3

3.5

Supply Current for Main

Timekeeping (Low Power Mode)

= V

= 2.7V

= 5.5V

10

5

SDA

SCL

20

I

Battery Supply Current

V

= 1.8V,

SDA

800

850

1000

3, 6, 7

BAT

= V

= 0V

DD

SCL

V

= 3.0V,

1200

nA

BAT

DD

= V

= 0V

SDA

I

Battery Input Leakage

V

= 5.5V, V = 1.8V

BAT

-100

1.8

100

2.6

nA

V

BATLKG

DD

V

Mode Threshold

Hysteresis

2.2

30

50

7

TRIP

BAT

V

mV

V/ms

7, 10

8

TRIPHYS TRIP

V

Hysteresis

BAT

BATHYS

V

Negative Slew rate

DD

10

DD SR-

RESET OUTPUT

V

Output Low Voltage

V

= 5.5V

0.4

400

V

OL

DD

= 3mA

I

OL

V

= 2.7V

DD

= 1mA

I

OL

I

Output Leakage Current

V

= 5.5V

100

nA

LO

DD

= 5.5V

OUT

FN6371.1

October 18, 2006

3

ISL12025

Watchdog Timer/Low Voltage Reset Parameters

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 5)

MAX

UNITS

ns

NOTES

t

V

Detect to RESET LOW

DD

500

250

9

RPD

t

Power-up Reset Time-Out Delay

100

1.0

400

ms

PURST

V

Minimum V

Output

for Valid RESET

DD

V

RVALID

V

ISL12025-4.5A Reset Voltage

Level

4.59

4.64

4.69

V

RESET

ISL12025 Reset Voltage Level

ISL12025-3 Reset Voltage Level

4.33

3.04

2.87

4.38

3.09

2.92

4.43

3.14

2.97

V

ISL12025-2.7A Reset Voltage

Level

ISL12025-2.7 Reset Voltage Level

Watchdog Timer Period

2.58

1.70

725

225

2.63

1.75

750

250

2.68

1.801

775

V

s

t

32.768kHz crystal between X1 and

X2

WDO

ms

275

t

Watchdog Timer Reset Time-Out 32.768kHz crystal between X1 and

275

RST

Delay

X2

2

t

I C Interface Minimum Restart

1.2

μs

RSP

Time

EEPROM SPECIFICATIONS

EEPROM Endurance

2,000,000

50

Cycles

Years

EEPROM Retention

Temperature ≤75°C

2

Serial Interface (I C) Specifications

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

V

SDA, and SCL Input Buffer LOW

Voltage

SBIB = 1 (Under V

mode)

-0.3

0.3 x V

DD

V

IL

DD

V

SDA, and SCL Input Buffer HIGH SBIB = 1 (Under V

Voltage

0.7 x V

V + 0.3

DD

V

IH

DD

Hysteresis SDA and SCL Input Buffer

Hysteresis

SBIB = 1 (Under V

0.05 x V

DD

V

I

SDA Output Buffer LOW Voltage

Input Leakage Current on SCL

I/O Leakage Current on SDA

I

= 4mA

= 5.5V

0

0.4

V

OL

V

0.1

10

μA

LI

IN

I

LO

TIMING CHARACTERISTICS

SCL Frequency

Pulse Width Suppression Time at Any pulse narrower than the max

f

400

50

kHz

ns

SCL

t

IN

SDA and SCL Inputs spec is suppressed.

t

SCL Falling Edge to SDA Output SCL falling edge crossing 30% of

Data Valid , until SDA exits the 30% to

900

ns

AA

V

DD

70% of V

window.

DD

t

Time the Bus Must Be Free before SDA crossing 70% of V

the Start of a New Transmission

during a

1300

BUF

DD

STOP condition, to SDA crossing

70% of V during the following

DD

START condition.

FN6371.1

October 18, 2006

4

ISL12025

2

Serial Interface (I C) Specifications (Continued)

SYMBOL

PARAMETER

Clock LOW Time

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

t

Measured at the 30% of V

crossing.

1300

ns

LOW

DD

t

Clock HIGH Time

Measured at the 70% of V

crossing.

600

ns

HIGH

t

START Condition Setup Time

START Condition Hold Time

SCL rising edge to SDA falling

edge. Both crossing 70% of V

SU:STA

HD:STA

.

DD

From SDA falling edge crossing

30% of V to SCL falling edge

t

DD

crossing 70% of V

.

DD

From SDA exiting the 30% to 70%

of V window, to SCL rising edge

Input Data Setup Time

Input Data Hold Time

100

0

ns

SU:DAT

HD:DAT

SU:STO

HD:STO

DD

crossing 30% of V

.

DD

From SCL falling edge crossing

70% of V to SDA entering the

t

DD

30% to 70% of V

window.

DD

From SCL rising edge crossing

70% of V , to SDA rising edge

t

STOP Condition Setup Time

600

0

DD

crossing 30% of V

.

DD

t

STOP Condition Hold Time for

Read, or Volatile Only Write

From SDA rising edge to SCL

falling edge. Both crossing 70% of

V

.

DD

From SCL falling edge crossing

30% of V , until SDA enters the

t

Output Data Hold Time

DH

DD

30% to 70% of V

window.

DD

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

20 +

0.1 x Cb

250

ns

R

DD

t

From 70% to 30% of V

20 +

F

DD

0.1 x Cb

Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip

SDA, and SCL Pin Capacitance

10

400

10

pF

ms

Cpin

t

Non-Volatile Write Cycle Time

12

20

10

WC

NOTES:

3. RESET Inactive (no reset).

4. V = V x 0.1, V = V

x 0.9, f = 400kHz.

SCL

IL IH

DD

5. V

= 2.63V (VDD must be greater than V

), V

= 0V.

BAT

RESET

6. Bit BSW = 0 (Standard Mode), V

7. Specified at +25°C.

≥1.8V.

BAT

8. In order to ensure proper timekeeping, the V

9. Parameter is not 100% tested.

specification must be followed.

DD SR-

10. t

is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write

WC

sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.

FN6371.1

October 18, 2006

5

ISL12025

Timing Diagrams

t

R

F

HIGH

LOW

t

HD:STO

SCL

t

SU:DAT

t

HD:DAT

t

SU:STA

SU:STO

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

DH

t

AA

SDA

(OUTPUT TIMING)

FIGURE 1. BUS TIMING

SCL

SDA

8TH BIT OF LAST BYTE

ACK

t

WC

STOP

START

CONDITION

FIGURE 2. WRITE CYCLE TIMING

t

>t

RSP

RSP WDO

t

RST

t

>t

RSP WDO

t

RST

t

<t

RSP WDO

SCL

SDA

RESET

START

STOP START

NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t

).

RST

FIGURE 3. WATCHDOG TIMING

V

RESET

V

DD

t

PURST

t

RPD

t

F

t

R

RESET

V

RVALID

FIGURE 4. RESET TIMING

FN6371.1

October 18, 2006

6

ISL12025

Typical Performance Curves Temperature is +25°C unless otherwise specified

0.90

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

BSW = 0 or 1

SCL,SDA pullups = 0V

BSW = 0 or 1

SCL,SDA pullups = Vbat

BSW = 0 or 1

1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

1.80

2.30

2.80

3.30

3.80

4.30

4.80

5.30

Vbat (V)

Vbat(V)

FIGURE 5. I

vs V

SBIB = 0

FIGURE 6. I

vs V

SBIB = 1

BAT,

BAT

BAT,

BAT

5.00

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

Vdd=5.5V

Vbat = 3.0V

Vdd=3.3V

-45 -35 -25 -15

-5

5

15

25

35

45

55

65

75

85

-45 -35 -25 -15

-5

5

15

25

35

45

55

65

75

85

Temperature

FIGURE 7. I

vs TEMPERATURE

FIGURE 8. I

vs TEMPERATURE

BAT

DD3

80

60

40

20

0

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

-20

-40

-32 -28 -24 -20 -16 -12 -8 -4

0

4

8

12 16 20 24 28

1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

ATR setting

Vdd (V)

FIGURE 10. ΔF

vs ATR SETTING

FIGURE 9. I

DD3

vs V

DD

OUT

FN6371.1

October 18, 2006

7

ISL12025

Serial Data (SDA)

Description

SDA is a bidirectional pin used to transfer data into and out

of the device. It has an open drain output and may be wire

ORed with other open drain or open collector outputs. The

input buffer is always active (not gated).

The ISL12025 device is a Real-Time Clock with

clock/calendar, two polled alarms with integrated 512x8

EEPROM configured in 16 Bytes per page format, oscillator

compensation, CPU Supervisor (Power-on Reset, Low

Voltage Sensing and Watchdog Timer) and battery backup

switch.

This open drain output requires the use of a pull-up resistor.

The pull-up resistor on this pin must use the same voltage

source as V . The output circuitry controls the fall time of

The oscillator uses an external, low-cost 32.768kHz crystal.

All compensation and trim components are integrated on the

chip. This eliminates several external discrete components

and a trim capacitor, saving board area and component cost.

DD

the output signal with the use of a slope-controlled pull-

2

down. The circuit is designed for 400kHz I C interface

speed.

V

The Real-Time Clock keeps track of time with separate

registers for Hours, Minutes, Seconds. The Calendar has

separate registers for Date, Month, Year and Day-of-week.

The calendar is correct through 2099, with automatic leap

year correction.

BAT

This input provides a backup supply voltage to the device.

V

supplies power to the device in the event the V

BAT

DD

supply fails. This pin can be connected to a battery, a

SuperCap or tied to ground if not used.

The 64-bit unique ID is a random numbers programmed,

verified and Locked at the factory and it is only accessible for

reading and cannot be altered by the customer.

RESET

The RESET signal output can be used to notify a host

processor that the watchdog timer has expired or the V

DD

voltage supply has dipped below the V

threshold. It is

The Dual Alarms can be set to any Clock/Calendar value for

a match. For instance, every minute, every Tuesday, or 5:23

AM on March 21. The alarms can be polled in the Status

Register. There is a repeat mode for the alarms allowing a

periodic interrupt.

RESET

an open drain, active LOW output. Recommended value for

the pull-up resistor is 10kΩ. If unused it can be tied to

ground.

X1, X2

The ISL12025 device integrates CPU Supervisory functions

(POR, WDT) and Battery Switch. There is Power-On-Reset

(RESET) output with 250ms delay from power-on. It will also

The X1 and X2 pins are the input and output, respectively, of

an inverting amplifier. An external 32.768kHz quartz crystal

is used with the ISL12025 to supply a timebase for the

real-time clock. Internal compensation circuitry provides high

accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can

be used to calibrate the crystal timing accuracy over

temperature either during manufacturing or with an external

temperature sensor and microcontroller for active

assert RESET when V

goes below the specified

DD

threshold is selectable via

threshold. The V

trip

VTS2/VTS1/VTS0 registers to five (5) preselected levels.

There is WatchDog Timer (WDT) with 3 selectable time-out

periods (0.25s, 0.75s and 1.75s) and disabled setting. The

WatchDog Timer activates the RESET pin when it expires.

compensation. X2 is intended to drive a crystal only, and

should not drive any external circuit (Figure 11).

The device offers a backup power input pin. This V

BAT

allows the device to be backed up by battery or SuperCap.

The entire ISL12025 device is fully operational from 2.7 to

5.5V and the clock/calendar portion of the ISL12025 device

remains fully operational down to 1.8V (Standby Power

Mode).

NO EXTERNAL COMPENSATION RESISTORS OR

CAPACITORS ARE NEEDED OR ARE RECOMMENDED

TO BE CONNECTED TO THE X1 AND X2 PINS.

The ISL12025 device provides 4k bits of EEPROM with eight

modes of BlockLock™ control. The BlockLock allows a safe,

secure memory for critical user and configuration data, while

allowing a large user storage area.

X1

X2

FIGURE 11. RECOMMENDED CRYSTAL CONNECTION

Pin Descriptions

Real-Time Clock Operation

Serial Clock (SCL)

The Real-Time Clock (RTC) uses an external 32.768kHz

quartz crystal to maintain an accurate internal representation

of the second, minute, hour, day, date, month, and year. The

RTC has leap-year correction. The clock also corrects for

months having fewer than 31 days and has a bit that controls

The SCL input is used to clock all data into and out of the

device. The input buffer on this pin is always active (not

gated). The pull-up resistor on this pin must use the same

voltage source as V

.

DD

FN6371.1

October 18, 2006

8

ISL12025

24 hour or AM/PM format. When the ISL12025 powers up

after the loss of both V and V , the clock will not

operate until at least one byte is written to the clock register.

addresses from 0000h to 003Fh. The defined addresses are

described in the Table 2. Writing to and reading from the

undefined addresses are not recommended.

DD

BAT

Reading the Real-Time Clock

CCR Access

The RTC is read by initiating a Read command and

specifying the address corresponding to the register of the

Real-Time Clock. The RTC Registers can then be read in a

Sequential Read Mode. Since the clock runs continuously

and read takes a finite amount of time, there is a possibility

that the clock could change during the course of a read

operation. In this device, the time is latched by the read

command (falling edge of the clock on the ACK bit prior to

RTC data output) into a separate latch to avoid time changes

during the read operation. The clock continues to run.

Alarms occurring during a read are unaffected by the read

operation.

The contents of the CCR can be modified by performing a

byte or a page write operation directly to any address in the

CCR. Prior to writing to the CCR (except the status register),

however, the WEL and RWEL bits must be set using a three

step process (see “Writing to the Clock/Control Registers” on

page 13.)

The CCR is divided into 6 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (5 bytes; non-volatile)

4. Unique ID (8 bytes, non-volatile)

5. Real-Time Clock (8 bytes; volatile)

6. Status (1 byte; volatile)

Writing to the Real-Time Clock

The time and date may be set by writing to the RTC

registers. RTC Register should be written ONLY with Page

Write. To avoid changing the current time by an uncompleted

write operation, write to the all 8 bytes in one write operation.

When writing the RTC registers, the new time value is

loaded into a separate buffer at the falling edge of the clock

during the Acknowledge. This new RTC value is loaded into

the RTC Register by a stop bit at the end of a valid write

sequence. An invalid write operation aborts the time update

procedure and the contents of the buffer are discarded. After

a valid write operation, the RTC will reflect the newly loaded

data beginning with the next “one second” clock cycle after

the stop bit is written. The RTC continues to update the time

while an RTC register write is in progress and the RTC

continues to run during any non-volatile write sequences.

Each register is read and written through buffers. The non-

volatile portion (or the counter portion of the RTC) is updated

only if RWEL is set and only after a valid write operation and

stop bit. A sequential read or page write operation provides

access to the contents of only one section of the CCR per

operation. Access to another section requires a new

operation. A read or write can begin at any address in the

CCR.

It is not necessary to set the RWEL bit prior to writing the

status register. Section 5 (status register) supports a single

byte read or write only. Continued reads or writes from this

section terminates the operation.

The state of the CCR can be read by performing a random

read at any address in the CCR at any time. This returns the

contents of that register location. Additional registers are

read by performing a sequential read. The read instruction

latches all Clock registers into a buffer, so an update of the

clock does not change the time being read. A sequential

read of the CCR will not result in the output of data from the

memory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus. After a

read of the CCR, the address remains at the previous

address +1 so the user can execute a current address read

of the CCR and continue reading the next Register.

Accuracy of the Real-Time Clock

The accuracy of the Real-Time Clock depends on the

accuracy of the quartz crystal that is used as the time base

for the RTC. Since the resonant frequency of a crystal is

temperature dependent, the RTC performance will also be

dependent upon temperature. The frequency deviation of

the crystal is a function of the turnover temperature of the

crystal from the crystal’s nominal frequency. For example, a

>20ppm frequency deviation translates into an accuracy of

>1 minute per month. These parameters are available from

the crystal manufacturer. Intersil’s RTC family provides

on-chip crystal compensation networks to adjust

Real-Time Clock Registers (Volatile)

load-capacitance to tune oscillator frequency from -34ppm to

+80ppm when using a 12.5pF load crystal. For more detailed

information see the “Application Section” on page 21.

SC, MN, HR, DT, MO, YR: Clock/Calendar Registers

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 00 to 59,

HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or

0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1

to 12, YR (Year) is 0 to 99.

Clock/Control Registers (CCR)

The Control/Clock Registers are located in an area separate

from the EEPROM array and are only accessible following a

slave byte of “1101111x” and reads or writes to addresses

[0000h:003Fh]. The clock/control memory map has memory

FN6371.1

October 18, 2006

9

ISL12025

DW: Day of the Week Register

OSCF: Oscillator Fail Indicator

This register provides a Day of the Week status and uses

three bits DY2 to DY0 to represent the seven days of the

week. The counter advances in the cycle

This bit is set to “1” if the oscillator is not operating. The bit is

set to “0” only if the oscillator is functioning. This bit is read

only, and is set/reset by hardware.

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value

to a specific day of the week is arbitrary and may be decided

by the system software designer. The default value is

defined as ‘0’.

RWEL: Register Write Enable Latch

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior to any

writes to the Clock/Control Registers. Writes to RWEL bit do

not cause a non-volatile write cycle, so the device is ready

for the next operation immediately after the stop condition. A

write to the CCR requires both the RWEL and WEL bits to be

set in a specific sequence.

Y2K: Year 2000 Register

Can have value 19 or 20. As of the date of the introduction of

this device, there would be no real use for the value 19 in a

true real-time clock, however.

24 Hour Time

WEL: Write Enable Latch

If the MIL bit of the HR register is 1, the RTC uses a 24-hour

format. If the MIL bit is 0, the RTC uses a 12-hour format and

H21 bit functions as an AM/PM indicator with a ‘1’,

representing PM. The clock defaults to standard time with

H21 = 0.

The WEL bit controls the access to the CCR during a write

operation. This bit is a volatile latch that powers up in the

LOW (disabled) state. While the WEL bit is LOW, writes to

the CCR address will be ignored, although acknowledgment

is still issued. The WEL bit is set by writing a “1” to the WEL

bit and zeroes to the other bits of the Status Register. Once

set, WEL remains set until either reset to 0 (by writing a “0”

to the WEL bit and zeroes to the other bits of the Status

Register) or until the part powers up again. Writes to WEL bit

do not cause a non-volatile write cycle, so the device is

ready for the next operation immediately after the stop

condition.

Leap Years

Leap years add the day February 29 and are defined as

those years that are divisible by 4.

Status Register (SR) (Volatile)

The Status Register is located in the CCR memory map at

address 003Fh. This is a volatile register only and is used to

control the WEL and RWEL write enable latches, read power

status and two alarm bits. This register is separate from both

the array and the Clock/Control Registers (CCR).

RTCF: Real-Time Clock Fail Bit

This bit is set to a ‘1’ after a total power failure. This is a read

only bit that is set internally when the device powers up after

having lost all power to the device (both V

and V

or V

BAT

= 0V).

is applied

DD

BAT

TABLE 1. STATUS REGISTER (SR)

The bit is set regardless of whether V

DD

ADDR

003Fh BAT AL1 AL0 OSCF

Default

7

6

5

4

3

0

2

1

0

first. The loss of only one of the supplies does not result in

setting the RTCF bit. The first valid write to the RTC after a

complete power failure (writing one byte is sufficient) resets

the RTCF bit to ‘0’.

RWEL WEL RTCF

0

1

Unused Bits:

BAT: Battery Supply

This bit set to “1” indicates that the device is operating from

, not V . It is a read-only bit and is set/reset by

Bit 3 in the SR is not used, but must be zero. The Data Byte

output during a SR read will contain a zero in this bit

location.

V

BAT DD

hardware (ISL12025 internally). Once the device begins

operating from V , the device sets this bit to “0”.

DD

AL1, AL0: Alarm Bits

These bits announce if either alarm 0 or alarm 1 match the

real-time clock. If there is a match, the respective bit is set to

‘1’. The falling edge of the last data bit in a SR Read

operation resets the flags. Note: Only the AL bits that are set

when an SR read starts will be reset. An alarm bit that is set

by an alarm occurring during an SR read operation will

remain set after the read operation is complete.

FN6371.1

October 18, 2006

10

ISL12025

TABLE 2. CLOCK/CONTROL MEMORY MAP

(Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation

(see device ordering information). * indicates set at the factory, read-only)

BIT

REG

ADDR.

TYPE

NAME

7

6

5

4

3

2

1

0

RANGE

003F

0037

0036

0035

0034

0033

0032

0031

0030

0027

0026

0025

0024

0023

0022

0021

0020

0014

0013

0012

0011

0010

Status

SR

Y2K

DW

YR

BAT

0

AL1

0

AL0

Y2K21

0

OSCF

Y2K20

0

Y2K13

0

RWEL

0

WEL

0

RTCF

Y2K10

DY0

Y10

01h

20h

00h

01h

00h

*

RTC

(SRAM)

19/20

0-6

0

DY2

Y12

G12

D12

H12

M12

S12

ID72

ID62

ID52

ID42

ID32

ID22

ID12

ID02

VTS2

DTR2

ATR2

0

DY1

Y11

G11

D11

H11

M11

S11

ID71

ID61

ID51

ID41

ID31

ID21

ID11

ID01

VTS1

DTR1

ATR1

0

Y23

0

Y22

0

Y21

0

Y20

G20

D20

H20

M20

S20

ID74

ID64

ID54

ID44

ID34

ID24

ID14

ID04

0

Y13

G13

D13

H13

M13

S13

ID73

ID63

ID53

ID43

ID33

ID23

ID13

ID03

0

0-99

1-12

1-31

0-23

0-59

MO

DT

G10

D10

0

D21

H21

M21

S21

ID75

ID65

ID55

ID45

ID35

ID25

ID15

ID05

0

HR

MIL

0

H10

MN

SC

M22

S22

ID76

ID66

ID56

ID46

ID36

ID26

ID16

ID06

BSW

0

M10

S10

0

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

PWR

DTR

ATR

INT

BL

ID77

ID67

ID57

ID47

ID37

ID27

ID17

ID07

SBIB

0

ID70

ID60

ID50

ID40

ID30

ID20

ID10

ID00

VTS0

DTR0

ATR0

0

*

Device ID

*

Control

(EEPROM)

4Xh

00h

18h

0

ATR5

AL0E

BP0

ATR4

0

ATR3

0

IM

AL1E

BP1

BP2

WD1

WD0

0

000F

000E

000D

000C

000B

000A

0009

0008

0007

0006

0005

0004

0003

0002

0001

0000

Alarm1

(EEPROM)

Y2K1

0

A1Y2K21 A1Y2K20 A1Y2K13

0

A1Y2K10

DY0

19/20

0-6

20h

00h

DWA1 EDW1

YRA1

0

DY2

DY1

Unused - Default = RTC Year value (No EEPROM) - Future expansion

MOA1

DTA1

HRA1

MNA1

SCA1

Y2K0

EMO1

EDT1

EHR1

EMN1

ESC1

0

A1G20

A1D20

A1H20

A1M20

A1S20

A1G13

A1D13

A1H13

A1M13

A1S13

A1G12

A1D12

A1H12

A1M12

A1S12

0

A1G11

A1D11

A1H11

A1M11

A1S11

0

A1G10

A1D10

A1H10

A1M10

A1S10

A0Y2K10

DY0

1-12

1-31

0-23

0-59

19/20

0-6

00h

20h

00h

0

A1D21

A1H21

A1M21

A1S21

0

A1M22

A1S22

0

Alarm0

(EEPROM)

A0Y2K21 A0Y2K20 A0Y2K13

DWA0 EDW0

YRA0

0

DY2

DY1

Unused - Default = RTC Year value (No EEPROM) - Future expansion

MOA0

DTA0

HRA0

MNA0

SCA0

EMO0

EDT0

EHR0

EMN0

ESC0

0

A0G20

A0D20

A0H20

A0M20

A0S20

A0G13

A0D13

A0H13

A0M13

A0S13

A0G12

A0D12

A0H12

A0M12

A0S12

A0G11

A0D11

A0H11

A0M11

A0S11

A0G10

A0D10

A0H10

A0M10

A0S10

1-12

1-31

0-23

0-59

00h

A0D21

A0H21

A0M21

A0S21

0

A0M22

A0S22

FN6371.1

October 18, 2006

11

ISL12025

frequency compensation of the RTC. Each bit has a different

Alarm Registers (Non-Volatile)

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation.

Alarm0 and Alarm1

The alarm register bytes are set up identical to the RTC

register bytes, except that the MSB of each byte functions as

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

X1

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

C

X1

CRYSTAL

OSCILLATOR

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match. See “Device Operation” on page 13

and “Application Section” on page 21 for more information.

X2

C

X2

FIGURE 12. DIAGRAM OF ATR

Control Registers (Non-Volatile)

The Control Bits and Registers described under this section

are non-volatile.

The effective on-chip series load capacitance, C

,

LOAD

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). C is changed via two digitally

LOAD

BL Register

controlled capacitors, C and C , connected from the X1

X1 X2

and X2 pins to ground (see Figure 12). The value of C and

X1

BP2, BP1, BP0 - Block Protect Bits

C

is given by the following formula:

X2

The Block Protect Bits, BP2, BP1 and BP0, determine which

blocks of the array are write protected. A write to a protected

block of memory is ignored. The block protect bits will

prevent write operations to one of eight segments of the

array. The partitions are described in Table 3.

C

= (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF

X

(EQ. 1)

The effective series load capacitance is the combination of

C

and C :

X2

TABLE 3.

X1

1

PROTECTED ADDRESSES

----------------------------------

C

=

LOAD

1

⎛

⎞

ISL12025

ARRAY LOCK

None

---------- ----------

+

⎝

⎠

(EQ. 2)

pF

C

X2

X1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None (Default)

16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9

⎛

⎝

⎞

⎠

-----------------------------------------------------------------------------------------------------------------------------

180 – 1FF

Upper 1/4

C

=

h

LOAD

2

100 – 1FF

Upper 1/2

h

For example:

000 – 1FF

Full Array

h

C

(ATR = 00000) = 12.5pF,

(ATR = 100000) = 4.5pF, and

(ATR = 011111) = 20.25pF.

LOAD

000 – 03F

h

First 4 Pages

First 8 Pages

First 16 Pages

Full Array

000 – 07F

h

000 – 0FF

h

The entire range for the series combination of load

capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.

Note that these are typical values.

000 – 1FF

h

Oscillator Compensation Registers

There are two trimming options.

DTR Register - DTR2, DTR1, DTR0: Digital

Trimming Register

- ATR. Analog Trimming Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the

number of counts per second and average the ppm error to

achieve better accuracy.

- DTR. Digital Trimming Register

These registers are non-volatile. The combination of analog

and digital trimming can give up to -64ppm to +110ppm of

total adjustment.

DTR2 is a sign bit, where:

DTR2 = 0 means frequency compensation is >0.

DTR2 = 1 means frequency compensation is <0.

ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,

ATR0: Analog Trimming Register

DTR1 and DTR0 are scale bits. DTR1 gives 10ppm

adjustment and DTR0 gives 20ppm adjustment.

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

FN6371.1

October 18, 2006

12

ISL12025

A range from -30ppm to +30ppm can be represented by

using the three bits previously explained.

TABLE 5.

VTS0

VTS2

VTS1

V

RESET

TABLE 4. DIGITAL TRIMMING REGISTERS

0

1

0

1

0

1

0

1

0

4.64V

4.38V

3.09V

2.92V

2.63V

DTR REGISTER

ESTIMATED FREQUENCY

DTR2

DTR1

DTR0

PPM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+10

+20

+30

0

Unique ID Registers

There are eight register bytes for storing the device ID.

(Address 0020h to 0027h). Each device contains these

bytes to provide a unique 64-bit ID programmed and tested

in the factory before shipment. These registers are read-

only, intended for serialization of end equipment, and cannot

be changed or overwritten.

-10

-20

-30

Device Operation

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0

SBIB: Serial Bus Interface (Enable)

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers

requires the following steps:

The serial bus can be disabled in Battery Backup Mode by

setting this bit to “1”. This will minimize power drain on the

battery. The Serial Interface can be enabled in Battery

Backup Mode by setting this bit to “0” (default is “0”). See

“Power Control Operation” on page 14.

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a start and

ended with a stop).

BSW: Power Control Bit

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also

a volatile cycle. The zeros in the data byte are required.

(Operation proceeded by a start and ended with a stop).

The Power Control bit, BSW, determines the conditions for

switching between V

options.

and Back Up Battery. There are two

DD

Option 1. Standard: Set “BSW = 0”

Write all eight bytes to the RTC registers, or one byte to the

SR, or one to five bytes to the control registers. This

Option 2. Legacy /Default Mode: Set “BSW = 1”

See “Power Control Operation” on page 14 for more details.

sequence starts with a start bit, requires a slave byte of

“11011110” and an address within the CCR and is terminated

by a stop bit. A write to the EEPROM registers in the CCR

will initiate a non-volatile write cycle and will take up to 20ms

to complete. A write to the RTC registers (SRAM) will require

2

Also see “I C Communications During Battery Backup and

LVR Operation” on page 23 for important details.

VTS2, VTS1, VTS0: V

Select Bits

RESET

The ISL12025 is shipped with a default V

much shorter cycle time (t = t

). Writes to undefined areas

BUF

threshold

DD

) per the ordering information table. This register is

have no effect. The RWEL bit is reset by the completion of a

write to the CCR, so the sequence must be repeated to

again initiate another change to the CCR contents. If the

sequence is not completed for any reason (by sending an

incorrect number of bits or sending a start instead of a stop,

for example) the RWEL bit is not reset and the device

remains in an active mode. Writing all zeros to the status

register resets both the WEL and RWEL bits. A read

operation occurring between any of the previous operations

will not interrupt the register write operation.

(V

RESET

a non-volatile with no protection, therefore any writes to this

location can change the default value from that marked on

the package. If not changed with a non-volatile write, this

value will not change over normal operating and storage

conditions. However, ISL12025 has four (4) additional

selectable levels to fit the customers application. Levels are:

4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The V

RESET

selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5.

Care should be taken when changing the V select

RESET

Alarm Operation

bits. If the V

voltage selected is higher than V , then

RESET

the device will go into RESET and unless V

DD

is increased,

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event and trigger some action

as a result. The host can be notified by polling the Status

Register (SR) Alarm bits. These two volatile bits (AL1 for

DD

the device will no longer be able to communicate using the

2

I C bus.

FN6371.1

October 18, 2006

13

ISL12025

Alarm 1 and AL0 for Alarm 0), indicate if an alarm has

happened. The AL1 and AL0 bits in the status register are

reset by the falling edge of the eighth clock of status register

read.

2. Other nonvolatile writes: It is possible to do writes of

less than an entire page, but the final byte must always

be addresses 0000h through 0004h or 0008h though

000Ch to trigger a nonvolatile write. Writing to those

blocks of 5 bytes sequentially, or individually, will trigger a

nonvolatile write. If the DWA0 or DWA1 registers need to

be set, then enough bytes will need to be written to

overlap with the other Alarm register and trigger the

nonvolatile write. For Example, if the DWA0 register is

being set, then the code can start with a multiple byte

write beginning at address 0006h, and then write 3 bytes

ending with the SCA1 register as follows:

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

1. Single Event Mode is enabled by setting the AL0E or

AL1E bit to “1”, the IM bit to “0”, and disabling the

frequency output. This mode permits a one-time match

between the alarm registers and the RTC registers. Once

this match occurs, the AL0 or AL1 bit is set to “1”. Once

the AL0 or AL1 bit is read, this will automatically resets it.

Both Alarm registers can be set at the same time to

trigger alarms. Polling the SR will reveal which alarm has

been set.

Addr Name

0006h DWA0

0007h Y2K0

0008h SCA1

2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is

enabled by setting the AL0E or AL1E bit to “1” the IM bit

to “1”, and disabling the frequency output. If both AL0E

and AL1E bits are set to 1, then only the AL0E PIM alarm

will function (AL0E overrides AL1E). This means that

once the Interrupt Mode alarm is set, it will continue to

alarm for each occurring match of the alarm and present

time. This mode is convenient for hourly or daily

hardware interrupts in microcontroller applications such

as security cameras or utility meter reading. Interrupt

Mode CANNOT be used for general periodic alarms,

however, since a specific time period cannot be

If the Alarm1 is used, SCA1 would need to have the correct

data written.

Power Control Operation

The power control circuit accepts a V

and a V input.

BAT

DD

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and battery sizes are available that can power

an Intersil RTC device for up to 10 years. Another option is

to use a SuperCap for applications where V

is interrupted

DD

for up to a month. See the “Application Section” on page 21

for more information.

programmed for interrupt, only matches to a specific time

of day. The Interrupt Mode is only stopped by disabling

the IM bit or the Alarm Enable bits.

There are two options for setting the change-over conditions

from V

to Battery Backup Mode. The BSW bit in the PWR

DD

Writing to the Alarm Registers

register controls this operation.

The Alarm Registers are non-volatile but require special

attention to insure a proper non-volatile write takes place.

Specifically, byte writes to individual registers are good for all

but registers 0006h and 0000Eh, which are the DWA0 and

DWA1 registers, respectively. Those registers will require a

special page write for nonvolatile storage. The

- Option 1 - Standard Mode

- Option 2 - Legacy Mode (Default)

2

Note that the I C bus may or may not be operational during

battery backup, which is controlled by the SBIB bit. See

“Backup Battery Operation” on page 22 for information.

recommended page write sequences are as follows:

Note that switching to battery backup initiates a

three-second timeout period, during which the device will

1. 16-byte page writes: The best way to write or update the

Alarm Registers is to perform a 16-byte write beginning at

address 0001h (MNA0) and wrapping around and ending

at address 0000h (SCA0). This will insure that non-

volatile storage takes place. This means that the code

must be designed so that the Alarm0 data is written

starting with Minutes register, and then all the Alarm1

data, with the last byte being the Alarm0 Seconds (the

page ends at the Alarm1 Y2k register and then wraps

around to address 0000h).

stay in Battery Backup Mode even if the V

resumes

DD

normal power. The three-second delay is intended to lock

out any power-up glitches that could cause communications

errors. Also note that very fast (<10µs) power ramp rates will

bypass this delay, so it is important to filter V

well.

DD

OPTION 1- STANDARD (POWER CONTROL) MODE

In the Standard Mode, the supply will switch over to the

battery when V

lower. In this mode, accidental operation from the battery is

drops below V

or V , whichever is

TRIP

BAT

DD

Alternatively, the 16-byte page write could start with

address 0009h, wrap around and finish with address

0008h. Note that any page write ending at address

0007h or 000Fh (the highest byte in each Alarm) will not

trigger a nonvolatile write, so wrapping around or

overlapping to the following Alarm's Seconds register is

advised.

prevented since the battery backup input will only be used

when the V

supply is shut off.

DD

To select Option 1, BSW bit in the Power Register must be

set to “BSW = 0”. A description of power switchover follows.

FN6371.1

October 18, 2006

14

ISL12025

whichever is the higher voltage. Care should be taken when

changing from Normal to Legacy Mode. If the V voltage is

Standard Mode Power Switchover

• Normal Operating Mode (V ) to Battery Backup Mode

BAT

DD

higher than V , then the device will enter battery back up

DD

(V

)

BAT

and unless the battery is disconnected or the voltage

To transition from the V

following conditions must be met:

to V mode, both of the

BAT

decreases, the device will no longer operate from V

.

DD

To select the Option 2, BSW bit in the Power Register must

be set to “BSW = 1”.

- Condition 1:

V

< V - V

BAT BATHYS

DD

where V

• Normal Mode (V ) to Battery Backup Mode (V

DD

)

≈ 50mV

BAT

BATHYS

- Condition 2:

To transition from the V

DD

to V

BAT

mode, the following

V

< V

DD

TRIP

conditions must be met:

where V

≈ 2.2V

V

< V - V

DD

BAT BATHYS

• Battery Backup Mode (V

BAT

) to Normal Mode (V

)

DD

• Battery Backup Mode (V

) to Normal Mode (V )

DD

BAT

The ISL12025 device will switch from the V

to V

BAT

DD

mode when one of the following conditions occurs:

The device will switch from the V

the following condition occurs:

to V mode when

DD

BAT

- Condition 1:

V

> V + V

BAT BATHYS

V

> V

BAT

+V

BATHYS

DD

where V

DD

≈ 50mV

BATHYS

- Condition 2:

The Legacy Mode power control conditions are illustrated in

Figure 15 below.

V

> V

+ V

DD

where V

TRIP TRIPHYS

≈ 30mV

TRIPHYS

V

DD

VOLTAGE

There are two discrete situations that are possible when

using Standard Mode: V < V and V >V .

TRIP

ON

V

BAT

TRIP

BAT

IN

These two power control situations are illustrated in

OFF

Figures 13 and 14.

BATTERY BACKUP

MODE

FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE

V

DD

Power-On Reset

V

TRIP

2.2V

1.8V

Application of power to the ISL12025 activates a

Power-On-Reset Circuit that pulls the RESET pin active.

This signal provides several benefits.

V

BAT

V

+ V

BATHYS

BAT

V

- V

BATHYS

BAT

- It prevents the system microprocessor from starting to

operate with insufficient voltage.

FIGURE 13. BATTERY SWITCHOVER WHEN V

< V

TRIP

BAT

- It prevents the processor from operating prior to

stabilization of the oscillator.

- It allows time for an FPGA to download its configuration

prior to initialization of the circuit.

BATTERY BACKUP

MODE

- It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

V

DD

V

BAT

3.0V

2.2V

When V

DD

exceeds the device V threshold value for

RESET

V

typically 250ms the circuit releases RESET, allowing the

system to begin operation. Recommended slew rate is

between 0.2V/ms and 50V/ms.

TRIP

V

+ V

TRIPHYS

TRIP

Watchdog Timer Operation

The watchdog timer timeout period is selectable. By writing a

value to WD1 and WD0, the watchdog timer can be set to 3

different time out periods or off. When the Watchdog timer is

set to off, the watchdog circuit is configured for low power

operation. See Table 6.

FIGURE 14. BATTERY SWITCHOVER WHEN V

> V

TRIP

BAT

OPTION 2 - LEGACY (POWER CONTROL) MODE

(DEFAULT)

The Legacy Mode follows conditions set in X1226 products.

In this mode, switching from V to V is simply done by

DD BAT

comparing the voltages and the device operates from

FN6371.1

October 18, 2006

15

ISL12025

Clock and Data

TABLE 6.

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. See Figure 16.

WD1

WD0

DURATION

1

0

1

0

1

0

disabled

250ms

750ms

1.75s

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. See Figure 17.

Watchdog Timer Restart

The Watchdog Timer is started by a falling edge of SDA

when the SCL line is high (START condition). The start

signal restarts the watchdog timer counter, resetting the

period of the counter back to the maximum. If another

START fails to be detected prior to the watchdog timer

expiration, then the RESET pin becomes active for one reset

time out period. In the event that the start signal occurs

during a reset time out period, the start will have no effect.

When using a single START to refresh watchdog timer, a

STOP condition should be followed to reset the device back

to Standby Power Mode. See Figure 3.

Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the device

into the Standby Power Mode after a read sequence. A stop

condition can only be issued after the transmitting device

has released the bus. See Figure 17.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting eight

bits. During the ninth clock cycle, the receiver will pull the

SDA line LOW to acknowledge that it received the eight bits of

data. See Figure 18.

Low Voltage Reset (LVR) Operation

When a power failure occurs, a voltage comparator

compares the level of the V

line versus a preset threshold

DD

), then generates a RESET pulse if it is

voltage (V

RESET

below V

. The reset pulse will timeout 250ms after the

RESET

V

line rises above V

. If the V remains below

DD

RESET

, then the RESET output will remain asserted low.

The device will respond with an acknowledge after

recognition of a start condition and if the correct Device

Identifier and Select bits are contained in the Slave Address

Byte. If a write operation is selected, the device will respond

with an acknowledge after the receipt of each subsequent

eight bit word. The device will not acknowledge if the slave

address byte is incorrect.

RESET

Power-up and power-down waveforms are shown in

Figure 4. The LVR circuit is to be designed so the RESET

signal is valid down to V

DD

= 1.0V.

When the LVR signal is active, unless the part has been

switched into the Battery Backup Mode, the completion of an

in-progress non-volatile write cycle is unaffected, allowing a

non-volatile write to continue as long as possible (down to

the Reset Valid Voltage). The LVR signal, when active, will

terminate any in-progress communications to the device and

prevents new commands from disrupting any current write

In the read mode, the device will transmit eight bits of data,

release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no stop

condition is generated by the master, the device will continue

to transmit data. The device will terminate further data

transmissions if an acknowledge is not detected. The master

must then issue a stop condition to return the device to

Standby Power Mode and place the device into a known

state.

2

operations. See “I C Communications During Battery

Backup and LVR Operation” on page 23.

Serial Communication

Interface Conventions

2

The device supports the I C Protocol.

SCL

SDA

DATA STABLE

DATA CHANGE

DATA STABLE

FIGURE 16. VALID DATA CHANGES ON THE SDA BUS

FN6371.1

October 18, 2006

16

ISL12025

SCL

SDA

START

STOP

FIGURE 17. VALID START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER

DEVICE IDENTIFIER

SLAVE ADDRESS BYTE

BYTE 0

ARRAY

CCR

1

0

1

0

1

0

R/W

A8

WORD ADDRESS 1

BYTE 1

0

WORD ADDRESS 0

BYTE 2

A7

D7

A6

D6

A5

D5

A4

D4

A3

D3

A2

D2

A1

D1

A0

D0

DATA BYTE

BYTE 3

FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)

Bit 3 through Bit 1 of the slave byte specify the device select

bits. These are set to ‘111’.

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The first four bits of the Slave Address Byte

specify access to either the EEPROM array or to the CCR.

Slave bits ‘1010’ access the EEPROM array. Slave bits

‘1101’ access the CCR.

The last bit of the Slave Address Byte defines the operation

to be performed. When this R/W bit is a one, then a read

operation is selected. A zero selects a write operation. See

Figure 19.

When shipped from the factory, EEPROM array is

UNDEFINED, and should be programmed by the customer

to a known state.

After loading the entire Slave Address Byte from the SDA

bus, the ISL12025 compares the device identifier and device

select bits with ‘1010111’ or ‘1101111’. Upon a correct

FN6371.1

October 18, 2006

17

ISL12025

compare, the device outputs an acknowledge on the SDA

line.

or page writes to trigger nonvolatile writes. See the Device

Operation section for more information.

Following the Slave Byte is a two byte word address. The

word address is either supplied by the master device or

obtained from an internal counter. On power-up the internal

address counter is set to address 0h, so a current address

read of the EEPROM array starts at address 0. When

required, as part of a random read, the master must supply

the 2 Word Address Bytes as shown in Figure 19.

Page Write

The ISL12025 has a page write operation. It is initiated in the

same manner as the byte write operation; but instead of

terminating the write cycle after the first data byte is

transferred, the master can transmit up to 15 more bytes to

the memory array and up to 7 more bytes to the clock/control

registers. The RTC registers require a page write (8 bytes),

individual register writes are not allowed. (Note: Prior to

writing to the CCR, the master must write a 02h, then 06h to

the status register in two preceding operations to enable the

write operation. See “Writing to the Clock/Control Registers”

on page 13.)

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read”

section. That is if the random read is from the array the slave

byte must be 1010111x in both instances. Similarly, for a

random read of the Clock/Control Registers, the slave byte

must be 1101111x in both places.

After the receipt of each byte, the ISL12025 responds with

an acknowledge, and the address is internally incremented

by one. The address pointer remains at the last address byte

written. When the counter reaches the end of the page, it

“rolls over” and goes back to the first address on the same

page. This means that the master can write 16 bytes to a

memory array page or 8 bytes to a CCR section starting at

any location on that page. For example, if the master begins

writing at location 10 of the memory and loads 15 bytes, then

the first 6 bytes are written to addresses 10 through 15, and

the last 6 bytes are written to columns 0 through 5.

Afterwards, the address counter would point to location 6 on

the page that was just written. If the master supplies more

than the maximum bytes in a page, then the previously

loaded data is over-written by the new data, one byte at a

time. See Figure 21.The master terminates the Data Byte

loading by issuing a stop condition, which causes the

ISL12025 to begin the non-volatile write cycle. As with the

byte write operation, all inputs are disabled until completion

of the internal write cycle. See Figure 22 for the address,

acknowledge, and data transfer sequence.

Write Operations

Byte Write

For a write operation, the device requires the Slave Address

Byte and the Word Address Bytes. This gives the master

access to any one of the words in the array or CCR.

(Note: Prior to writing to the CCR, the master must write a

02h, then 06h to the status register in two preceding

operations to enable the write operation. See “Writing to the

Clock/Control Registers” on page 13.) Upon receipt of each

address byte, the ISL12025 responds with an acknowledge.

After receiving both address bytes the ISL12025 awaits the

eight bits of data. After receiving the 8 data bits, the

ISL12025 again responds with an acknowledge. The master

then terminates the transfer by generating a stop condition.

The ISL12025 then begins an internal write cycle of the data

to the non-volatile memory. During the internal write cycle,

the device inputs are disabled, so the device will not respond

to any requests from the master. The SDA output is at high

impedance. See Figure 20.

Stops and Write Modes

A write to a protected block of memory is ignored, but will still

receive an acknowledge. At the end of the write command,

the ISL12025 will not initiate an internal write cycle, and will

continue to ACK commands.

Stop conditions that terminate write operations must be sent

by the master after sending at least 1 full data byte and its

associated ACK signal. If a stop is issued in the middle of a

data byte, or before 1 full data byte + ACK is sent, then the

ISL12025 resets itself without performing the write. The

contents of the array are not affected.

Byte writes to all of the nonvolatile registers are allowed,

except the DWAn registers which require multiple byte writes

S

T

A

R

T

SIGNALS FROM

THE MASTER

S

T

WORD

ADDRESS 1

WORD

ADDRESS 0

SLAVE

ADDRESS

O

DATA

P

SDA BUS

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIGURE 20. BYTE WRITE SEQUENCE

FN6371.1

October 18, 2006

18

ISL12025

6 BYTES

ADDRESS

10

ADDRESS = 5

ADDRESS

15

ADDRESS POINTER ENDS

AT ADDR = 5

FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10

1 ≤ n ≤ 16 for EEPROM array

1 ≤ n ≤ 8 for CCR

S

T

A

R

T

SIGNALS FROM

THE MASTER

S

T

O

P

WORD

ADDRESS 1

SLAVE

ADDRESS

WORD

ADDRESS 0

DATA

(1)

DATA

(n)

SDA BUS

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIGURE 22. PAGE WRITE SEQUENCE

acknowledge, then transmits eight data bits. The master

terminates the read operation by not responding with an

acknowledge during the ninth clock and issuing a stop

condition. See Figure 23 for the address, acknowledge, and

data transfer sequence.

Acknowledge Polling

Disabling of the inputs during non-volatile write cycles can

be used to take advantage of the typical 5ms write cycle

time. Once the stop condition is issued to indicate the end of

the master’s byte load operation, the ISL12025 initiates the

internal non-volatile write cycle. Acknowledge polling can

begin immediately. To do this, the master issues a start

condition followed by the Memory Array Slave Address Byte

for a write or read operation (AEh or AFh). If the ISL12025 is

still busy with the non-volatile write cycle, then no ACK will

be returned. When the ISL12025 has completed the write

operation, an ACK is returned and the host can proceed with

the read or write operation. See the flow chart in

S

T

O

P

T

A

R

T

SIGNALS FROM

THE MASTER

SLAVE

ADDRESS

SDA BUS

1

1 1 1 1

A

C

K

SIGNALS FROM

THE SLAVE

DATA

Figure 24. Note: Do not use the CCR Slave byte (DEh or

DFh) for Acknowledge Polling.

FIGURE 23. CURRENT ADDRESS READ SEQUENCE

Read Operations

There are three basic read operations: Current Address

Read, Random Read, and Sequential Read.

Current Address Read

Internally the ISL12025 contains an address counter that

maintains the address of the last word read incremented by

one. Therefore, if the last read was to address n, the next

read operation would access data from address n+1. On

power-up, the sixteen bit address is initialized to 0h. In this

way, a current address read immediately after the power-on

reset can download the entire contents of memory starting at

the first location. Upon receipt of the Slave Address Byte

with the R/W bit set to one, the ISL12025 issues an

FN6371.1

October 18, 2006

19

ISL12025

Byte with the R/W bit set to zero, the master must first

perform a “dummy” write operation.

Byte load completed

by issuing STOP.

Enter ACK Polling

The master issues the start condition and the slave address

byte, receives an acknowledge, then issues the word

address bytes. After acknowledging receipt of each word

address byte, the master immediately issues another start

condition and the slave address byte with the R/W bit set to

one. This is followed by an acknowledge from the device and

then by the eight bit data word. The master terminates the

read operation by not responding with an acknowledge and

then issuing a stop condition. See Figure 25 for the address,

acknowledge, and data transfer sequence.

Issue START

Issue Memory Array Slave

Address Byte

AFh (Read) or AEh (Write)

Issue STOP

NO

ACK

returned?

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of the

second start shown in Figure 25. The ISL12025 then goes

into Standby Power Mode after the stop and all bus activity

will be ignored until a start is detected. This operation loads

the new address into the address counter. The next Current

Address Read operation will read from the newly loaded

address. This operation could be useful if the master knows

the next address it needs to read, but is not ready for the

data.

YES

Non-volatile write

cycle complete. Continue

command sequence?

Issue STOP

YES

Continue normal

Read or Write

command

Sequential Read

sequence

Sequential reads can be initiated as either a current address

read or random address read. The first data byte is

transmitted as with the other modes; however, the master

now responds with an acknowledge, indicating it requires

additional data. The device continues to output data for each

acknowledge received. The master terminates the read

operation by not responding with an acknowledge and then

issuing a stop condition.

PROCEED

FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a stop condition during the

ninth cycle or hold SDA HIGH during the ninth clock cycle

and then issue a stop condition.

The data output is sequential, with the data from address n

followed by the data from address n + 1. The address

counter for read operations increments through all page and

column addresses, allowing the entire memory contents to

be serially read during one operation. At the end of the

address space the counter “rolls over” to the start of the

address space and the ISL12025 continues to output data

for each acknowledge received. See Figure 26 for the

acknowledge and data transfer sequence.

Random Read

Random read operations allow the master to access any

location in the ISL12025. Prior to issuing the Slave Address

S

T

A

R

T

S

T

A

R

T

S

T

O

P

SIGNALS FROM

THE MASTER

SLAVE

ADDRESS

WORD

ADDRESS 0

SLAVE

ADDRESS

WORD

ADDRESS 1

SDA BUS

1

1 1 1 1

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

DATA

FIGURE 25. RANDOM ADDRESS READ SEQUENCE

FN6371.1

October 18, 2006

20

ISL12025

S

T

O

P

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE MASTER

SDA BUS

1

A

C

K

SIGNALS FROM

THE SLAVE

DATA

(1)

DATA

(2)

DATA

(n-1)

DATA

(n)

(n is any integer greater than 1)

FIGURE 26. SEQUENTIAL READ SEQUENCE

-40 and +85°C. It is possible to address this variable drift by

adjusting the load capacitance of the crystal, which will result

in predictable change to the crystal frequency. The Intersil

RTC family allows this adjustment over temperature since

the devices include on-chip load capacitor trimming. This

control is handled by the Analog Trimming Register, or ATR,

which has 6 bits of control. The load capacitance range

covered by the ATR circuit is approximately 3.25pF to

18.75pF, in 0.25pF increments. Note that actual capacitance

would also include about 2pF of package related

Application Section

Crystal Oscillator and Temperature Compensation

Intersil has now integrated the oscillator compensation

circuity on-chip, to eliminate the need for external

components and adjust for crystal drift over temperature and

enable very high accuracy time keeping (<5ppm drift).

The Intersil RTC family uses an oscillator circuit with on-chip

crystal compensation network, including adjustable

load-capacitance. The only external component required is

the crystal. The compensation network is optimized for

operation with certain crystal parameters which are common

in many of the surface mount or tuning-fork crystals available

today. Table 7 summarizes these parameters.

capacitance. In-circuit tests with commercially available

crystals demonstrate that this range of capacitance allows

frequency control from +116ppm to -37ppm, using a 12.5pF

load crystal.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature

is available for the Intersil RTC family. There are three bits

known as the Digital Trimming Register or DTR, and they

operate by adding or skipping pulses in the clock signal. The

range provided is ±30ppm in increments of 10ppm. The

default setting is 0ppm. The DTR control can be used for

coarse adjustments of frequency drift over temperature or for

crystal initial accuracy correction.

Table 8 contains some crystal manufacturers and part

numbers that meet the requirements for the Intersil RTC

products.

The turnover temperature in Table 7 describes the

temperature where the apex of the of the drift vs.

temperature curve occurs. This curve is parabolic with the

2

drift increasing as (T-T0) . For an Epson MC-405 device, for

example, the turnover temperature is typically +25°C, and a

peak drift of >110ppm occurs at the temperature extremes of

TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S

PARAMETER

MIN

TYP

MAX

UNITS

kHz

ppm

°C

NOTES

Frequency

32.768

Frequency Tolerance

±100

30

Down to 20ppm if desired

Turnover Temperature

20

25

Typically the value used for most crystals

Operating Temperature Range

Parallel Load Capacitance

Equivalent Series Resistance

-40

85

°C

12.5

pF

50

kΩ

For best oscillator performance

FN6371.1

October 18, 2006

21

ISL12025

TABLE 8. CRYSTAL MANUFACTURERS

MANUFACTURER

Citizen

PART NUMBER

TEMP RANGE

-40 to +85°C

-10 to +60°C

-40 to +85°C

+25°C FREQUENCY TOLERANCE

CM201, CM202, CM200S

MC-405, MC-406

RSM-200S-A or B

32S12A or B

±20ppm

Epson

Raltron

SaRonix

Ecliptek

ECS

ECPSM29T-32.768K

ECX-306/ECX-306I

FSM-327

Fox

A final application for the ATR control is in-circuit calibration

for high accuracy applications, along with a temperature

sensor chip. Once the RTC circuit is powered up with battery

backup, and frequency drift is measured. The ATR control is

then adjusted to a setting which minimizes drift. Once

adjusted at a particular temperature, it is possible to adjust at

other discrete temperatures for minimal overall drift, and

store the resulting settings in the EEPROM. Extremely low

overall temperature drift is possible with this method. The

Intersil evaluation board contains the circuitry necessary to

implement this control.

The X1 and X2 connections to the crystal are to be kept as

short as possible. A thick ground trace around the crystal is

advised to minimize noise intrusion, but ground near the X1

and X2 pins should be avoided as it will add to the load

capacitance at those pins. Keep in mind these guidelines for

other PCB layers in the vicinity of the RTC device. A small

decoupling capacitor at the V

pin of the chip is mandatory,

DD

with a solid connection to ground (Figure 27).

Oscillator Measurements

When a proper crystal is selected and the layout guidelines

above are observed, the oscillator should start up in most

circuits in less than one second. Some circuits may take

slightly longer, but startup should definitely occur in less than

5s. When testing RTC circuits, the most common impulse is

to apply a scope probe to the circuit at the X2 pin (oscillator

output) and observe the waveform. DO NOT DO THIS!

Although in some cases you may see a usable waveform,

due to the parasitics (usually 10pF to ground) applied with

the scope probe, there will be no useful information in that

waveform other than the fact that the circuit is oscillating.

The X2 output is sensitive to capacitive impedance so the

voltage levels and the frequency will be affected by the

parasitic elements in the scope probe. Applying a scope

probe can possibly cause a faulty oscillator to start up, hiding

other issues (although in the Intersil RTC’s, the internal

circuitry assures startup when using the proper crystal and

layout).

For more detailed operation, see Intersil’s application note

AN154 on Intersil’s website at www.intersil.com.

Layout Considerations

The crystal input at X1 has a very high impedance and will

pick up high frequency signals from other circuits on the

board. Since the X2 pin is tied to the other side of the crystal,

it is also a sensitive node. These signals can couple into the

oscillator circuit and produce double clocking or

mis-clocking, seriously affecting the accuracy of the RTC.

Care needs to be taken in layout of the RTC circuit to avoid

noise pickup. Figure 27 shows a suggested layout for the

ISL12025 or ISL12027 devices.

The best way to analyze the RTC circuit is to power it up and

read the real-time clock as time advances. Alternatively the

frequency can be checked by setting an alarm for each

minute. Using the pulse interrupt mode setting, the once-per-

minute interrupt functions as an indication of proper

oscillation.

Backup Battery Operation

Many types of batteries can be used with the Intersil RTC

products. 3.0V or 3.6V Lithium batteries are appropriate, and

sizes are available that can power a Intersil RTC device for

up to 10 years. Another option is to use a supercapacitor for

applications where V

may disappear intermittently for

DD

short periods of time. Depending on the value of

FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8

supercapacitor used, backup time can last from a few days

FN6371.1

October 18, 2006

22

ISL12025

to two weeks (with >1F). A simple silicon or Schottky barrier

diode can be used in series with V to charge the

Mode. In actuality the V

switching to battery backup, which will disable I C

ANYTIME the device goes into Battery Backup Mode.

will go below V

before

RESET

DD

2

DD

supercapacitor, which is connected to the V

pin. Try to

BAT

2

Regardless of the battery voltage, the I C will work down

use Schottky diodes with very low leakages, <1µA desirable.

Do not use the diode to charge a battery (especially lithium

batteries!).

to the V

voltage (see Figure 29).

RESET

• Mode B - In this mode the selection bits indicate

switchover to battery backup at V <V

communications in battery backup. In order to

communicate in Battery Backup Mode, the V

voltage must be less than the V

2

, and I C

DD BAT

There are two possible modes for battery backup operation,

Standard and Legacy Mode. In Standard Mode, there are no

operational concerns when switching over to battery backup

since all other devices functions are disabled. Battery drain

RESET

voltage AND V

BAT

DD

2

must be greater than V

bus pins must go to V

. Also, pull-ups on the I C

to communicate. This mode is

RESET

BAT

is minimal in Standard Mode, and return to Normal V

DD

powered operations predictable. In Legacy modes, the V

the same as the normal operating mode of the X1227

device

BAT

pin can power the chip if the voltage is above V

and

DD

V

. This makes it possible to generate alarms and

TRIP

• Mode C - In this mode the selection bits indicate a low

communicate with the device under battery backup, but the

supply current drain is much higher than the Standard Mode

and backup time is reduced. During initial power-up, the

default mode is the Legacy Mode.

V

switchover combined with no communications in

DD

battery backup. Operation is actually identical to Mode A

2

with I C communications down to V

communications (see Figure 28).

= V

, then no

DD

RESET

• Mode D - In this mode the selection bits indicate

switchover to battery backup at V < V

2

I C Communications During Battery Backup and

, and no I C

DD

BAT

LVR Operation

communications in battery backup. This mode is unique in

2

that there is I C communication as long as V

is higher

Operation in Battery Backup Mode and LVR is affected by

the BSW and SBIB bits as described previously. These bits

allow flexible operation of the serial bus and EEPROM in

Battery Backup Mode, but certain operational details need to

be clear before utilizing the different modes. The most

DD

, whichever is greater. This mode is

than V

or V

RESET

BAT

2

the safest for guaranteeing I C communications only

when there is a Valid V

(see Figure 29).

DD

significant detail is that once V

2

goes below V , then

I C communications cease regardless of whether the device

DD

RESET

V

BAT

2.7V TO 5.5V

DD

2

is programmed for I C operation in Battery Backup Mode.

SUPERCAPACITOR

V

Table 9 describes four different modes possible with using

the BSW and SBIB bits, and how they are affect LVR and

battery backup operation.

SS

• Mode A - In this mode selection bits indicate a low V

switchover combined with I C operation in Battery Backup

DD

FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT

2

.

2

TABLE 9. I C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (Shaded Row is same as X1227 operation)

2

VBAT

SWITCHOVER

VOLTAGE

I C ACTIVE IN

BATTERY

BACKUP?

BSW

BIT

EEPROMWRITE/READ

IN BATTERY BACKUP?

MODE

SBIB BIT

NOTES

Operation of I C bus down to

2

A

0

1

0

1

Standard Mode,

NO

YES

NO

V

= 2.2V typ

V

= V

, then below that no

TRIP

DD

RESET

communications. Battery switchover at

V

.

TRIP

2

B

0

1

Legacy Mode,

< V

YES, only if

Operation of I C bus into Battery Backup

Mode, but only for

(X1227

Mode)

V

>V

DD

BAT

BAT RESET

V

> V

.

BAT

DD

RESET

Bus must have pullups to V

.

BAT

2

C

Standard Mode,

= 2.2V typ

NO

Operation of I C bus down to

V

= V

, then below that no

RESET

TRIP

DD

communications. Battery switchover at

V

.

TRIP

2

D

Legacy Mode,

< V

NO

Operation of I C bus down to V

or

RESET

V

, whichever is higher.

BAT

DD

BAT

.

FN6371.1

October 18, 2006

23

ISL12025

V

(3.0V)

BAT

(2.63V)

V

DD

V

RESET

V

TRIP

(2.2V)

tPURST

RESET

2

I C BUS ACTIVE

I

(BATTERY BACKUP MODE)

BAT

(VDD POWER, V

NOT CONNECTED)

BAT

FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C

V

(3.0V)

BAT

V

DD

V

(2.63V)

RESET

V

TRIP

(2.2V)

tPURST

RESET

2

I C BUS ACTIVE

I

(BATTERY BACKUP MODE)

BAT

FIGURE 30. RESET OPERATION IN MODE D

FN6371.1

October 18, 2006

24

ISL12025

After these registers are set, an alarm will be generated when

Alarm Operation Examples

the RTC advances to exactly 11:30am on January 1 (after

seconds change from 59 to 00) by setting the AL0 bit in the

status register to “1”.

Below are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1 – Alarm 0 set with single interrupt (IM = “0”)

A single alarm will occur on January 1 at 11:30am.

A. Set Alarm0 registers as follows:

Example 2 – Pulsed interrupt once per minute (IM = “1”)

Interrupts at one minute intervals when the seconds register

is at 30s.

A. Set Alarm0 registers as follows:

BIT

ALARM0

REGISTER 7

6

0

5

0

1

4

0

1

3

0

2

0

1

0

HEX

DESCRIPTION

BIT

ALARM0

REGISTER 7

SCA0

MNA0

0

1

00h Seconds disabled

6

5

4

3

2

1

0 HEX

DESCRIPTION

B0h Minutes set to 30,

enabled

SCA0

1

0

1

0

B0h Seconds set to 30,

enabled

HRA0

DTA0

MOA0

DWA0

1

0

1

0

1

0

91h Hours set to 11,

enabled

MNA0

HRA0

DTA0

MOA0

DWA0

0

00h Minutes disabled

00h Hours disabled

00h Date disabled

81h Date set to 1,

enabled

81h Month set to 1,

enabled

00h Month disabled

00h Day of week disabled

00h Day of week

disabled

B. Set the Interrupt register as follows:

B. Also, the AL0E bit must be set as follows:

BIT

CONTROL

REGISTER 7

6

5

4

3

2

1

0 HEX

DESCRIPTION

BIT

CONTROL

REGISTER

INT

1

0

1

0

x0h Enable Alarm and Int

Mode

7

6

5

4

3

2

1

0

HEX DESCRIPTION

INT

0

1

0

x0h Enable Alarm

Note that the status register AL0 bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

FN6371.1

October 18, 2006

25

ISL12025

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN6371.1

October 18, 2006

26

ISL12025

Thin Shrink Small Outline Plastic Packages (TSSOP)

M8.173

N

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

INCHES

MIN

MILLIMETERS

GAUGE

PLANE

SYMBOL

MAX

0.047

0.006

0.051

0.0118

0.0079

0.120

0.177

MIN

-

MAX

1.20

0.15

1.05

0.30

0.20

3.05

4.50

NOTES

A

A1

A2

b

-

1

2

3

0.002

0.031

0.0075

0.0035

0.116

0.169

0.05

0.80

0.19

0.09

2.95

4.30

-

L

0.25

0.010

-

0.05(0.002)

SEATING PLANE

A

9

-A-

D

c

-

D

3

-C-

α

E1

e

4

A2

e

A1

0.026 BSC

0.65 BSC

-

c

b

0.10(0.004)

E

0.246

0.256

6.25

0.45

6.50

0.75

-

0.10(0.004) M

C

A M B S

L

0.0177

0.0295

6

N

8

7

NOTES:

o

0

8

0

8

-

α

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

Rev. 1 12/00

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6371.1

October 18, 2006

27


型号：	ISL12025IVZ
厂家：	Intersil
描述：	Real-Time Clock/Calendar with EEPROM 实时时钟/日历与EEPROM 外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件：	总27页 (文件大小：402K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL12025IVZ [INTERSIL]

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