ID82C55A-5 [INTERSIL]
CMOS Programmable Peripheral Interface; CMOS可编程外设接口
| 型号： | ID82C55A-5 |
| 厂家： | 
Intersil |
| 描述： | CMOS Programmable Peripheral Interface |
| 文件： | 总26页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C55A
CMOS Programmable
Peripheral Interface
June 1998
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
TEMPERATURE PKG.
5MHz
8MHz
PACKAGE
RANGE
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
o
o
CP82C55A-5
IP82C55A-5
CS82C55A-5
IS82C55A-5
CD82C55A-5
ID82C55A-5
CP82C55A
IP82C55A
CS82C55A
IS82C55A
CD82C55A
ID82C55A
0 C to 70 C
40 Ld PDIP
o
o
-40 C to 85 C
o
o
0 C to 70 C
44 Ld PLCC
o
o
-40 C to 85 C
o
o
0 C to 70 C
40 Ld
CERDIP
o
o
-40 C to 85 C
o
o
MD82C55A-5/B MD82C55A/B
8406601QA 8406602QA
-55 C to 125 C
SMD#
44 Pad
CLCC
o
o
MR82C55A-5/B MR82C55A/B
-55 C to 125 C
J44.A
J44.A
8406601XA
8406602XA
SMD#
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
82C55A (PLCC)
TOP VIEW
TOP VIEW
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PA3
PA2
PA1
PA0
RD
PA4
6
5 4 3 2 1 44 43 42 41 40
PA5
PA6
PA7
WR
RESET
D0
6
5 4 3 2 1 44 43 42 41 40
3
39
38
7
8
GND
NC
NC
RESET
D0
4
CS
GND
A1
A0
PC7
NC
7
8
9
39
38
37 D1
RESET
D0
5
37
36
35
34
33
32
31
9
A1
6
CS
10
11
12
13
14
15
16
17
A0
D1
10
11
12
13
14
15
16
17
D2
D3
NC
D4
D5
D6
D7
V
36
35
34
33
32
31
30
29
7
GND
A1
PC7
PC6
PC5
PC4
PC0
PC1
PC2
D2
8
D1
D3
9
A0
D2
D4
PC6
PC5
PC4
PC0
PC1
10
11
12
13
14
15
16
17
18
19
20
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
D3
D5
D4
D6
D5
30 D7
29 NC
D6
CC
D7
18 1920 21 22 23 24 25 26 27 28
18 19 20 21 22 23 24 25 26 27 28
26 V
CC
PB7
25
24
23
22
21
PB6
PB5
PB4
PB3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2969.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
82C55A
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
V
26
V
CC
CC
recommended for decoupling.
GND
7
GROUND
D0-D7
27-34
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET
CS
35
6
I
I
I
I
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
RD
5
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WR
36
8, 9
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
A0-A1
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PA0-PA7
1-4, 37-40
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PB0-PB7
PC0-PC7
18-25
10-17
I/O
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
I/O
PA7-PA0
+5V
GROUP A
PORT A
(8)
POWER
SUPPLIES
GND
GROUP A
CONTROL
GROUP A
PORT C
UPPER
(4)
I/O
PC7-PC4
BI-DIRECTIONAL
DATA BUS
DATA BUS
BUFFER
D7-D0
GROUP B
PORT C
LOWER
(4)
8-BIT
INTERNAL
DATA BUS
I/O
PC3-PC0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-PB0
A0
RESET
CS
2
82C55A
Functional Description
I/O
PA7-
PA0
+5V
GND
GROUP A
PORT A
(8)
POWER
SUPPLIES
Data Bus Buffer
GROUP A
CONTROL
This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.
I/O
PC7-
PC4
GROUP A
PORT C
UPPER
(4)
BI-DIRECTIONAL
DATA BUS
I/O
DATA
PC3-
PC0
BUS
BUFFER
GROUP B
PORT C
LOWER
(4)
D7-D0
8-BIT
INTERNAL
DATA BUS
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
I/O
PB7-
PB0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
A0
RESET
(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.
CS
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
Group A and Group B Controls
82C55A BASIC OPERATION
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con-
trol word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that ini-
tializes the functional configuration of the 82C55A.
INPUT OPERATION
A1
0
A0
0
RD WR CS
(READ)
Port A → Data Bus
Port B → Data Bus
Port C → Data Bus
Control Word → Data Bus
0
0
0
0
1
1
1
1
0
0
0
0
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
0
1
1
0
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
1
1
OUTPUT OPERATION
(WRITE)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus → Port A
Data Bus → Port B
Data Bus → Port C
Data Bus → Control
DISABLE FUNCTION
Data Bus → Three-State
Data Bus → Three-State
X
X
X
X
X
1
X
1
1
0
3
82C55A
Ports A, B, and C
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or “personality” to further enhance the power and flexibility of
the 82C55A.
ADDRESS BUS
CONTROL BUS
DATA BUS
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port con-
tains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
RD, WR
D7-D0
A0-A1
CS
82C55A
C
MODE 0
MODE 1
B
8
A
8
I/O
4
I/O
4
I/O
I/O
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
C
INPUT MODE
MASTER
RESET
B
A
OR MODE
CHANGE
8
I/O
8
I/O
INTERNAL
DATA IN
EXTERNAL
PORT A PIN
PB7-PB0 CONTROL CONTROL PA7-PA0
OR I/O OR I/O
INTERNAL
DATA OUT
(LATCHED)
MODE 2
C
B
8
A
OUTPUT MODE
BI-
I/O
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
DIRECTIONAL
V
CC
PB7-PB0
PA7-PA0
RESET
OR MODE
CHANGE
CONTROL
P
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
INTERNAL
DATA IN
EXTERNAL
PORT B, C
PIN
INTERNAL
DATA OUT
(LATCHED)
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
OUTPUT MODE
PORT B
1 = INPUT
0 = OUTPUT
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
MODE SELECTION
0 = MODE 0
1 = MODE 1
Operational Description
GROUP A
Mode Selection
PORT C (UPPER)
1 = INPUT
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
MODE SELECTION
00 = MODE 0
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional ini-
tialization required. This eliminates the need to pullup or pull-
down resistors in all-CMOS designs. The control word
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
4
82C55A
The modes for Port A and Port B can be separately defined, This function allows the programmer to enable or disable a
while Port C is divided into two portions as required by the CPU interrupt by a specific I/O device without affecting any
Port A and Port B definitions. All of the output registers, other device in the interrupt structure.
including the status flip-flops, will be reset whenever the
INTE Flip-Flop Definition
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu-
tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode se-
lection and device Reset.
The mode definitions and possible mode combinations may Operating Modes
seem confusing at first, but after a cursory review of the
Mode 0 (Basic Input/Output). This functional configuration
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi-
nition vs. PC layout and complete functional flexibility to sup-
port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ-
ten to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software • Input are not latched
requirements in control-based applications.
• 16 different Input/Output configurations possible
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
MODE 0 PORT DEFINITION
A
B
GROUP A
PORTC
GROUP B
PORTC
CONTROL WORD
D4 D3
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0 PORT A (Upper)
#
0
1
2
3
4
5
6
7
8
9
PORT B (Lower)
D7 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Output
Output Output
Output Output
Output Output
Output Output
Output
Input
Input
Output
Input
X
X
X
1 = SET
0 = RESET
DON’T
CARE
Input
BIT SELECT
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
Output
Output
Output
Output
Input
Input
Input
Output Output
Output
Input
Input
Output
Input
Input
Input
Input
BIT SET/RESET FLAG
0 = ACTIVE
Output
Output
Output Output
Input
Output
Input
Input
Output
Input
FIGURE 5. BIT SET/RESET FORMAT
Input
Output 10
Output 11
Interrupt Control Functions
Input
Input
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.
Input
Input
Input
Input
Input
12 Output Output
Input
13 Output
Input
Output
Input
Input
14
15
Input
Input
Input
5
82C55A
Mode 0 (Basic Input)
tRR
RD
tIR
tHR
INPUT
CS, A1, A0
D7-D0
tAR
tRA
tRD
tDF
Mode 0 (Basic Output)
tWW
WR
tWD
tDW
D7-D0
CS, A1, A0
OUTPUT
tAW
tWA
tWB
Mode 0 Configurations
CONTROL WORD #0
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #1
CONTROL WORD #3
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
6
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #4
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #5
CONTROL WORD #9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #6
CONTROL WORD #10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #7
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
7
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #12
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #13
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
Operating Modes
MODE 1 (PORT A)
PA7-PA0
Mode 1 - (Strobed Input/Output). This functional configura-
tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1/0
INTE
PC4
STBA
A
1
0
1
1
PC5
IBFA
PC6, PC7
1 = INPUT
0 = OUTPUT
Mode 1 Basic Function Definitions:
• Two Groups (Group A and Group B)
INTRA
I/O
PC3
2
RD
• Each group contains one 8-bit port and one 4-bit
control/data port
PC6, PC7
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
MODE 1 (PORT B)
PB7-PB0
• The 4-bit port is used for control and status of the 8-bit
port.
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTE
PC2
Input Control Signal Definition
B
STBB
IBFB
1
1
1
PC1
(Figures 6 and 7)
STB (Strobe Input)
INTRB
PC0
A “low” on this input loads data into the input latch.
RD
IBF (Input Buffer Full F/F)
FIGURE 6. MODE 1 INPUT
A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg-
ment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.
8
82C55A
tST
STB
IBF
tSIB
tSIT
tRIB
INTR
RD
tRIT
tPH
INPUT FROM
PERIPHERAL
tPS
FIGURE 7. MODE 1 (STROBED INPUT)
INTE A
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU Controlled by Bit Set/Reset of PC6.
when and input device is requesting service. INTR is set by
INTE B
the condition: STB is a “one”, IBF is a “one” and INTE is a
“one”. It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the pe-
ripheral device and then latch data into the peripheral device on
the rising edge of OBF.
INTE A
Controlled by bit set/reset of PC4.
INTE B
MODE 1 (PORT A)
Controlled by bit set/reset of PC2.
8
PA7-PA0
PC7
CONTROL WORD
Output Control Signal Definition
D7 D6 D5 D4 D3 D2 D1 D0
OBFA
ACKA
(Figure 8 and 9)
1
0
1
1
1/0
INTE
A
PC6
OBF - Output Buffer Full F/F). The OBF output will go “low”
to indicate that the CPU has written data out to be specified
port. This does not mean valid data is sent out of the part at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
PC4, PC5
1 = INPUT
0 = OUTPUT
INTRA
PC3
2
WR
PC4, PC5
ACK - Acknowledge Input). A “low” on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
MODE 1 (PORT B)
PB7-PB0
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
OBFB
ACKB
PC1
INTR - (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is
reset by the falling edge of WR.
1
1
0
INTE
PC2
B
INTRB
PC0
WR
FIGURE 8. MODE 1 OUTPUT
9
82C55A
tWOB
WR
tAOB
OBF
INTR
tWIT
ACK
tAK
tAIT
OUTPUT
tWB
FIGURE 9. MODE 1 (STROBED OUTPUT)
8
8
PA7-PA0
PC4
PA7-PA0
PC7
STBA
IIBFA
INTRA
I/O
OBFA
ACKA
INTRA
I/O
RD
WR
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
PC5
PC3
PC6
PC3
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
1
0
1
0
1
0
1/0
1
1
2
2
PC6, PC7
PC4, PC5
PC6, PC7
PC4, PC5
1 = INPUT
0 = OUTPUT
1 = INPUT
0 = OUTPUT
8
PB7, PB0
PB7, PB0
8
PC1
PC2
PC0
PC2
PC1
PC0
OBFB
ACKB
INTRB
STBB
IBFB
WR
RD
INTRB
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O
applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Mode 2 (Strobed Bi-Directional Bus I/O)
Output Operations
The functional configuration provides a means for communi-
cating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bi-directional
bus I/O). “Hand shaking” signals are provided to maintain
proper bus flow discipline similar to Mode 1. Interrupt gener-
ation and enable/disable functions are also available.
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the
three-state output buffer of port A to send out the data. Oth-
erwise, the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF). Con-
trolled by bit set/reset of PC4.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A)
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
Bi-Directional Bus I/O Control Signal Definition
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
(Figures 11, 12, 13, 14)
by bit set/reset of PC4.
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
10
82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTRA
PC3
1
1
1/0 1/0 1/0
PA7-PA0
PC7
8
OBFA
ACKA
INTE
PC6
PC2-PC0
1 = INPUT
0 = OUTPUT
1
INTE
2
STBA
IBFA
PC4
PC5
PORT B
1 = INPUT
0 = OUTPUT
WR
RD
GROUP B MODE
0 = MODE 0
1 = MODE 1
3
PC2-PC0
I/O
FIGURE 11. MODE CONTROL WORD
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
tAOB
OBF
INTR
ACK
tWOB
tAK
tST
STB
IBF
tSIB
tPS
tAD
tKD
PERIPHERAL
BUS
tRIB
tPH
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF •
MASK • ACK • WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)
11
82C55A
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC3
PC3
INTRA
INTRA
PA7-PA0
PA7-PA0
8
8
OBFA
ACKA
OBFA
ACKA
PC7
PC6
PC4
PC7
PC6
PC4
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
1
1/0
1
1
0
0
1/0
STBA
IBFA
STBA
IBFA
I/O
PC2-PC0
1 = INPUT
0 = OUTPUT
PC2-PC0
1 = INPUT
0 = OUTPUT
PC5
PC5
3
3
8
PC2-PC0
I/O
PC2-PC0
RD
RD
PB7-PB0
PB7, PB0
8
WR
WR
MODE 2 AND MODE 1 (OUTPUT)
MODE 2 AND MODE 1 (INPUT)
PC3
PC3
INTRA
INTRA
PA7-PA0
PA7-PA0
8
8
OBFA
ACKA
OBFA
ACKA
PC7
PC6
PC4
PC7
PC6
PC4
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STBA
IBFA
STBA
IBFA
1
1
1
0
1
1
1
1
PC5
PC5
PB7-PB0
PB7-PB0
8
8
OBFB
ACKB
STBB
IBFB
PC1
PC2
PC0
PC2
PC1
PC0
RD
RD
INTRB
INTRB
WR
WR
FIGURE 14. MODE 2 COMBINATIONS
12
82C55A
MODE DEFINITION SUMMARY
MODE 1
MODE 0
MODE 2
IN
OUT
IN
OUT
GROUP A ONLY
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Mode 0
or Mode 1
Only
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
INTRB
IBFB
STBB
INTRA
STBA
IBFA
I/O
INTRB
OBFB
ACKB
INTRA
I/O
I/O
ACKA
OBFA
I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA
I/O
Special Mode Combination Considerations
INPUT CONFIGURATION
D5 D4 D3 D2
There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a “Set Mode” command.
D7
D6
D1
D0
I/O
I/O
IBFA INTEA INTRA INTEB IBFB INTRB
GROUP A
OUTPUT CONFIGURATION
GROUP B
During a read of Port C, the state of all the Port C lines,
except the ACK and STB lines, will be placed on the data
bus. In place of the ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 17.
D7
D6
D5
D4
D3
D2
D1
D0
OBFA INTEA
I/O
I/O
INTRA INTEB OBFB INTRB
GROUP B
Through a “Write Port C” command, only the Port C pins
programmed as outputs in a Mode 0 group can be written.
No other pins can be affected by a “Write Port C” command,
nor can the interrupt enable flags be accessed. To write to
any Port C output programmed as an output in Mode 1 group
or to change an interrupt enable flag, the “Set/Reset Port C
Bit” command must be used.
GROUP A
FIGURE 15. MODE 1 STATUS WORD FORMAT
D7
D6
D5
D4
D3
D2
D1
D0
OBFA INTE1 IBFA INTE2 INTRA
X
X
X
GROUP A
GROUP B
With a “Set/Reset Port Cea Bit” command, any Port C line
programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C fare not affected by a
“Set/Reset Port C Bit” command. Writing to the correspond-
ing Port C bit positions of the ACK and STB lines with the
“Set Reset Port C Bit” command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.
(Defined by Mode 0 or Mode 1 Selection)
FIGURE 16. MODE 2 STATUS WORD FORMAT
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.
13
82C55A
Reading Port C Status (Figures 15 and 16)
Applications of the 82C55A
In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts “hand shaking”
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the “status” of
each peripheral device and change the program flow
accordingly.
The 82C55A is a very powerful tool for interfacing peripheral
equipment to the microcomputer system. It represents the
optimum use of available pins and flexible enough to inter-
face almost any I/O device without the need for additional
external logic.
Each peripheral device in a microcomputer system usually
has a “service routine” associated with it. The routine
manages the software interface between the device and the
CPU. The functional definition of the 82C55A is programmed
by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the
detailed operational description, a control word can easily be
developed to initialize the 82C55A to exactly “fit” the
application. Figures 18 through 24 present a few examples
of typical applications of the 82C55A.
There is not special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
perform this function.
INTERRUPT
ENABLE FLAG
ALTERNATE PORT C
PIN SIGNAL (MODE)
POSITION
INTE B
INTE A2
INTE A1
PC2
ACKB (Output Mode 1)
or STBB (Input Mode 1)
PC4
PC6
STBA (Input Mode 1 or
Mode 2)
ACKA (Output Mode 1 or
Mode 2)
FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
INTERRUPT
REQUEST
PC3 PA0
PA1
HIGH SPEED
PRINTER
PA2
PA3
PA4
PA5
PA6
PA7
MODE 1
(OUTPUT)
HAMMER
RELAYS
PC7
PC6
PC5
DATA READY
ACK
PAPER FEED
FORWARD/REV.
PC4
82C55A
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PAPER FEED
FORWARD/REV.
RIBBON
MODE 1
(OUTPUT)
CARRIAGE SEN.
PC1
PC2
DATA READY
ACK
PC0
INTERRUPT
REQUEST
CONTROL LOGIC
AND DRIVERS
FIGURE 18. PRINTER INTERFACE
14
82C55A
INTERRUPT
REQUEST
PC3 PA0
PA1
R0
R1
PA2
PA3
PA4
R2
R3
R4
FULLY
DECODED
KEYBOARD
INTERRUPT
REQUEST
PA5
PA6
PA7
R5
SHIFT
CONTROL
PC3 PA0
PA1
R0
R1
R2
MODE 1
(INPUT)
PA2
FULLY
DECODED
KEYBOARD
PA3
PA4
R3
R4
PC4
PC5
STROBE
ACK
PA5
PA6
PA7
R5
SHIFT
CONTROL
MODE 1
(INPUT)
82C55A
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
B4
B5
PC4
PC5
PC6
PC7
STROBE
ACK
BUST LT
TEST LT
82C55A
BURROUGHS
SELF-SCAN
DISPLAY
MODE 1
(OUTPUT)
TERMINAL
ADDRESS
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
BACKSPACE
CLEAR
MODE 0
(INPUT)
PC1
PC2
PC6
PC7
DATA READY
ACK
BLANKING
CANCEL WORD
INTERRUPT
REQUEST
FIGURE 20. KEYBOARD AND TERMINAL ADDRESS
INTERFACE
FIGURE 19. KEYBOARD AND DISPLAY INTERFACE
INTERRUPT
REQUEST
LSB
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PC6
PC7
PC3 PA0
PA1
R0
R1
R2
R3
R4
R5
SHIFT
CONTROL
PA2
PA3
PA4
CRT CONTROLLER
• CHARACTER GEN.
• REFRESH BUFFER
• CURSOR CONTROL
12-BIT
A/D
PA5
PA6
PA7
MODE 0
(OUTPUT)
CONVERTER
(DAC)
MODE 1
(OUTPUT)
ANALOG
OUTPUT
PC7
PC6
PC5
PC4
DATA READY
ACK
BLANKED
82C55A
BLACK/WHITE
PC0
PC1
82C55A
STB DATA
BIT
SET/RESET
PC2
PC1
PC0
ROW STB
COLUMN STB
CURSOR H/V STB
PC2
PC3
SAMPLE EN
STB
PB0
PB1
PB2
LSB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
8-BIT
MODE 0
(OUTPUT)
ANALOG
INPUT
D/A
CONVERTER
(ADC)
PB3
CURSOR/ROW/COLUMN
ADDRESS
H&V
MODE 0
(INPUT)
PC4
PC5
PC6
PC7
MAB
FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL
FIGURE 22. BASIC CRT CONTROLLER INTERFACE
15
82C55A
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PC3 PA0
PA1
PC3 PA0
PA1
D0
D1
D2
D3
D4
D5
D6
D7
R0
R1
R2
R3
R4
R5
R6
R7
PA2
PA3
PA4
PA5
PA2
PA3
PA4
FLOPPY DISK
CONTROLLER
AND DRIVE
B LEVEL
PAPER
TAPE
READER
PA5
PA6
PA7
MODE 1
(INPUT)
MODE 2
PA6
PA7
PC4
PC5
PC7
PC6
PC4
PC5
PC6
DATA STB
ACK (IN)
DATA READY
STB
ACK
STOP/GO
ACK (OUT)
MACHINE TOOL
82C55A
82C55A
PC2
PC1
PC0
TRACK “0” SENSOR
SYNC READY
INDEX
PC0
PC1
PC2
START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID
MODE 0
(INPUT)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
MODE 0
(OUTPUT)
MODE 0
(OUTPUT)
FLUID ENABLE
EMERGENCY STOP
BUSY LT
FIGURE 23. BASIC FLOPPY DISC INTERFACE
FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE
16
82C55A
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical, Note 1)
θ
θ
JC
JA
o
o
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
50 C/W
10 C/W
o
o
65 C/W
14 C/W
o
50 C/W
N/A
N/A
o
46 C/W
Operating Conditions
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Junction Temperature
CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V
Operating Temperature Range
o
o
o
C82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
o
o
o
I82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
M82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
(PLCC Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
Electrical Specifications
V
= 5.0V ±10%; T = 0 C to +70 C (C82C55A);
CC A
o
o
T = -40 C to +85 C (I82C55A);
T = -55 C to +125 C (M82C55A)
A
o
o
A
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
Logical One Input Voltage
2.0
2.2
-
V
I82C55A, C82C55A,
M82C55A
IH
V
Logical Zero Input Voltage
Logical One Output Voltage
-
0.8
-
V
V
IL
V
3.0
I
I
= -2.5mA,
= -100µA
OH
OH
OH
V
-0.4
CC
V
Logical Zero Output Voltage
Input Leakage Current
-
0.4
V
I
+2.5mA
OL
OL
I
-1.0
+1.0
µA
V
= V
or GND,
I
IN CC
DIP Pins: 5, 6, 8, 9, 35, 36
IO
I/O Pin Leakage Current
Bus Hold High Current
-10
-50
50
-2.5
-
+10
-400
400
µA
µA
µA
mA
µA
VO = V
or GND DIP Pins: 27 - 34
CC
IBHH
IBHL
VO = 3.0V. Ports A, B, C
VO = 1.0V. Port A ONLY
Ports A, B, C. Test Condition 3
Bus Hold Low Current
IDAR
ICCSB
ICCOP
Darlington Drive Current
Standby Power Supply Current
Operating Power Supply Current
Note 2, 4
10
V
= 5.5V, V = V
IN
or GND. Output Open
CC
CC
o
-
1
mA/MHz T = +25 C, V
= 5.0V, Typical (See Note 3)
CC
A
NOTES:
2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA).
4. Tested as V
OH
at -2.5mA.
o
Capacitance T = 25 C
A
SYMBOL
CIN
PARAMETER
TYPICAL
UNITS
pF
TEST CONDITIONS
Input Capacitance
I/O Capacitance
10
20
FREQ = 1MHz, All Measurements are
referenced to device GND
CI/O
pF
17
82C55A
o
o
AC Electrical Specifications
V
= +5V± 10%, GND = 0V; T = -55 C to +125 C (M82C55A) (M82C55A-5);
CC A
o
o
T = -40 C to +85 C (I82C55A) (I82C55A-5);
A
o
o
T = 0 C to +70 C (C82C55A) (C82C55A-5)
A
82C55A-5
82C55A
TEST
SYMBOL
READ TIMING
(1) tAR
PARAMETER
MIN
MAX
MIN
MAX
UNITS
CONDITIONS
Address Stable Before RD
Address Stable After RD
RD Pulse Width
0
0
-
-
0
0
-
-
ns
ns
ns
ns
ns
ns
(2) tRA
(3) tRR
250
-
-
150
-
-
(4) tRD
Data Valid From RD
200
75
-
120
75
-
1
2
(5) tDF
Data Float After RD
10
300
10
300
(6) tRV
Time Between RDs and/or WRs
WRITE TIMING
(7) tAW
Address Stable Before WR
Address Stable After WR
WR Pulse Width
0
-
-
-
-
-
0
-
-
-
-
-
ns
ns
ns
ns
ns
(8) tWA
20
20
(9) tWW
100
100
30
100
100
30
(10) tDW
(11) tWD
OTHER TIMING
(12) tWB
(13) tIR
Data Valid to WR High
Data Valid After WR High
WR = 1 to Output
-
350
-
-
350
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Peripheral Data Before RD
Peripheral Data After RD
ACK Pulse Width
0
0
(14) tHR
(15) tAK
0
-
0
-
200
-
200
-
(16) tST
STB Pulse Width
100
-
100
-
(17) tPS
Peripheral Data Before STB High
Peripheral Data After STB High
ACK = 0 to Output
20
-
20
-
(18) tPH
(19) tAD
(20) tKD
(21) tWOB
(22) tAOB
(23) tSIB
(24) tRIB
(25) tRIT
(26) tSIT
(27) tAIT
(28) tWIT
(29) tRES
50
-
50
-
-
175
250
150
150
150
150
200
150
150
200
-
-
175
250
150
150
150
150
200
150
150
200
-
1
ACK = 1 to Output Float
WR = 1 to OBF = 0
20
20
2
-
-
1
ACK = 0 to OBF = 1
STB = 0 to IBF = 1
-
-
1
-
-
1
RD = 1 to IBF = 0
-
-
1
RD = 0 to INTR = 0
-
-
1
STB = 1 to INTR = 1
ACK = 1 to INTR = 1
WR = 0 to INTR = 0
Reset Pulse Width
-
-
1
-
-
-
-
1
1
500
500
1, (Note)
NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum.
18
82C55A
Timing Waveforms
tRR (3)
RD
tIR (13)
tHR (14)
INPUT
CS, A1, A0
D7-D0
tAR (1)
tRA (2)
tRD (4)
tDF (5)
FIGURE 25. MODE 0 (BASIC INPUT)
tWW (9)
WR
tWD (11)
tDW
(10)
D7-D0
CS, A1, A0
OUTPUT
tAW (7)
tWA (8)
tWS (12)
FIGURE 26. MODE 0 (BASIC OUTPUT)
tST (16)
STB
IBF
tSIB
(23)
tSIT
(26)
tRIB (24)
tRIT
(25)
INTR
RD
tPH
(18)
INPUT FROM
PERIPHERAL
tPS (17)
FIGURE 27. MODE 1 (STROBED INPUT)
19
82C55A
Timing Waveforms (Continued)
tWOB (21)
WR
tAOB (22)
OBF
tWIT
(28)
INTR
ACK
tAK (15)
tAIT (27)
OUTPUT
tWB (12)
FIGURE 28. MODE 1 (STROBED OUTPUT)
DATA FROM
CPU TO 82C55A
WR
(NOTE)
tAOB
(22)
OBF
INTR
ACK
tWOB
(21)
tAK
(15)
tST
(16)
STB
IBF
(NOTE)
tSIB
(23)
tAD (19)
tKD
(20)
tPS (17)
PERIPHERAL
BUS
tRIB (24)
tPH (18)
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
FIGURE 29. MODE 2 (BI-DIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD • OBF •
MASK • ACK • WR)
20
82C55A
Timing Waveforms (Continued)
A0-A1,
CS
A0-A1,
CS
tWA (8)
tRA (2)
tDF (5)
tAW (7)
tAR (1)
tRR (3)
DATA
BUS
RD
tDW (10)
tWD (11)
(4) tRD
DATA
BUS
WR
VALID
HIGH IMPEDANCE
tWW (9)
FIGURE 30. WRITE TIMING
FIGURE 31. READ TIMING
AC Test Circuit
AC Testing Input, Output Waveforms
V1
INPUT
OUTPUT
VIH + 0.4V
VOH
1.5V
1.5V
R1
OUTPUT FROM
DEVICE UNDER
TEST
VIL - 0.4V
VOL
TEST
POINT
AC Testing: All AC Parameters tested as per test circuits. Input RISE and
FALL times are driven at 1ns/V.
R2
C1
(SEE NOTE)
TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
R2
C1
NOTE: Includes STRAY and JIG Capacitance
1
2
3
1.7V
523Ω
2kΩ
Open
1.7kΩ
Open
150pF
50pF
50pF
V
CC
1.5V
750Ω
Burn-In Circuits
MD82C55A CERDIP
MR82C55A CLCC
F6
F7
F8
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
F11
F12
F13
3
F9
F4
F3
F14
F2
4
44
43 42 41 40
6
5
4
3
2
1
5
GND
F0
7
39
38
37
36
35
34
33
32
31
30
29
F5
6
F5
8
7
GND
F0
F15
F11
9
F15
8
10
11
12
13
14
15
16
17
F1
F11
F12
F1
F10
F6
9
F12
F13
F14
F15
F11
F12
F10
10
11
12
13
14
15
16
17
18
19
20
F6
F13
F7
F8
F9
F14
F15
F11
F12
F7
F8
F9
F10
F6
V
CC
F10
F6
F13
F14
F15
F11
F12
18 19 20 21 22 23 24 25 26 27 28
C1
F7
F8
C1
F9
F10
NOTES:
NOTES:
1. V
= 5.5V ± 0.5V
1. C1 = 0.01µF minimum
CC
2. VIH = 4.5V ± 10%
3. VIL = -0.2V to 0.4V
4. GND = 0V
2. All resistors are 47kΩ ± 5%
3. f0 = 100kHz ± 10%
4. f1 = f0 ÷ 2; f2 = f1 ÷ 2; . . . ; f15 = f14 ÷ 2
21
82C55A
Die Characteristics
DIE DIMENSIONS:
95 x 100 x 19 ±1mils
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
0.78 x 10 A/cm
5
2
Metallization Mask Layout
82C55A
RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
WR
RESET
D0
CS
GND
A1
A0
D1
D2
PC7
PC6
PC5
PC4
PC0
D3
D4
D5
D6
D7
V
CC
PC1
PC2
PD3
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
22
82C55A
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INCHES MILLIMETERS
INDEX
AREA
1 2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.980
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
2.095
-
4.95
0.558
1.77
0.381
53.2
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
50.3
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
40
40
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
23
82C55A
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.042 (1.07)
N44.65 (JEDEC MS-018AC ISSUE A)
0.048 (1.22)
0.004 (0.10)
C
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.056 (1.42)
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
SYM-
BOL
C
L
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.685
0.650
0.291
0.685
0.650
0.291
0.180
0.120
0.695
0.656
0.319
0.695
0.656
0.319
-
2.29
3.04
-
-
D2/E2
D2/E2
17.40
16.51
7.40
17.65
16.66
8.10
C
L
D1
D2
E
3
E1 E
4, 5
-
17.40
16.51
7.40
17.65
16.66
8.10
VIEW “A”
E1
E2
N
3
4, 5
6
0.020 (0.51)
MIN
44
44
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allow-
able mold protrusion is 0.010 inch (0.25mm) per side. Dimen-
sions D1 and E1 include mold mismatch and are measured at
the extreme material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
24
82C55A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.225
0.026
0.023
0.065
0.045
0.018
0.015
2.096
0.620
MIN
-
MAX
5.72
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
1.65
-
1.14
4
BASE
PLANE
Q
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
53.24
15.75
5
S1
b2
eA
A A
e
E
0.510
12.95
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.070
-
3.18
5.08
1.78
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
40
40
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
25
82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
J44.A MIL-STD-1835 CQCC1-N44 (C-5)
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES MILLIMETERS
MIN
D3
SYMBOL
A
MAX
0.120
0.088
0.039
0.028
MIN
1.63
1.37
0.84
0.56
MAX
3.05
2.24
0.99
0.71
NOTES
o
j x 45
0.064
0.054
0.033
0.022
6, 7
A1
B
-
4
2, 4
-
B1
B2
B3
D
0.072 REF
1.83 REF
E3
E
B
0.006
0.640
0.022
0.662
0.15
0.56
-
16.26
16.81
-
D1
D2
D3
E
0.500 BSC
0.250 BSC
12.70 BSC
6.35 BSC
-
-
o
h x 45
-
0.662
0.662
-
16.81
16.81
2
-
0.010 S E F S
A1
0.640
16.26
E1
E2
E3
e
0.500 BSC
0.250 BSC
0.662
0.050 BSC
0.015
12.70 BSC
6.35 BSC
16.81
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
PLANE 2
PLANE 1
-
-
2
-
-E-
e1
h
-
-
2
5
5
-
0.040 REF
0.020 REF
j
0.007 M E F S H S
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.90
0.08
1.40
1.40
2.41
0.38
B1
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
e
-
L3
L
-H-
-
11
11
44
11
11
44
3
3
3
-F-
Rev. 0 5/18/94
NOTES:
B3
E1
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
E2
B2
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L1
D2
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
e1
D1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
26
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