ICL7116 [INTERSIL]
31/2 Digit, LCD/LED Display, A/D Converter with Display Hold; 31/2位， LCD / LED显示，A / D转换器，显示保持
| 型号： | ICL7116 |
| 厂家： | 
Intersil |
| 描述： | 31/2 Digit, LCD/LED Display, A/D Converter with Display Hold |
| 文件： | 总14页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL7116, ICL7117
1
3 / Digit, LCD/LED Display,
2
A/D Converter with Display Hold
January 1998
Features
Description
• HOLD Reading Input Allows Indefinite Display Hold
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
The Intersil ICL7116 and ICL7117 are high performance, low
1
power, 3 / digit, A/D converters. Included are seven segment
2
decoders, display drivers, a reference, and a clock. The
ICL7116 is designed to interface with a liquid crystal display
(LCD) and includes a multiplexed backplane drive. The
ICL7117 will directly drive an instrument size, light emitting
diode (LED) display.
• Direct Display Drive
- LCD ICL7116
- LED lCL7117
The ICL7116 and ICL7117 have all of the features of the
ICL7106 and ICL7107 with the addition of a HOLD Reading
input. With this input, it is possible to make a measurement
and retain the value on the display indefinitely. To make room
for this feature the reference low input has been connected
to Common internally rather than being fully differential.
These circuits retain the accuracy, versatility, and true econ-
omy of the ICL7106 and ICL7107. They feature auto-zero to
• Low Noise - Less Than 15µV
(Typ)
P-P
• On Chip Clock and Reference
• Low Power Dissipation - Typically Less Than 10mW
• No Additional Active Circuits Required
• Surface Mount Package Available
o
less than 10µV, zero drift of less than 1µV/ C, input bias cur-
Ordering Information
rent of 10pA maximum, and roll over error of less than one
count. The versatility of true differential input is of particular
advantage when measuring load cells, strain gauges and
other bridge-type transducers. And finally, the true economy
of single power supply operation (ICL7116) enables a high
performance panel meter to be built with the addition of only
eleven passive components and a display.
TEMP.
o
PART NUMBER RANGE ( C)
PACKAGE
40 Ld PDIP
44 Ld MQFP
40 Ld PDIP
PKG. NO.
E40.6
ICL7116CPL
ICL7116CM44
ICL7117CPL
0 to 70
0 to 70
0 to 70
Q44.10x10
E40.6
Pinouts
ICL7116, ICL7117 (PDIP)
ICL7116 (MQFP)
TOP VIEW
TOP VIEW
1
2
40 OSC 1
39 OSC 2
38 OSC 3
37 TEST
36 REF HI
35 V+
HLDR
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
3
4
(1’s)
5
6
44 43 42 41 40 39 38 37 36 35 34
1
NC
G2
C3
A3
G3
NC
NC
33
32
31
30
29
7
34
33
C
C
+
-
REF
REF
2
8
3
4
5
6
7
8
9
TEST
OSC 3
NC
9
32 COMMON
31 IN HI
30 IN LO
29 A-Z
10
11
12
13
14
15
16
17
18
19
20
(10’s)
OSC 2
OSC 1
HLDR
D1
28
27
26
25
24
23
BP
POL
AB4
E3
28 BUFF
27 INT
26 V-
10
11
C1
F3
25 G2 (10’s)
24 C3
(100’s)
B1
B3
12 13 14 15 16 17 18 19 20 21 22
(100’s)
23 A3
22 G3
(1000) AB4
POL
21 BP/GND
(MINUS)
A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3083.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
ICL7116, ICL7117
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
ICL7116, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7117, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7117, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-
Clock Input
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
50
80
o
o
o
o
(MQFP - Lead Tips Only)
ICL7116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications (Note 3) T = 25 C, f
= 48kHz, V
= 100mV
REF
A
CLOCK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Zero Input Reading
Ratiometric Reading
Rollover Error
V
V
= 0V, Full Scale = 200mV
-000.0 ±000.0 +000.0 Digital
IN
lN
Reading
= V
, V
REF REF
= 100mV
999
999/
1000
1000
±1
Digital
Reading
-V = +V
IN
195mV Difference in Reading for Equal
-
-
±0.2
Counts
lN
Positive and Negative Inputs Near Full Scale
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 5)
±0.2
±1
Counts
Common Mode Rejection Ratio
Noise
V
V
= ±1V, V = 0V, Full Scale = 200mV (Note 5)
IN
-
-
50
15
-
-
µV/V
µV
CM
= 0V, Full Scale = 200mV (Peak-To-Peak Value
IN
Not Exceeded 95% of Time) (Note 5)
Leakage Current Input
V
V
V
V
= 0 (Note 5)
o
-
1
10
1
pA
lN
lN
IN
IN
o
o
Zero Reading Drift
= 0, 0 C To 70 C (Note 5)
-
0.2
1
µV/ C
o
o
o
Scale Factor Temperature Coefficient
V+ Supply Current
= 199mV, 0 C To 70 C (Note 5)
-
-
5
ppm/ C
= 0 (Does Not Include LED Current for ICL7117)
1.0
0.6
3.0
1.8
1.8
3.2
mA
mA
V
V- Supply Current
ICL7117 Only
-
COMMON Pin Analog Common Voltage
25kΩ Between Common and Positive Supply (With
2.4
Respect to + Supply)
o
Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With
-
80
-
ppm/ C
Respect to + Supply) (Note 5)
DISPLAY DRIVER (ICL7116 ONLY)
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V, (Note 4)
4
5.5
6
V
DISPLAY DRIVER (ICL7117 ONLY)
Segment Sinking Current
(Except Pins 19 and 20)
V+ = 5V, Segment Voltage = 3V
5
10
4
8
16
7
-
-
-
mA
mA
mA
Pin 19 Only
Pin 20 Only
NOTES:
3. Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117. ICL7116 is tested in the circuit of Figure 1. ICL7117 is
tested in the circuit of Figure 2.
4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times con-
version rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
2
ICL7116, ICL7117
Typical Applications and Test Circuits
+ -
IN
9V
+
-
C
C
C
C
C
R
R
R
R
R
= 0.1µF
= 0.47µF
= 22µF
= 100pF
= 0.01µF
= 24kΩ
= 47kΩ
= 100kΩ
= 1kΩ
1
2
3
4
5
1
2
3
4
5
R
R
R
5
1
C
5
C
R
4
4
3
R
2
C
C
2
3
C
1
DISPLAY
= 1MΩ
ICL7116
DISPLAY
FIGURE 1. ICL7116 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
C
C
C
C
C
R
R
R
R
R
R
= 0.1µF
= 0.47µF
= 22µF
= 100pF
= 0.01µF
= 24kΩ
= 47kΩ
= 100kΩ
= 1kΩ
1
2
3
4
5
1
2
3
4
5
6
R
6
+5V
-5V
+
-
TO
DECIMAL
POINT
IN
R
5
R
R
1
TP
TP
TP TP
1 2
3
5
C
5
R
2
R
4
C
C
C
3
3
4
2
DISPLAY
= 1MΩ
= 150Ω
TP
C
4
1
ICL7117
DISPLAY
FIGURE 2. ICL7117 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
3
ICL7116, ICL7117
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
• DISPLAY COUNT
V
IN
f
= 0.45/RC
--------------
COUNT = 1000 ×
OSC
V
REF
C
f
> 50pF; R > 50kΩ
OSC
OSC
(Typ) = 48kHz
OSC
• OSCILLATOR PERIOD
= RC/0.45
• CONVERSION CYCLE
t
t
= t
= t
x 4000
CYC
CYC
CL0CK
x 16,000
t
OSC
• INTEGRATION CLOCK FREQUENCY
= f /4
OSC
= 48KHz; t
when f
= 333ms
OSC
CYC
• COMMON MODE INPUT VOLTAGE
f
CLOCK
OSC
• INTEGRATION PERIOD
= 1000 x (4/f
(V- + 1V) < V < (V+ - 0.5V)
lN
• AUTO-ZERO CAPACITOR
t
)
OSC
INT
• 60/50Hz REJECTION CRITERION
/t or t /t = Integer
0.01µF < C < 1µF
AZ
• REFERENCE CAPACITOR
t
INT 60Hz lNT 50Hz
0.1µF < C
< 1µF
REF
• OPTIMUM INTEGRATION CURRENT
= 4µA
• V
COM
I
INT
• FULL SCALE ANALOG INPUT VOLTAGE
(Typ) = 200mV or 2V
Biased between V+ and V-.
• V V+ - 2.8V
COM
Regulation lost when V+ to V- < 6.8V.
If V is externally pulled down to (V + to V -)/2,
V
lNFS
• INTEGRATE RESISTOR
COM
the V
V
INFS
circuit will turn off.
COM
R
= ----------------
INT
I
INT
• ICL7116 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
• INTEGRATE CAPACITOR
Digital supply is generated internally
(t
)(I
)
INT INT
V
V
V+ - 4.5V
TEST
C
= -------------------------------
INT
INT
• ICL7116 DISPLAY: LCD
• INTEGRATOR OUTPUT VOLTAGE SWING
Type: Direct drive with digital logic supply amplitude.
• ICL7117 POWER SUPPLY: DUAL ±5.0V
(t
)(I
)
INT INT
C
V
= -------------------------------
INT
INT
V+ = +5V to GND
V- = -5V to GND
• V
MAXIMUM SWING:
INT
Digital Logic and LED driver supply V+ to GND
(V- + 1.0V) < V
< (V+ - 0.5V), V (Typ) = 2V
INT
INT
• ICL7117 DISPLAY: LED
Type: Non-Multiplexed Common Anode
Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE
(COUNTS)
SIGNAL INTEGRATE
PHASE FIXED
DE-INTEGRATE PHASE
0 - 1999 COUNTS
2999 - 1000
1000 COUNTS
TOTAL CONVERSION TIME = 4000 x t
= 16,000 x t
OSC
CLOCK
4
ICL7116, ICL7117
Pin Descriptions
PIN NUMBER
44 PIN
40 PIN DIP FLATPACK
NAME
HLDR
D1
FUNCTION
Input
DESCRIPTION
1
8
Display Hold Control.
2
9
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Output
Output
Input
Driver Pin for Segment “D” of the display units digit.
Driver Pin for Segment “C” of the display units digit.
Driver Pin for Segment “B” of the display units digit.
Driver Pin for Segment “A” of the display units digit.
Driver Pin for Segment “F” of the display units digit.
Driver Pin for Segment “G” of the display units digit.
Driver Pin for Segment “E” of the display units digit.
Driver Pin for Segment “D” of the display tens digit.
Driver Pin for Segment “C” of the display tens digit.
Driver Pin for Segment “B” of the display tens digit.
Driver Pin for Segment “A” of the display tens digit.
Driver Pin for Segment “F” of the display tens digit.
Driver Pin for Segment “E” of the display tens digit.
Driver pin for segment “D” of the display hundreds digit.
Driver pin for segment “B” of the display hundreds digit.
Driver pin for segment “F” of the display hundreds digit.
Driver pin for segment “E” of the display hundreds digit.
Driver pin for both “A” and “B” segments of the display thousands digit.
Driver pin for the negative sign of the display.
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
C1
4
B1
5
A1
6
F1
7
G1
8
E1
9
D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
BP/GND
G3
Driver pin for the LCD backplane/Power Supply Ground.
Driver pin for segment “G” of the display hundreds digit.
Driver pin for segment “A” of the display hundreds digit.
Driver pin for segment “C” of the display hundreds digit.
Driver pin for segment “G” of the display tens digit.
Negative power supply.
A3
C3
G2
V-
INT
BUFF
A-Z
Integrator amplifier output. To be connected to integrating capacitor.
Input buffer amplifier output. To be connected to integrating resistor.
Integrator amplifier input. To be connected to auto-zero capacitor.
30
31
38
39
IN LO
IN HI
Input
Differential inputs. To be connected to input voltage to be measured. LO and HI
designators are for reference and do not imply that LO should be connected to
lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.
32
40
COMMON
Supply/
Output
Internal voltage reference output.
Connection pins for reference capacitor.
Power Supply.
33
34
41
42
C
-
REF
C
+
REF
35
36
43
44
V+
Supply
Input
REF HI
TEST
37
3
Display test. Turns on all segments when tied to V+.
Device clock generator circuit connection pins.
38
39
40
4
6
7
OSC3
OSC2
OSC1
Output
Output
Input
5
ICL7116, ICL7117
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
Detailed Description
Analog Section
V
IN
Figure 3 shows the Analog Section for the ICL7116 and
ICL7117. Each measurement cycle is divided into three
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE).
----------------
DISPLAY COUNT = 1000
.
V
REF
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative sup-
ply. In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator out-
put does not saturate. A worst case condition would be a large
positive common mode voltage with a near full scale negative
differential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common mode voltage. For these critical appli-
cations the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of
accuracy. The integrator output can swing to within 0.5V of
either supply without loss of linearity.
Auto-Zero Phase
During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor C to compensate
AZ
for offset voltages in the buffer amplifier, integrator, and compar-
ator. Since the comparator is included in the loop, the A-Z accu-
racy is limited only by the noise of the system. In any case, the
offset referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the inter-
nal short is removed, and the internal input high and low are
connected to the external pins. The converter then integrates
the differential voltage between IN HI and IN LO for a fixed time.
This differential voltage can be within a wide common mode
range: up to 1V from either supply. If, on the other hand, the
input signal has no return with respect to the converter power
supply, IN LO can be tied to analog COMMON to establish the
correct common mode voltage. At the end of this phase, the
polarity of the integrated signal is determined.
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
STRAY
STRAY
C
REF
R
C
C
INT
INT
AZ
BUFFER
REF HI
36
V+
35
C
+
C
-
A-Z
INT
27
REF
REF
34
33
28
29
V+
A-Z
INTEGRATOR
-
+
TO
DIGITAL
SECTION
10µA
-
+
+
2.8V
31
IN HI
DE-
DE+
INT
6.2V
A-Z
INPUT
HIGH
A-Z
COMPARATOR
A-Z
DE-
+
-
N
DE+
32
30
COMMON
IN LO
INPUT
LOW
A-Z AND DE(±)
INT
26
V-
FIGURE 3. ANALOG SECTION OF ICL7116 AND ICL711
6
ICL7116, ICL7117
Analog COMMON
V+
This pin is included primarily to set the common mode
voltage for battery operation (ICL7116) or for any system
where the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approxi-
mately 2.8V less than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (>6.8V), the COM-
MON voltage will have a low voltage coefficient (0.001%/V),
low output impedance ( 15Ω), and a temperature coefficient
V
6.8V
REF HI
ZENER
COMMON
I
Z
ICL7116
ICL7117
V-
o
typically less than 80ppm/ C.
FIGURE 4A.
The limitations of the on chip reference should also be
recognized, however. With the ICL7117, the internal heat-
ing which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature
Coefficient (TC), internal chip dissipation, and package
thermal resistance can increase noise near full scale from
V+
V
6.8kΩ
20kΩ
ICL7116
ICL7117
ICL8069
REF HI
1.2V
REFERENCE
25µV to 80µV
. Also the linearity in going from a high
P-P
dissipation count such as 1000 (20 segments on) to a low
dissipation count such as 1111 (8 segments on) can suffer
by a count or more. Devices with a positive TC reference
may require several counts to pull out of an over-range con-
dition. This is because over-range is a low dissipation
mode, with the three least significant digits blanked. Simi-
larly, units with a negative TC may cycle between over
range and a non-over range count as the die alternately
COMMON
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
TEST
heats and cools. All these problems are of course The TEST pin serves two functions. On the ICL7116 it is
eliminated if an external reference is used.
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other annunciator the user may want to include on the
LCD display. Figures 5 and 6 show such an application. No
more than a 1mA load should be applied.
The ICL7116, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 4.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
V+
1MΩ
TO LCD
DECIMAL
POINT
ICL7116
BP
21
TEST
37
TO LCD
BACKPLANE
Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 30mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.
FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA under
these conditions.
CAUTION: On the ICL7116, in the lamp test mode, the segments
have a constant DC voltage (no square-wave) and may burn the
LCD display if left in this mode for several minutes.
7
ICL7116, ICL7117
Digital Section
V+
Figures 7 and 8 show the digital section for the ICL7116 and
ICL7117, respectively. In the ICL7116, an internal digital
ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to absorb
the relative large capacitive currents when the back plane
(BP) voltage is switched. The BP frequency is the clock fre-
quency divided by 800. For three readings/second this is a
60Hz square wave with a nominal amplitude of 5V. The seg-
ments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON. In
all cases negligible DC voltage exists across the segments.
V+
BP
TO LCD
DECIMAL
POINTS
ICL7116
TEST
DECIMAL
POINT
SELECT
CD4030
GND
FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
HOLD Reading Input
Figure 8 is the Digital Section of the ICL7117. It is identical
to the ICL7116 except that the regulated supply and back
plane drive have been eliminated and the segment drive has
been increased from 2mA to 8mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
The HLDR input will prevent the latch from being updated
when this input is at logic “1”. The chip will continue to make
A/D conversions, however, the results will not be updated to
the internal latches until this input goes low. This input can be
left open or connected to TEST (ICL7116) or GROUND
(ICL7117) to continuously update the display. This input is
CMOS compatible, and has a 70kΩ (See Figure 7) typical
resistance to either TEST (ICL7116) or GROUND (ICL7117).
In both devices, the polarity indication is “on” for negative
analog inputs. If IN LO and IN HI are reversed, this indication
can be reversed also, if desired.
a
a
a
f
f
f
a
b
b
b
g
g
g
c
e
e
e
c
c
c
b
d
d
d
BACKPLANE
21
LCD PHASE DRIVER
7
7
7
TYPICAL SEGMENT OUTPUT
V+
SEGMENT
DECODE
SEGMENT
DECODE
SEGMENT
DECODE
÷200
0.5mA
LATCH
SEGMENT
OUTPUT
2mA
1000’s
100’s
10’s
1’s
COUNTER
COUNTER
COUNTER
COUNTER
INTERNAL DIGITAL GROUND
TO SWITCH DRIVERS
35
FROM COMPARATOR OUTPUT
V+
CLOCK
† THREE INVERTERS
ONE INVERTER SHOWN
FOR CLARITY
6.2V
500Ω
LOGIC CONTROL
÷
4
†
TEST
V-
INTERNAL
DIGITAL
37
V
= 1V
TH
70kΩ
GROUND
26
40
39
38
1
HLDR
OSC 1
OSC 3
OSC 2
FIGURE 7. ICL7116 DIGITAL SECTION
8
ICL7116, ICL7117
a
a
a
f
f
f
a
b
b
b
g
g
g
c
e
e
e
c
c
c
b
d
d
d
7
7
7
SEGMENT
DECODE
SEGMENT
DECODE
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
LATCH
0.5mA
TO
SEGMENT
1000’s
COUNTER
100’s
COUNTER
10’s
COUNTER
1’s
COUNTER
8mA
TO SWITCH DRIVERS
35
37
FROM COMPARATOR OUTPUT
DIGITAL GROUND
V+
V+
CLOCK
TEST
†
÷4
LOGIC CONTROL
500Ω
† THREE INVERTERS
ONE INVERTER SHOWN
FOR CLARITY
DIGITAL
GROUND
21
70kΩ
40
39
38
1
HLDR
OSC 1
OSC 3
OSC 2
FIGURE 8. ICL7117 DIGITAL SECTION
System Timing
INTERNAL TO PART
Figure 9 shows the clocking arrangement used in the
ICL7116 and ICL7117. Two basic clocking arrangements
can be used:
÷4
CLOCK
1. Figure 9A, an external oscillator connected to pin 40.
2. Figure 9B, an R-C oscillator using all three pins.
40
39
38
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and auto-
zero (1000 counts to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference de-
integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
GND ICL7117
TEST ICL7116
FIGURE 9A. EXTERNAL OSCILLATOR
INTERNAL TO PART
÷4
CLOCK
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
40
39
R
38
C
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
1
40kHz, 33 / kHz, etc. should be selected. For 50Hz rejec-
3
2
tion, Oscillator frequencies of 200kHz, 100kHz, 66 / kHz,
3
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/second) will reject both 50Hz and 60Hz (also
400Hz and 440Hz).
FIGURE 9B. RC OSCILLATOR
FIGURE 9. CLOCK CIRCUITS
9
ICL7116, ICL7117
have a full scale reading when the voltage from the
transducer is 0.682V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
Component Value Selection
Integrating Resistor
and select V
= 0.341V. Suitable values for integrating
REF
Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 4µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 470kΩ is near optimum and
similarly a 47kΩ for a 200mV scale.
resistor and capacitor would be 120kΩ and 0.22µF. This
makes the system slightly quieter and also avoids a divider
network on the input. The ICL7117 with ±5V supplies can
accept input signals up to ±4V. Another advantage of this
system occurs when a digital reading of zero is desired for
V
≠ 0. Temperature and weighing systems with a variable
IN
fare are examples. This offset reading can be conveniently
generated by connecting the voltage transducer between IN
HI and COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.
Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately. 0.5V from
either supply). In the ICL7116 or the ICL7117, when the
analog COMMON is used as a reference, a nominal +2V full-
scale integrator swing is fine. For the ICL7117 with +5V
supplies and analog COMMON tied to supply ground, a
±3.5V to +4V swing is nominal. For three readings/second
ICL7117 Power Supplies
3. The ICL7117 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2
capacitors, and an inexpensive lC. Figure 10 shows this
application. See ICL7660 data sheet for an alternative.
(48kHz clock) nominal values for C
are 0.22µF and 0.1µF,
lNT
respectively. Of course, if different oscillator frequencies are
used, these values should be changed in inverse proportion
to maintain the same output swing.
V+
An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.
CD4009
V+
OSC 1
IN914
+
10
µF
-
Auto-Zero Capacitor
OSC 2
OSC 3
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very important, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of recov-
ery from overload and is adequate for noise on this scale.
0.047
µF
ICL7117
GND
IN914
V-
Reference Capacitor
A 0.1µF capacitor gives good results in most applications.
Generally 1µF will hold the roll-over error to 0.5 counts in this
instance.
V- = 3.3V
FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V
Oscillator Components
For all ranges of frequency a 100kΩ resistor is recommended
and the capacitor is selected from the equation:
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
0.45
------------
f =
For 48kHz Clock (3 Readings/sec),
C = 100pF.
1. The input signal can be referenced to the center of the
common mode range of the converter.
RC
2. The signal is less than ±1.5V.
Reference Voltage
The analog input required to generate full scale output (2000
3. An external reference is used.
counts) is: V = 2V
. Thus, for the 200mV and 2V scale,
lN REF
V
should equal 100mV and 1V, respectively. However, in
REF
many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
10
ICL7116, ICL7117
Application Notes
Typical Applications
The ICL7116 and ICL7117 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatil-
ity of these A/D converters.
AnswerFAX
DOC. #
NOTE #
DESCRIPTION
AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
9016
9017
9018
The following application notes contain very useful
information on understanding and applying this part and
are available from Intersil Corporation.
AN018 “Do’s and Don’ts of Applying A/D
Converters”
AN023 “Low Cost Digital Panel Meter Designs”
9023
9032
AN032 “Understanding the Auto-Zero and
Common Mode Performance of the
ICL7136/7/9 Family”
AN046 “Building a Battery-Operated Auto
Ranging DVM with the ICL7106”
9046
9047
9052
AN047 “Games People Play with Intersil’ A/D
Converters,” edited by Peter Bradshaw
1
AN052 “Tips for Using Single Chip 3 / Digit A/D
2
Converters”
Typical Applications
OSC 1 40
OSC 1 40
100kΩ
100kΩ
OSC 2 39
OSC 2 39
OSC 3 38
SET V
OSC 3 38
SET V
REF
REF
100pF
100pF
TEST 37
REF HI 36
V+ 35
= 100mV
TEST 37
REF HI 36
V+ 35
= 100mV
+5V
1kΩ
22kΩ
1MΩ
1kΩ
22kΩ
1MΩ
C
C
34
33
C
34
33
REF
REF
REF
REF
0.1µF
0.1µF
C
COMMON 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
COMMON 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
V - 26
+
+
IN
0.01µF
IN
0.01µF
0.47µF
0.47µF
47kΩ
-
-
+
47kΩ
9V
-
0.22µF
0.22µF
-5V
V - 26
G2 25
G2 25
C3 24
C3 24
TO DISPLAY
TO DISPLAY
A3 23
A3 23
G3 22
G3 22
GND 21
BP 21
TO BACKPLANE
Values shown are for 200mV full scale, 3 readings/sec. IN LO may
be tied to either COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See discussion under
Analog COMMON.)
Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).
FIGURE 11. ICL7116 USING THE INTERNAL REFERENCE
FIGURE 12. ICL7117 USING THE INTERNAL REFERENCE
11
ICL7116, ICL7117
Typical Applications (Continued)
OSC 1 40
OSC 1 40
OSC 2 39
OSC 3 38
TEST 37
REF HI 36
V+ 35
100kΩ
100kΩ
OSC 2 39
OSC 3 38
SET V
= 1.000V
SET V
REF
REF
100pF
100pF
TEST 37
= 100mV
REF HI 36
+5V
V+ 35
V +
25kΩ
24kΩ
1kΩ 10kΩ 15kΩ
C
C
34
33
C
34
33
REF
REF
REF
0.1µF
0.1µF
C
REF
1.2V (ICL8069)
COMMON 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
COMMON 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
1MΩ
0.01µF
1MΩ
+
+
IN
IN
0.01µF
0.047µF
470kΩ
-
-
0.47µF
47kΩ
0.22µF
0.22µF
-
V - 26
V
V - 26
G2 25
G2 25
C3 24
C3 24
TO DISPLAY
TO DISPLAY
A3 23
A3 23
G3 22
G3 22
GND 21
GND 21
An external reference must be used in this application, since the
voltage between V+ and V- is insufficient for correct operation of the
internal reference.
FIGURE 13. ICL7116 AND ICL7117: RECOMMENDED
FIGURE 14. ICL7117 OPERATED FROM SINGLE +5V SUPPLY
COMPONENT VALUES FOR 2.0V FULL SCALE
V+
OSC 1 40
OSC 1 40
100kΩ
100kΩ
OSC 2 39
OSC 2 39
OSC 3 38
OSC 3 38
SCALE
100pF
TEST 37
100pF
TEST 37
FACTOR
ADJUST
REF HI 36
REF HI 36
V+ 35
V+ 35
22kΩ
100kΩ 1MΩ
C
C
34
33
C
C
34
33
REF
REF
REF
0.1µF
100kΩ 220kΩ
0.1µF
REF
COMMON 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
V - 26
COMMON 32
IN HI 31
IN LO 30
A-Z 29
ZERO
ADJUST
SILICON NPN
MPS 3704 OR
SIMILAR
0.01µF
0.47µF
47kΩ
0.47µF
47kΩ
BUFF 28
INT 27
9V
0.22µF
0.22µF
V - 26
V
G2 25
G2 25
C3 24
C3 24
TO DISPLAY
TO DISPLAY
A3 23
A3 23
G3 22
G3 22
BP 21
GND 21
TO BACKPLANE
A silicon diode-connected transistor has a temperature coefficient of
o
The resistor values within the bridge are determined by the desired
sensitivity.
about -2mV/ C. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiometer adjusted for a 100.0 reading.
FIGURE 15. ICL7117 MEASUREING RATIOMETRIC VALUES OF
QUAD LOAD CELL
FIGURE 16. ICL7116 USED AS A DIGITAL CENTIGRADE
THERMOMETER
12
ICL7116, ICL7117
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
N
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
AREA
1 2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.980
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
2.095
-
4.95
0.558
1.77
0.381
53.2
-
-
BASE
PLANE
A2
A
-C-
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
50.3
5
C
eC
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25)
C
B
S
M
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
40
40
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
13
ICL7116, ICL7117
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
MILLIMETERS
SYM-
BOL
MIN
MAX
MIN
-
MAX
2.35
NOTES
A
A1
A2
B
-
0.093
0.010
0.083
0.018
0.016
0.530
0.398
0.530
0.398
0.037
-
0.004
0.077
0.012
0.012
0.510
0.390
0.510
0.390
0.026
0.10
1.95
0.30
0.30
12.95
9.90
12.95
9.90
0.65
0.25
-
2.10
-
-B-
-A-
0.45
6
E
B1
D
0.40
-
E1
13.45
10.10
13.45
10.10
0.95
3
D1
E
4, 5
3
E1
L
4, 5
e
-
N
44
0.032 BSC
44
0.80 BSC
7
PIN 1
e
-
SEATING
PLANE
Rev. 1 1/94
-H-
A
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
0.10
0.004
-C-
o
o
5 -16
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane
0.40
0.016
0.20
0.008
MIN
D
A-B
M
C
S
S
-C-
.
o
0
MIN
4. Dimensions D1 and E1 to be determined at datum plane
-H-
B
.
A2
o
A1
B1
o
o
0 -7
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.13/0.17
0.005/0.007
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
o
5 -16
L
7. “N” is the number of terminal positions.
BASE METAL
WITH PLATING
0.13/0.23
0.005/0.009
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Mercure Center
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FAX: (407) 724-7240
14
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