ICL7104 [INTERSIL]
14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter; 14位/ 16位微处理器兼容，双芯片， A / D转换器
| 型号： | ICL7104 |
| 厂家： | 
Intersil |
| 描述： | 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter |
| 文件： | 总21页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL8052/ICL7104,
ICL8068/ICL7104
14-Bit/16-Bit, Microprocessor-
August 1997
Compatible, 2-Chip, A/D Converter
Features
Description
• 16-Bit/14-Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
The ICL7104, combined with the ICL8052 or ICL8068,
forms a member of Intersil’ high performance A/D converter
family. The ICL7104-16, performs the analog switching and
digital function for a 16-bit binary A/D converter, with full
three-state output, UART handshake capability, and other
outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil’ integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including ±0 null indication), single reference operation,
very high input impedance, true input integration over a
constant period for maximum EMI rejection, fully
• Ideally Suited for Interface to UARTs and
Microprocessors
• Conversion on Demand or Continuously
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage for True Ratiometric
Operation
rationmetric operation, over-range indication, and
a
medium quality built-in reference. The chip pair also offers
optional input buffer gain for high sensitivity applications, a
built-in clock oscillator, and output signals for providing an
external Auto-Zero capability in preconditioning circuitry,
synchronizing external multiplexers, etc.
• Onboard Clock and Reference
• Auto-Zero, Auto-Polarity
• Accuracy Guaranteed to 1 Count
• All Outputs TTL Compatible
• ±4V Analog Input Range
Ordering Information
• Status Signal Available for External Sync, A/Z in
Preamp, Etc.
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
14 Ld PDIP
ICL8052CPD
lCL8052CDD
lCL8052ACPD
ICL8052ACDD
ICL8068CDD
ICL8068ACDD
lCL8068ACJD
ICL7104-14CPL
lCL7104-16CPL
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
E14.3
14 Ld CERDIP
14 Ld PDIP
F14.3
E14.3
F14.3
F14.3
F14.3
F14.3
E40.6
E40.6
14 Ld CERDIP
14 Ld CERDIP
14 Ld CERDIP
14 Ld CERDIP
40 Ld PDIP
40 Ld PDIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number 3091.1
5-6
ICL8052/ICL7104, ICL8068/ICL7104
Pinouts
ICL8052/ICL8068
(CERDIP, PDIP)
TOP VIEW
ICL7104
(PDIP)
TOP VIEW
ICL7104-16
V++
ICL7104-14
V++
ICL7104-14
40 V-
ICL7104-16
1
2
3
4
5
6
7
8
9
V-
1
14 INT OUT
13 +BUFF IN
12 +INT IN
11 -INT IN
-1.2V
DIG GND
STTS
POL
DIG GND
STTS
POL
39 COMP IN
COMP OUT
REF CAP
2
3
4
38 REFCAP 1
37
36 AZ
ANALOG
35
V
REF
REF BYPASS
GND
OR
OR
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 14
BIT 13
BIT 12
BIT 11
V
5
6
7
10 -BUFF IN
REF
GND
34 REFCAP 2
33 BUF IN
32 ANALOG I/P
31 V+
REF OUT
9
8
BUFF OUT
V++
ICL8052/
ICL8068
REF SUPPLY
BIT 10 10
BIT 9 11
NC 12
ICL7104-14
(OUTLINE DWGS DL,
JL, PL)
(OUTLINE DWGS DD, JD, PD)
30 CE/LD
29 SEN
NC 13
28 R/H
BIT 8 14
BIT 7 15
BIT 6 16
BIT 5 17
BIT 4 18
BIT 3 19
BIT 2 20
27 MODE
26 CLK 2
25 CLK 1
24 CLK 3
23 HBEN
22 LBEN
21 BIT 1
HBEN
MBEN
Functional Block Diagram
R
C
INT
INT
+15V -15V
BITS
-BUF IN BUF OUT -INT IN INT OUT
OR POL16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
REF
OUT
8
7
1
10
BUFFER
9
11
INTEG.
14
COMP.
5
4
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21
6
3
INT.
REF.
COMP
OUT
THREE-STATE OUTPUTS
LATCHES
-
-
A1
+
A2
-
300pF
24
+5V
HBEN
23 MBEN
22
+
A3
5kΩ
8052/8068
+INT IN 12
2
+
-1.2V
AZ
5
+BUF IN 13
50kΩ
10kΩ
-15V
LBEN
10µF
C
COUNTER
30 CE/LD
+BUF IN
33
AZ
COMP IN 300kΩ
36
39
SW3
7104
29 SEN
27 MODE
28 R/H
37
ZERO
CROSSING
DETECTOR
V
SW5
SW6
SW4
REF
CONTROL LOGIC
SW1
SW8 SW2
32
35
ANALOG
INPUT
SW7
SW9
ANALOG
GND
38
REF CAP (1)
34
REF CAP (2)
1
31
2
40
25
26
3
+15V
+5V
-15V CLOCK CLOCK STTS
(1) (2)
C
REF
FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM
5-7
ICL8052/ICL7104, ICL8068/ICL7104
Pin Descriptions
PIN NO.
SYMBOL
V++
OPTION
DESCRIPTION
Positive Supply Voltage: Nominally +15V.
Digital Ground: 0V, ground return.
1
2
3
GND
STTS
Status Output: HI during integrate and deintegrate until data is latched. LO when analog section
is in auto-zero configuration.
4
5
6
POL
OR
Polarity: Three-state output. HI for positive input.
Over Range: Three-state output.
BIT 16
BIT 14
-16
-14
Most Significant Bit (MSB).
7
8
BIT 15
BIT 13
-16
-14
DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true.
BIT 14
BIT 12
-16
-14
9
BIT 13
BIT 11
-16
-14
10
11
12
13
BIT 12
BIT 10
-16
-14
BIT 11
BIT 9
-16
-14
BIT 10
NC
-16
-14
BIT 9
NC
-16
-14
14
15
16
17
18
19
20
21
22
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LBEN
Least Significant Bit (LSB).
LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30)
activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a
low byte flag output. See Figures 11, 12, 13.
23
24
MBEN
HBEN
-16
-14
-16
-14
MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22)
HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22)
HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22).
RC oscillator pin: Can be used as clock output.
HBEN
CLOCK3
5-8
ICL8052/ICL7104, ICL8068/ICL7104
Pin Descriptions (Continued)
PIN NO.
25
SYMBOL
CLOCK 1
CLOCK 2
MODE
OPTION
DESCRIPTION
Clock Input: External clock or ocsillator.
26
Clock Output: Crystal or RC oscillator.
27
INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly
controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure
13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered
and data output as in Figures 11 and 12 at conversion completion.
17
15
28
R/H
RUN/HOLD: Input HI conversions continuously performed every 2 (-16) or 2 (-14) clock
pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts
before input integrate.
29
30
SEN
SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates
‘send’.
CE/LD
CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable;
when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe
(-ve going) used in handshake mode. See Figures 11 and 12.
31
32
33
34
35
36
37
38
39
40
V+
Positive Logic Supply Voltage: Nominally +5V.
Analog Input: High Side.
AN I/P
BUF IN
REFCAP2
AN. GND
A-Z
Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086).
Reference Capacitor: Negative Side.
Analog Ground: Input low side and reference low side.
Auto-Zero node.
V
Voltage Reference: Input (positive side).
Reference Capacitor: Positive side.
REF
REFCAP1
COMP-IN
V-
Comparator Input: From 8052/8068.
Negative Supply Voltage: Nominally -15V.
5-9
ICL8052/ICL7104, ICL8068/ICL7104
Absolute Maximum Ratings
Thermal Information
o
o
ICL8052, ICL8068
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Differential Input Voltage
Thermal Resistance (Typical, Note 1)
14 Ld PDIP Package . . . . . . . . . . . . . .
40 Ld PDIP Package . . . . . . . . . . . . . .
14 Ld CERDIP Package . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
100
60
75
N/A
N/A
20
(8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V
o
(8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V Maximum Junction Temperature (Ceramic Package). . . . . . . . . 175 C
o
Input Voltage (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Output Short Circuit Duration All Outputs (Note 3). . . . . . . Indefinite
ICL7104
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
o
o
o
V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
V++ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V
Positive Supply Voltage (GND to V++) . . . . . . . . . . . . . . . . . . . . 17V
Negative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . .-17V
Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to V-
Digital Input Voltage
(Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
o
3. Short circuit may be to ground or either supply. Rating applies to 70 C ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this
reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are
applied.
o
ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, T = 25 C, f
= 200kHz
CLOCK
A
TEST
PARAMETER
Clock Input, CLK 1
SYMBOL
CONDITIONS
= +5V to 0V
= 0V to +5V
= +5V
MIN
TYP
±7
MAX
±30
10
UNITS
µA
I
I
I
V
V
V
V
V
V
±2
-10
1
IN
IN
IH
IN
IN
IN
IN
IN
IN
Comparator I/P, COMP IN (Note 6)
Inputs with Pulldown, MODE
±0.001
5
µA
30
µA
I
= 0V
-10
-10
-30
±0.01
±0.01
-5
10
µA
IL
Inputs with Pullups
SEN, R/H
LBEN, MBEN, HBEN, CE/LD (Note 7)
I
= +5V
10
µA
IH
I
= 0V
-1
µA
IL
Input High Voltage, All Digital Inputs
Input Low Voltage, All Digital Inputs
V
2.5
-
2.0
1.5
-
1.0
0.4
-
V
V
IH
V
IL
Digital Outputs Three-Stated On,
LBEN, MBEN (16 Only), HBEN, CE/LD
BIT n, POL, OR (Note 8)
V
I
I
I
= 1.6mA
= -10µA
= -240µA
-
0.27
4.5
V
OL
OL
OH
OH
V
-
V
OH
V
2.4
-10
3.5
-
V
OH
Digital Outputs Three-Stated Off
Bit n, POL, OR
I
0 ≤ V
OUT
≤ V+
±0.001
+10
µA
OL
Non Three-State Digital Output
STTS
V
I
I
I
I
I
I
= 3.2mA
-
2.4
-
0.3
3.3
0.5
4.5
0.27
3.5
0.4
V
V
V
V
V
V
OL
OL
V
= -400µA
-
OH
OH
Clock 2
V
= 320µA
-
-
OL
OL
OH
OL
OH
V
= -320µA
= 1.6mA
= -320µA
-
OH
Clock 3 (-14 Only)
V
-
0.4
-
OL
V
2.4
OH
5-10
ICL8052/ICL7104, ICL8068/ICL7104
o
ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, T = 25 C, f
= 200kHz (Continued)
CLOCK
A
TEST
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Switch
Switch 1
Switches 2, 3
r
r
r
-
25k
4k
-
Ω
Ω
DS(ON)
DS(ON)
DS(ON)
-
-
20k
10k
-
Switches 4, 5, 6, 7, 8, 9
Switch Leakage
2k
Ω
I
-
15
pA
kHz
D(OFF)
Clock Frequency (Note 9)
Supply Currents
f
DC
200
400
CLOCK
+5V Supply Current
I+
Frequency = 200kHz
-
200
600
µA
All outputs high impedance
+5V Supply Current
-5V Supply Current
I++
I-
Frequency = 200kHz
Frequency = 200kHz
-
-
0.3
25
1.0
mA
200
µA
Supply Voltage Range
Logic Supply
V+
V++
V-
Note 10
4
-
-
-
11
16
V
V
V
Positive Supply
Negative Supply
NOTES:
10
-16
-10
6. This specification applies when not in Auto-Zero phase.
7. Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode.
8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode.
9. Clock circuit shown in Figures 14 and 15.
10. V+ must not be more positive than V++.
ICL8068 Electrical Specifications V
= ±15V, Unless Otherwise Specified
SUPPLY
ICL8068
TEST
ICL8068A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
V
V
V
V
V
= 0V
-
-
20
175
90
65
-
-
20
80
65
mV
pA
dB
dB
OS
CM
CM
CM
CM
Input Current (Either Input) (Note 11)
Common-Mode Rejection Ratio
I
= 0V
250
150
IN
CMRR
= ±10V
= ±2V
70
-
-
-
70
-
90
-
-
Non-Linear Component of Common-
Mode Rejection Ratio (Note 12)
110
110
Large Signal Voltage Gain
Slew Rate
A
R
= 50kΩ
L
20,000
-
-
-
-
-
20,000
-
-
-
-
-
V/V
V/µs
MHz
mA
V
SR
-
-
-
6
2
5
-
-
-
6
2
5
Unity Gain Bandwidth
GBW
Output Short-Circuit Current
COMPARATOR AMPLIFIER
Small-Signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing
VOLTAGE REFERENCE
Output Voltage
I
SC
A
R = 30kΩ
-
4000
13
-
-
-
-
-
-
-
-
V/V
V
VOL
L
+V
12
12
13
O
-V
-2.0
-2.6
-2.0
-2.6
V
O
V
1.5
-
1.75
5
2.0
-
1.60
-
1.75
5
1.90
-
V
O
Output Resistance
R
Ω
O
5-11
ICL8052/ICL7104, ICL8068/ICL7104
ICL8068 Electrical Specifications V
= ±15V, Unless Otherwise Specified (Continued)
SUPPLY
ICL8068
TEST
ICL8068A
PARAMETER
Temperature Coefficient
Supply Voltage Range
Supply Current Total
SYMBOL
CONDITIONS
MIN
TYP
MAX
-
MIN
TYP
40
-
MAX
-
UNITS
o
TC
-
±10
-
50
-
-
±10
-
ppm/ C
V
±16
14
±16
14
V
SUPPLY
I
-
8
mA
SUPPLY
ICL8052 Electrical Specifications V
= ±15V, Unless Otherwise Specified
SUPPLY
ICL8052
TEST
ICL8052A
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
V
V
V
V
V
= 0V
-
-
20
5
75
50
-
-
-
20
2
75
10
-
mV
pA
dB
dB
OS
CM
CM
CM
CM
Input Current (Either Input) (Note 11)
Common-Mode Rejection Ratio
I
= 0V
IN
CMRR
= ±10V
= ±2V
70
-
90
110
70
-
90
110
Non-Linear Component of Common-
Mode Rejection Ratio (Note 12)
-
-
Large Signal Voltage Gain
Slew Rate
A
R
= 50kΩ
L
20,000
-
6
-
-
-
-
20,000
-
6
-
-
-
-
V/V
V/µs
MHz
mA
V
SR
-
-
-
-
-
-
Unity Gain Bandwidth
Output Short-Circuit Current
COMPARATOR AMPLIFIER
Small-Signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing
VOLTAGE REFERENCE
Output Voltage
GBW
1
1
I
20
20
SC
A
R = 30kΩ
-
4000
13
-
-
-
-
-
-
-
-
V/V
V
VOL
L
+V
12
12
13
O
O
-V
-2.0
-2.6
-2.0
-2.6
V
V
1.5
1.75
5
2.0
-
1.60
1.75
5
1.90
-
V
O
Output Resistance
R
-
-
Ω
O
o
Temperature Coefficient
Supply Voltage Range
Supply Current Total
NOTES:
TC
-
±10
-
50
-
-
-
±10
-
40
-
-
ppm/ C
V
±16
12
±16
12
V
SUPPLY
I
6
6
mA
SUPPLY
o
11. The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature,
T . Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation
J
the junction temperature rises above the ambient temperature as a result of internal power dissipation, P . T = T + R
P where
D
D
J
A
θJA
R
is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
θJA
12. This is the only component that causes error in dual-slope converter.
5-12
ICL8052/ICL7104, ICL8068/ICL7104
System Electrical Specifications: ICL8068/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, f
= 200kHz (Note 16)
CLOCK
ICL8068A/ICL7104-16
MIN TYP MAX
ICL8068A/ICL7104-14
MIN TYP MAX
TEST
CONDITIONS
PARAMETER
Zero Input Reading
UNITS
V
V
= 0V, V = 2V -00000 ±00000 +00000 -00000 ±00000 +00000 Counts
REF
IN
IN
Ratiometric Error (Note 13)
= V
REF
= 2V
-1
-
0
1
1
-1
-
0
1
1
LSB
LSB
Linearity Over ± Full Scale (Error of
-4V ≤ V ≤ +4V
IN
0.5
0.5
Reading from Best Straight Line)
Differential Linearity (Difference
between Worst Case Step of Adjacent
Counts and Ideal Step)
-4V ≤ V ≤ +4V
IN
-
-
-
0.01
0.5
2
-
1
-
-
-
-
0.01
0.5
2
-
1
-
LSB
LSB
Rollover Error (Difference in Reading
for Equal Positive & Negative Voltage
Near Full Scale)
-V = +V
IN
4V
IN
Noise (P-P Value Not Exceeded 95%
of Time)
V
= 0V,
µV
IN
Full Scale = 4V
Leakage Current at Input (Note 14)
Zero Reading Drift
V
V
= 0V
-
-
100
0.5
165
-
-
-
100
0.5
165
-
pA
IN
IN
o
= 0V,
µV/ C
o
o
0 C to 70 C
o
Scale Factor Temperature Coefficient
(Note 15)
V
= 4V,
-
2
5
-
2
5
ppm/ C
IN
o
o
0 C to 50 C
ext. ref. 0ppm/ C
o
System Electrical Specifications: ICL8052/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, f
= 200kHz (Note 16)
CLOCK
ICL8052A/ICL7104-14
MIN TYP MAX
ICL8052A/ICL7104-16
MIN TYP MAX
TEST
CONDITIONS
PARAMETER
Zero Input Reading
UNITS
V
V
= 0V, V = 2V -00000 ±00000 +00000 -00000 ±00000 +00000 Counts
REF
IN
IN
Ratiometric Error (Note 15)
= V
REF
= 2V
-1
-
0
1
1
-1
-
0
1
1
LSB
LSB
Linearity Over ± Full Scale (Error of
-4V ≤ V ≤ +4V
IN
0.5
0.5
Reading from Best Straight Line)
Differential Linearity (Difference
between Worst Case Step of Adjacent
Counts and Ideal Step)
-4V ≤ V ≤ +4V
IN
-
-
-
0.01
0.5
30
-
1
-
-
-
-
0.01
0.5
30
-
1
-
LSB
LSB
Rollover Error (Difference in Reading
for Equal Positive and Negative
Voltage Near Full Scale)
-V = +V ≈ 4V
IN IN
Noise (Peak-to-Peak Value Not
Exceeded 95% of Time)
V
= 0V,
µV
IN
Full Scale = 4V
Leakage Current at Input (Note 14)
Zero Reading Drift
V
V
= 0V
-
-
20
30
-
-
-
20
30
-
pA
IN
IN
o
= 0V,
0.5
0.5
µV/ C
o
o
0 C to 70 C
o
Scale Factor Temperature Coefficient
V
= 4V,
-
2
-
-
2
-
ppm/ C
IN
o
o
0 C to 50 C
ext. ref. 0ppm/ C
o
NOTES:
13. Tested with low dielectric absorption integrating capacitor.
14. The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature,
T . Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal oper-
o
J
ation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P . T = T + R
P
D
D
J
A
θJA
where R
θJA
is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
o
15. The temperature range can be extended to 70 C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the
high temperature leakage of the 8068. See note 14 above.
16. System Electrical Specifications are not tested; for reference only.
5-13
ICL8052/ICL7104, ICL8068/ICL7104
CONTROL
CONVERT
MODE
R/H
OR
≥18
POL
MSB
7104 -16
8052A/
8068A
18
LSB
CE/LD HBEN MBEN LBEN
OR CHIP SELECT 2
CHIP SELECT 1
FIGURE 2. FULL 18-BIT THREE-STATE OUTPUT
CONVERT
R/H
CONVERT
CONVERT
R/H
MODE CE/LD
7104
MODE CE/LD
7104
R/H
OR
MODE CE/LD
7104
OR
OR
2
8
2
POL
POL
MSB
POL
10
8
MSB
MSB
8052A/
8068A
8052A/
8068A
8052A/
8068A
16
8
LSB
LSB
LSB
HBEN MBEN LBEN
CONTROL
HBEN MBEN LBEN
HBEN MBEN LBEN
CONTROL
CONTROL
FIGURE 3. VARIOUS COMBINATIONS OF BYTE DISABLES
t
CEA
CE/LD
AS INPUT
t
BEA
HBEN
AS INPUT
MBEN
AS INPUT
LBEN
AS INPUT
t
t
DHB
DAB
HIGH BYTE
DATA
DATA
DATA
VALID
VALID
t
t
DHC
DAC
MIDDLE
BYTE
ENABLE
DATA
VALID
DATA
VALID
LOW BYTE
ENABLE
DATA
VALID
= HIGH IMPEDANCE
FIGURE 4. DIRECT MODE TIMING DIAGRAM
5-14
ICL8052/ICL7104, ICL8068/ICL7104
TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
XBEN (Min) Pulse Width.
MIN
TYP
300
300
200
350
350
280
1000
MAX
UNIT
ns
t
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BEA
DAB
DHB
Data Access Time from XBEN.
Data Hold Time from XBEN.
CE/LD Min. Pulse Width.
ns
t
ns
t
ns
CEA
DAC
DHC
t
Data Access Time from CE/LD.
Data Hold Time from CE/LD.
CLOCK 1 High Time.
ns
t
ns
t
ns
CWH
TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
20
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Mode Pulse (Min).
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MW
t
Mode Pin Set-Up Time.
-
-150
200
SM
ME
MB
t
Mode Pin High to Low Z CE/LD High Delay.
Mode Pin High to XBEN Low Z (High) Delay.
Clock 1 High to CE/LD Low Delay.
Clock 1 High to CE/LD High Delay.
Clock 1 High to XBEN Low Delay.
Clock 1 High to XBEN High Delay.
Clock 1 High to Data Enabled Delay.
Clock 1 Low to Data Disabled Delay.
Send ENABLE Set-Up Time.
-
t
-
200
t
-
700
CEL
t
-
600
CEH
t
-
900
CBL
CBH
CDH
t
-
700
t
-
1100
1100
-350
2000
2000
1000
t
-
CDL
t
-
SS
t
Clock 1 High to XBEN Disabled Delay.
Clock 1 High to CE/LD Disabled Delay.
Clock 1 High Time.
-
-
CBZ
CEZ
t
t
1250
CWH
5-15
ICL8052/ICL7104, ICL8068/ICL7104
t
t
SM
CWH
H
L
CLOCK 1
(PIN 25)
t
MW
H
L
EITHER:
MODE PIN
DON’T CARE
STABLE
OR
INTERNAL
LATCH PULSE IF
MODE “HI”
IGNORED
IGNORED
UART
INTERNAL
MODE
NORM
t
t
CEH
CEL
H
CE/LD
L
t
t
ME
CEZ
t
EXT
EXT
SS
SEN
H
DON’T CARE
DON’T CARE
(EXTERNAL
SIGNAL)
L
t
MB
H
L
HBEN
t
t
t
CBL
CBH
CBZ
H
L
O/R, POL
01-14
DATA VALID, STABLE
t
t
CDL
CDH
H
L
LBEN
DATA VALID, STABLE
BITS 1-5
HANDSHAKE MODE
TRIGGERED BY
THREE-STATE
-16 HAS EXTRA (MBEN) PHASE
OR
THREE-STATE WITH PULLUP
FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM
Detailed Description
ANALOG SECTION
Deintegrate Phase III (Figures 6C and 6D)
Figure 6 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL7104/8068 in the 3
different phases of operation. If the Run/Hold pin is left open
or tied to V+, the system will perform conversions at a rate
determined by the clock frequency: 131,072 for - 16 and
32,368 for - 14 clock periods per cycle (see Figure 8
conversion timing).
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. If the input signal was positive,
switches 7 and 8 are closed and a voltage which is V
REF
more negative than during Auto-Zero is impressed on the
buffer input. Negative inputs will cause +V to be applied
REF
to the buffer input via switches 6 and 9. Thus, the reference
capacitor generates the equivalent of a (+) reference or a (-)
reference from the single reference voltage with negligible
error. The reference voltage returns the output of the integra-
tor to the zero-crossing point established in Phase I. The
time, or number of counts, required to do this is proportional
to the input voltage. Since the Deintegrate phase can be
twice as long as the Input integrate phase, the input voltage
Auto-Zero Phase I (Figure 6A)
During Auto-Zero, the input of the buffer is shorted to analog
ground thru switch 2, and switch 1 closes a loop around the
integrator and comparator. The purpose of the loop is to
charge the Auto-Zero capacitor until the integrator output no
longer changes with time. Also, switches 4 and 9 recharge
the reference capacitor to V
.
required to give a full scale reading = 2V
.
REF
REF
Input Integrate Phase II (Figure 6B)
NOTE: Once a zero crossing is detected, the system automatically
reverts to Auto-Zero phase for the leftover Deintegrate time (unless
RUN/HOLD is manipulated, see RUN/HOLD input in detailed
description, digital section).
During input integrate the Auto-Zero loop is opened and the
analog input is connected to the buffer input thru switch 3.
(The reference capacitor is still being charged to V
REF
during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous sate (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
entire Input Integrate cycle. If V is not equal to zero, an
IN
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to V . At the end of this phase, the sign of
IN
the ramp is latched into the polarity F/F.
5-16
ICL8052/ICL7104, ICL8068/ICL7104
R
INT
C
INT
AN
I/P
BUFFER
INTEGRATOR
COMP.
3
-
-
ZERO
CROSS.
DET.
A1
+
A2
+
-
D
Q
A3
+
ZERO
CROSSING
F/F
2
8
6
7
C
AZ
CL
9
1
CL
POL
-
C
+
V
REF
4
REF
FIGURE 6A. PHASE I AUTO-ZERO
R
INT
C
INT
D
POL
F/F
CL
Q
Q
POL
AN
I/P
BUFFER
INTEGRATOR
COMP.
PHASE II
3
-
-
ZERO
CROSS.
DET.
A1
+
A2
+
-
D
A3
+
ZERO
CROSSING
F/F
2
8
6
7
C
AZ
CL
9
1
CL
POL
-
C
+
REF
V
REF
4
FIGURE 6B. PHASE II INTEGRATE INPUT
R
C
INT
INT
+AN
I/P
BUFFER
INTEGRATOR
COMP.
3
-
-
ZERO
CROSS.
DET.
A1
+
A2
+
-
D
Q
A3
+
ZERO
CROSSING
F/F
2
8
6
7
C
AZ
CL
9
1
CL
POL
-
C
+
V
REF
4
REF
FIGURE 6C. PHASE III + DEINTEGRATE
R
C
INT
INT
-AN
I/P
BUFFER
INTEGRATOR
COMP.
3
-
-
ZERO
CROSS.
DET.
A1
+
A2
+
-
D
Q
A3
+
ZERO
CROSSING
F/F
2
8
6
7
C
AZ
CL
9
1
CL
POL
-
C
+
V
REF
4
REF
FIGURE 6D. PHASE III DEINTEGRATE
5-17
ICL8052/ICL7104, ICL8068/ICL7104
TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
B5 B4
LBEN
ICL7104-16 POL O/R B16 B15 B14 B13 B12 B11 B10 B9
B8
B8
B7
B7
B6
B6
B3
B3
B2
B2
B1
B1
HBEN
ICL7104-14
POL O/R B14 B13 B12 B11 B10 B9
B5
B4
TABLE 4. TYPICAL COMPONENT VALUES (V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, f
= 200kHz)
CLOCK
ICL8052/8068 WITH
ICL7104-16
ICL7104-14
UNIT
Full scale V
Buffer Gain
200
10
800
1
4000
1
100
10
47
0.1
1
4000
1
mV
V/V
kΩ
µF
IN
R
C
C
C
100
0.33
1
43
0.33
1
200
0.33
1
180
0.1
1
INT
INT
AZ
µF
10
1
1
10
50
6.1
1
µF
REF
REF
V
100
3.1
400
12
2000
61
2000
244
mV
µV
Resolution
10-50K
R
C
INT
INT
100kΩ
+15V -15V
-BUF IN BUF OUT -INT IN INT OUT
REF
OUT
8
7
1
10
BUFFER
9
11
INTEG.
14
6
3
INT.
REF.
COMP.
COMP
OUT
300pF
-
-
A1
+
A2
-
+5V
+
A3
5kΩ
8068
2
+
-1.2V
5
+BUF IN 13
+INT IN 12
10kΩ
-15V
TO ICL7104
FIGURE 7. ADDING BUFFER GAIN TO ICL8068
Buffer Gain
At the end of the auto-zero interval, the instantaneous noise on the order of 1 to 2µV, allowing full 16-bit use with full scale
voltage on the auto-zero capacitor is stored, and subtracts inputs of a low as 150mV. Note that at this level, thermoelec-
from the input voltage while adding to the reference voltage tric EMFs between PC boards, IC pins, etc., due to local
during the next cycle. The result is that this noise voltage temperature changes can be very troublesome. For further
effectively is somewhat greater than the input noise voltage discussion, see Application Note AN030.
of the buffer itself during integration. By introducing some
voltage gain into the buffer, the effect of the auto-zero noise
(referred to the input) can be reduced to the level of the
ICL8052 vs ICL8068
The ICL8052 offers significantly lower input leakage currents
than the ICL8068, and may be found preferable in systems
with high input impedances. However, the ICL8068 has
substantially lower noise voltage, and for systems where
system noise is a limiting factor, particularly in low signal
level conditions, will give better performance.
inherent buffer noise. This generally occurs with a buffer gain
of between 3 and 10. Further increase in buffer gain merely
increases the total offset to be handled by the auto-zero
loop, and reduces the available buffer and integrator swings,
without improving the noise performance of the system. The
circuit
recommended
for
doing
this
with
the
ICL8068/ICL7104 is shown in Figure 7. With careful layout,
the circuit shown can achieve effective input noise voltages
5-18
ICL8052/ICL7104, ICL8068/ICL7104
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
Component Value Selection
For optimum performance of the analog section, care must
be taken in the selection of values for the integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
This ratiometric condition should read half scale (100...000)
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at reason-
able cost. Polystyrene and polycarbonate capacitors may
also be used in less critical applications.
Integrating Resistor
Auto-Zero and Reference Capacitor
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current should be small
compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not
affected. Values of 5 to 40µA give good results with a
nominal of 20µA. The exact value may be chosen by:
The size of the auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
NOTE: When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero capacitor.
As a rule of thumb, the reference capacitor should be approximately
the gain times the value of the auto-zero capacitor. The dielectric
absorption of the reference cap and auto-zero cap are only important
at power-on or when the circuit is recovering from an overload. Thus,
smaller or cheaper caps can be used here if accurate readings are
not required for the first few seconds of recovery.
full scale voltage (see note)
R
= ------------------------------------------------------------------------
INT
20µA
NOTE: If gain is used in the buffer amplifier then
(BufferGain) (full scale voltage)
R
= ---------------------------------------------------------------------------------------
INT
20µA
Reference Voltage
Integrating Capacitor
The analog input required to generate a full scale output is
V
= 2V
.
IN
REF
The product of integrating resistor and capacitor is selected
to give 9 volt swing for full scale inputs. This is a compromise
between possibly saturating the integrator (at +14 volts) due
to tolerance build-up between the resistor, capacitor and
clock and the errors a lower voltage swing could induce due
to offsets referred to the output of the comparator. In
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. The resolution of
the ICL7104 at 16 bits is one part in 65536, or 15.26ppm.
Thus, if the reference has a temperature coefficient of
50ppm/C (on board reference) a temperature change of
1/3C will introduce a one-bit absolute error. For this reason,
it is recommended that an external high quality reference be
used where the ambient temperature is not controlled or
where high-accuracy absolute measurements are being
made.
general, the value of C
is given by:
INT
(32768 for - 16)
(8192 for -14)
× 20µA × clock period
= ---------------------------------------------------------------------------------------------------------
C
INT
Integrator Output Voltage Swing
A very important characteristic of the integrating capacitor is
that it have low dielectric absorption to prevent roll-over or
COUNTS
PHASE I
32768
8192
PHASE II
32768
PHASE III
65536
-16
-14
8192
16384
POLARITY
DETECTED
ZERO CROSSING
OCCURS
INTEGRATOR
OUTPUT
ZERO CROSSING
DETECTED
AZ PHASE I
INT PHASE II
DEINT PHASE III
AZ
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V
IN
CONFIGURATION
FIGURE 8. CONVERSION TIMING
5-19
ICL8052/ICL7104, ICL8068/ICL7104
ensure a low level when the pin is left open), the converter is
Detailed Description
in its “Direct” output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
DIGITAL SECTION
The digital section includes the clock oscillator circuit, a
16-bit or 14-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 9 (16-bit version shown).
Throughout this description, logic levels will be referred to as
“low” or “high”. The actual logic levels are defined under
“ICL7104 Electrical Specification”. For minimum power con-
sumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3 - 5kΩ
pullup resistors added for maximum noise immunity.
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 8 for details of
this timing. This signal may be used as a “data valid” flag
(data never changes while STATUS is low) to drive inter-
rupts, or for monitoring the status of the converter.
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
B5 B4
LBEN
B5 B4
ICL7104-16 POL O/R B16 B15 B14 B13 B12 B11 B10 B9
B8
B8
B7
B7
B6
B6
B3
B3
B2
B2
B1
B1
HBEN
ICL7104-14
POL O/R B14 B13 B12 B11 B10 B9
18/16 THREE-STATE OUTPUTS
18/16 LATCHES
HBEN
MBEN
(-16 ONLY)
INITIAL
CLEAR
18/16 BIT COUNTER
LATCH
LBEN
CLOCK
COMP OUT
CE/LD
TO
AZ
CONVERSION
CONTROL
LOGIC
OSCILLATOR
AND CLOCK
CIRCUITRY
HANDSHAKE
LOGIC
ANALOG
INT
DEINT(+)
DEINT(-)
SECTION
2
26
R/H
24
23
25
21
27
SEND
STATUS
CLOCK CLOCK CLOCK
(1) (2) (3)
MODE
FIGURE 9. DIGITAL SECTION
5-20
ICL8052/ICL7104, ICL8068/ICL7104
OPTION -14
-16
MIN
7161 28665
8185 32761
MAX
DEINT TERMINATED
AT ZERO CROSSING
DETECTION
STATIC IN
HOLD STATE
INT
PHASE
INTEGRATOR
OUTPUT
7 COUNTS
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
RUN/HOLD
INPUT
FIGURE 10. RUN/HOLD OPERATION
Run/Hold Input
Integrate (Phase II) begins seven clock periods after the high
level is detected.
When the Run/Hold input is connected to V+ or left open
(this input has pullup resistor to ensure a high level when the
pin is left open), the circuit will continuously perform
conversion cycles, updating the output latches at the end of
every Deintegrate (Phase III) portion of the conversion cycle
(See Figure 8). (See under “Handshake Mode” for
exception.) In this mode of operation, the conversion cycle
will be performed in 131,072 for 7104-16 and 32768 for
7104-14 clock periods, regardless of the resulting value.
Direct Mode
When the MODE pin is left at a low level, the data outputs
[bits 1 through 8 low order byte, See Table 3 for format of
middle (-16) and high order bytes] are accessible under
control of the byte and CHIP ENABLE terminals as inputs.
These ENABLE inputs are all active low, and are provided
with pullup resistors to ensure an inactive high level when
left open. When the CHIP ENABLE input is low, taking a byte
ENABLE input low will allow the outputs of that byte to
become active (three-stated on). This allows a variety of
parallel data accessing techniques to be used. The timing
requirements for these outputs are shown under AC
Specifications and Table 1.
If Run/Hold goes low at any time during Deintegrate (Phase
III) after the zero crossing has occurred, the circuit will
immediately terminate Deintegrate and jump to Auto-Zero.
This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Hold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Hold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STATUS output will
go high) seven clock periods after the high level is detected
at Run/Hold. See Figure 10 for details.
It should be noted that these control inputs are asynchro-
nous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the data
while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STATUS output will prevent this.
Data is never updated while STATUS is low. Also note the
potential bus conflict described under “Initial Clear Circuitry”.
Using the Run/Hold input in this manner allows an easy
“convert on demand” interface to be used. The converter
may be held at idle in Auto-Zero with Run/Hold low. When
Run/Hold goes high the conversion is started, and when the
STATUS output goes low the new data is valid (or trans-
ferred) to the UART - see Handshake Mode). Run/Hold may
now go low terminating Deintegrate and ensuring a minimum
Auto-Zero time before stopping to wait for the next
conversion. Alternately, Run/Hold can be used to minimize
conversion time by ensuring that it goes low during Deinte-
grate, after zero crossing, and goes high after the hold point
is reached. The required activity on the Run/Hold input can
be provided by connecting it to the CLOCK3 (-14), CLOCK2
(-16) Output. In this mode the conversion time is dependent
on the input value measured. Also refer to Intersil Application
Bulletin A030 for a discussion of the effects this will have on
Auto-Zero performance.
Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7104 to digital systems, where
the A/D converter becomes active in controlling the flow of
data instead of passively responding to chip and byte
ENABLE inputs. This mode is specifically designed to allow
a direct interface between the ICL7104 and industry-stan-
dard UARTs (such as the Intersil CMOS UARTs, IM6402/3)
with no external logic required. When triggered into the
handshake mode, the ICL7104 provides all the control and
flag signals necessary to sequence the three (ICL7106-16)
or two (ICL7104-14) bytes of data into the UART and initiate
their transmission in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the
number of lines to the central controlling processor.
If the Run/Hold input goes low and stays low during Auto-
Zero (Phase I), the converter will simply stop at the end of
the Auto-Zero and wait for Run/Hold to go high. As above,
5-21
ICL8052/ICL7104, ICL8068/ICL7104
Entry into the handshake mode will occur if either of two LBEN while the remaining byte outputs (see Table 3) are
conditions are fulfilled; first, if new data is latched (i.e., a activated. The handshake mode is terminated when all bytes
conversion is completed) while MODE pin (pin 27) is high, in are sent (3 for -16, 2 for -14).
which case entry occurs at the end of the latch cycle; or
Figure 12 shows an output sequence where the SEN input is
secondly, if the MODE pin goes from low to high, when entry
used to delay portions of the sequence, or handshake, to
will occur immediately (if new data is being latched, entry is
ensure correct data transfer. This timing diagram shows the
delayed to the end of the latch cycle). While in the
relationships that occur using an industry-standard IM6402/3
handshake mode, data latching is inhibited, and the MODE
CMOS UART to interface to serial data channels. In this
pin is ignored. (Note that conversion cycles will continue in
interface, the SEN input to the ICL7104 is driven by the
the normal manner). This allows versatile initiation of hand-
TBRE (Transmitter Buffer Register Empty) output of the
shake operation without danger of false data generation; if
UART, and the CE/LD terminal of the ICL7104 drives the
the MODE pin is held high, every conversion (other than
TBRL (Transmitter Buffer Register Load) input to the UART.
those completed during handshake operations) will start a
The data outputs are paralleled into the eight Transmitter
new handshake operation, while if the MODE pin is pulsed
Buffer Register inputs.
high, handshake operations can be obtained “on demand.”
Assuming the UART Transmitter Buffer Register is empty,
When the converter enters the handshake mode, or when
the SEN input will be high when the handshake mode is
the MODE input is high, the chip and byte ENABLE termi-
entered after new data is stored. The CE/LD and HBEN ter-
nals become TTL-compatible outputs which provide the con-
minals will go low after SEN is sensed, and the high order
trol signals for the output cycle. The Send ENABLE pin
byte outputs become active. When CE/LD goes high at the
(SEN) (pin 29) is used as an indication of the ability of the
end of one clock period, the high order byte data is clocked
external device to receive data. The condition of the line is
into the UART Transmitter Buffer Register. The UART TBRE
sensed once every clock pulse, and if it is high, the next (or
output will now go low, which halts the output cycle with the
first) byte is enabled on the next rising CLOCK 1 (pin 25)
HBEN output low, and the high order byte outputs active.
clock edge, the corresponding byte ENABLE line goes low,
When the UART has transferred the data to the Transmitter
and the CHIP ENABLE / LOAD pin (pin 30) (CE/LD) goes
Register and cleared the Transmitter Buffer Register, the
low for one full clock pulse only, returning high.
TBRE returns high. On the next ICL7104 internal clock high
On the next falling CLOCK 1 clock pulse edge, if SEN to low edge, the high order byte outputs are disabled, and
remains high, or after it goes high again, the byte output one-half internal clock later, the HBEN output returns high.
lines will be put in the high impedance state (or three-stated At the same time, the CE/LD and MBEN (-16) or LBEN out-
off). One half pulse later, the byte ENABLE pin will be puts go low, and the corresponding byte outputs become
cleared high, and (unless finished) the CE/LD and the next active. Similarly, when the CE/LD returns high at the end of
byte ENABLE pin will go low. This will continue until all three one clock period, the enabled data is clocked into the UART
(2 in the case of the 14-bit device) bytes have been sent. Transmitter Buffer Register, and TBRE again goes low.
The bytes are individually put into the low impedance state When TBRE returns to a high it will be sensed on the next
i.e.: three-stated on during most of the time that their byte ICL7104 internal clock high to low edge, disabling the data
ENABLE pin is (active) low. When receipt of the last byte has outputs. For the 16-bit device, the sequence is repeated for
been acknowledged by a high SEN, the handshake mode LBEN. One-half internal clock later, the handshake mode will
will be cleared, re-enabling data latching from conversion, be cleared, and the chip and byte ENABLE terminals return
and recognizing the condition of the MODE pin again. The high and stay active (as long as MODE stays high).
byte and CHIP ENABLE will be three-stated off, if MODE is
With the MODE input remaining high as in these examples,
low, but held by their (weak) pullups. These timing relation-
the converter will output the results of every conversion
ships are illustrated in Figures 11, 12, and 13, and Table 2.
except those completed during a handshake operation. By
Figure 11 shows the sequence of the output cycle with SEN triggering the converter into handshake mode with a low to
held high. The handshake mode (Internal MODE high) is high edge on the MODE input, handshake output sequences
entered after the data latch pulse (since MODE remains high may be performed on demand. Figure 13 shows a
the CE/LD, LBEN, MBEN and HBEN terminals are active as handshake output sequence triggered by such an edge. In
outputs). The high level at the SEN input is sensed on the addition, the SEN input is shown as being low when the con-
same high to low internal clock edge. On the next to high verter enters handshake mode. In this case, the whole out-
internal clock edge, the CE/LD and the HBEN outputs put sequence is controlled by the SEN input, and the
assume a low level and the high-order byte (POL and OR, sequence for the first (high order) byte is similar to the
and except for -16, Bits 9 - 14) outputs are enabled. The sequence for the other bytes. This diagram also shows the
CE/LD output remains low for one full internal clock period output sequence taking longer than a conversion cycle. Note
1
only, the data outputs remain active for 1 / internal clock that the converter still makes conversions, with the STATUS
2
periods, and the high byte ENABLE remains low for two output and Run/Hold input functioning normally. The only
clock periods. Thus the CE/LD output low level or low to high difference is that new data will not be latched when in
edge may be used as a synchronizing signal to ensure valid handshake mode, and is therefore lost.
data, and the byte ENABLE as an output may be used as a
byte identification flag. With SEN remaining high the con-
verter completes the output cycle using CE/LD, MBEN and
5-22
ICL8052/ICL7104, ICL8068/ICL7104
ZERO-CROSSING OCCURS
INTEGRATOR OUTPUT
INTERNAL CLOCK
ZERO-CROSSING DETECTED
FOR -16 MBEN SEQUENCE INSERTED HERE
INTERNAL LATCH
STATUS OUTPUT
MODE INPUT
UART
NORM
TERMINATES
UART MODE
INTERNAL MODE
SEN
SENSED
SEN
SENSED
SEN INPUT
CE/LOAD
HBEN
MODE LOW NOT IN HANDSHAKE MODE
DISABLES OUTPUTS CE/LD, HBEN, MBEN, LBEN
HIGH BYTE DATA
DATA VALID
LBEN
LOW BYTE DATA
LBEN
DATA VALID
MODE HIGH ACTIVATES
CE/LD, HBEN, LBEN
LOW BYTE DATA
DATA VALID
THREE-STATE WITH PULLUP
DON’T CARE
THREE-STATE HIGH IMPEDANCE
FIGURE 11. HANDSHAKE WITH SEN HELD POSITIVE
ZERO-CROSSING OCCURS
ZERO-CROSSING DETECTED
INTEGRATOR
OUTPUT
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
MODE
INPUT
UART
NORM
INTERNAL
MODE
SEN INPUT
(UART TBRE)
CE/LOAD
(UART TBRL)
HBEN
HIGH BYTE
DATA
DATA VALID
MBEN
MIDDLE
BYTE DATA
DATA VALID
LBEN
LOW BYTE
DATA
DATA VALID
DON’T CARE
THREE-STATE HIGH IMPEDANCE
FIGURE 12. HANDSHAKE - TYPICAL UART INTERFACE TIMING
5-23
ICL8052/ICL7104, ICL8068/ICL7104
POSITIVE TRANSITION
CAUSES ENTRY INTO
UART MODE
ZERO-CROSSING OCCURS
ZERO-CROSSING DETECTED
INTERNAL
CLOCK
LATCH PULSE INHIBITED
IN UART MODE
INTERNAL
LATCH
STATUS OUTPUT UNAFFECTED
BY UART MODE
STATUS
OUTPUT
DEINT PHASE III
MODE
INPUT
UART
INTERNAL
NORM
MODE
SEN INPUT
CE/LOAD
AS OUTPUT
HBEN
HIGH BYTE
DATA
DATA VALID
MBEN
MIDDLE
DATA VALID
BYTE DATA
LBEN
LOW BYTE
DATA
DATA VALID
DON’T CARE
THREE-STATE HIGH IMPEDANCE
THREE-STATE WITH PULLUP
FIGURE 13. HANDSHAKE TRIGGERED BY MODE
Initial Clear Circuitry
The internal logic of the 7104 is supplied by an internal
regulator between V++ and Digital Ground. The regulator
includes a low-voltage detector that will clear various
registers. This is intended to ensure that on initial power-up,
the control logic comes up in Auto-Zero, with the 2nd, 3rd,
and 4th MSB bits cleared, and the “mode” F/F cleared (i.e.,
in “direct” mode). This, however, will also clear these regis-
ters if the supply voltage “glitches” to a low enough value.
Additionally, if the supply voltage comes up too fast, this
clear pulse may be too narrow for reliable clearing. In gen-
eral, this is not a problem, but if the UART internal “MODE”
F/F should come up set, the byte and chip ENABLE lines will
become active outputs. In many systems this could lead to
bus conflicts, especially in non-handshake systems. In any
case, SEN should be high (held high for non-handshake sys-
tems) to ensure that the MODE F/F will be cleared as fast as
possible (see Figure 11 for timing). For these and other
reasons, adequate supply bypass is recommended.
25
24
26
R
CLOCK
1
CLOCK
2
CLOCK
3
C
f
= 0.45/RC
OSC
NOTE: Clock 3 has the same output drive as the bit outputs.
FIGURE 14. RC OSCILLATOR (ICL7104-14 ONLY)
As a result of pin count limitations, the ICL7104-16 has only
CLOCK 1 and CLOCK 2 available, and cannot be used as
an RC oscillator. The internal clock will correspond to the
inverse of the signal on CLOCK 2. Figure 15 shows a crystal
oscillator circuit, which can be used with both 7104 versions.
If an external clock is to be used, it should be applied to
CLOCK 1. This internal clock will correspond to the signal
applied to this pin.
Oscillator
The ICL7104-14 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated as an RC or crystal
oscillator.
V+
Figure 14 shows the oscillator configured for RC operation.
The internal clock will be of the same frequency and phase
as the voltage on the CLOCK 3 pin. The resistor and
capacitor should be connected as shown. The circuit will
oscillate at a frequency given by f = 0.45/RC. A 50 - 100kΩ
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 32768 (-16), 8192 (-14) clock periods is
close to an integral multiple of the 60Hz period.
25
26
CLOCK
1
CLOCK
2
†CAPACITOR VALUE
DEPENDS ON CRYSTAL
TYP 0-30pF
†
CRYSTAL
FIGURE 15. CRYSTAL OSCILLATOR
5-24
ICL8052/ICL7104, ICL8068/ICL7104
Application Notes
Power Supply Sequencing
Because of the nature of the CMOS process used to Some application notes that may be found useful are listed
fabricate the ICL7104, and the multiple power supplies here:
used, there are certain conditions of these supplies under
which a disabling and potentially damaging SCR action can
AnswerFAX
DOC. #
NOTE #
DESCRIPTION
occur. All of these conditions involve the V+ supply (Norm
+5V) being more positive than the V++ supply. If there is
any possibility of this occurring during start-up, shut down,
under transient conditions during operation, or when insert-
ing a PC board into a “hot” socket, etc., a diode should be
placed between V+ and V++ to prevent it. A germanium or
Schottky rectifier diode would be best, but in most cases a
silicon rectifier is adequate.
AN016 “Selecting A/D Converters”, by Dave
Fullagar
9016
AN017 “The Integrating A/D Converter”, by Lee
Evans
9017
9018
AN018 “Do’s and Don’ts of Applying A/D
Converters,” by Peter Bradshaw and Skip
Osgood
Analog and Digital Grounds
AN030 “Building a Battery-Operated Auto
Ranging DVM with the ICL7106”
9030
Extreme care must be taken to avoid ground loops in the
layout of ICL8068 or ICL8052/7104 circuits, especially in
16-bit and high sensitivity circuits. It is most important that
return currents from digital loads are not fed into the analog
ground line. A recommended connection sequence for the
ground lines is shown in Figure 16.
REF
VOLTAGE
BUFF
OUT
EXTERNAL
REFERENCE
(IF USED)
+15V
-15V
BUFF
-IN
(IF USED)
V
PIN 35
ICL7104
AN GND
PIN 35
ICL7104
AN GND
REF
I/P
FILTER
CAP
+
V
C
IN
-
AZ
8068 PIN 2
COMP
BOARD
EDGE
SUPPLY
RETURN
DIGITAL
LOGIC
DIG GND
ICL7104
PIN 2
DEVICE PIN
+5V SUPPLY BYPASS CAPACITOR(S)
FIGURE 16. GROUNDING SEQUENCE
5-25
ICL8052/ICL7104, ICL8068/ICL7104
ICL7104 with ICL8052/8068 Integrating A/D Converter Equations
• Oscillator
• Integrate Capacitor
(t
)(I
)
CRYSTAL or RC (RC on -14 Part Only)
INT INT
V
C
= -------------------------------
INT
f
f
(Typ) 200kHz
= 0.45/RC (ICL7104-14 Only)
INT
OSC
OSC
• Integrator Output Voltage
C
> 50pF and R > 50K
OSC
• Oscillator Period
= 1/f
OSC
(t
)(I
)
INT INT
V
= -------------------------------
INT
C
INT
t
OSC
OSC
• Integration Clock Frequency
= f
V
(Typ) = 9V
INT
• Output Count
f
CLOCK
OSC
V
IN
• Integration Period
--------------
Count = 8192 ×
(7104-14)
V
REF
t
t
= 8192 x t
OSC
(7104-14)
(7104-16)
INT
INT
V
= 32768 x t
IN
OSC
--------------
Count = 32768 ×
(7104-16)
V
REF
• 60/50Hz Rejection Criterion
/t or t /t = Integer
• Output Type:
t
INT 60Hz INT 50Hz
Binary Amplitude with Polarity and Overrange Bits.
• Optimum Integration Current
= 20µA
• Power Supply: ±15V, +5V
I
INT
• Full Scale Analog Input Voltage
(Typ) = 200mV to 2V = 2V
V++ = +15V
V- = -15V
V+ = +5V
V
INFS
REF
V
1.75V
REF
If V
• Integrate Resistor
not used, float output pin.
REF
(BufferGain) × V
• Auto Zero Capacitor Values
INFS
R
= ------------------------------------------------------------
INT
I
INT
0.01µF < C < 1µF
AZ
• Reference Capacitor Value
C
= (Buffer Gain) x C
REF
AZ
AUTOZERO
(COUNT)
INTEGRATE
(FIXED COUNT)
DEINTEGRATE
(COUNT)
ICL7104 - 14
ICL7104 - 16
24,576 - 8,193
98,304 - 32,769
8192
32768
0 - 16383
0 - 65535
CONVERSION TIME (IN CONTINUOUS MODE):
32,768 † t
131,072 † t
(7104 - 14)
(7104 - 16)
OSC
OSC
FIGURE 17.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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5-26
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