HS9-565ARH [INTERSIL]
Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter; 抗辐射高速，单片式数位类比转换器
| 型号： | HS9-565ARH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter |
| 文件： | 总10页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
HS-565ARH
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
March 1996
Features
Description
The HS-565ARH is a fast, radiation hardened 12-bit current out-
put, digital-to-analog converter. The monolithic chip includes a
precision voltage reference, thin-film R-2R ladder, reference
control amplifier and twelve high-speed bipolar current
switches.
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements
are Contained in SMD# 5962-96755 and Harris’ QM
Plan
The Harris Semiconductor Dielectric Isolation process provides
latch-up free operation while minimizing stray capacitance and
leakage currents, to produce an excellent combination of speed
and accuracy. Also, ground currents are minimized to produce a
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max low and constant current through the ground terminal, which
reduces error due to code-dependent ground currents.
• Monotonicity Guaranteed Over Temperature
HS-565ARH die are laser trimmed for a maximum integral nonlin-
earity error of ±0.25 LSB at +25oC. In addition, the low noise bur-
• 0.50 LSB Max Nonlinearity Guaranteed Over
Temperature
ied zener reference is trimmed both for absolute value and mini-
• Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC
mum temperature coefficient.
• Total Dose Hardness to 100K RAD
Functional Diagram
• ±0.75 LSB Accuracy Guaranteed Over Temperature
BIP.
REF OUT VCC
(±0.125 LSB Typical at +25oC)
OFF.
8
11
4
3
20V
SPAN
+
5K
5K
Applications
10V
10
9
10V
SPAN
-
9.95K
IO
IREF
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
DAC
0.5mA
19.95K
6
5
REF
IN
OUT
+
-
3.5K
3K
2.5K
(4X IREF
X CODE)
REF
GND
7
12
24 . . . 13
MSB LSB
-VEE PWR
GND
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
PACKAGE
o
o
5962R9675501VJC
-55 C to +125 C
24 Lead SBDIP
o
o
5962R9675501VXC
-55 C to +125 C
24 Lead Ceramic Flatpack
24 Lead SBDIP
o
HS1-565ARH (SAMPLE)
HS9-565ARH (SAMPLE)
+25 C
o
+25 C
Sample
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Spec Number 518795
File Number 3278.2
Copyright © Harris Corporation 1996
1
HS-565ARH
Pinouts
HS1-565ARH
MIL-STD-1835 CDIP2-T24
(SBDIP)
TOP VIEW
NC
NC
1
2
24 BIT 1 IN (MSB)
23 BIT 2 IN
22
VCC
3
BIT 3 IN
REF OUT
REF GND
REF IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
15 BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
4
5
6
-VEE
7
BIPOLAR RIN
IDAC OUT
10V SPAN
8
9
10
20V SPAN 11
PWR GND 12
H59-565ARH
MIL-STD-1835 CDFP4-F24
(CERAMIC FLATPACK)
TOP VIEW
BIT 1 IN
(MSB)
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
2
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
3
VCC
4
REF OUT
REF GND
REF IN
5
6
7
-VEE
8
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
9
10
11
12
BIT 12 IN
(LSB)
Spec Number 518795
2
Specifications HS-565ARH
Absolute Maximum Ratings
Thermal Information
o
o
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +18V Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to -18V
Voltage on DAC Output (Pin 9). . . . . . . . . . . . . . . . . . . . -3V to +12V
Digital Input (Pins 13 - 24) to Power Ground . . . . . . . . . . -1V to +7V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . . . . . . . . ±12V
10V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . . ±12V
20V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . . ±24V
SBDIP Package. . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package
60
80
17
15
o
Maximum Package Power Dissipation at +125 C
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.62W
If Device Power Exceeds Package Dissipation Capability, Provide
Heat Sinking or Derate Linearly at the Following Rate:
o
Junction Temperature (TJ) (Max) . . . . . . . . . . . . . . . . . . . . . +175 C
o
o
o
SBDIP Package
16.67mW/ C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
o
o
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
Ceramic Flatpack Package
12.5mW/ C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range (VCC) . . . . . . . . . . . . . +11.4V to +16.5V Digital Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Operating Voltage Range (VEE). . . . . . . . . . . . . . . -11.4V to -16.5V Digital Input High Voltage . . . . . . . . . . . . . . . . . . . . . +2.2V to +5.5V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUPA
SUB-
LIMITS
PARAMETERS
Resolution
SYMBOL
CONDITIONS
GROUP
TEMPERATURE
MIN
TYP
MAX UNITS
o
o
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
1, 2, 3
1, 2, 3
-55 C to +125 C
-
-
12
Bits
o
o
Accuracy
ILE
VSSD = VSSA = 0V,
-55 C to +125 C
-
±0.125 ±0.75
LSB
VCC = +15V, VEE = -15V,
Error Relative to Full Scale
o
o
Digital Input High Current
Digital Input Low Current
Differential Nonlinearity
IIH
IIL
VSSD = VSSA = 0V, VIN = 5.5V
VCC = +15V, VEE = -15V
1, 2, 3
1, 2, 3
1, 2, 3
-55 C to +125 C
-
-20
-
0.01
-2.0
+1.0
-
µA
µA
o
o
VSSD = VSSA = 0V, V = 0V
-55 C to +125 C
IN
VCC = +15V, VEE = -15V
o
o
DLE
VSSD = VSSA = 0V,
-55 C to +125 C
±0.25
±0.50
LSB
VCC = +15V, VEE = -15V,
o
+25 C (Monotonicity
Guaranteed Over Temp)
Power Supply Currents
VCC
o
o
ICC
IEE
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C to +125 C
-
9.0
-9.5
10
11.8
mA
mA
V
o
o
VEE
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
-55 C to +125 C
-14.5
9.9
-
10.1
-
o
o
Reference Output
Voltage
Ref Out VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
-55 C to +125 C
o
o
Reference Output
Current
IREF
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
Available for external loads
-55 C to +125 C
1.5
2.5
mA
Output Current
Unipolar
o
o
I
I
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
All Bits On
1, 2, 3
1, 2, 3
-55 C to +125 C
-1.6
-2.0
-2.4
mA
mA
OUT1
OUT2
o
o
Bipolar
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
All Bits On or Off
-55 C to +125 C
±0.8
±1.0
±1.2
Spec Number 518795
3
Specifications HS-565ARH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
GROUPA
SUB-
GROUP
LIMITS
TYP
PARAMETERS
Output Offset
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX UNITS
o
o
Unipolar
VOS
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
Figure 3, R2 = 50Ω Fixed
1, 2, 3
-55 C to +125 C
-
±0.01
±0.05
±0.05
±0.15
% of
F.S.
o
o
Bipolar
BPOE
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
R3 and R4 = 50Ω Fixed
Figure 4
1, 2, 3
-55 C to +125 C
-
% of
F.S.
Power Supply Gain
Sensitivity
o
o
VCC
+PSS
-PSS
Note 3
Note 3
1, 2, 3
1, 2, 3
-55 C to +125 C
-
-
3
10
25
ppm of
F.S./%
o
o
VEE
-55 C to +125 C
15
ppm of
F.S./%
Temperature
Coefficients
o
o
o
Unipolar Zero
Bipolar Zero
With Internal Reference
With Internal Reference
With Internal Reference
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C to +125 C
-
-
-
-
1
5
2
20
ppm/ C
o
o
o
-55 C to +125 C
ppm/ C
o
o
o
Gain (Full Scale)
External Adjustments
-55 C to +125 C
10
50
ppm/ C
o
o
AE
Fixed 50Ω Resistor for R2
Figures 3
-55 C to +125 C
±0.10
±0.25
% of
F.S.
o
o
Gain Error
Bipolar Zero Error
NOTES:
BPAE
BPZE
Fixed 50Ω Resistor for R3 and
R4, Figure 4
1, 2, 3
1, 2, 3
-55 C to +125 C
-
-
±0.10
±0.05
±0.25
±0.10
% of
F.S.
o
o
Fixed 50Ω Resistor for R3 and
R4, Figure 4
-55 C to +125 C
% of
F.S.
1. All voltages referenced to VSSD = VSSA = 0V
2. Unless otherwise specified VCC = +15V and VEE = -15V.
3. The Power Supply Gain Sensitivity is tested in reference to a VCC = +15V and VEE = -15V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank. See AC Specifications in Table 3
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS
SYMBOL
CONDITIONS
f = 1MHz
NOTES
1, 2
TEMPERATURE
MIN
-
TYP
20
-
MAX
-
UNITS
pF
o
Output Capacitance
COUT
+25 C
o
o
Output Compliance
Voltage
1
-55 C to +125 C
-1.5
10
V
o
o
Programmable Output
Ranges
1
1
1
1
1
1
-55 C to +125 C
0
-2.5
0
-
-
-
-
-
-
5
2.5
10
5
V
V
V
V
V
o
o
-55 C to +125 C
o
o
-55 C to +125 C
o
o
-55 C to +125 C
-5
o
o
-55 C to +125 C
-10
±0.25
10
-
o
o
Gain Adjustment Range
Figures 3, 4
Figure 4
-55 C to +125 C
% of
F.S.
o
o
Bipolar Zero
Adjustment Range
1
1
1
-55 C to +125 C
±0.15
15K
-
-
% of
F.S.
o
o
Reference Input
Impedance
RREF
ROUT
VSSD = VSSA = 0V, -15
VCC = +15V, VEE = -15V
-55 C to +125 C
20K
2.5K
25K
3.2K
Ω
o
o
Output Resistance
VSSD = VSSA = 0V,
-55 C to +125 C
1.8K
Ω
VCC = +15V, VEE = -15V,
Exclusive of Span Resistors
Spec Number 518795
4
Specifications HS-565ARH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
TYP
PARAMETERS
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Settling Time (Note 3)
TS1
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
High Z External Load
1
-55 C to +125 C
-
350
500
ns
o
o
TS2
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
75Ω External Load
1
-55 C to +125 C
-
150
250
ns
Full Scale Transition
Rise Time
o
o
TRISE VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
1
1
-55 C to +125 C
-
-
15
30
30
60
ns
ns
o
o
Fall Time
NOTES:
TFALL VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
-55 C to +125 C
1. The parameters listed in Table 3 are controlled via design or process and are not tested. These parameters are characterized upon initial
design release.
2. 24 lead DIP package only.
3. Reference the Settling Time discussion and Figure 3.
TABLE 4. POST 100 K RAD ELECTRICAL PERFORMANCE
o
Post 100K RAD Electrical Performance Is Per Table 1 (+25 C Only) Except As Follows:
LIMITS
o
PARAMETER
DIGITAL INPUTS
SYMBOL
CONDITIONS: +25 C ONLY
MIN
MAX
UNITS
Low Current
Low Voltage
High Voltage
UNIPOLAR
I
V
= 0.0V
IN
-40
-
-
0.5
-
µA
V
IL
V
(Note 1)
(Note 1)
IL
V
2.5
V
IH
Full Scale Error
BIPOLAR
AE
Figure 3, R2 = 50Ω Fixed
-
±0.85
% of F.S.
Offset Error
BPOE
BPZE
BPAE
DLE
Figure 4, R3 and R4 = 50Ω Fixed
Figure 5, R3 and R4 = 50Ω Fixed
Figure 5, R3 and R4 = 50Ω Fixed
Monotonicity Guaranteed
-
-
-
-
-
±0.25
±0.25
±0.85
±1.0
% of F.S
% of F.S.
% of F.S.
LSB
Zero Error
Full Scale Error
Differential Nonlinearity
Accuracy
ILE
Error Relative to Full Scale
±1.0
LSB
NOTES:
1. This parameter is an applied condition of test.
o
TABLE 5. BI DELTA PARAMETERS (±25 C)
PARAMETER
DELTA LIMIT
±1.18mA
±1.45mA
±240µA
±240µA
±0.02%
±0.15%
±0.10%
±0.10%
±1.0µA
I
CC
I
EE
I
I
OUT1
OUT2
VOS
AE
BPOE
BPZE
I
IL
I
±40nA
IH
Spec Number 518795
5
Specifications HS-565ARH
Radiation Bias Circuit
Burn-In Bias Circuit
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
NC
BIT 1
BIT 2
BIT 3
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
NC
NC
+15V
+15V
3
3
VCC
VCC
C1
D1
4
4
REF OUT BIT 4
REF GND BIT 5
REF OUT
REF GND
REF IN
-VEE
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
5
5
+5V
6
6
REF IN
-VEE
BIT 6
BIT 7
BIT 8
BIT 9
-15V
D2
-15V
7
7
C2
C3
8
8
BIP OFF
OUT
BIP OFF
OUT
9
9
+10V
D3
+10V
10
11
12
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
F11
NOTES:
NOTE:
Power Supply Levels are ±0.5V
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11:
VIH = 5.0V ±0.5V
VIL = 0.0V ±0.5V
F0 = 100kHz ±10% (50% Duty Cycle)
F1 = F0/2
F2 = F0/4
F3 = F0/8
F4 = F0/16
F5 = F0/32
F6 = F0/64
F7 = F0/128
F8 = F0/256
F9 = F0/512
F10 = F0/1024
F11 = F0/2048
Definitions of Specifications
Digital Inputs
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of ±1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
The HS-565ARH accepts digital input codes in binary format
and may be user connected for any one of three binary
codes. Straight binary, Two’s Complement (see note below),
or Offset Binary, (See Operating Instructions).
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50 LSB of final value.
DIGITAL
INPUT
ANALOG OUTPUT
(NOTE)
TWO’S
STRAIGHT
BINARY
OFFSET
BINARY
MSB . LSB
000 . . .000
100 . . .000
111 . . .111
COMPLEMENT
Drift
Zero
-FS (Full Scale)
Zero
Zero
-FS
Gain Drift - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per oC (ppm of FSR/oC). Gain error is
measured with respect to +25oC at high (TH) and low (TL)
temperatures. Gain drift is calculated for both high (TH - 25oC)
and low ranges (+25oC - TL) by dividing the gain error by the
respective change in temperature. The specification is the
larger of the two representing worst case drift.
0.50 FS
+FS - 1LSB
+FS - 1LSB
Zero - 1LSB
+FS - 1LSB
011 . . .111 0.50 FS - 1LSB Zero - 1LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an impor-
tant measure of its accuracy. It describes the deviation from
an ideal straight line transfer curve drawn between zero (all
bits OFF) and full scale (all bits ON).
Offset Drift - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per oC (ppm of FSR/oC). Offset error
is measured with respect to +25oC at high (TH) and low (TL)
temperatures. Offset drift is calculated for both high (TH - 25oC)
and low (+25oC - TL) ranges by dividing the offset error by the
Differential Nonlinearity - For a D/A converter, it is the
difference between the actual output voltage change and the
Spec Number 518795
6
HS-565ARH
respective change in temperature. The specification given is No Trim Operation
the larger of the two, representing worst case drift.
The HS-565ARH will perform as specified without calibration
Power Supply Sensitivity
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 3
replace R2 with 50Ω; also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 4,
replace R3 and R4 with 50Ω resistors.
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -15V
or +15V supplies. It is specified under DC conditions and
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%).
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be ±0.50 LSB plus the op amp offset.
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
The feedback capacitor C must be selected to minimize
settling time.
R4
100Ω
Glitch
R3
VCC
REF OUT
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
BIP.
100Ω
4
3
8
OFF.
11
10
20V SPAN
10V SPAN
HS-565ARH
+
-
5K
5K
10V
VO
IREF
9.95K
DAC
DAC
OUT
0.5mA
19.95K
6
5
C
-
IO
REF
IN
+
-
9
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
REF
GND
R (SEE
TABLE 7)
Applying the HS-565ARH
CODE
INPUT
OP AMP Selection
The HS-565ARH’s current output may be converted to
voltage using the standard connections shown in Figures 3
and 4. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 4. BIPOLAR VOLTAGE OUTPUT
Calibration
Calibration provides the maximum accuracy from
converter by adjusting its gain and offset errors to zero, For
the HS-565ARH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 3 or 4.
2 2
) + (t )
a
(t
D
A
where tD, tA are settling times for the DAC and amplifier.
+15V
-15V
100kΩ
R1
50kΩ
R2
100Ω
100Ω
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
VCC
REF OUT
BIP.
4
3
8
OFF.
11
20V SPAN
HS-565ARH
+
-
5K
5K
10V
10
VO
10V SPAN
IREF
9.95K
Next adjust positive FS. This is a gain error adjustment,
which rotates the output characteristic about the negative FS
value.
DAC
19.95
K
DAC
OUT
0.5mA
6
5
C
-
IO
REF
IN
+
-
9
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
REF
GND
R (SEE
TABLE 7)
CODE
INPUT
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 3. UNIPOLAR VOLTAGE OUTPUT
Spec Number 518795
7
HS-565ARH
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test methods before using the specified
settling time as a basis for design.
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 5A and5B
for the measurement of case (d).
Procedure
As shown in Figure 5B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of several
microseconds. This assures that the DAC output has
settled to its final wave.
The approach used for several years at Harris calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB
a reasonable
• Switch on the LSB (+5V)
magnitude (814mV for the HS-565ARH, which provides the
comparator with enough overdrive to establish an accurate
±0.50 LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for a
common application - use in a successive approximation A/
D converter. Considerable experience has shown this to be a
reliable and repeatable way to measure settling time.
• Adjust the VLSB supply for 50% triggering at COMPARA-
TOR OUT. This is indicated by traces of equal brightness
on the oscilloscope display as shown in Figure 5B. Note
DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
The usual specification is based on a 10V step, produced
by simultaneously switching all bits from off-to-on (tON) or
on-to-off (tOFF). The slower of the two cases is specified,
as measured from 50% of the digital input transition to the
final entry within a window of 0.50 LSB about the settled
value. Four measurements characterize a given type of
DAC:
• Adjust the VLSB supply to reduce the DVM reading by
5 LSBs (DVM reads 10X, so this sets the comparator
to sense the final settled value minus 0.50 LSB). Com-
parator output disappears.
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
• Reduce generator number 2 delay until comparator output
reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 5B. Settling
time equals tX + tD, i.e. tX + 15ns.
TABLE 7. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
CALIBRATION
ADJUST
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
MODE
TO SET VO
Unipolar (See Figure 3)
0 to +10V
0 to +5V
±10V
VO
VO
NC
VO
VO
Pin 10
Pin 9
VO
1.43K
All 0’s
All 1’s
R1
R2
0V
+9.99756V
1.1K
All 0’s
All 1’s
R1
R2
0V
+4.99878V
Bipolar (See Figure 4)
1.69K
1.43K
1.1K
All 0’s
All 1’s
R3
R4
-10V
+9.99512V
±5V
Pin 10
Pin 9
All 0’s
All 1’s
R3
R4
-5V
+4.99756V
±2.5V
All 0’s
All 1’s
R3
R4
-2.5V
+2.49878V
Spec Number 518795
8
HS-565ARH
SYNC
IN
PULSE
GENERATOR
NO. 1
PULSE
GENERATOR
NO. 2
OUT
OUT
TRIG
OUT
C
20V ± 20%
BIAS
A
HS-565ARH
TURN ON
8
24
TURN OFF
11
23
.
.
.
5K
5K
+3V
.
9.95K
10
9
.
50%
A
B
NC
.
DIGITAL
INPUT
0V
0V
.
.
-0.50LSB
STROBE IN
D
.
.
B
+
DAC
OUTPUT
.
~100
kHz
COMPARATOR
OUT
.
.
-
14
-400mV
(TURN OFF)
2.5K
SETTLING TIME
tD = COMPARATOR DELAY
P
5
13
2mA
5V
tX
50%
COMP.
STROBE
2V
C
12
LSB
90
10
200K
0.8V
“EQUAL BRIGHTNESS”
VLSB
SUPPLY
DVM
0.1µF
COMP.
OUT
4V
D
0V
FIGURE 5A.
FIGURE 5B.
Other Considerations
Grounds
Layout
The HS-565ARH has two ground terminals, pin 5 (REF GND)
and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point
exists, then separate paths are required to pins 5 and 12).
Connections to pin 9 (IOUT) on the HS-565ARH are most crit-
ical for high speed performance. Output capacitance of the
DAC is only 20pF, so a small change of additional capacitance
may alter the op amp’s stability and affect settling time. Con-
nections to pin 9 should be short and few. Component leads
should be short on the side connecting to pin 9 (as for feed-
back capacitor C). See the Settling Time section.
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the analog/
signal and digital/power grounds.
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve the
HS-565ARH also. If no op amp is used, a 0.01µF ceramic
capacitor from each supply terminal to pin 12 is sufficient,
since supply current variations are small.
NOTE: Current cancellation is a two step process within the HS-
565ARH in which code dependent variations are eliminated,
the resulting DC current is supplied internally. First an
auxiliary 9-bit R-2R ladder is driven by the complement of the
DACs input code. Together, the main and auxiliary ladders
draw a continuous 2.25mA from the internal ground node, re-
gardless of input code. Part of the DC current is supplied by
the zener voltage reference, and the remainder is sourced
from the positive supply via a current mirror which is laser
trimmed for zero current through the external terminal (pin 5).
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Die Size . . . . . . . . . . . . . . . . . . . . . . . . . 179 mils x 107 mils
Tie Substrate to . . . . . . . . . . . . . . . . . . . .Reference Ground
Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar - DI
Spec Number 518795
9
HS-565ARH
Die Characteristics
DIE DIMENSIONS:
179 mils x 107 mils x 19 mils
WORST CASE CURRENT DENSITY:
2.0 x 105 A/cm2
METALLIZATION:
Type: Al/Copper
Thickness: 16kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
HS-565ARH
(MSB)
BIT 1
VCC NC
NC
1
A
BIT 2
3
3
VREF OUT
BIT 3
VREF
GND
BIT 4
BIT 5
VREF IN
-VS
BIT 6
BIPOLAR
12
BIT 7
BIT 8
IDAC
OUT
BIT 9
10V
SPAN
BIT 10
20V
POWER
GND
BIT 12
(LSB)
BIT 11
SPAN
Spec Number 518795
10
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