HS0-RTX2010RH-Q_技术文档

HS-RTX2010RH

Data Sheet

March 2000

File Number 3961.3

Radiation Hardened Real Time Express™

Microcontroller

Features

• Electrically Screened to SMD # 5962-95635

• QML Qualiﬁed per MIL-PRF-38535 Requirements

• Fast 125ns Machine Cycle

The HS-RTX2010RH is a radiation-hardened 16-bit

microcontroller with on-chip timers, an interrupt controller, a

multiply-accumulator, and a barrel shifter. It is particularly

well suited for space craft environments where very high

speed control tasks which require arithmetically intensive

calculations, including ﬂoating point math to be performed in

hostile space radiation environments.

• 1.2µM TSOS4 CMOS/SOS Process

• Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si)

2

• Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm

-10

• Single Event Upset Error Rate . . . . <1 x 10 Errors/Bit-Day

This processor incorporates two 256-word stacks with

multitasking capabilities, including conﬁgurable stack

partitioning and over/underﬂow control.

(Note)

o

• -55 C - 125 C, 5V ±10% Operation

• Single Cycle Instruction Execution

Instruction execution times of one or two machine cycles are

achieved by utilizing a stack oriented, multiple bus

architecture. The high performance ASIC Bus, which is

unique to the RTX product, provides for extension of the

microcontroller architecture using off-chip hardware and

application speciﬁc I/O devices.

• Fast Arithmetic Operations

- Single Cycle 16-Bit Multiply

- Single Cycle 16-Bit Multiply Accumulate

- Single Cycle 32-Bit Barrel Shift

- Hardware Floating Point Support

RTX Microcontrollers support the C and Forth programming

languages. The advantages of this product are further

enhanced through third party hardware and software support.

• C Software Development Environment

• Direct Execution of Fourth Language

• Single Cycle Subroutine Call/Return

• Four Cycle Interrupt Latency

Combined, these features make the HS-RTX2010RH an

extremely powerful processor serving numerous

applications in high performance space systems. The

HS-RTX2010RH has been designed for harsh space

radiation environments and features outstanding Single

Event Upset (SEU) resistance and excellent total dose

response.

• On-Chip Interrupt Controller

• Three On-Chip 16-Bit Timer/Counters

• Two On-Chip 256 Word Stacks

• ASIC Bus™ for Off-Chip Architecture Extension

• 1 Megabyte Total Address Space

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

• Word and Byte Memory Access

• Fully Static Design - DC to 8MHz Operation

• 84 Lead Quad Flat Package or 85 Pin Grid Array

• Third Party Software and Hardware Development Systems

Detailed Electrical Speciﬁcations for these devices are

contained in SMD 5962-95635. A “hot-link” is provided

on our homepage for downloading.

www.intersil.com/spacedefense/space.asp

NOTE: Single Event Upset error rates are Adams 10% worst case

environment under worst case conditions for upset.

Ordering Information

Applications

INTERNAL

MKT. NUMBER

TEMP. RANGE

o

ORDERING NUMBER

5962F9563501QXC

5962F9563501QYC

5962F9563501V9A

5962F9563501VXC

5962F9563501VYC

( C)

• Space Systems Embedded Control

• Digital Filtering

HS8-RTX2010RH-8

HS9-RTX2010RH-8

HS0-RTX2010RH-Q

HS8-RTX2010RH-Q

HS9-RTX2010RH-Q

55 to 125

25

• Image Processing

• Scientiﬁc Instrumentation

• Optical Systems

55 to 125

HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto

HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto

• Control Systems

• Attitude/Orbital Control

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

Real Time Express™, RTX™, and ASIC Bus™ are trademarks of Intersil Corporation.

HS-RTX2010RH

Block Diagram

OFF CHIP

MAIN

PERIPHERALS

MEMORY

HS-RTX2010RH

CLOCK AND

CONFIGURATION

CONTROL

MEMORY BUS

INTERFACE

ASIC BUS

CONTROL

INPUTS

INTERFACE

MEMORY

PAGE

INTERRUPT

INPUTS

INTERRUPT

CONTROL

256-WORD

RETURN

STACK

TIMER

TIMER/

INPUTS

RTX CORE

STACK

COUNTERS

PROCESSOR

CONTROLLERS

256-WORD

PARAMETER

STACK

BARREL

SHIFTER

MAC

Pinouts

HS8-RTX2010RH

MIL-STD-1835 CMGA3-P85C

A

B

C

D

E

F

G

H

J

K

L

K

J

H

G

F

E

D

C

B

A

11

10

9

11 MD08 MD07 MD06 GND MD02 MD01 PCLK UDS GND MA19

MA16

MA16 MA19 GND UDS PCLK MD01 MD02 GND MD06 MD07 MD08

MD11 MD09 VDD MD05 MD03 NEW BOOT LDS MA18 MA17 MA14

10

9

MA14

MA17 MA18 LDS BOOT NEW MD03 MD05 VDD MD09 MD11

MD12 MD10

MD04 MD00 MR/W

MA15 VDD

VDD MA15

MD10 MD12

MD13 MD14

MR/W MD00 MD04

8

8 MD14 MD13

MA13 MA12

GND MA10 MA09

MA08 MA07 MA11

MA12 MA13

7

7 GA00 MD15 GA01

MA09 MA10 GND

MA11 MA07 MA08

MA06 MA05 MA04

GA01 MD15 GA00

GA02 GND TCLK

INTSUP NMI INTA

HS-RTX2010RH

TOP VIEW

BOTTOM VIEW

PINS UP

6

GND GA02

6 TCLK

PINS DOWN

5

INT-

SUP

5

4

INTA NMI

MA04 MA05

MA06

4

VDD E I1

MA02 MA03

GD01 MA01

ALIGN.

E I1 VDD

MA03 MA02

MA01 GD01

3

2

E I2

E I4

GD14 GD11 GD10

GD10 GD11 GD14

E I4 E I2

2

E I3 RESET WAIT GIO GD13 GD12 GD08 GD06 GD03 GD02 GD00

E I5 ICLK GR/W GD15 GND GD07 GD09 VDD GD05 GD04 GND

GD00 GD02 GD03 GD06 GD08 GD12 GD13 GIO WAIT RESET E I3

GND GD04 GD05 VDD GD09 GD07 GND GD15 GR/W ICLK E I5

1

A

B

C

D

E

F

G

H

J

K

L

K

J

H

G

F

E

D

C

B

A

A1

NOTE: An overbar on a signal name represents an active LOW signal.

2

HS-RTX2010RH

Pinouts (Continued)

HS9-RTX2010RH

(LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A

RESET 12

WAIT 13

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

MD08

VDD

MD07

MD06

MD05

GND

MD04

MD03

MD02

MD01

MD00

MR/W

PCLK

BOOT

NEW

UDS

ICLK

GR/W 15

14

GIO

GD15

16

17

GD14 18

GD13

GND

19

20

21

22

23

24

25

26

27

28

29

30

31

32

GD12

GD11

GD10

GD09

GD08

GD07

VDD

GD06

GD05

GD04

GD03

GND

HS-RTX2010RH

TOP VIEW

LDS

GND

MA19

MA18

MA17

NOTE: An overbar on a signal name represents an active LOW signal.

PGA And CQFP

Pin/Signal Assignments

Pin/Signal Assignments ^(Continued)

PGA

SIGNAL

NAME

PGA

SIGNAL

NAME

CQFP

1

TYPE

Output; Address Bus

Output

CQFP

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

TYPE

I/O; Data Bus

C6

A6

A5

B5

C5

A4

B4

A3

A2

B3

A1

B2

C2

B1

C1

D2

D1

E3

E2

E1

F2

F3

G3

GA02

TCLK

INTA

NMI

G1

G2

F1

H1

H2

J1

GD09

GD08

GD07

VDD

2

I/O; Data Bus

3

Output

I/O; Data Bus

4

Input

Power

5

INTSUP

VDD

Input

GD06

GD05

GD04

GD03

GND

I/O; Data Bus

6

Power

I/O; Data Bus

7

EI1

Input

K1

J2

I/O; Data Bus

8

EI2

Input

I/O; Data Bus

9

EI3

Input

L1

K2

K3

L2

L3

K4

L4

J5

Ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

EI4

Input

GD02

GD01

GD00

MA01

MA02

MA03

MA04

MA05

MA06

MA07

MA08

GND

I/O; Data Bus

EI5

Input

I/O; Data Bus

RESET

WAIT

ICLK

GR/W

GIO

Input

I/O; Data Bus

Input

Output; Address Bus

Ground

Input

Output

GD15

GD14

GD13

GND

GD12

GD11

GD10

I/O; Data Bus

Ground

K5

L5

K6

J6

I/O; Data Bus

J7

L7

K7

MA09

MA10

Output; Address Bus

3

HS-RTX2010RH

PGA And CQFP

Pin/Signal Assignments ^(Continued)

PGA And CQFP

Pin/Signal Assignments ^(Continued)

PGA

SIGNAL

NAME

PGA

SIGNAL

NAME

CQFP

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

TYPE

Output; Address Bus

Power

CQFP

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

-

TYPE

I/O; Data Bus

L6

L8

MA11

MA12

MA13

VDD

E11

E10

E9

MD02

MD03

MD04

GND

I/O; Data Bus

Ground

K8

L9

D11

D10

C11

B11

C10

A11

B10

B9

L10

K9

MA14

MA15

MA16

MA17

MA18

MA19

GND

Output; Address Bus

Ground

MD05

MD06

MD07

VDD

I/O; Data Bus

Power

L11

K10

J10

K11

J11

H10

H11

F10

G10

G11

G9

MD08

MD09

MD10

MD11

MD12

MD13

MD14

GND

I/O; Data Bus

Ground

LDS

Output

A10

A9

UDS

Output

NEW

BOOT

PCLK

MR/W

MD00

MD01

Output

B8

Output

A8

Output

B6

Output

B7

MD15

GA00

GA01

-

I/O; Data Bus

Output; Address Bus

Isolated Alignment Pin

F9

I/O; Data Bus

A7

F11

C7

C3

Output Signal Descriptions

RESET

SIGNAL CQFP LEVEL

DESCRIPTION

OUTPUTS

NEW

60

61

1

NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress.

BOOT

BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing

bit 3 of the Configuration Register.

MR/W

UDS

63

59

1

MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress.

UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being

accessed.

LDS

58

1

LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being

accessed.

GIO

16

15

62

1

0

ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress.

GR/W

PCLK

ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress.

PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK.

Held low extra cycles when WAIT is asserted.

TCLK

INTA

2

3

0

TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles.

INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress.

Input Signal, Bus, and Power Connection Descriptions

CQFP

SIGNAL

INPUTS

LEAD

DESCRIPTION

WAIT

ICLK

13

14

12

WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended.

INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels).

RESET

A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle

setup and hold times.

4

HS-RTX2010RH

Input Signal, Bus, and Power Connection Descriptions (Continued)

CQFP

SIGNAL

EI2, EI1

LEAD

DESCRIPTION

8, 7

EXTERNAL INTERRUPTS 2, 1: Active HIGH level-sensitive inputs to the Interrupt Controller. Sampled on the rising

edge of PCLK. See Timing Diagrams for detail.

EI5-EI3

11-9

EXTERNAL INTERRUPTS 5, 4, 3: Dual purpose inputs; active HIGH level-sensitive Interrupt Controller inputs;

active HIGH edge-sensitive Timer/Counter inputs. As interrupt inputs, they are sampled on the rising edge of PCLK.

See Timing Diagrams for detail.

NMI

4

5

NON-MASKABLE INTERRUPT: Active HIGH edge-sensitive Interrupt Controller input capable of interrupting any

processor cycle when NMI is set to Mode 0. See the Interrupt Suppression and Interrupt Controller Sections.

INTSUP

INTERRUPT SUPPRESS: A HIGH on this pin inhibits all maskable interrupts, internal and external.

ADDRESS BUSES (OUTPUTS)

GA02

1

ASIC ADDRESS: 3-bit ASIC Address Bus, which carries address information for external ASIC devices.

GA01

84

GA00

83

MA19-MA14

MA13-MA09

MA08-MA01

DATA BUSES (I/O)

GD15-GD13

GD12-GD07

GD06-GD03

GD02-GD00

MD15

56-51

49-45

43-36

MEMORY ADDRESS: 19-bit Memory Address Bus, which carries address information for Main Memory.

17-19

21-26

28-31

33-35

82

ASIC DATA: 16-bit bidirectional external ASIC Data Bus, which carries data to and from off-chip I/O devices.

MEMORY DATA: 16-bit bidirectional Memory Data Bus, which carries data to and from Main Memory.

MD14-MD08

MD07-MD05

MD04-MD00

80-74

72-70

68-64

POWER CONNECTIONS

VDD

6, 27,

Power supply +5V connections. A 0.1µF, low impedance decoupling capacitor should be placed between VDD and

50, 73

GND. This should be located as close to the RTX package as possible.

GND

20, 32,

44, 57,

69, 81

Power supply ground return connections.

t

PULSE WIDTH

TYPICAL

CLOCK OR

STROBE

4.0V

0.5V

2.25V

2.25V 2.25V

t

SETUP

HOLD

4.0V

0.5V

TYPICAL

INPUT

2.25V

t

DELAY

TYPICAL

OUTPUT

2.25V

t

VALID

HOLD

TYPICAL

DATA

OUTPUT

2.75V

1.75V

2.75V

1.75V

FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT

5

HS-RTX2010RH

Timing Diagrams

t

1

t

3

2

ICLK

t

19

11

TCLK

t

12

13

t

4

t

5

WAIT

t

5

t

20

15

PCLK

(NOTE 1)

t

16

17

PCLK

(NOTE 2)

t

20

t

51

50

GIO

(NOTE 3)

NOTES:

1. NORMAL CYCLE: This waveform describes a normal PCLK cycle and a PCLK cycle with a Wait state.

2. EXTENDED CYCLE: This waveform describes a PCLK cycle for a USER memory access or an external ASIC Bus read cycle when the CYCEXT

bit or ARCE bit is set.

3. EXTENDED CYCLE: This waveform describes a GIO cycle for an external ASIC Bus read when the ARCE bit is set.

4. An active HIGH signal on the RESET input is guaranteed to reset the processor if its duration is greater than or equal to 4 rising edges of ICLK

plus 1/2 ICLK cycle setup and hold times. If the RESET input is active for less than four rising edges of ICLK, the processor will not reset.

FIGURE 2. CLOCK AND WAIT TIMING

t

6

EI5 - EI3

t

8

7

FIGURE 3. TIMER/COUNTER TIMING

6

HS-RTX2010RH

Timing Diagrams (Continued)

PCLK

t

26

28

MA

t

LDS

UDS

29

t

31

NEW

BOOT

MR/W

t

21

t

22

MD

IN

t

35

t

32

t

33

34

MD

OUT

NOTES:

5. If both LDS and UDS are low, no memory access is taking place in the current cycle. This only occurs during streamed instructions that do not

access memory.

6. During a streamed single cycle instruction, the Memory Data Bus is driven by the processor.

FIGURE 4. MEMORY BUS TIMING

ICLK

t

51

50

GIO

PCLK

GA

t

69

48

49

t

52

t

54

t

56

58

GR/W

t

40A, B

43

t

42

41A, B

GD

IN

t

65

62

t

61

63

GD

OUT

NOTES:

7. GIO remains high for internal ASIC bus cycles.

8. GR/W goes low and GD is driven for all ASIC write cycles, including internal ones.

9. During non-ASIC write cycles, GD is not driven by the HS-RTX2010RH. Therefore, it is recommended that all GD pins be pulled to VCC or GND

to minimize power supply current and noise.

10. t

and t

specifications are for Streamed Mode of operation only.

41B

40B

FIGURE 5. ASIC BUS TIMING

7

HS-RTX2010RH

Timing Diagrams (Continued)

e

5

1

2

3

4

PCLK

EI

t

44

t

47

46

47

46

INTSUP

t

67

68

INTA

MA

26

28

INT VECTOR

NOTES:

11. Events in an interrupt sequence are as follows:

e . The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e and the rising edge of

1

PCLK prior to e , the interrupt vector will be for NMI.

5

e . If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK.

2

e . The core samples the state of the interrupt requests from the Interrupt Controller on the falling edge of PCLK. If INTSUP is high, maskable

3

interrupts will not be detected at this time.

e . When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge

4

of PCLK.

e . Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the

5

highest priority interrupt request active at this time.

12. t is only required to determine when the Interrupt Acknowledge cycle will occur.

44

13. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs.

FIGURE 6. INTERRUPT TIMING: WITH INTERRUPT SUPPRESSION

e

5

1

2

4

PCLK

t

44

EI

t

47

46

INTSUP

t

68

67

INTA

MA

t

28

26

INT VECTOR

FIGURE 7. INTERRUPT TIMING: WITH NO INTERRUPT SUPPRESSION

8

HS-RTX2010RH

Timing Diagrams (Continued)

e

5

1

2

4

PCLK

t

44

NMI

t

68

67

INTA

t

28

26

MA

NMI

VECTOR

NOTES:

14. Events in an interrupt sequence are as follows:

e . The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e and the rising edge of

1

PCLK prior to e , the interrupt vector will be for NMI.

5

e . If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK.

2

e . When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge

4

of PCLK.

e . Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the

5

highest priority interrupt request active at this time.

15. t is only required to determine when the Interrupt Acknowledge cycle will occur.

44

16. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs.

17. NMI has a glitch filter which requires the signal that initiates NMI last at least two rising and two falling edges of ICLK.

FIGURE 8. NON-MASKABLE INTERRUPT TIMING

HS-RTX2010RH Microcontroller

The HS-RTX2010RH is designed around the RTX Processor

core, which is part of the Intersil Standard Cell Library.

remaining elements are contained in on-chip memory (“stack

memory”).

This processor core has eight 16-bit internal registers, an

ALU, internal data buses, and control hardware to perform

instruction decoding and sequencing.

The top element of the Return Stack is 21 bits wide, and is

stored in registers

and

, while the remaining

IPR

I

elements are contained in stack memory.

On-chip peripherals which the HS-RTX2010RH includes are

Memory Page Controller, an Interrupt Controller, three

Timer/Counters, and two Stack Controllers. Also included

are a Multiplier-Accumulator (MAC), a Barrel Shifter, and a

Leading Zero Detector for ﬂoating point support.

The highly parallel architecture of the RTX is optimized for

minimal Subroutine Call/Return overhead. As a result, a

Subroutine Call takes one Cycle, while a Subroutine Return

is usually incorporated into the preceding instruction and

does not add any processor cycles. This parallelism

provides for peak execution rates during simultaneous bus

operations which can reach the equivalent of 32 million

Forth language operations per second at a clock rate of

8MHz. Typical execution rates exceed 8 million operations

per second.

Off-chip user interfaces provide address and data access to

Main Memory and ASIC I/O devices, user deﬁned interrupt

signals, and Clock/Reset controls.

Figure 9 shows the data paths between the core, on-chip

peripherals, and off-chip interfaces.

Intersil factory applications support for this device is limited.

RTS-C C-Compiler support is provided by Highland Software

at highlandsoft@compuserve.com. Development system

tools are supported by Micro Processor Engineering Limited

(UK) at 441 703 631441. A HS-RTX2010RH programmers

reference manual can be obtained through your local Intersil

Sales Ofﬁce.

The HS-RTX2010RH microcontroller is based on a two-stack

architecture. These two stacks, which are Last-In-First-Out

(LIFO) memories, are called the Parameter Stack and the

Return Stack.

Two internal registers,

and

, provide the top

two elements of the 16-bit wide Parameter Stack, while the

9

HS-RTX2010RH

OFF-CHIP

USER

INTERFACES

MEMORY BUS

INTERFACE

ASIC BUS

INTERFACE

CLOCK AND

RESET CONTROL

HS-RTX2010RH

MEMORY

PAGE

INTERRUPT

CONTROL

IPR

IMR

IVR

IBC

DPR

UPR

CPR

UBR

TIMER/COUNTERS

STACK

CONTROL

TC0

TC1

TC2

TP0

TP1

TP2

SPR

SVR

SUR

BYTE

SWAP

BARREL

SHIFTER

-1

I

+1

LEADING ZERO

DETECTOR

CR MD SR

TOP

PC

16 x 16

MAC

MXR

MHR

MLR

256 x 16

256 x 21

RETURN

STACK

Y

ALU

T

PARAMETER

INSTRUCTION

DECODER

STACK

MEMORY

NOTE:

contains the 5 most signiﬁcant bits (20-16) of the top element of the Return Stack.

IPR

FIGURE 9. HS-RTX2010RH FUNCTIONAL BLOCK DIAGRAM

HS-RTX2010RH Operation

Control of all data paths and the Program Counter Register,

Instructions which access memory require two clock cycles

to be executed. During the ﬁrst cycle of a memory access

instruction, the instruction is decoded, the address of the

memory location to be accessed is placed on the Memory

Address Bus (MA19-MA01), and the memory data

(MD15-MD00), is read or written. During the second cycle,

ALU operations are performed, the address of the next

instruction to be executed is placed on the Memory Address

Bus, and the next instruction is fetched, as indicated in the

bottom half of Figure 10.

(

), is provided by the Instruction Decoder. This hardware

PC

determines what function is to be performed by looking at

the contents of the Instruction Register, ( ), and

IR

subsequently determines the sequence of operations

through data path control.

Instructions which do not perform memory accesses execute

in a single clock cycle while the next instruction is being

fetched.

As shown in Figure 10, the instruction is latched into

at

IR

the beginning of a clock cycle. The instruction is then decoded

by the processor. All necessary internal operations are

performed simultaneously with fetching the next instruction.

10

HS-RTX2010RH

PCLK

EXECUTION SEQUENCE WITH NO MEMORY DATA ACCESS:

END OF BEGIN

FIRST SECOND

CLOCK CLOCK

CYCLE CYCLE

BEGIN

FIRST

CLOCK

CYCLE

CONCURRENT

OPERATIONS

PERFORM INTERNAL OPERATIONS AND

ALU OPERATIONS, AS REQUIRED

ADDRESS OF

INSTRUCTION

IS PLACED ONTO

MA19-MA01

BUS

LATCHES INTO

FETCH

IR

ASIC BUS OPERATIONS

EXECUTION SEQUENCE WITH MEMORY DATA ACCESS:

BEGIN

FIRST

CLOCK

CYCLE

END OF

BEGIN

END OF

SECOND

CLOCK

CYCLE

FIRST SECOND

CLOCK CLOCK

CYCLE CYCLE

CONCURRENT

OPERATIONS

PERFORM ALU OPERATIONS

ADDRESS OF

MEMORY

LOCATION

IS PLACED ONTO

MA19-MA01

BUS

INSTRUCTION

LATCHES

INTO

READ OR WRITE

MEMORY DATA

PLACE ADDRESS OF

FETCH NEXT

INSTRUCTION

NEXT INSTRUCTION

ONTO MA19-MA01

IR

FIGURE 10. INSTRUCTION EXECUTION SEQUENCE

also holds the most signiﬁcant 16 bits of 32-bit products and

32-bit dividends.

RTX Data Buses and Address Buses

The RTX core bus architecture provides for unidirectional

data paths and simultaneous operation of some data buses.

This parallelism allows for maximum efﬁciency of data ﬂow

internal to the core.

: The Next Register holds the second element of the

is the implicit data source or

EXT

destination for certain instructions, and has no ASIC address

assignment. During a stack “push”, the contents of

Addresses for accessing external (off-chip) memory or

ASIC devices are output via either the Memory Data Bus

(MA19-MA01) or the ASIC Address Bus (GA02-GA00). See

Table 3. External data is transferred by the ASIC Data Bus

(GD15-GD00) and the Memory Data Bus (MD15-MD00),

both of which are bidirectional.

TOP

are put into

. This register is used to hold the least

accessed through , as described in the Memory

: The Instruction Register is actually a latch which

IR

RTX Internal Registers

contains the instruction currently being executed, and has no

ASIC address assignment. In certain instructions, an

operand can be embedded in the instruction code, making

the implicit source for that operand (as in the case of

short literals). Input to this register comes from Main

Memory (see Tables 6 thru 22 for code information).

The core of the HS-RTX2010RH is a macrocell available

through the Intersil Standard Cell Library. This core contains

eight 16-bit internal registers, which may be accessed

implicitly or explicitly, depending upon the register accessed

and the function being performed.

IR

: The Conﬁguration Register is used to indicate and

: The Top Register contains the top element of the

CR

TOP

control the current status/setup of the RTX microcontroller,

through the bit assignments shown in Figure 11. This

register is accessed explicitly through read and write

operations, which cause interrupts to be suppressed for one

cycle, guaranteeing that the next instruction will be

performed before an Interrupt Acknowledge cycle is allowed

to be performed.

Parameter Stack++.

is the implicit data source or

TOP

destination for certain instructions, and has no ASIC address

assignment. The contents of this register may be directed to

any I/O device or to any processor register except the

Instruction Register.

is also the T input to the ALU.

TOP

Input to

must come through the ALU. This register

TOP

11

HS-RTX2010RH

Timer/Counter Registers

CR

,

: The Timer/Counter Registers are

TC0 TC1 TC2

15141312 1110 9 8 7 6 5 4 3 2 1 0

16-bit read-only registers which contain the current count

value for each of the three Timer/Counters. The counter is

decremented at each rising clock edge of TCLK. Reading

from these registers at any time does not disturb their

contents. The sequence of Timer/Counter operations is

shown in Figure 23 in the Timer/Counters section.

R/W; CARRY

R/W; COMPLEX CARRY

R/W; BYTE ORDER BIT

RESETS TO 0. MODES:

1 = ADDRESSING MODE 1

0 = ADDRESSING MODE 0

R/W; BOOT

DRIVES OUTPUT SIGNAL

TO SELECT BOOT ROM;

,

: The Timer Preload Registers are

TP0 TP1 TP2

WRITE - ONLY (READS AS 0);

SET INTERRUPT DISABLE;

0 = INT. ENABLED;

write-only registers which contain the initial 16-bit count

values which are written to each timer. After a timer counts

down to zero, the preload register for that timer reloads its

initial count value to that timer register at the next rising clock

edge, synchronously with TCLK. Writing to these registers

causes the count to be loaded into the corresponding Timer/

Counter register on the following cycle.

1 = INT. DISABLED

RESERVED (NOTE)

NMI MODE

1 = RETURN FROM NMI POSSIBLE

0 = NO RETURN FROM NMI

(RTX 2000 MODE)

RESERVED (NOTE)

ARCE; ASIC READ CYCLE EXTEND

WHEN SET EXTENDS CYCLE ON

EXTERNAL ASIC READS

Multiplier-Accumulator (MAC) Registers:

: The Multiplier High Product Register holds the most

MHR

signiﬁcant 16 bits of the 32-bit product generated by the RTX

Multiplier. If the register’s ROUND bit is set, this

READ ONLY; INTERRUPT

DISABLE STATUS

READ ONLY;

INTERRUPT LATCH

IBC

register contains the rounded 16-bit output of the multiplier.

In the Accumulator context, this register holds the middle 16

bits of the MAC.

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

FIGURE 11. BIT ASSIGNMENTS

CR

: The Program Counter Register contains the address

PC

of the next instruction to be fetched from Main Memory. At

RESET, the contents of are set to 0.

: The Multiplier Lower Product Register holds the least

MLR

signiﬁcant 16 bits of the 32-bit product generated by the RTX

Multiplier. It is also the register which holds the least

signiﬁcant 16 bits of the MAC Accumulator.

PC

: The Index Register contains 16 bits of the 21-bit top

I

element of the Return Stack, and is also used to hold the

count for streamed and loop instructions (see Figure 19). In

: The MAC Extension Register holds the most significant

MXR

16 bits of the MAC Accumulator. When using the Barrel Shifter,

this register holds the shift count. When using the Leading Zero

Detector, the leading zero count is stored in this register.

addition,

from

can be used to hold data and can be written

. The contents of may be accessed in

I

TOP

I

either the push/pop mode in which values are moved to/from

stack memory as required, or in the read/write mode in

which the stack memory is not affected. The ASIC address

Interrupt Controller Registers

: The Interrupt Vector Register is a read-only register

IVR

which holds the current Interrupt Vector value. See Figure 12

and Table 4.

used for

determines what type of operation will be

I

performed (see Table 5). When the Streamed Instruction

Mode (see RTX Programmer’s Reference Manual) is used, a

IBC BIT 15

IBC BIT 14

count is written to

and the next instruction is executed

I

IBC

BIT 13

BIT 12

BIT 11

that number of times plus one (i.e., count + 1).

: The Multi-Step Divide Register holds the divisor

MD

during Step Divide operations, while the 32-bit dividend is in

and may also be used as a general

IBC BIT 10

VECTOR ADDRESS

(SEE TABLE 1)

.

EXT MD

TOP

purpose scratch pad register.

ALL ZEROS

: The Square Root Register holds the intermediate

SR

values used during Step Square Root calculations.

15 14 13 12 1110 9

8

7

6

5

4

3

2

I1BC0

IVR

SR

may also be used as a general purpose scratch pad register.

MA15-MA00

FIGURE 12.

On-Chip Peripheral Registers

BIT ASSIGNMENTS

IVR

The HS-RTX2010RH has an on-chip Interrupt Controller, a

Memory Page Controller, two Stack Controllers, three

Timer/Counters, a Multiplier-Accumulator, a Barrel Shifter,

and a Leading Zero Detector. Each of these peripherals

utilizes on-chip registers to perform its functions.

: The Interrupt Base/Control Register is used to store

IBC

the Interrupt Vector base address and to specify

conﬁguration information for the processor, as indicated by

the bit assignments in Figure 13.

12

HS-RTX2010RH

PARAMETER STACK

FATAL ERROR

RETURN STACK FATAL ERROR

IMR

15141312 1110 9 8 7 6 5 4 3 2 1 0

RESERVED (NOTE)

SUR

SVR

EI1

(EXTERNAL INPUT PIN)

IBC

PSU, PARAMETER STACK

UNDERFLOW

151413 12 1110 9

8 7 6 5 4 3 2 1 0

RSU, RETURN STACK

UNDERFLOW

READ-ONLY; FATAL

STACK ERROR FLAG

PSV, PARAMETER STACK

OVERFLOW

RSV, RETURN STACK

OVERFLOW

EI2

TCI 0

TCI 1

TCI 2

READ-ONLY; PARAMETER

STACK UNDERFLOW FLAG

READ-ONLY; RETURN

STACK UNDERFLOW FLAG

EI3

EI4

EI5

READ-ONLY; PARAMETER

STACK OVERFLOW FLAG

SWI

READ-ONLY; RETURN

STACK OVERFLOW FLAG

RESERVED (NOTE)

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

FIGURE 14. BIT ASSIGNMENTS

DPRSEL: SELECTS

PAGE REGISTER FOR

DATA MEMORY ACCESS

= 1: SELECT DPR

IMR

Stack Controller Registers

= 0: SELECT CPR

: The Stack Pointer Register holds the stack pointer

SPR

value for each stack. Bits 0-7 represent the next available

stack memory location for the Parameter Stack, while bits 8-

15 represent the next available stack memory location for the

Return Stack. These stack pointer values must be accessed

ROUND: MULTIPLIER

CONTROL BIT; SELECTS

ROUNDING OF 16 x 16

BIT MULTIPLICATION

= 1: ROUNDED 16-BIT

PRODUCT

= 0: UNROUNDED

together, as

. See Figure 15.

SPR

32-BIT PRODUCT

: The Stack Overﬂow Limit Register is a write-only

SVR

CYCEXT: ALLOWS

EXTENDED CYCLE LENGTH

FOR USER MEMORY

INSTRUCTION CYCLES; SEE

CLOCK AND WAIT

register which holds the overﬂow limit values (0 to 255) for

the Parameter Stack (bits 0-7) and the Return Stack (bits

8-15). These values must be written together. See Figure 16.

TIMING DIAGRAMS

: The Stack Underﬂow Limit Register holds the

SELECT TIMER/COUNTER

INPUT SIGNALS: TCLK

OR EI5 - EI3 (TABLE 6)

SUR

underﬂow limit values for the Parameter Stack and the

Return Stack. In addition, this register is utilized to deﬁne the

use of substacks for both stacks. These values must be

accessed together. See Figure 17.

FIGURE 13.

BIT ASSIGNMENTS

IBC

: The Interrupt Mask Register has a bit assigned for

IMR

each maskable interrupt which can occur. When a bit is set,

the interrupt corresponding to that bit will be masked. Only

the Non-Maskable Interrupt (NMI) cannot be masked. See

Figure 14 for bit assignments for this register.

SPR

15141312 1110 9 8 7 6 5 4 3 2 1 0

PSP, PARAMETER STACK

POINTER

RSP, RETURN STACK

POINTER

FIGURE 15.

SVR

BIT ASSIGNMENTS

SPR

15 14 1312 1110 9 8 7 6 5 4 3 2 1 0

PVL: PARAMETER

STACK OVERFLOW LIMIT.

NUMBER OF WORDS FROM

TOP OF CURRENT SUBSTACK

RVL: RETURN STACK

OVERFLOW LIMIT.

NUMBER OF WORDS FROM

TOP OF CURRENT SUBSTACK

FIGURE 16.

BIT ASSIGNMENTS

SVR

13

HS-RTX2010RH

BIT ASSIGNMENTS DURING SUBROUTINE OPERATIONS

IPR

20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0

SUR

I

15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0

8

PSF: PARAMETER STACK

START FLAG

PARAMETER SUBSTACK BITS:

= 00: EIGHT 32 WORD STACKS

= 01: FOUR 64 WORD STACKS

= 10: TWO 128 WORD STACKS

= 11: ONE 256 WORD STACK

TYPE OF RETURN

= 1: INTERRUPT RETURNS:

= 0: SUBROUTINE RETURNS:

DEFINES RETURN ADDRESS

PSU: PARAMETER

WHERE DPRSEL BIT IS

STORED DURING INTERRUPT

OR SUBROUTINE CALL

STACK UNDERFLOW LIMIT

0 - 31 WORDS FROM

BOTTOM OF SUBSTACK

BIT ASSIGNMENTS DURING NON-SUBROUTINE OPERATIONS

RSF: RETURN STACK

START FLAG

I

IPR

RETURN SUBSTACK BITS:

= 00: EIGHT 32 WORD STACKS

= 01: FOUR 64 WORD STACKS

= 10: TWO 128 WORD STACKS

= 11: ONE 256 WORD STACK

20 19 18 17 16 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1 0

USED FOR TEMPORARY

STORAGE OF VARIABLES,

LOOP COUNTS, AND

STREAM COUNTS

RSU: RETURN STACK

UNDERFLOW LIMIT

0 - 31 WORDS FROM

BOTTOM OF SUBSTACK

CURRENT CODE

PAGE VALUE

FIGURE 17.

BIT ASSIGNMENTS

SUR

FIGURE 19.

AND

BIT ASSIGNMENTS

I

IPR

Memory Page Controller Registers

DPR

: The Code Page Register contains the value for the

CPR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1 0

current 32K-word Code page. See Figure 18 for bit ﬁeld

assignments.

RESERVED

(NOTE)

MA19

MA18

MA17

MA16

CPR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1 0

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

RESERVED

(NOTE)

FIGURE 20.

BIT ASSIGNMENTS

DPR

MA19

MA18

MA17

MA16

USER PAGE

REGISTER

UPR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1 0

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

FIGURE 18. BIT ASSIGNMENTS

RESERVED

(NOTE)

CPR

MA19

MA18

MA17

MA16

: The Index Page Register extends the Index Register

IPR

(

) by 5 bits; i.e., when a Subroutine Return is performed,

I

USER BASE

ADDRESS

REGISTER

the

contains the Code page from which the subroutine

UBR

IPR

was called, and comprises the 5 most signiﬁcant bits of the

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1 0

top element of the Return Stack. See Figure 19. During

MA15 - MA06

nonsubroutine operation, writing to

causes the current

. Reading or writing

I

Code page value to be written to

IPR

MA05

MA04

MA03

MA02

MA01

directly to

does not push the Return Stack.

IPR

: The Data Page Register contains the value for the

DPR

current 32K-word Data page. See Figure 20 for bit ﬁeld

assignments.

: The User Page Register contains the value for the

UPR

current User page. See Figure 21 for bit ﬁeld assignments.

NOT USED TO GENERATE

THIS ADDRESS

: The User Base Address Register contains the base

address for User Memory Instructions. See Figure 21 for bit

ﬁeld assignments.

UBR

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1 0

INSTRUCTION

REGISTER

I R

NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.

FIGURE 21. AND BIT ASSIGNMENTS

UPR

UBR

14

HS-RTX2010RH

are cleared and execution begins at page 0, word 0

when the processor is reset.

CPR

Initialization of Registers

Initialization of the on-chip registers occurs when a HIGH

level on the RTX RESET pin is held for a period of greater

than or equal to four rising edges of ICLK plus 1/2 ICLK

cycle setup and hold times. While the RESET input is HIGH,

the TCLK and PCLK clock outputs are held reset in the LOW

state.

The RESET has a Schmitt trigger input, which allows the

use of a simple RC network for generation of a power-on

RESET signal. This helps to minimize the circuit board

space required for the RESET circuit.

To ensure reliable operation even in noisy embedded control

environments, the RESET input is ﬁltered to prevent a reset

caused by a glitch of less than four ICLK cycles duration.

Table 1 shows initialization values and ASIC addresses for

the on-chip registers. As indicated, both the

and the

PC

TABLE 1. REGISTER INITIALIZATION AND ASIC ADDRESS ASSIGNMENTS

INITIALIZED

HEX

REGISTER

ADDR

CONTENTS

DESCRIPTION/COMMENTS

0000 0000 0000 0000 Top Register

1111 1111 1111 1111 Next Register

0000 0000 0000 0000 Instruction Register

TOP

00H 01H 1111 1111 1111 1111 Index Register

02H

I

03H

04H

06H

07H

08H

09H

0AH

0BH

0100 0000 0000 1000 Configuration Register: Boot = 1; Interrupts Disabled; Byte Order = 0.

1111 1111 1111 1111 Multi-Step Divide Register

CR

MD

SR

0000 0010 0000 0000 Square Root Register

0000 0000 0000 0000 Program Counter Register

PC

0000 0000 0000 0000 Interrupt Mask Register

IMR

SPR

0000 0000 0000 0000 Stack Pointer Register: The beginning address for each stack is set to a value of ‘0’.

0000 0111 0000 0111 Stack Underflow Limit Register

SUR

IVR

0000 0010 0000 0000 Interrupt Vector Register: Read only; this register holds the current Interrupt Vector

value, and is initialized to the “No Interrupt” value.

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

1111 1111 1111 1111 Stack Overflow Limit Register: Write-only; Each stack limit is set to its maximum value.

0000 0000 0000 0000 Index Page Register

SVR

IPR

0000 0000 0000 0000 Data Page Register: The Data Address Page is set for page ‘0’.

0000 0000 0000 0000 User Page Register: The User Address Page is set for page ‘0’.

0000 0000 0000 0000 Code Page Register: The Code Address Page is set for page ‘0’.

0000 0000 0000 0000 Interrupt Base/Control Register

DPR

UPR

CPR

IBC

0000 0000 0000 0000 User Base Address Register: The User base address is set to ‘0’ within the User page.

0000 0000 0000 0000 MAC Extension Register

UBR

MXR

/

0000 0000 0000 0000 Timer/Counter Register 0: Set to time out after 65536 clock periods or events.

0000 0000 0000 0000 Timer/Counter Register 1: Set to time out after 65536 clock periods or events.

0000 0000 0000 0000 Timer/Counter Register 2: Set to time out after 65536 clock periods or events.

0000 0000 0000 0000 Multiplier Lower Product Register

TC0

TC1

TC2

TP0

TP1

TP2

MLR

MHR

0000 0000 0000 0000 Multiplier High Product Register

15

HS-RTX2010RH

HS-RTX2010RH Stack Controllers

Dual Stack Architecture

The two stacks of the HS-RTX2010RH are controlled by

identical Programmable Stack Controllers.

The HS-RTX2010RH features a dual stack architecture. The

two 256-word stacks are the Parameter Stack and the

Return Stack, both of which may be accessed in parallel by a

single instruction, and which minimize overhead in passing

parameters between subroutines. The functional structure of

each of these stacks is shown in Figure 22.

The operation of the Programmable Stack Controllers

depends on the contents of three registers. These registers

are

, the Stack Pointer Register,

, the Stack

SPR

Overﬂow Limit Register, and

SVR

, the Stack Underﬂow

SUR

Limit Register (see Figures 15, 16, and 17).

The Parameter Stack is used for temporary storage of data

and for passing parameters between subroutines. The top two

contains the address of the next stack memory

SPR

location to be accessed in a stack push (write) operation.

After a push, the is incremented (post-increment

elements of this stack are contained in the

and

registers of the processor, and the remainder of this stack is

located in stack memory. The stack memory assigned to the

Parameter Stack is 256 words deep by 16 bits wide.

SPR

operation). In a stack pop (read) operation, the stack

memory location with an address one less than the

SPR

will be accessed, and then the

(pre-decrement operation). At start-up, the ﬁrst stack

location to have data pushed into it is location zero.

will be decremented

SPR

The Return Stack is used for storing return addresses when

performing Subroutine Calls, or for storing values temporarily.

Because the HS-RTX2010RH uses a separate Return Stack, it

can call and return from subroutines and interrupts with a

minimum of overhead. The Return Stack is 21 bits wide. The

Upper and lower limit values for the stacks are set into the

Stack Overﬂow Limit Register and in the Stack Underﬂow

Limit Register. These values allow interrupts to be generated

prior to the occurrence of stack overﬂow or underﬂow error

conditions (see section on Stack Error Conditions for more

detail). Since the HS-RTX2010RH can take up to four clock

cycles to respond to an interrupt, the values set in these

registers should include a safety margin which allows valid

stack operation until the processor executes the interrupt

service routine.

16-bit Index Register,

, and the 5-bit Index Page Register,

I

, hold the top element of this stack, while the remaining

IPR

elements are located in stack memory. The stack memory

portion of the Return Stack is 21 bits wide, by 256 words deep.

The data on the Return Stack takes on different meaning,

depending upon whether the Return Stack is being used for

temporary storage of data or to hold a return address during

a subroutine operation (Figure 19).

SPR

15 141312 1110 9 8

7

6

5 4

3

2

1 0

SUR

15 141312 1110 9 8 7 6 5 4

PARAMETER STACK

TOP

RETURN STACK

I

15141312 1110 9 8 7 6 5 4 3 2 1 0

IPR

20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0

PSU

RSU

PSP

RSP

STACK MEMORY

(ON-CHIP)

STACK MEMORY

(ON-CHIP)

RVL

PVL

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

SVR

FIGURE 22. DUAL STACK ARCHITECTURE

16

HS-RTX2010RH

read but not written to. All stack error ﬂags are cleared

whenever a new value is written to

Substacks

.

SPR

Each 256-word stack may be subdivided into up to eight 32

word substacks, four 64 word substacks, or two 128 word

substacks. This is accomplished under hardware control for

simpliﬁed management of multiple tasks. Stack size is

selected by writing to bits 1 and 2 of the

SUR

Parameter Stack, and bits 9 and 10 for the Return Stack.

Fatal Stack Error: Each stack can also experience a fatal

stack error. This error condition occurs when an attempt is

made to push data onto or to pop data off of the highest

location of the substack. It does not generate an interrupt

(since the normal stack limits can be used to generate the

interrupt). The fatal errors for the stacks are logically OR’ed

together to produce bit 0 of the Interrupt Base Control

for the

Substacks are implemented by making bits 5-7 of the

(for the Parameter Stack) and bits 13-15 of the

Return Stack) control bits. For example, if there were eight

32 word substacks implemented in the Parameter Stack, bits

SPR

(for the

SPR

Register, and they are cleared whenever

is written to.

SPR

The implication of a fatal error is that data on the stack may

have been corrupted or that invalid data may have been read

from the stack.

5-7 of the

are not incremented, but instead are used

SPR

as an offset pointer into the Parameter Stack to indicate the

beginning point (i.e., sub stack number) of each 32 word

substack implemented. Because of this, a particular

substack is selected by writing a value which contains both

the stack pointer value and the substack number to the

HS-RTX2010RH Timer/Counters

The HS-RTX2010RH has three 16-bit timers, each of which

can be conﬁgured to perform timing or event counting. All

decrement synchronously with the rising edge of TCLK.

Timer registers are readable in a single machine cycle.

.

SPR

Each stack has a Stack Start Flag (PSF and RSF) which

may be used for implementing virtual stacks. For the

The timer selection bits of the

determine whether a

IBC

timer is to be conﬁgured for external event counting or

internal time-base timing. This conﬁgures the respective

counter clock inputs to the on-chip TCLK signal for internal

timing, or to the EI5 - EI3 input pins for external signal event

counting. EI5, EI4, and EI3 are synchronized internally with

Parameter Stack, the Start Flag is bit zero of the

, and

SUR

for the Return Stack it is bit eight. If the Stack Start Flag is

one, the stack starts at the bottom of the stack or substack

(location 0). If the Stack Start Flag is zero, the substack

starts in the middle of the stack. An exception to this occurs

TCLK. See Table 3 for Timer/Clock selection by

values.

bit

if the overﬂow limit in

is set for a location below the

IBC

SVR

middle of the stack. In this case, the stacks always start at

the bottom locations. See Table 2 for the possible stack

conﬁgurations. Manipulating the Stack Start Flag provides a

mechanism for creating a virtual stack in memory which is

maintained by interrupt driven handlers.

The timers (

,

and

) are all free-running,

TC2

TC0 TC1

and when they time out, they reload automatically with the

programmed initial value from their respective Timer Pre

load Registers (

→

,

→

, and

TC1 TP2

TPO

TC0 TP1

→

), then continue timing or counting.

Possible applications for substacks include use as a

recirculating buffer (to allow quick access for a series of

repeated values such as coefﬁcients for polynomial

evaluation or a digital ﬁlter), or to log a continuous stream of

data until a triggering event (for analysis of data before and

after the trigger without having to store all of the incoming

data). The latter application could be used in a digital

oscilloscope or logic analyzer.

TC2

Each timer provides an output to the Interrupt Controller to

indicate when a time-out for the timer has occurred.

The HS-RTX2010RH can determine the state of a timer at

any time either by reading the timer’s value, or upon a time-

out by using the timer’s interrupt (see the Interrupt Controller

section for more information about how timer interrupts are

handled). Figure 23 shows the sequence of Timer/Counter

operations.

Stack Error Conditions

Stack errors include overﬂow, underﬂow, and fatal errors.

Overﬂows occur when an attempt is made to push data onto

a full stack. Since the stacks wrap around, the result is that

existing data on the stack will be overwritten by the new data

when an overﬂow occurs. Underﬂows occur when an attempt

is made to pop data off an empty stack, causing invalid data

to be read from the stack. In both cases, a buffer zone may

be set up by initializing

and

so that stack error

SUR

SVR

interrupts are generated prior to an actual overﬂow or

underﬂow. The limits may be determined from the contents

of

and

using Table 2. The state of all stack

SUR

SVR

errors may be determined by examining the ﬁve least

signiﬁcant bits of

, where the stack error ﬂags may be

IBC

17

HS-RTX2010RH

TCLK

RISING

EDGE

TCLK

RISING

EDGE

INTA CYCLE OR

ASIC READ COMMAND

TOP

REGISTER

PRELOAD

REGISTER

ACTIVATE

TIMEOUT

INTERRUPT

LOAD TC0

EXECUTE

COUNT

INTERRUPT

RESET

TIMER/COUNTER

TP0

PRELOAD

REGISTER

ACTIVATE

TIMEOUT

INTERRUPT

CONTROLLER

LOAD TC1

EXECUTE

COUNT

INTERRUPT

RESET

TIMER/COUNTER

TP1

PRELOAD

REGISTER

ACTIVATE

TIMEOUT

INTERRUPT

RESET

EXECUTE

COUNT

LOAD TC2

TIMER/COUNTER

TP2

FIGURE 23. HS-RTX2010RH TIMER/COUNTER OPERATION

TABLE 3. TIMER/COUNTER

BIT VALUES

TIMER CLOCK SOURCE

IBC

BIT 09

BIT 08

TC2

TCLK

EI5

TC1

TCLK

EI4

TC0

TCLK

EI3

0

1

0

1

0

1

EI3

EI4

EI3

processor performs a special Subroutine Call to the address

in Memory Page 0 contained in the vector. This special

subroutine call is different in that it saves a status bit on the

Return Stack indicating the call was caused by an interrupt.

Thus, when the Interrupt Handler executes a Subroutine

Return, the processor knows to automatically re-enable

interrupts. Before the Interrupt Handler returns, it must

ensure that the condition that caused the interrupt is cleared.

Otherwise the processor will again be interrupted

immediately upon its return.

HS-RTX2010RH Interrupt Controller

The HS-RTX2010RH Interrupt Controller manages interrupts

for the HS-RTX2010RH Microcontroller core. Its sources

include two on-chip peripherals and six external interrupt

inputs. The two classes of on-chip peripherals that produce

interrupts are the Stack Controllers and the Timer/Counters.

Interrupt Controller Operation

When one of the interrupt sources requests an interrupt, the

Interrupt Controller checks whether the interrupt is masked

in the Interrupt Mask Register. If it is not, the controller

attempts to interrupt the processor. If processor interrupts

are enabled (bit 4 of the Conﬁguration Register), the

processor will execute an Interrupt Acknowledge cycle,

during which it disables interrupts to ensure proper

completion of the INTA cycle.

Processor interrupts are enabled and disabled by clearing

and setting the Interrupt Disable Flag. When the RTX is

reset, this ﬂag is set (bit 04 of the

= 1), disabling the

CR

interrupts. This bit is a write-only bit that always reads as 0,

allowing interrupts to be enabled in only 2 cycles with a

simple read/write operation in which the processor reads the

bit value, then writes it back to the same location. The actual

status of the Interrupt Disable Flag can be read from bit 14

In response to the Interrupt Acknowledge cycle, the Interrupt

Controller places an Interrupt Vector on the internal ASIC

Bus, based on the highest priority pending interrupt. The

of

.

CR

21

HS-RTX2010RH

TABLE 4. INTERRUPT SOURCES, PRIORITIES AND VECTORS

VECTOR ADDRESS BITS

PRIORITY

INTERRUPT SOURCE

Non-Maskable Interrupt

External Interrupt 1

Parameter Stack Underflow

Return Stack Underflow

Parameter Stack Overflow

Return Stack Overflow

External Interrupt 2

Timer/Counter 0

SENSITIVITY

Pos Edge

High Level

Edge

BIT

09

0

1

08

1

0

07

1

0

1

0

06

1

0

1

0

1

0

1

0

05

1

0

1

0

1

0

1

0

1

0

1

0

1

0

IMR

0 (High)

NMI

EI1

N/A

1

01

02

03

04

05

06

07

08

09

10

11

12

13

N/A

2

PSU

RSU

PSV

RSV

EI2

3

4

5

6

7

TCI0

TCI1

TCI2

EI3

8

9

Timer/Counter 1

Edge

Timer/Counter 2

Edge

10

External Interrupt 3

External Interrupt 4

External Interrupt 5

Software Interrupt

High Level

N/A

11

EI4

12

EI5

13 (Low)

N/A

SWI

None

No Interrupt

During read and write operations to the Conﬁguration

Register, ( ), interrupts are inhibited to allow the program

Acknowledge cycle, the entry point to the Interrupt Handlers

must reside on Memory Page zero.

CR

to save and restore the state of the Interrupt Enable bit.

Because address bits MA04-MA01 are always zero in an

Interrupt Acknowledge cycle, Interrupt Vectors are 32 bytes

apart. This means that Interrupt Handler routines that are 32

bytes or less can be compiled directly into the Interrupt

Table. Interrupt Handlers greater than 32 bytes must be

compiled separately and called from the Interrupt Table.

In addition to disabling interrupts at the processor level, all

interrupts except the Non-Maskable Interrupt (NMI) can be

individually masked by the Interrupt Controller by setting the

appropriate bit in the Interrupt Mask Register (

).

IMR

Resetting the HS-RTX2010RH causes all bits in the

be cleared, thereby unmasking all interrupts.

to

IMR

The rest of the vector is generated as indicated in Table 1. To

guarantee that the Interrupt Vector will be stable during an

INTA cycle, the Interrupt Controller inhibits the generation of a

new Interrupt Vector while INTA is high, and will not begin

generating a new Interrupt Vector on either edge of INTA.

The NMI on the HS-RTX2010RH has two modes of operation

which are controlled by the NMI_MODE Flag (bit 11 of the

). When this bit is cleared (0), the NMI can not be

CR

masked, and can interrupt any cycle. This allows a fast

response to the NMI, but may not allow a return from interrupt

to operate correctly. NMI_MODE is cleared when the

processor is Reset. When NMI_MODE is set (1), a return

from the NMI service routine will result in the processor

continuing execution in the state it was in when it was

interrupted. When in this second mode NMI may be inhibited

by the processor during certain critical operations (see

Interrupt Suppression), and may, therefore, not be serviced as

quickly as in the first mode of operation. When servicing an

NMI_MODE set to 1, further NMIs and maskable interrupts

are disabled until the NMI Interrupt Service Routine has

completed, and a return from interrupt has been executed.

The Interrupt Vector can also be read from the Interrupt

Vector Register (

) directly. This allows interrupt

IVR

requests to be monitored by software, even if they are

disabled by the processor. If no interrupts are being

requested, bit 09 of the

will be 1.

IVR

External interrupts EI5-EI1 are active HIGH level-sensitive

inputs. (Note: When used as Timer/Counter inputs, EI5-EI3

are edge sensitive). Therefore, the Interrupt Handlers for

these interrupts must clear the source of interrupt prior to

returning to the interrupted code. The external NMI,

however, is an edge-sensitive input which requires a rising

edge to request an interrupt. The NMI input also has a glitch

filter circuit which requires that the signal that initiates the NMI

must last at least two rising and two falling edges of ICLK.

The Interrupt Controller prioritizes interrupt requests and

generates an Interrupt Vector for the highest priority interrupt

request. The address that the vector points to is determined

by the source of the interrupt and the contents of the

Finally, a mechanism is provided by which an interrupt can

be requested by using a software command. The Software

Interrupt (SWI) is requested by executing an instruction that

will set an internal ﬂip-ﬂop attached to one input of the

Interrupt Base/Control Register (

). See Figure 12 for

IBC

the Interrupt Vector Register bit assignments. Because

address bits MA19-MA16 are always zero in an Interrupt

22

HS-RTX2010RH

Interrupt Controller. The SWI is reset by executing an

instruction that clears the ﬂip-ﬂop. The ﬂip-ﬂop is accessed

by I/O Reads and Writes.

Stack Architecture” for more information regarding how the

limits set into and are used.

IBC

Stack Overﬂow: A stack overﬂow occurs when data is

pushed onto the stack location pointed to by the

SUR

Because the SWI interrupt may not be serviced immediately,

the instructions which immediately follow the SWI instruction

should not depend on whether or not the interrupt has been

serviced, and should cause a one or two-cycle idle condition

(Typically, this is done with one or two NOP instructions).

, as

SVR

determined in Table 5. After the processor is reset, this is

location 255 in either the Parameter Stack or Return Stack.

A stack overﬂow interrupt request stays in effect until cleared

by writing a new value to the

. In addition to generating

SPR

an interrupt, the state of the stack overﬂow ﬂags may be

read out of the , bit 3 for the Parameter Stack, and bit

If an interrupt condition occurs, but “goes away” before the

processor has a chance to service it, a “No Interrupt” vector is

generated. A “No Interrupt” vector is also generated if an

Interrupt Acknowledge cycle takes less than two cycles to

execute and no other interrupt conditions need to be serviced.

IBC

4 for the Return stack. See Figures 13, 15 and 16.

Stack Underﬂow: The stack underﬂow limit occurs when

data is popped off the stack location immediately below that

pointed to by the

, as determined in Table 2. The state

SUR

of the stack underﬂow error ﬂags may be read out of bits 1

and 2 of the for the Parameter and Return stacks

To prevent unforeseen errors, it is recommended that valid

code be supplied at every Interrupt Vector location, including

the “No Interrupt” vector, which should always be initialized

with valid code.

IBC

respectively. In the reset state of the

be generated at the same time that a fatal error is detected.

An underﬂow buffer region can be set up by selecting an

underﬂow limit greater than zero by writing the

, an underﬂow will

SUR

It is recommended that Interrupt Handlers save and restore

the contents of

.

CR

corresponding value into the

. The stack underﬂow

SUR

interrupt request stays in effect until a new value is written

into the , at which time it is cleared.

Interrupt Suppression

The HS-RTX2010RH allows maskable interrupts and Mode

1 NMIs (the NMI_MODE Flag in bit 11 of the

SPR

is set) to

CR

Timer/Counter Interrupts

be suppressed, delaying them temporarily while critical

operations are in progress. Critical operations are instruction

sequences and hardware operations that, if interrupted,

would result in the loss of data or misoperation of the

hardware. (Note: Only the processor may suppress NMIs.)

The timers generate edge-sensitive interrupts whenever they

are decremented to 0. Because they are edge-sensitive and

are cleared during an Interrupt Acknowledge cycle or during

the direct reading of

by software, no action is required

IVR

by the handlers to clear the interrupt request.

Standard critical operations during which interrupts are

automatically suppressed by the processor include Streamed

The HS-RTX2010RH ALU

The HS-RTX2010RH has a 16-bit ALU capable of

performing standard arithmetic and logic operations:

instructions (see the description of the

register), Long Call

I

sequences (see “Subroutine Calls and Returns”), and loading

. In addition to this, external devices can also suppress

CR

maskable interrupts during critical operations by applying a

HIGH level on the INTSUP pin for as long as required.

• ADD and SUBTRACT (A-B and B-A; with and without

carry)

Since the Mode 0 NMI (the NMI_MODE Flag in bit 11 of the

• AND, OR, XOR, NOR, NAND, XNOR, NOT

is cleared) can cause the processor to perform an

CR

The

and

registers can also undergo single bit

Interrupt Acknowledge Cycle in the middle of these critical

operations, thereby preventing a normal return to the

interrupted instruction, a Subroutine Return should be used

with care from a Mode 0 NMI service routine. The Mode 0

NMI should be used only to indicate critical system errors,

and the Mode 0 NMI handler should re-initialize the system.

shifts in the same cycle as a logic or arithmetic operation.

In Figure 24, the control and data paths to the ALU are

shown. Except for

core registers can be addressed explicitly, as can other

internal registers in special operations such as in Step

instructions. In each of these cases, the input would be

addressed as a device on the ASIC Bus.

and

, each of the internal

Interrupts which have occurred while interrupt suppression is

in effect will be recognized on a priority basis as soon as the

suppression terminates, provided the condition which

generated the interrupt still exists.

When executing these instructions, the arithmetic/logic

operand (a) starts out in

and is placed on the T-bus.

TOP

Operand (b) arrives at the ALU on the Y-bus, but can come

from one of the following four sources: ; an internal

Stack Error Interrupts

bits of . The source of operand (b) is determined by

The Stack Controllers request an interrupt whenever a stack

overﬂow or underﬂow condition exists. These interrupts can

IR

be cleared by rewriting

. See the section on “Dual

SPR

the instruction code in

operation is placed into

. The result of the ALU

IR

.

TOP

23

HS-RTX2010RH

PROGRAM

MEMORY

TOP

T-BUS

5 LEAST

SIGNIFICANT

BITS

I R

ASIC BUS

DEVICE

INTERNAL

REGISTERS

SELECT

OPERAND

(A)

OPERAND (B)

Y

T

ALU

CONTROL

ALU

SHIFTER

NOTE: Data Paths are represented by solid lines; Control Paths are represented by dashed lines.

FIGURE 24. ALU OPERATIONS-CONTROL PATHS AND DATA FLOW

Step Arithmetic instructions which are performed through the

ALU are divide and square root. Execution of each step of the

arithmetic operation takes one cycle, a 32/16-bit Step Divide

takes 21 cycles, and a 32/16-bit Step Square Root takes 25

cycles. Sign and scaling functions are controlled by the ALU

function and shift options, which are part of the coded

place to the left (2*

). When the subtraction is

MD

is OR’ed into

performed,

, and is shifted

SR

one place to the right. At the end of the operation, the square

root of the original value is in and , and the

MD

.

TOP

HS-RTX2010RH Floating Point/DSP On

Chip Peripherals

instruction contained in

and the Programmer’s Reference Manual for details.

. See Table 20 and Table 21

IR

Unsigned Step Divide operation assumes a double precision

(32-bit) dividend, with the most signiﬁcant word placed in

The HS-RTX2010RH Multiplier-Accumulator

The Hardware Multiplier-Accumulator (MAC) on the

HS-RTX2010RH functions as both a Multiplier, and a

Multiplier- Accumulator. When used as a Multiplier alone, it

multiplies two 16-bit numbers, yielding a 32-bit product in

one clock cycle. When used as a Multiplier-Accumulator, it

multiplies two 16-bit numbers, yielding an intermediate 32-bit

product, which is then added to the 48-bit Accumulator. This

entire process takes place in a single clock cycle.

, the less signiﬁcant word in

, and the divisor in

are equal to or

TOP

(and therefore no borrow

TOP

MD

greater than the contents in

MD

is generated), then the contents of

are subtracted

MD

. The result of the subtraction is

from the contents of

placed into

TOP

. The contents of

and are

then jointly shifted left one bit (32-bit left shift), where the

value shifted into the least signiﬁcant bit of is the value

TOP

Read and Write instructions to ASIC Bus addresses

assigned to the MAC.

of the Borrow bit on the ﬁrst pass, or the value of the

Complex Carry bit on each of the subsequent passes. On

the 15th and ﬁnal pass, only

is shifted left, receiving

is not

TOP

, and the

The MAC’s input operands come from three possible

sources (see Figure 25):

shifted. The ﬁnal result leaves the quotient in

EXT

remainder in

.

TOP

During a Step Square Root operation, the 32-bit argument is

assumed to be in and , as in the Step Divide

1. The

and

registers.

EXT

TOP

2. The Parameter (Data) Stack and memory via

Manual).

operation. The ﬁrst step begins with

containing zeros.

MD

The Step Square Root is performed much like the Step

Divide, except that the input from the Y-bus is the logical OR

3. Memory via

and an input from the ASIC Bus

EXT

(Streamed mode only - see the Programmer’s Reference

Manual).

of the contents of

and the value in

shifted one

MD

SR

24

HS-RTX2010RH

DATA STACK

ASIC BUS

REGISTER

TOP

5

MAC

16 x 16

32-BIT BRL SHIFTER

32

48

16

MXR

MHR

MLR

FIGURE 25. HS-RTX2010RH FLOATING POINT/DSP LOGIC

These inputs can be treated as either signed (two’s

1. If the most signiﬁcant bit of the

is set (1), the

MHR

MLR

is incremented.

complement) or unsigned integers, depending on the form of

the instruction used. In addition, if the ROUND option is

selected, the Multiplier can round the result to 16 bits. Note

that the MAC instructions do not pop the Parameter Stack;

2. If the most signiﬁcant bit of the

is not set (0), the

is left unchanged.

MHR

The ROUND bit functions independently of whether the

signed or unsigned bit is used.

the contents of

and

remain intact.

For the Multiplier, the product is read from the Multiplier High

Product Register, , which contains the upper 16 bits of

The multiply instructions suppress interrupts during the

MHR

multiplication cycle. Reading

, or

also

MLR

MHR

the product, and the Multiplier Low Product Register,

which contains the lower 16 bits. For the Multiplier-

,

MLR

suppresses interrupts during the read. This allows a

multiplication operation to be performed, and both the upper

and lower registers to be read sequentially, with no danger of

a non-NMI interrupt service routine corrupting the contents

of the registers between reads. The multiply-accumulate

instructions do not suppress interrupts during instruction

execution.

Accumulator, the accumulated product is read from the

Multiplier Extension Register, , which contains the

MXR

, which contains the middle 16 bits,

upper 16 bits, the

MHR

, which contains the low 16 bits. The registers

and the

MLR

may be read in any order, and there is no requirement that

all registers be read. Reading from any of the three registers

For additional information on the HS-RTX2010RH MAC see

the Programmer’s Reference Manual.

moves its value into

, and pushes the original value in

TOP

. If the read is from

into

or , the

MLR

TOP

memory. This permits overwriting the original operands left

in and , which are not popped by the MAC

MHR

original value of

is lost, i.e. it is not pushed onto stack

The HS-RTX2010RH On-Chip Barrel Shifter And

Leading Zero Detector

TOP

32-bit Leading Zero Detector for added ﬂoating-point and

DSP performance. The inputs to the Barrel Shifter and

Leading Zero Detector are the top two elements of the

operations. If the read is from

, the original value of

MXR

is pushed onto the stack. In addition to this, any of the

. This

TOP

and the Parameter Stack into .

into

rounded to 16 bits. This is accomplished by setting the ROUND

bit in the Interrupt Base/Control Register, , to 1. If the

TOP

Parameter Stack, the

and

registers.

The Barrel Shifter uses a 5-bit count stored in the

MXR

Register to determine the number of places to right or left

shift the double word operand contained in the and

IBC

TOP

registers. The output of the Barrel Shifter is stored in

ROUND bit is set to 1, all operations that use the Multiplier

automatically round the least significant 16 bits of the result into

the most significant 16 bits. The rounding is achieved by adding

8000H to the least significant 16 bits (during the same cycle as

the multiply). Thus, if the ROUND bit is set:

and

registers, with the top 16 bits in

MHR

MLR

and the bottom 16 bits in

.

MLR

25

HS-RTX2010RH

The Leading Zero Detector is used to normalize the double

word operand contained in the and registers.

Setting the Cycle Extend bit (CYCEXT), which is bit 7 of the

Register, will cause extended cycles to be used for all

TOP

The number of leading zeroes in the double word operand

are counted, and the count stored in the register. The

EXT

IBC

accesses to USER memory. Setting the ASIC Read Cycle

Extend bit (ARCE), which is bit 13 of the Register, will

MXR

double word operand is then logically shifted left by this

CR

cause extended cycles to be used for all Read accesses on

the external ASIC Bus. Both the CYCEXT bit and the ARCE

bit are cleared on Reset.

count, and the result stored in the

MHR

registers. Again the upper 16 bits are in

and

MLR

, and the

MHR

lower 16 bits are in

. This entire operation is done in

MLR

HS-RTX2010RH Memory Access

one clock cycle with the normalize instruction.

The HS-RTX2010RH Memory Bus Interface

HS-RTX2010RH ASIC Bus Interface

The HS-RTX2010RH can address 1 Megabyte of memory,

divided into 16 non-overlapping pages of 64K bytes. The

memory page accessed depends on whether the memory

access is for Code (instructions and literals), Data, User

Memory, or Interrupt Code. The page selected also depends

on the contents of the Page Control Registers: the Code

The HS-RTX2010RH ASIC Bus services both internal

processor core registers and the on-chip peripheral

registers, and eight external off-chip ASIC Bus locations. All

ASIC Bus operations require a single cycle to execute and

transfer a full 16-bit word of data. The external ASIC Bus

maps into the last eight locations of the 32 location ASIC

Address Space. The three least signiﬁcant bits of the

address are available as the ASIC Address Bus. The

addresses therefore map as shown in Table 5.

Page Register (

), the Data Page Register (

), the

CPR

User Page Register (

DPR

), and the Index Page Register

UPR

). Furthermore, the User Base Address Register

(

IPR

) and the Interrupt Base/Control Register (

) are

IBC

UBR

TABLE 5. ASIC BUS MAP

ASIC BUS SIGNAL

used to determine the complete address for User Memory

accesses and Interrupt Acknowledge cycles. External

memory data is accessed through

.

EXT

GA02

GA01

GA00

ASIC ADDRESS

When executing code other than an Interrupt Service

routine, the memory page is determined by the contents of

0

1

0

1

0

1

0

1

0

1

0

1

0

1

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

the

. Bits 03-00 generate address bits MA19-MA16, as

CPR

shown in Figure 18. The remainder of the address (MA15-

MA01) comes from the Program Counter Register ( ).

PC

After resetting the processor, both the

and the

CPR

PC

are cleared and execution begins at page 0, word 0.

A new Code page is selected by writing a 4-bit value to the

. The value for the Code page is input to the

CPR

through a preload procedure which withholds the value for

one clock cycle before loading the to ensure that the

CPR

next instruction is executed from the same Code page as the

instruction which set the new Code page. Execution

immediately thereafter will continue with the next instruction

in the new page.

HS-RTX2010RH Extended Cycle Operation

The HS-RTX2010RH bus cycle operation can be optionally

extended for two types of accesses:

1. USER Memory Cycles

An Interrupt Acknowledge cycle is a special case of an

Instruction Fetch cycle. When an Interrupt Acknowledge

2. ASIC Bus Read Operations

The extension of normal HS-RTX2010RH bus cycle timing

allows the interface of the processor to some peripherals,

and slow memory devices, without using externally

generated wait states. The bus cycle is extended by the

same amount (1 TCLK) as it would be if one wait state was

added to the cycle, but the control signal timing is somewhat

different (see Timing Diagrams). In a one wait state bus

cycle, PCLK is High for 1/2 TCLK period, and Low for 1-1/2

TCLK periods (i.e., PCLK is held Low for one additional

TCLK period). In an extended cycle, PCLK is High for 1

TCLK period, and Low for 1 TCLK period (i.e., both the High

and Low portions of the PCLK period are extended by 1/2

TCLK period).

cycle occurs, the contents of the

on the Return Stack and then the

and

are saved

CPR

PC

is cleared to point to

page 0. The Interrupt Controller generates a 16-bit address,

or “vector”, which points to the code to be executed to

process the interrupt. To determine how the Interrupt Vector

is formed, refer to Figure 12 for the register bit assignments,

and also to the Interrupt Controller section.

The page for data access is provided by either

or

CPR

, as shown in Figures 18 and 20. Data Memory

DPR

Access instructions can be used to access data in a memory

page other than that containing the program code. This is

done by writing the desired page number into the Data Page

Register (

) and setting bit 5 (DPRSEL) of the

IBC

DPR

26

HS-RTX2010RH

Register to 1. If

is set to equal

, or if DPRSEL = 0,

CPR

from these two registers are logically OR’ed to produce the

address of the word in memory. See Figure 21.

DPR

data will be accessed in the Code page. The status of the

DPRSEL bit is saved and restored as a result of a

Subroutine Call or Return. When the HS-RTX2010RH is

Word And Byte Main Memory Access

Using Main Memory Access instructions, the HS-RTX2010RH

can perform either word or single byte Main Memory

accesses, as well as byte swapping within 16-bit words.

reset,

points to page 0 and DPRSEL resets to 0,

DPR

selecting the

.

CPR

USER MEMORY consists of blocks of 32 words that can be

located anywhere in memory. The word being accessed in a

block is pointed to by the ﬁve least signiﬁcant bits of the User

Memory instruction (see Table 17), eliminating the need to

Bit 12 of the Memory Access Opcode (see Table 16), is used

to determine whether byte or word operations are to be

performed (where bit 12 = 0 signiﬁes a word operation, and

bit 12 = 1 signiﬁes a byte operation). In addition, the

determination of whether a byte swap is to occur depends on

whether Addressing Mode 0 or Mode 1 is in effect (as

explicitly load an address into

before reading or

TOP

writing to the location. Upon HS-RTX2010RH reset,

is

UBR

cleared and points to the block starting at word 0, while

is cleared so that it points to page 0. The word in the

determined by bit 2 of the

), and on whether an even

CR

or odd address is being accessed (see Figures 26 and 27).

UPR

block is pointed to by the ﬁve least signiﬁcant bits of the User

Memory instruction and bits 05-01 of the

. These bits

UBR

IR

CR ADDRESS

ADDRESS

EVEN/ODD

CR

BIT 12 BIT 2

IR

DATA ACCESS (16-BIT)

DATA ACCESS (8 -BIT)

BYTE WRITE

EVEN/ODD

BIT 12 BIT 2

WORD WRITE

PROCESSOR

0

PROCESSOR

0

1

15

8

7

0

1

0

15

8

7

UNCHANGED

0

1

15

8

7

0

15

8

7

0

MEMORY

BYTE READ

WORD READ

PROCESSOR

0

PROCESSOR

0

15

0

1

0

1

15

1

0

1

15

8

7

0

1

15

8

7

0

MEMORY

PROCESSOR

0

BYTE WRITE

WORD WRITE

PROCESSOR

0

15

1

0

1

0

1

0

UNCHANGED

1

0

1

0

8

7

0

15

8

7

0

MEMORY

PROCESSOR

0

WORD READ

15

BYTE READ

PROCESSOR

0

15

1

0

1

0

1

0

1

8

7

0

15

8

7

0

15

MEMORY

FIGURE 26. MEMORY ACCESS (WORD)

FIGURE 27. MEMORY ACCESS (BYTE)

27

HS-RTX2010RH

Whenever a word of data is read by a Data Memory operation

into the processor, it is first placed in the Register. By

the time the instruction that reads that word of data is

completed, however, the data may have been moved,

optionally inverted, or operated on by the ALU, and placed in

lower byte position (MD07-MD00), while the upper byte is

set to 0 (MD15-MD08 set to 0). See Figure 27. A Byte Write

operation accessing an odd address will cause the byte to

be swapped from the lower byte position (MD07-MD00) of

the processor register into the upper byte position

(MD15-MD08) of the Memory location. The data in the lower

byte position (MD07-MD00) in that Memory location will be

left unaffected.

Register. Whenever a Data Memory operation

TOP

writes to memory, the data comes from the

Register.

(see Figure 11 in the “RTX Internal Registers

NOTE: These features are for Main Memory data access only, and

have no effect on instruction fetches, long literals, or User Data

Memory.

CR

Section). This bit is used to determine whether the default

(Mode 0) or byte swap (Mode 1) method will be used in the

Data Memory accesses.

Subroutine Calls And Returns

The RTX can perform both “short” subroutine calls and

“long” subroutine calls. A short subroutine call is one for

which the subroutine code is located within the same Code

page as the Call instruction, and no processor cycle time is

Word Access is designated when the

Memory Access Opcode, and can take one of two forms,

depending upon the status of , bit 2.

bit 12 = 0 in the

IR

CR

bit 2 = 0, the Mode 0 method of word access is

When

CR

expended in reloading the

.

CPR

designated. Word access to an even address (A0 = 0) results

in an unaltered transfer of data, as shown in Figure 26. Word

access to/from an odd address (A0 = 1) while in this mode will

effectively cause the Byte Order Bit to be complemented and

will result in the bytes being swapped.

Performing a long subroutine call involves transferring

execution to a different Code page. This requires that the

be loaded with the new Code page as described in

CPR

the Memory Access Section, followed immediately by the

Subroutine Call instruction. This adds two additional cycles

to the execution time for the Subroutine Call.

When the

bit 2 = 1, the Mode 1 method of word

CR

access is designated. Access to an even address (A0 = 0)

results in a data transfer in which the bytes are swapped.

Word access to an odd address (A0 = 1) while in this mode

will effectively cause the Byte Order Bit to be complemented

with the net result that no byte swap takes place when the

data word is transferred. See Figure 26.

For all instructions except Subroutine Calls or Branch

instructions, bit 5 of the instruction code represents the

Subroutine Return Bit. If this bit is set to 1, a Return is

performed whereby the return address is popped from the

Return Stack, as indicated in Figure 19. The page for the

return address comes from the

. The contents of the

, and the contents of

IPR

PC

Byte Access is designated when the

Memory Access Opcode, and can also take one of two

forms, depending on the value of Bit 2.

bit 12 = 1 in the

IR

Register are written to the

I

the

are written to the

so that execution resumes

CPR

IPR

CR

bit 2 = 0, a Byte Read from an even

at the point following the Subroutine Call. The Return Stack

is also popped at this time.

When the

CR

address in Mode 0 causes the upper byte (MD15-MD08) of

memory data to be read into the lower byte position

HS-RTX2010RH Software

The HS-RTX2010RH is designed around the same

architecture as the RTX 2000, and is a hardware

implementation of the Virtual Forth Engine. As such, it does

not require the additional assembly or machine language

software development typical of most real-time

microcontrollers.

(MD07-MD00) of

is set to 0. A Byte Write operation accessing an even

address will cause the byte to be written from the lower byte

position (MD07-MD00) of

(MD15-MD08) of memory. The data in the lower byte

position (MD07-MD00) in memory will be left unaltered.

Accessing an odd address for either of these operations will

cause the Byte Order Bit to be complemented, with the net

result that no swap will occur. See Figure 27.

, while the upper byte (MD15-MD08)

combines multiple high level instructions into single machine

instructions without having to rely on either pipelines or

caches. This optimization yields an effective throughput

which is faster than the processor’s clock speed, while

avoiding the unpredictable execution behavior exhibited by

most RISC processors caused by pipeline ﬂushes and cache

misses.

When

bit 2 = 1, the Mode 1 method of memory

CR

access is used. Accessing an even address in this mode

means that a Byte Read operation will cause the lower byte

of data to be transferred without a swap operation. A Byte

Write in this mode will also result in an unaltered byte

transfer. Conversely, accessing an odd address for a byte

operation while in Mode 1 will cause the Byte Order Bit to be

complemented. In a Byte Read operation, this will result in

the upper byte (MD15-MD08) of data being swapped into the

2010 Compilers

Intersil offers a complete ANSI C cross development

environment for the HS-RTX2010RH. The environment

provides a powerful, user-friendly set of software tools

28

HS-RTX2010RH

designed to help the developers of embedded real-time

The HS-RTX2010RH TForth compiler from Intersil translates

Forth-83 source code to HS-RTX2010RH machine

instructions. This compiler also provides support for all of the

HS-RTX2010RH instructions speciﬁc to the processor’s

registers, peripherals, and ASIC Bus. See the tables in the

following sections for instruction set information.

control systems get their designs to market quickly. The

environment includes the optimized ANSI C language

compiler, symbolic menu driven C language debugger, RTX

assembler, linker, proﬁler, and PROM programmer interface.

TABLE 6. INSTRUCTION SET SUMMARY

DEFINITION

Read data (byte or word) from memory location addressed by contents of

NOTATIONS

m-read

m-write

g-read

Register into

Register.

TOP

Write contents (byte or word) of

Register into memory location addressed by contents of

TOP

chip peripheral registers can be done with a g-read command.

Register. A read of one of the on-

TOP

g-write

Write contents of

peripheral registers can be done with a g-write command.

Register to ASIC address (address field ggggg of instruction). A write to one of the on-chip

TOP

u-read

u-write

SWAP

DUP

Read contents (word only) of User Space location (address field uuuuu of instruction) into

Register.

TOP

Write contents (word only) of

Register into User Space location (address field uuuuu of instruction).

TOP

Exchange contents of

and

registers.

Copy contents of

Register to

Register, pushing previous contents of

onto Stack Memory.

Register to

Register, pushing original contents of

to

Register and

TOP

original contents of

Register to Stack Memory.

Pop Parameter Stack, discarding original contents of

and the original contents of the top Stack Memory location in

Register, leaving the original contents of

in

NEXT TOP

TOP

.

alu-op

shift

Perform 1’s complement on contents of

Register, if i bit in instruction is 1.

TOP

Perform appropriate cccc or aaa ALU operation from Table 20 on contents of

and

registers.

TOP

Perform appropriate shift operation (ssss field of instruction) from Table 21 on contents of

registers.

and/or

Push short literal d from ddddd field of instruction onto Parameter Stack (where ddddd contains the actual value of the

short literal). The original contents of

onto Stack Memory.

are pushed into

, and the original contents of.

are pushed

R

Push long literal D from next sequential location in program memory onto Parameter Stack. The original contents of

are pushed into , and the original contents of are pushed onto Stack Memory.

TOP

Perform a Return From Subroutine if bit = 1.

NOTE: All unused opcodes are reserved for future architectural enhancements.

TABLE 7. INSTRUCTION REGISTER BIT FIELDS (BY FUNCTION)

FUNCTION CODE

ggggg

DEFINITION

Address field for ASIC Bus locations

Address field for User Space memyyory locations

ALU functions (see Table 20)

uuuuu

cccc aaa

ddddd

Short literals (containing a value from 0 to 31)

Shift Functions (see Table 21)

ssss

29

HS-RTX2010RH

TABLE 8. HS-RTX2010RH

AND

ACCESS OPERATIONS (Note)

PC

I

RETURN

BIT

ASIC

ADDRESS

OPERATION

(g-read, g-write)

VALUE

ggggg

00000

00001

REGISTER

FUNCTION

Read mode

Write mode

Read mode

0

1

0

1

0

1

Pushes the contents of

into

(with no pop of the Return Stack)

, then performs a Subroutine Return

I

TOP

I

Pops the contents of

into

(with no push of the Return Stack)

I

TOP

Performs a Subroutine Return, then pushes the contents of

into

I

TOP

Pushes the contents of

into

, popping the Return Stack

I

TOP

without popping the Return Stack, then

I

executes the Subroutine Return

Write mode

Read mode

0

1

0

00001

00010

Pushes the contents of into

popping the Parameter Stack

I

TOP

I

Performs a Subroutine Return, then pushes the contents of

into

I

TOP

Pushes the contents of

is not popped)

shifted left by one bit, into

(the Return Stack

I

TOP

Read mode

Write mode

1

0

00010

Pushes the contents of

is not popped), then performs a Subroutine Return

shifted left by one bit, into

(the Return Stack

I

TOP

Pushes the contents of into as a “stream” count, indicating that the

next instruction is to be performed a specified number of times; the Parameter

Stack is popped

TOP

I

Write mode

Read mode

Write mode

1

0

1

0

00010

00111

Performs a Subroutine Return, then pushes the stream count into

I

Pushes the contents of

into

TOP

PC

into

, then performs a Subroutine Return

TOP

PC

Performs a Subroutine Call to the address contained in

Parameter Stack

, popping the

TOP

Write mode

1

00111

Pushes the contents of

Subroutine Return

onto the Return Stack before executing the

TOP

PC

NOTE: See the RTX Programmer’s Reference Manual for a complete listing of typical software functions.

TABLE 9. HS-RTX2010RH RESERVED I/O OPCODES

INSTRUCTION CODE

OPERATION

15 14 13 12

1 0 1

11 10 9 8

0 0 0 0

7 6 5 4

1 0 R 0

0 0 R 0

1 0 R 1

0 0 R 1

3 2 1 0

1 1 0 1

0 0 0 0

1

Select

DPR

CPR

1 0 1 1

Select

Set SOFTINT

Clear SOFTINT

TABLE 10. SUBROUTINE CALL INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

0 a a a

11 10 9 8

a a a a

7 6 5 4

a a a a

3 2 1 0

a a a a

Call word address

aaaa aaaa aaaa aaa0, in the page

Subroutine Call Bit

(Bit 15 = 0: Call,

Bit 15 = 1: No Call)

indicated by

. This address is

CPR

produced when the processor

performs a left shift on the address in

the instruction code.

30

HS-RTX2010RH

TABLE 11. SUBROUTINE RETURN

INSTRUCTION CODE

11 10 9 8 7 6 5 4

- - - R -

Subroutine Return Bit (Note)

OPERATION

15 14 13 12

3 2 1 0

- - - -

-

Return from subroutine

(Bit 5, R = 0: No return R = 1: Return)

NOTE: Does not apply to Subroutine Call or Branch Instructions. A Subroutine Return can be combined with any other instruction

(as implied here by hyphens).

TABLE 12. BRANCH INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

1 0 0 0

1 0 0 1

11 10 9 8

0 b b a

1 b b a

0 b b a

1 b b a

7 6 5 4

a a a a

3 2 1 0

a a a a

DROP and branch if

= 0

TOP

Branch if

= 0

TOP

Unconditional branch

Branch and decrement

if

≠ 0;

I

Pop

if

= 0

I

Branch Address

(Note)

NOTE: See the Programmer’s Reference Manual for further information regarding the branch address ﬁeld.

TABLE 13. REGISTER AND I/O ACCESS INSTRUCTIONS

INSTRUCTION CODE

11 10 9 8 7 6 5 4

OPERATION

15 14 13 12

1 0 1 1

3 2 1 0

g g g g

0 0 0

1 1 1

i

0 0 R g

1 0 R g

g-read DROP

inv

g-read

inv

c

c c

g-read OVER

DUP g-write

g-write

alu-op

inv

0 0 0

1 1 1

i

inv

c

c c

g-read SWAP

alu-op

TABLE 14. SHORT LITERAL INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

1 0 1 1

11 10 9 8

0 0 0

1 1 1 i

c c

1 1 1

c c

7 6 5 4

0 1 R d

1 1 R d

3 2 1 0

d d d d

i

d DROP

d

inv

c

d OVER

alu-op

i

d SWAP DROP

d SWAP

inv

c

alu-op

31

HS-RTX2010RH

TABLE 15. LONG LITERAL INSTRUCTIONS

INSTRUCTION CODE

OPERATION

(1ST CYCLE)

(2ND CYCLE)

15 14 13 12

1 1 0 1

11 10 9 8

0 0 0 i

1 1 1 i

c c c c

1 1 1 i

c c c c

7 6 5 4

0 0 R 0

1 0 R 0

3 2 1 0

0 0 0 0

D SWAP

inv

SWAP inv

SWAP OVER alu-op

DROP inv

alu-op

TABLE 16. MEMORY ACCESS INSTRUCTIONS

INSTRUCTION CODE OPERATION

(1ST CYCLE)

(2ND CYCLE)

15 14 13 12

11 10 9 8

0 0 0 i

1 1 1 i

c c c c

0 0 0 p

7 6 5 4

0 0 R 0

0 1 R 0

3 2 1 0

0 0 0 0

1 1 1 s

m-read SWAP

inv

SWAP inv

SWAP OVER alu-op

NOP

(SWAP DROP) DUP

m-read SWAP

1 1 1 s

1 1 1 p

a a a p

0 1 R d

d d d d

(SWAP DROP) m-read d

NOP

(SWAP DROP) DUP m-read

SWAP d SWAP alu-op

1 1 1 s

0 0 0 i

1 1 1 i

c c c c

0 0 0 p

1 0 R 0

1 1 R 0

0 0 0 0

OVER SWAP m-write

m-read SWAP

inv

DROP inv

alu-op

NOP

(OVER SWAP) SWAP

OVER m-write

1 1 1 s

1 1 1 p

a a a p

1 1 R d

d d d d

(OVER SWAP) m-write d

NOP

(OVER SWAP) SWAP OVER

m-write d SWAP alu-op

If (p = 0), perform either

(SWAP DROP) or (OVER SWAP)

If s = 0, Memory is accessed by word

If s = 1, Memory is accessed by byte

NOTE: SWAP d SWAP ≡ d ROT

32

HS-RTX2010RH

TABLE 17. USER SPACE INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

1 1 0 0

11 10 9 8

0 0 0 i

1 1 1 i

c c c c

0 0 0 i

1 1 1 i

c c c c

7 6 5 4

0 0 R u

1 0 R u

3 2 1 0

u u u u

(1ST CYCLE)

u-read SWAP

DUP u-write

u-read SWAP

(2ND CYCLE)

inv

SWAP inv

SWAP OVER alu-op

inv

DROP inv

alu-op

TABLE 18. ALU FUNCTION INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

1 0 1 0

11 10 9 8

0 0 0 i

1 1 1 i

c c c c

0 0 0 i

1 1 1 i

c c c c

0 0 0 i

1 1 1 i

c c c c

0 0 0 i

1 1 1 i

c c c c

7 6 5 4

0 0 R 0

0 1 R 0

1 0 R 0

1 1 R 0

3 2 1 0

s s s s

inv shift

DROP DUP

OVER SWAP

SWAP DROP

DROP

inv shift

alu-op shift

inv shift

alu-op shift

inv shift

SWAP DROP DUP

SWAP

inv shift

SWAP OVER

DUP

alu-op shift

inv shift

OVER

inv shift

OVER OVER

alu-op shift

TABLE 19. STEP MATH FUNCTIONS (NOTE 25)

INSTRUCTION CODE OPERATION

15 14 13 12

1 0 1 0

11 10 9 8

- -

7 6 5 4

- - - 1

3 2 1 0

- -

-

(See the Programmer’s Reference Manual)

NOTE:

25. These instructions perform multi-step math functions such as multiplication, division and square root functions. Use of either the Streamed

instruction mode or masking of interrupts is recommended to avoid erroneous results when performing Step Math operations.

Unsigned Division:

Load dividend into

Load divisor into

Execute single step form of D2 (Note 25) instruction 1 time

Execute opcode A41A 1 time

Square Root Operations:

and

Load value into

Load 8000H into

Load 0 into

MD

and

MD

SR

Execute single step form of D2 (Note 25) instruction 1 time

Execute opcode A51A 1 time

Execute opcode A45A 14 times

Execute opcode A458 1 time

Execute opcode A55A 14 times

The quotient is in

, the remainder in

Execute opcode A558 1 time

The root is in

, the remainder in

TOP

HS-RTX2010RH

TABLE 20. ALU LOGIC FUNCTIONS/OPCODES

cccc

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

aaa

FUNCTION

001

AND

NOR

SWAP-

SWAP-c

OR

010

011

100

101

110

With Borrow

NAND

+

+c

With Carry

XOR

XNOR

-

-c

With Borrow

TABLE 21. SHIFT FUNCTIONS

REGISTER

Nn N0

TOP

OF C

SHIFT ssss

0000

NAME

FUNCTION

T15

Z15

Z14

CY

0

Tn

T0

N15

No Shift

CY

Z15

0

Zn

Z0

TN15

TN14

Z0

TNn

TN0

0

0001

0<

Sign Extend

Z15

Zn-1

Zn+1

Zn

Z15

0

0010

2*

Arithmetic Left Shift

Rotate Left

TNn

0011

2*c

CY

Z1

TNn

0100

cU2/

c2/

Right Shift Out of Carry

Rotate Right Through Carry

Logical Right Shift

TNn

0101

Z0

Z1

TNn

0110

U2/

2/

0

Z1

TNn

0111

Arithmetic Right Shift

Z15

CY

Z15

0

Z15

Z14

CY

0

Z1

TNn

1000

N2*

N2*c

D2*

D2*c

cUD2/

Left Shift of

Z0

TNn-1

TNn+1

Rotate

Left

Zn

Z0

CY

32-Bit Left Shift

Zn-1

Zn+1

TN15

Z1

0

1011

32-Bit Rotate Left

CY

1100

32-Bit Right Shift Out of Carry

32-Bit Rotate Right Through Carry

32-Bit Logical Right Shift

32-Bit Right Shift

TN1

1101 (Note) cD2/

TN0

0

Z1

Z0

1110

1111

UD2/

D2/

Z1

Z0

Z15

Z1

Z0

NOTE: See the Programmer’s Reference Manual.

Where: T15-Most significant bit of

C-Carry bit

CY-Carry bit before operation

Zn-ALU output

Z15-Most significant bit 15 of ALU output

TNn-Original value of typical bit of

TOP

Tn-Typical bit of

T0-Least significant bit of

N15-Most significant bit of

TOP

N0-Least significant bit of

HS-RTX2010RH

TABLE 22. MAC/BARREL SHIFTER/LZD INSTRUCTIONS

INSTRUCTION CODE

OPERATION

15 14 13 12

1 0 1 1

11 10 9 8

0 0 0 0

1 1 1 0

7 6 5 4

0 0 R 0

0 0 R 1

1 0 R 1

0 0 R 1

1 0 R 1

0 0 R 1

1 0 R 1

3 2 1 0

1 0 0 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

1 1 1 1

0 0 0 1

0 0 1 0

0 0 1 1

0 1 1 0

0 1 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

0 0 1 0

0 1 1 0

0 1 1 1

0 0 1 0

0 1 1 0

0 1 1 1

Forth 0 =

Double Shift Right Arithmetic

Double Shift Right Logical

Clear MAC Accumulator

Double Shift Left Logical

Floating Point Normalize

Shift MAC Output Regs Right

Streamed MAC Between Stack and Memory

Streamed MAC Between ASIC Bus and Memory

Mixed Mode Multiply

Unsigned Multiply

Signed Multiply

Signed Multiply and Subtract from Accumulator

Mixed Mode Multiply Accumulate

Unsigned Multiply Accumulate

Signed Multiply Accumulate

Load MXR Register

Load MLR Register

Load MHR Register

Store MXR Register

Store MLR Register

Store MHR Register

35

HS-RTX2010RH

Die Characteristics

DIE DIMENSIONS:

Substrate:

TSOS5 CMOS,

364 mils x 371 mils x 21 mils ±1mil

Silicon on Sapphire

INTERFACE MATERIALS:

Glassivation:

Backside Finish:

Silicon

Type: SiO

2

ASSEMBLY RELATED INFORMATION:

Thickness: 8kÅ ±1kÅ

Top Metallization:

Substrate Potential:

Type: Al/Si/Cu

Unbiased (SOS)

Thickness: 7.5kÅ ±2kÅ

ADDITIONAL INFORMATION:

Worst Case Current Density:

5

2

1.0 x 10 A/cm

Metallization Mask Layout

HS-RTX2010RH

(74) MD08

(73) VCC

RESET (12)

WAIT (13)

(72) MD07

(71) MD06

(70) MD05

(69) GND

ICLK (14)

GR/W (15)

GIO (16)

GD15 (17)

GD14 (18)

GD13 (19)

GND (20)

GD12 (21)

GD11 (22)

(68) MD04

(67) MD03

(66) MD02

(65) MD01

(64) MD00

(63) MR/W

GD10 (23)

GD09 (24)

GD08 (25)

GD07 (26)

VCC (27)

(62) PCLK

(61) BOOT

(60) NEW

(59) UDS

(58) LDS

(57) GND

GD06 (28)

GD05 (29)

GD04 (30)

GD03 (31)

GND (32)

(56) MA19

(55) MA18

(54) MA17

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

36


型号：	HS0-RTX2010RH-Q
厂家：	Intersil
描述：	Radiation Hardened Real Time Express⑩ Microcontroller 抗辐射实时Express⑩微控制器微控制器
文件：	总36页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HS0-RTX2010RH-Q [INTERSIL]

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