HIP2101IRZ [INTERSIL]
100V/2A Peak, Low Cost, High Frequency Half Bridge Driver; 100V / 2A峰值，低成本，高频率半桥驱动器
| 型号： | HIP2101IRZ |
| 厂家： | 
Intersil |
| 描述： | 100V/2A Peak, Low Cost, High Frequency Half Bridge Driver |
| 文件： | 总12页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP2101
®
Data Sheet
October 21, 2004
FN9025.8
100V/2A Peak, Low Cos t, High Frequency
Half Bridge Driver
Features
• Drives N-Channel MOSFET Half Bridge
The HIP2101 is a high frequency, 100V Half Bridge
N-Channel power MOSFET driver IC. It is equivalent to the
HIP2100 with the added advantage of full TTL/CMOS
compatible logic input pins. The low-side and high-side gate
drivers are independently controlled and matched to 13ns.
This gives users total control over dead-time for specific
power circuit topologies. Undervoltage protection on both
the low-side and high-side supplies force the outputs low. An
on-chip diode eliminates the discrete diode required with
other driver ICs. A new level-shifter topology yields the low-
power benefits of pulsed operation with the safety of DC
operation. Unlike some competitors, the high-side output
returns to its correct state after a momentary undervoltage of
the high-side supply.
• SOIC, EPSOIC, QFN and DFN Package Options
• SOIC, EPSOIC and DFN Packages Compliant with 100V
Conductor Spacing Guidelines of IPC-2221
• Pb-free Product Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1Ω Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1000pF Load with Rise and Fall Times Typ. 10ns
• TTL/CMOS Input Thresholds Increase Flexibility
• Independent Inputs for Non-Half Bridge Topologies
• No Start-Up Problems
Ordering Information
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
TEMP.
PKG.
DWG. #
PART NUMBER
RANGE (°C)
PACKAGE
• Low Power Consumption
• Wide Supply Range
HIP2101IB
-40 to 125 8 Ld SOIC
M8.15
HIP2101IBZ (Note 1) -40 to 125 8 Ld SOIC (Pb-free) M8.15
• Supply Undervoltage Protection
• 3Ω Output Driver Resistance
• QFN/DFN Package:
HIP2101EIB
-40 to 125 8 Ld EPSOIC
M8.15C
M8.15C
HIP2101EIBZ
(Note 1)
-40 to 125 8 Ld EPSOIC
(Pb-free)
- Compliant to JEDEC PUB95 MO-220
HIP2101IR
-40 to 125 16 Ld 5x5 QFN
L16.5x5
L16.5x5
QFN - Quad Flat No Leads - Package Outline
HIP2101IRZ (Note 1) -40 to 125 16 Ld 5x5 QFN
(Pb-free)
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
HIP2101IR4
-40 to 125 12 Ld 4x4 DFN
L12.4x4A
L12.4x4A
Applications
HIP2101IR4Z
(Note 1)
-40 to 125 12 Ld 4x4 DFN
(Pb-free)
• Telecom Half Bridge Power Supplies
• Avionics DC-DC Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
2. Add “T” suffix for Tape and Reel packing option.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HIP2101
Pinouts
HIP2101 (SOIC, EPSOIC)
HIP2101IR4 (DFN)
HIP2101 (QFN)
TOP VIEW
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
LO
V
V
DD
V
1
2
3
4
5
6
12
11
10
9
LO
DD
16 15 14 13
HB
HO
HS
SS
EPAD
NC
NC
HB
HO
HS
V
SS
NC
HB
HO
NC
NC
1
2
3
4
12
11
LI
NC
NC
LI
HI
EPAD
V
SS
EPAD
10 LI
8
7
HI
9
NC
5
6
7
8
NOTE: EPAD = Exposed PAD.
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
V
DD
HB
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
REFERENCE
HIP2101
AND
ISOLATION
V
SS
FN9025.8
2
HIP2101
Functional Block Diagram
HB
HO
V
DD
HI
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
HS
UNDER
VOLTAGE
LO
DRIVER
LI
V
SS
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
+48V
+12V
SECONDARY
CIRCUIT
HIP
2101
PWM
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
HIP
2101
PWM
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
FN9025.8
3
HIP2101
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
V
-V
(Notes 3, 4). . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JC
DD, HB HS
JA
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V
SOIC (Note 5) . . . . . . . . . . . . . . . . . . .
EPSOIC (Note 6) . . . . . . . . . . . . . . . . .
QFN (Note 6) . . . . . . . . . . . . . . . . . . . .
95
40
37
40
N/A
3.0
6.5
3.0
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
+0.3V
DD
Voltage on HO (Note 4) . . . . . . . . . . . . . . . V
-0.3V to V
HS
HB
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
DFN (Note 6) . . . . . . . . . . . . . . . . . . . .
o
Max Power Dissipation at 25 C in Free Air (SOIC, Note 5) . . . . 1.3W
o
Average Current in V
to HB diode. . . . . . . . . . . . . . . . . . . 100mA
DD
Max Power Dissipation at 25 C in Free Air (EPSOIC, Note 6). . 3.1W
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Max Power Dissipation at 25 C in Free Air (QFN, Note 6). . . . . 3.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65°C to 150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . .-55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only). . 300°C
For Recommended soldering conditions see Tech Brief TB389.
Maximum Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . .+9V to 14.0VDC
DD
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . V +8V to V +14.0V and V
HS HS DD
-1V to V +100V
DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The HIP2101 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to V unless otherwise specified.
SS
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ
the
JA
JC,
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, No Load on LO or HO, Unless Otherwise Specified
HS
DD
HB
T = -40°C TO
J
T
= 25°C
125°C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
SUPPLY CURRENTS
V
V
Quiescent Current
Operating Current
I
LI = HI = 0V
f = 500kHz
LI = HI = 0V
f = 500kHz
-
-
-
-
-
-
0.3
1.7
0.45
3.0
0.15
2.5
1.5
-
-
-
-
-
-
-
0.6
3.4
0.2
3
mA
mA
mA
mA
µA
DD
DD
DD
I
I
DDO
Total HB Quiescent Current
Total HB Operating Current
I
0.1
HB
HBO
1.5
HB to V Current, Quiescent
SS
I
V
= V = 114V
HB
0.05
0.7
10
-
HBS
HS
HB to V Current, Operating
SS
I
f = 500kHz
mA
HBSO
INPUT PINS
Low Level Input Voltage Threshold
V
0.8
1.65
1.65
200
-
2.2
-
0.8
-
-
V
V
IL
High Level Input Voltage Threshold
Input Pulldown Resistance
V
-
-
2.2
500
IH
R
100
kΩ
I
UNDER VOLTAGE PROTECTION
V
V
Rising Threshold
V
7
-
7.3
0.5
6.9
0.4
7.8
-
6.5
8
-
V
V
V
V
DD
DD
DDR
DDH
HBR
HBH
Threshold Hysteresis
V
-
6
-
HB Rising Threshold
V
V
6.5
-
7.5
-
8
-
HB Threshold Hysteresis
FN9025.8
4
HIP2101
Electrical Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
SS HS
DD
HB
T = -40°C TO
J
T
= 25°C
125°C
J
PARAMETERS
BOOT STRAP DIODE
Low-Current Forward Voltage
High-Current Forward Voltage
Dynamic Resistance
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
V
I
I
I
= 100µA
= 100mA
= 100mA
-
-
-
0.45
0.7
0.70
0.92
1
-
-
-
0.7
1
V
V
Ω
DL
VDD-HB
VDD-HB
VDD-HB
V
DH
R
0.8
1.5
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLL
OHL
OHL
LO
LO
V
= -100mA, V
OHL
= V -V
DD LO
I
V
V
= 0V
LO
LO
Peak Pulldown Current
HO GATE DRIVER
I
= 12V
2
-
-
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLH
OHH
OHH
HO
HO
V
= -100mA, V
= V -V
HB HO
OHH
I
V
V
= 0V
HO
HO
Peak Pulldown Current
I
= 12V
2
-
-
OLH
Switching Specifications
V
= V
= 12V, V = V
SS
= 0V, No Load on LO or HO, Unless Otherwise Specified
HS
DD
HB
T
= -40°C
J
T
= 25°C
TO 125°C
J
TEST
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX MIN MAX UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Lower Turn-On and Upper Turn-Off
Delay Matching: Lower Turn-Off and Upper Turn-On
Either Output Rise/Fall Time
t
-
-
-
-
-
-
-
-
-
-
-
-
25
25
25
25
2
43
43
43
43
13
13
-
-
-
-
-
-
-
-
-
-
-
-
-
56
56
56
56
16
16
-
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
LPHL
t
t
HPHL
t
LPLH
HPLH
t
MON
t
2
MOFF
t
t
C = 1000pF
10
0.5
20
10
-
RC, FC
L
Either Output Rise/Fall Time (3V to 9V)
t
t
C = 0.1µF
0.6
-
0.8
-
R, F
L
Either Output Rise Time Driving DMOS
t
C = IRFR120
L
RD
Either Output Fall Time Driving DMOS
t
C = IRFR120
-
-
FD
L
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
t
-
50
-
PW
t
10
-
BS
FN9025.8
5
HIP2101
Pin Des criptions
SYMBOL
DESCRIPTION
V
Positive Supply to lower gate drivers. De-couple this pin to V . Bootstrap diode connected to HB.
SS
DD
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
HS
High-Side Output. Connect to gate of High-Side power MOSFET.
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI
LI
High-Side input.
Low-Side input.
V
Chip negative supply, generally will be ground.
Low-Side Output. Connect to gate of Low-Side power MOSFET.
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
SS
LO
EPAD
Timing Diagrams
LI
HI
HI,
LI
t
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
LPLH
t
t
MOFF
MON
HO,
LO
FIGURE 3.
FIGURE 4.
Typical Performance Curves
3.500
3.000
2.500
2.000
1.500
1.000
4.000
3.500
150°C, 125°C
25°C
150°C
3.000
125°C
2.500
2.000
1.500
1.000
0.500
0.000
25°C
-40°C
-40°C
0.500
0.000
10
30
50
70
90 200 400
600
800 1000
10
30
50
70
90 200 400
600
800 1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 5B.
FIGURE 5A.
FIGURE 5. OPERATING CURRENT vs FREQUENCY
FN9025.8
6
HIP2101
Typical Performance Curves (Continued)
500
400
300
200
100
10
V
= V
= 9V
DD
HB
V
= V
= 12V
= 14V
HB
HB
DD
DD
V
= V
T = 150°C
T = -40°C
T = 125°C
T = 25°C
1
0.1
0.01
-50
0
50
TEMPERATURE (°C)
100
10
100
1000
150
FREQUENCY (kHz)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 6. HB TO VSS OPERATING CURRENT vs
FREQUENCY
7.6
7.4
500
V
= V
= 9V
DD
HB
V
= V
= 12V
= 14V
400
300
200
100
HB
HB
DD
DD
V
V
DDR
HBR
V
= V
7.2
7.0
6.8
6.6
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
30
0.54
0.5
t
t
HPHL
HPLH
t
V
LPHL
LPLH
DDH
25
20
15
0.46
0.42
0.38
0.34
0.3
t
V
HBH
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FN9025.8
7
HIP2101
Typical Performance Curves (Continued)
2.5
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
, V
HO LO
(V)
V
, V (V)
LO HO
FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT
VOLTAGE
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE
1
0.1
60
50
I
vs V
HB
HB
40
30
20
10
0
0.01
0.001
I
vs V
DD
DD
-4
1•10
-5
1•10
1•10-6
0
5
10
(V)
15
0.3
0.4
0.5
0.6
0.7
0.8
V
, V
DD HB
FORWARD VOLTAGE (V)
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
120
100
80
60
40
20
0
12
14
15
TO V VOLTAGE (V)
16
V
DD
SS
FIGURE 16. VHS VOLTAGE vs V
DD
VOLTAGE
FN9025.8
8
HIP2101
Dual Flat No-Lead Plas tic Package (DFN)
Micro Lead Frame Plas tic Package (MLFP)
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
SYMBOL
MIN
NOMINAL
0.85
MAX
0.90
0.05
0.70
NOTES
0.15
C
A
A
A1
A2
A3
b
-
0.00
-
-
D
A
0.01
-
D/2
0.65
-
D1
0.20 REF
0.23
-
D1/2
0.18
2.65
1.43
0.30
2.95
1.73
5, 8
2X
N
0.15
C B
D
4.00 BSC
3.75 BSC
2.80
-
D1
D2
E
-
E1/2
E/2
9
7, 8
E1
E
B
6
4.00 BSC
3.75 BSC
1.58
-
INDEX
AREA
E1
E2
e
-
7, 8
0.15
C B
1
2
3
2X
0.50 BSC
-
-
TOP VIEW
0.15
C A
k
0.635
0.30
-
-
2X
0
4X
L
0.40
0.50
8
A2
A
0.10
0.08
C
//
N
12
2
C
Nd
P
6
3
0.24
-
0.42
0.60
12
-
C
A1
A3
SEATING
PLANE
SIDE VIEW
θ
-
-
Rev. 0 8/03
7
8
NOTES:
D2
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. N is the number of terminals.
(Nd-1)Xe
REF.
D2/2
3. Nd refer to the number of terminals on D.
1
2 3
6
4. All dimensions are in millimeters. Angles are in degrees.
INDEX
AREA
NX k
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
7
8
4X P
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
N N-1
e
5
NX b
0.10
M
C A
B
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.
C
L
A1
NX b
5
5
L
C
C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
FN9025.8
9
HIP2101
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.28
2.55
2.55
0.33
0.40
2.85
2.85
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
2.70
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
2.70
7, 8
0.80 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
4
-
3
0.60
12
9
θ
-
-
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9025.8
10
HIP2101
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9025.8
11
HIP2101
Small Outline Expos ed Pad Plas tic Packages (EPSOIC)
M8.15C
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.811
MAX
1.68
0.13
0.49
0.25
4.98
3.99
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
0.050 BSC
1.27 BSC
-
o
h x 45
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
-C-
5
α
µ
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
o
o
o
o
0
8
0
8
-
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
-
-
0.126
0.099
-
-
3.200
2.514
11
11
P1
Rev. 0 11/03
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9025.8
12
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