HI9P5051-9 [INTERSIL]
CMOS Analog Switches; CMOS模拟开关
| 型号： | HI9P5051-9 |
| 厂家： | 
Intersil |
| 描述： | CMOS Analog Switches |
| 文件： | 总11页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-5042 thru HI-5051
TM
Data Sheet
April 2000
File Number 3127.4
CMOS Analog Switches
Features
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25Ω
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
operating signal voltage and current. r
remains
ON
• Break-Before-Make Switching
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
- Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns
- Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
o
o
• No Latch-Up
0 C and 75 C. r
is nominally 25Ω for HI-5049 and
ON
HI-5051 and 50Ω for HI-5042 through HI-5047.
• Input MOS Gates are Protected from Electrostatic
Discharge
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
• DTL, TTL, CMOS, PMOS Compatible
Applications
o
very low input and output leakage currents (0.8nA at 25 C).
• High Frequency Switching
• Sample and Hold
This family of switches also features very low power
operation (1.5mW at 25 C).
o
There are 7 devices in this switch series which are
• Digital Filters
differentiated by type of switch action and value of r
(see
ON
• Operational Amplifier Gain Switching
Functional Description Table). The HI-504X and HI-505X
series switches can directly replace IH-5040 series devices,
and are functionally compatible with the DG180 and DG190
family.
Functional Diagram
S
Ordering Information
A
N
P
PART
NUMBER
TEMP. RANGE
o
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
PKG. NO.
F16.3
D
HI1-5042-2
HI1-5043-2
HI1-5043-5
HI3-5043-5
HI9P5043-5
HI1-5047-5
HI1-5049-5
HI1-5051-2
HI1-5051-5
HI3-5051-5
HI9P5051-9
-55 to 125
-55 to 125
0 to 75
F16.3
F16.3
0 to 75
E16.3
M16.15
F16.3
Functional Description
0 to 75
16 Ld SOIC
PART NUMBER
TYPE
r
ON
0 to 75
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
HI-5042
SPDT
50Ω
50Ω
50Ω
25Ω
25Ω
0 to 75
F16.3
HI-5043
HI-5047
HI-5049
HI-5051
Dual SPDT
4PST
-55 to 125
0 to 75
F16.3
F16.3
Dual DPST
Dual SPDT
0 to 75
E16.3
M16.15
-40 to 85
16 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HI-5042 thru HI-5051
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
Dual Control
SPDT
4PST
DUAL SPDT
DUAL DPST
HI-5042 (50Ω)
HI-5047 (50Ω)
HI-5043 (50Ω), HI-5051 (25Ω)
HI-5049 (25Ω)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
S
S
D
S
S
D
D
D
1
1
1
1
2
1
2
2
1
15
14
13
12
11
10
9
15
14
13
12
11
10
9
2
3
4
5
6
7
8
A
A
1
A
V-
V
A
V-
V
1
V-
V
D
S
V-
V
D
S
D
S
D
S
3
1
3
R
R
R
3
4
R
2
1
4
3
4
V
S
V
L
V
V
S
S
L
L
L
V+
V+
V+
D
V+
D
D
4
4
4
A
A
2
2
S
3
S
D
2
S
D
D
2
2
2
3
NOTE: Unused pins may be internally connected. Ground all
unused pins.
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT)
SPDT
DUAL SPDT
HI-5042 (50Ω)
HI-5043 (50Ω)
V
V+
11
V
V+
11
L
L
12
12
16
4
1
3
1
3
16
4
S
S
D
D
S
S
D
D
1
1
1
3
1
3
15
A
1
2
2
10
9
A
S
2
15
8
6
D
D
A
2
4
2
4
5
S
13
14
V-
13
14
V-
V
V
R
R
4PST
HI-5047 (50Ω)
DUAL DPST
HI-5049 (25Ω)
DUAL SPDT
HI-5051 (25Ω)
V
V+
11
V
V+
11
V
L
V+
11
L
L
12
12
12
16
16
1
3
4
16
9
3
1
3
S
S
S
S
S
D
D
D
D
D
D
1
2
1
3
1
3
1
2
1
3
1
3
4
4
1
8
6
S
15
15
A
A
1
1
S
S
D
D
3
4
3
4
10
10
9
5
A
S
A
S
2
2
8
6
9
5
8
6
15
A
D
D
D
D
2
4
2
4
2
4
2
4
5
S
S
13
14
V-
13
14
V-
13
14
V-
V
V
V
R
R
R
2
HI-5042 thru HI-5051
Schematic Diagrams
V+
P15
P16
V
L
P14
QN1
R3
R6
QP1
N13
QP3
QP5
QP4
R4
R5
QP6
QP7
P13
QP8
V+
TO V ’
R
R2
R7
QN2
V
R
QP2
V-
N14
N15
N16
to V ’
L
NOTE: Connect V+ to V for minimizing power consumption when driving from CMOS circuits.
L
TTL/CMOS REFERENCE CIRCUIT (NOTE)
A
(A )
2
1
N1
V+
N3
V-
IN
OUT
P2
N2
P1
A
(A )
2
1
SWITCH CELL
V+
P3
P5
P1
N1
V+
P4
P8
N8
P9
N9
P10
N10
P11
P12
N12
P6
N6
P7
D1
D2
A1
A1
R4
V '
R
A
A2
A2
200Ω
V '
L
N7
N11
P2
N2
V-
N4
N5
N3
V-
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
3
HI-5042 thru HI-5051
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+, V-
Digital and Analog Input Voltage . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA
Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
V
R
CERDIP Package. . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
75
110
90
22
N/A
N/A
o
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range
HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
(SOIC - Lead Tips Only)
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Supplies = +15V, -15V; V = 0V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.8V, V = 5V,
R
AH
AL
L
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded
-2
-5, -9
TYP
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switch ON Time, t
(Note 5)
(Note 5)
(Note 3)
(Note 4)
(Note 4)
25
25
25
25
25
25
25
25
25
25
-
-
370
280
5
500
-
-
-
-
-
-
-
-
-
-
370
280
5
500
ns
ns
ON
Switch OFF Time, t
Charge Injection, Q
OFF Isolation
500
500
OFF
-
20
-
-
-
-
-
-
-
-
-
mV
dB
dB
pF
pF
pF
pF
pF
75
80
-
80
88
11
11
22
5
80
88
11
11
22
5
Crosstalk
-
Input Switch Capacitance, C
-
S(OFF)
Output Switch Capacitance, C
Output Switch Capacitance, C
-
-
D(OFF)
D(ON)
-
-
Digital Input Capacitance, C
-
-
A
Drain To Source Capacitance, C
-
0.5
-
0.5
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
Full
Full
Full
-
2.4
-
-
-
0.8
-
-
2.4
-
-
-
0.8
-
V
V
AL
Input High Threshold, V
AH
Input Leakage Current (High or Low), I
0.01
1.0
0.01
1.0
µA
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
Full
-15
-
+15
-15
-
+15
V
ON Resistance, r
ON
HI-5042 to HI-5047
(Note 2)
(Note 2)
25
Full
25
-
-
-
-
50
-
75
150
45
-
-
-
-
50
-
75
150
45
Ω
Ω
Ω
Ω
HI-5049, HI-5051
25
-
25
-
Full
50
50
Channel-to-Channel Match, ∆r
ON
HI-5042 to HI-5047
25
25
-
-
-
-
2
1
10
5
-
-
-
-
2
1
10
5
Ω
Ω
HI-5049, HI-5051
OFF Input or Output Leakage Current,
= I
25
0.8
100
2
0.8
100
2
nA
nA
I
S(OFF)
D(OFF)
Full
200
200
4
HI-5042 thru HI-5051
Electrical Specifications Supplies = +15V, -15V; V = 0V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.8V, V = 5V,
R
AH
AL
L
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded (Continued)
-2
TYP
0.01
2
-5, -9
TYP
0.01
2
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
MAX
2
MIN
MAX
2
UNITS
nA
ON Leakage Current, I
25
-
-
-
-
D(ON)
Full
200
200
nA
POWER REQUIREMENTS
Quiescent Power Dissipation, P
25
25
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-
1.5
-
mW
mA
mA
mA
mA
mA
D
I+, I-, I , I
-
-
-
-
-
0.2
0.3
0.3
0.3
0.3
-
-
-
-
-
0.3
0.5
0.5
0.5
0.5
L
R
I+, +15V Quiescent Current
I-, -15V Quiescent Current
(Note 5)
(Note 5)
(Note 5)
(Note 5)
Full
Full
Full
Full
I , +5V Quiescent Current
L
I , Ground Quiescent Current
R
NOTES:
2. V
OUT
= ±10V, I
=
1mA.
OUT
3. V = 0V, C = 10nF.
IN
L
4. R = 100Ω, f = 100kHz, V = 2.0V
IN
, C = 5pF.
L
L
P-P
5. V = 0V, V = 5V.
AL AH
o
Test Circuits and Waveforms T = 25 C, V+ = +15V, V- = -15V, V = +5V, V = 0V, V = 3V and V = 0.8V
A
L
R
AH
AL
Unless Otherwise Specified
1mA
V
2
r
=
ON
V
2
1mA
IN
OUT
±V
IN
FIGURE 1A. TEST CIRCUIT
80
60
40
20
0
1.2
1.1
1.0
0.9
0.8
0.7
V
= 0V
IN
V+ = +12V
V- = -12V
V+ = +10V
V- = -10V
V+ = +15V
V- = -15V
0.6
-50
-25
0
25
50
o
75
100
125
0
5
10
15
-5
-15
-10
TEMPERATURE ( C)
ANALOG SIGNAL LEVEL (V)
FIGURE 1B. ON RESISTANCE vs ANALOG SIGNAL LEVEL
FIGURE 1C. NORMALIZED ON RESISTANCE vs TEMPERATURE
FIGURE 1. ON RESISTANCE
5
HI-5042 thru HI-5051
o
Test Circuits and Waveforms T = 25 C, V+ = +15V, V- = -15V, V = +5V, V = 0V, V = 3V and V = 0.8V
A
L
R
AH
AL
Unless Otherwise Specified (Continued)
100nA
10nA
1nA
OFF LEAKAGE CURRENT
I
I
S(OFF)
A
D(OFF)
A
IN
OUT
I
= I
D(OFF)
S(OFF)
±
10V
±10V
ON LEAKAGE CURRENT
IN
OUT
I
D(ON)
100pA
10pA
I
D(ON)
A
±10V
25
50
75
TEMPERATURE ( C)
100
125
o
FIGURE 2A. LEAKAGE CURRENTS vs TEMPERATURE
FIGURE 2. LEAKAGE CURRENTS
FIGURE 2B. TEST CIRCUITS
1.4
1.3
1.2
1.1
1.0
IN
OUT
I
±V
IN
V
IN
r
= ---------
ON
I
0
20
40
60
80
ANALOG CURRENT (mA)
FIGURE 3A. NORMALIZED ON RESISTANCE vs ANALOG
CURRENT
FIGURE 3B. TEST CIRCUIT
FIGURE 3. NORMALIZED ON RESISTANCE
-200
-160
IN
OUT
V
OUT
V
IN
50Ω
2V
P-P
R
R
R
= 100Ω
L
L
-120
-80
V
OUT
---------------
OFF ISOLATION = 20 Log
= 10kΩ
L
V
IN
-40
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FIGURE 4A. OFF ISOLATION vs FREQUENCY
FIGURE 4B. TEST CIRCUIT
FIGURE 4C. OFF ISOLATION
6
HI-5042 thru HI-5051
o
Test Circuits and Waveforms T = 25 C, V+ = +15V, V- = -15V, V = +5V, V = 0V, V = 3V and V = 0.8V
A
L
R
AH
AL
Unless Otherwise Specified (Continued)
200
160
120
80
SWITCHED
CHANNEL
V
IN
50Ω
R
V
L
OUT
2V
P-P
R
L
40
V
IN
---------------
CROSSTALK = 20 Log
V
OUT
0
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FIGURE 5A. CROSSTALK vs FREQUENCY
FIGURE 5B. TEST CIRCUIT
FIGURE 5. CROSSTALK
200
160
120
80
40
0
+10V
-10V
A
TOGGLE
AT 50%
DUTY
V
V
V+
I
V-
I
L
R
I
+
-
L
+5V
+15V -15V
1K
10K
100K
1M
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
FIGURE 6A. POWER CONSUMPTION vs FREQUENCY
FIGURE 6. POWER CONSUMPTION
FIGURE 6B. TEST CIRCUIT
V
AH
V
A
IN
IN
90%
90%
1
OUT 1
OUT 2
+10V
OUT 1
OUT 2
t
ON
t
OFF
2
90%
90%
1K
1K
V
A
t
ON
t
OFF
FIGURE 7A. TEST CIRCUIT
FIGURE 7B. MEASUREMENT POINTS
7
HI-5042 thru HI-5051
o
Test Circuits and Waveforms T = 25 C, V+ = +15V, V- = -15V, V = +5V, V = 0V, V = 3V and V = 0.8V
A
L
R
AH
AL
Unless Otherwise Specified (Continued)
V
A
V
A
OUTPUT
OUTPUT
V
= 0V to 5V
V
= 0V to 10V
A
A
Vertical: 2V/Div.
Vertical: 5V/Div.
Horizontal: 200ns/Div.
Horizontal: 200ns/Div.
FIGURE 7C. WAVEFORMS WITH TTL COMPATIBLE LOGIC
INPUT
FIGURE 7D. WAVEFORMS WITH CMOS COMPATIBLE LOGIC
INPUT
720
660
600
540
480
420
360
720
660
600
540
480
420
t
ON
360
300
240
180
120
60
t
ON
300
240
180
120
60
t
OFF
t
OFF
2.4
3.0
3.6
DIGITAL “HIGH” (V)
4.2
4.8
0
0.5
1.0
1.5
DIGITAL “LOW” (V)
FIGURE 7E. SWITCHING TIMES vs POSITIVE DIGITAL VOLTAGE
FIGURE 7. SWITCH t
FIGURE 7F. SWITCHING TIMES vs NEGATIVE DIGITAL VOLTAGE
AND t
ON
OFF
8
HI-5042 thru HI-5051
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-C-
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
9
HI-5042 thru HI-5051
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
10
HI-5042 thru HI-5051
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Intersil Corporation
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Intersil Ltd.
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11
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