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HI9P0549-9Z [INTERSIL]

Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection; 单16和8 ，差分8通道和4通道CMOS模拟的MUX与Active过压保护
HI9P0549-9Z
型号： HI9P0549-9Z
厂家： Intersil    Intersil
描述：

Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection
单16和8 ，差分8通道和4通道CMOS模拟的MUX与Active过压保护
文件： 总24页 (文件大小：533K)
中文：  中文翻译
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HI-546, HI-547, HI-548, HI-549  
®
Data Sheet  
September 21, 2005  
FN3150.5  
Single 16 and 8, Differential 8-Channel  
and 4-Channel CMOS Analog MUXs with  
Active Overvoltage Protection  
Features  
• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70V  
• No Channel Interaction During Overvoltage  
P-P  
The HI-546, HI-547, HI-548 and HI-549 are analog  
multiplexers with active overvoltage protection and  
• Guaranteed r  
Matching  
ON  
guaranteed r  
matching. Analog input levels may greatly  
• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V  
• Break-Before-Make Switching  
ON  
exceed either power supply without damaging the device or  
disturbing the signal path of other channels. Active  
protection circuitry assures that signal fidelity is maintained  
even under fault conditions that would destroy other  
multiplexers.  
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V  
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns  
• Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Analog inputs can withstand constant 70V  
levels with  
P-P  
±15V supplies. Digital inputs will also sustain continuous  
faults up to 4V greater than either supply. In addition, signal  
sources are protected from short circuiting should  
Applications  
• Data Acquisition  
• Industrial Controls  
• Telemetry  
multiplexer supply loss occur. Each input presents 1kΩ of  
resistance under this condition. These features make the  
HI-546, HI-547, HI-548 and HI-549 ideal for use in systems  
where the analog inputs originate from external equipment  
or separately powered circuitry. All devices are fabricated  
with 44V Dielectrically Isolated CMOS technology. The  
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel  
differential, the HI-548 is a single 8-Channel and the HI-549  
is a 4-Channel differential device. If input overvoltage  
protection is not needed the HI-506/507/508/509  
multiplexers are recommended. For further information see  
Application Notes AN520 and AN521.  
For MIL-STD-883 compliant parts, request the HI-546/883,  
HI-547/883, HI-548/883 and HI-549/883 datasheets.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
HI-546, HI-547, HI-548, HI-549  
Ordering Information (Continued)  
Ordering Information  
TEMP.  
TEMP.  
PART  
NUMBER  
PART  
MARKING  
RANGE  
PKG.  
PART  
NUMBER  
PART  
MARKING  
RANGE  
PKG.  
o
o
( C)  
PACKAGE DWG. #  
( C)  
PACKAGE DWG. #  
HI9P0548-5** HI9P548-5  
0 to 75  
0 to 75  
16 Ld SOIC  
M16.15  
M16.15  
HI1-0546-5  
HI1-0546-2  
HI3-0546-5  
HI4P0546-5  
HI1-546-5  
HI1-546-2  
HI3-546-5  
HI4P546-5  
HI4P546-5Z  
0 to 75  
28 Ld CERDIP F28.6  
HI9P0548-5Z** HI9P548-5Z  
(Note)  
16 Ld SOIC  
(Pb-free)  
-55 to 125 28 Ld CERDIP F28.6  
0 to 75  
0 to 75  
0 to 75  
28 Ld PDIP  
28 Ld PLCC  
E28.6  
HI9P0548-9  
HI9P548-9  
-40 to 85 16 Ld SOIC  
M16.15  
M16.15  
N28.45  
N28.45  
HI9P0548-9Z  
(Note)  
HI9P548-9Z  
-40 to 85 16 Ld SOIC  
(Pb-free)  
HI4P0546-5Z  
(Note)  
28 Ld PLCC  
(Pb-free)  
HI1-0549-2  
HI3-0549-5  
HI4P0549-5  
HI1-549-2  
HI3-549-5  
HI4P549-5  
HI4P549-5Z  
-55 to 125 16 Ld CERDIP F16.3  
HI9P0546-9** HI9P546-9  
-40 to 85 28 Ld SOIC  
M28.3  
M28.3  
0 to 75  
0 to 75  
0 to 75  
16 Ld PDIP  
20 Ld PLCC  
E16.3  
HI9P0546-9Z** HI9P546-9Z  
(Note)  
-40 to 85 28 Ld SOIC  
(Pb-free)  
N20.35  
N20.35  
HI4P0549-5Z  
(Note)  
20 Ld PLCC  
(Pb-free)  
HI1-0547-5  
HI3-0547-5  
HI1-547-5  
HI3-547-5  
HI3-0547-5Z  
0 to 75  
0 to 75  
0 to 75  
28 Ld CERDIP F28.6  
28 Ld PDIP  
E28.6  
E28.6  
HI9P0549-9  
HI9P549-9  
-40 to 85 16 Ld SOIC  
M16.15  
M16.15  
HI3-0547-5Z  
(Note)  
28 Ld PDIP*  
(Pb-free)  
HI9P0549-9Z  
(Note)  
HI9P549-9Z  
-40 to 85 16 Ld SOIC  
(Pb-free)  
HI4P0547-5  
HI4P547-5  
0 to 75  
0 to 75  
28 Ld PLCC  
N28.45  
N28.45  
*Pb-free PDIPs can be used for through hole wave solder processing  
only. They are not intended for use in Reflow solder processing  
applications.  
HI4P0547-5Z  
(Note)  
HI4P547-5Z  
28 Ld PLCC  
(Pb-free)  
HI9P0547-9  
HI9P547-9  
-40 to 85 28 Ld SOIC  
M28.3  
M28.3  
**Add “96” suffix for tape and reel.  
HI9P0547-9Z  
(Note)  
HI9P547-9Z  
-40 to 85 28 Ld SOIC  
(Pb-free)  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
HI1-0548-2  
HI1-0548-5  
HI3-0548-5  
HI4P0548-5  
HI1-548-2  
HI1-548-5  
HI3-548-5  
HI4P548-5  
-55 to 125 16 Ld CERDIP F16.3  
0 to 75  
0 to 75  
0 to 75  
16 Ld CERDIP F16.3  
16 Ld PDIP  
20 Ld PLCC  
E16.3  
N20.35  
Pinouts  
HI-546 (CERDIP, PDIP, SOIC)  
HI-547 (CERDIP, PDIP, SOIC)  
TOP VIEW  
TOP VIEW  
+V  
1
2
3
4
5
6
7
8
9
28 OUT A  
27 -V  
+V  
1
2
3
4
5
6
7
8
9
28 OUT  
27 -V  
SUPPLY  
SUPPLY  
NC  
OUT B  
SUPPLY  
SUPPLY  
26 IN 8A  
25 IN 7A  
24 IN 6A  
23 IN 5A  
22 IN 4A  
21 IN 3A  
NC  
IN 8B  
IN 7B  
IN 6B  
IN 5B  
IN 4B  
IN 3B  
NC  
IN 16  
IN 15  
IN 14  
IN 13  
IN 12  
IN 11  
26 IN 8  
25 IN 7  
24 IN 6  
23 IN 5  
22 IN 4  
21 IN 3  
20  
IN 2A  
20  
IN 2  
IN 2B 10  
IN 1B 11  
GND 12  
19 IN 1A  
IN 10 10  
IN 9 11  
GND 12  
19 IN 1  
18 ENABLE  
18 ENABLE  
17 ADDRESS A  
16 ADDRESS A  
15 ADDRESS A  
17 ADDRESS A  
16 ADDRESS A  
15 ADDRESS A  
0
1
2
0
1
2
V
13  
V
13  
REF  
REF  
NC 14  
ADDRESS A 14  
3
2
HI-546, HI-547, HI-548, HI-549  
Pinouts (Continued)  
HI-546 (PLCC)  
TOP VIEW  
HI-547 (PLCC)  
TOP VIEW  
4
3
2
1
28 27 26  
4
3
2
1
28 27 26  
5
6
25  
24  
23  
22  
21  
20  
IN 7B  
IN 6B  
IN 5B  
IN 4B  
IN 3B  
IN 2B  
IN 1B  
5
6
25 IN 7  
IN 7A  
IN 6A  
IN 5A  
IN 4A  
IN 3A  
IN 2A  
IN 15  
IN 14  
IN 13  
IN 12  
IN 11  
IN 10  
IN 9  
24  
23  
22  
21  
20  
19  
IN 6  
IN 5  
IN 4  
IN 3  
IN 2  
IN 1  
7
7
8
8
9
9
10  
11  
10  
11  
19 IN 1A  
12 13 14 15 16 17 18  
12 13 14 15 16 17 18  
HI-548 (CERDIP, PDIP, SOIC)  
HI-549 (CERDIP, PDIP, SOIC)  
TOP VIEW  
TOP VIEW  
A
1
2
3
4
5
6
7
8
16 A  
15 A  
A
1
2
3
4
5
6
7
8
16 A  
1
0
1
2
0
ENABLE  
ENABLE  
15 GND  
14 +V  
SUPPLY  
-V  
14 GND  
13 +V  
-V  
SUPPLY  
IN 1  
SUPPLY  
IN 1A  
13 IN 1B  
12 IN 2B  
11 IN 3B  
10 IN 4B  
SUPPLY  
IN 2  
IN 3  
IN 4  
OUT  
12 IN 5  
11 IN 6  
10 IN 7  
IN 2A  
IN 3A  
IN 4A  
9
IN 8  
9
OUT B  
OUT A  
HI-548 (PLCC)  
HI-549 (PLCC)  
TOP VIEW  
TOP VIEW  
3
2
1
20 19  
3
2
1
20 19  
-V  
+V  
4
5
6
7
8
18  
17  
16  
SUPPLY  
IN 1A  
SUPPLY  
IN 1B  
NC  
4
5
6
7
8
18  
17  
16  
15  
14  
-V  
SUPPLY  
IN 1  
GND  
+V  
SUPPLY  
NC  
IN 2A  
IN 3A  
NC  
IN 2  
IN 3  
NC  
15 IN 2B  
14 IN 3B  
IN 5  
IN 6  
9
10 11 12 13  
9
10 11 12 13  
3
HI-546, HI-547, HI-548, HI-549  
TRUTH TABLE HI-547 (Continued)  
TRUTH TABLE HI-546  
A
A
A
0
EN  
H
“ON” CHANNEL PAIR  
A
A
A
A
0
EN  
L
“ON” CHANNEL  
2
1
3
2
1
H
L
L
5
6
7
8
X
X
X
X
None  
1
H
H
H
L
H
H
H
L
H
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
L
H
H
L
3
L
L
H
L
4
L
H
H
H
H
L
5
TRUTH TABLE HI-548  
L
L
H
L
6
A
A
A
0
EN  
L
“ON” CHANNEL  
2
1
L
H
H
L
7
X
L
X
L
X
None  
L
H
L
8
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
H
H
H
H
H
H
H
H
9
L
L
L
L
H
L
10  
11  
12  
13  
14  
15  
16  
L
H
H
L
L
H
H
L
L
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
L
H
H
H
H
H
H
TRUTH TABLE HI-549  
TRUTH TABLE HI-547  
A
A
EN  
L
“ON” CHANNEL PAIR  
1
0
A
A
A
0
EN  
L
“ON” CHANNEL PAIR  
X
X
None  
2
1
X
X
X
None  
L
L
L
H
L
H
1
2
3
4
L
L
L
L
L
L
L
H
L
H
1
2
3
4
H
H
H
H
H
H
H
H
H
H
H
H
Functional Diagrams  
HI-546  
HI-547  
OUT  
A
OUT  
1K  
1K  
1K  
IN 1  
IN 2  
IN 1A  
1K  
1K  
OUT  
B
IN 8A  
IN 1B  
DECODER/  
DRIVER  
1K  
1K  
DECODER/  
DRIVER  
IN 8B  
IN 16  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
5V  
REF  
LEVEL  
SHIFT  
ISOLATION  
ISOLATION  
† DIGITAL INPUT  
†
†
†
†
† DIGITAL INPUT  
† † † †  
†
PROTECTION  
PROTECTION  
V
A
A
A
2
EN  
V
A
A
A
A EN  
3
REF  
0
1
REF  
0
1
2
4
HI-546, HI-547, HI-548, HI-549  
Functional Diagrams (Continued)  
HI-548  
HI-549  
OUT  
A
OUT  
1K  
1K  
IN 1A  
IN 1  
1K  
1K  
1K  
OUT  
B
IN 4A  
IN 1B  
IN 2  
DECODER/  
DRIVER  
1K  
1K  
DECODER/  
DRIVER  
IN 4B  
IN 8  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
OVERVOLTAGE  
CLAMP AND  
SIGNAL  
5V  
REF  
LEVEL  
SHIFT  
5V  
REF  
LEVEL  
SHIFT  
ISOLATION  
ISOLATION  
† DIGITAL INPUT  
†
†
†
† DIGITAL INPUT  
†
†
†
†
PROTECTION  
PROTECTION  
A
A
EN  
A
A
1
A
EN  
0
1
0
2
Schematic Diagrams  
ADDRESS DECODER  
V+  
P
P
P
P
P
P
P
N
TO P-CHANNEL  
DEVICE OF  
THE SWITCH  
N
N
A
OR A  
0
0
N
N
N
N
A
OR A  
1
1
TO N-CHANNEL  
DEVICE OF  
THE SWITCH  
A
OR A  
2
2
A
OR A  
3
3
ENABLE  
DELETE A OR A INPUT FOR HI-547, HI-548, HI-549  
3
3
DELETE A OR A INPUT FOR HI-549  
2
2
V-  
5
HI-546, HI-547, HI-548, HI-549  
Schematic Diagrams (Continued)  
MULTIPLEX SWITCH  
FROM  
DECODE  
OVERVOLTAGE PROTECTION  
N
V+  
P
Q5  
D6  
D7  
D4  
D5  
R11  
1K  
N
OUT  
IN  
N
Q6  
V-  
P
FROM  
DECODE  
6
HI-546, HI-547, HI-548, HI-549  
Schematic Diagrams (Continued)  
ADDRESS INPUT BUFFER AND LEVEL SHIFTER  
TTL REFERENCE  
CIRCUIT  
V+  
R10  
R9  
Q1  
V
REF  
Q4  
D3  
GND  
LEVEL SHIFTER  
V+  
P
N
P
P
P
P
P
P
P
P
OVERVOLTAGE  
P
R2  
R3  
PROTECTION  
LEVEL  
R5  
R7  
R8  
SHIFTED  
ADDRESS  
TO  
V+  
D2  
R4  
DECODE  
R6  
N
N
N
N
N
N
N
N
R1  
200  
Ω
D1  
N
V-  
V-  
GND  
ADD  
IN  
7
HI-546, HI-547, HI-548, HI-549  
Absolute Maximum Ratings  
Thermal Information  
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V  
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V  
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
16 Ld CERDIP Package. . . . . . . . . . .  
28 Ld CERDIP Package. . . . . . . . . . .  
28 Ld PDIP Package*. . . . . . . . . . . . .  
16 Ld PDIP Package . . . . . . . . . . . . .  
28 Ld PLCC Package. . . . . . . . . . . . .  
20 Ld PLCC Package. . . . . . . . . . . . .  
28 Ld SOIC Package . . . . . . . . . . . . .  
16 Ld SOIC Package . . . . . . . . . . . . .  
Maximum Junction Temperature  
85  
55  
60  
90  
70  
80  
75  
105  
32  
18  
Digital Input Voltage (V , V ) . . . . . . . . . . . . . (V-) -4V to (V+) +4V  
EN  
A
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Analog Signal (V , V  
). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V  
IN OUT  
or 20mA, Whichever Occurs First  
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA  
Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA  
Operating Conditions  
o
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C  
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C  
Temperature Ranges  
HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C  
HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
o
o
o
o
o
o
o
o
o
o
(PLCC, SOIC - Lead Tips Only)  
*Pb-free PDIPs can be used for through hole wave solder processing  
only. They are not intended for use in Reflow solder processing  
applications.  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications Supplies = +15V, -15V; V  
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V; Unless  
AH AL  
Otherwise Specified. For Test Conditions, Consult Test Circuits Section  
REF  
-2  
-5, -9  
TYP  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MIN  
TYP  
MAX  
MIN  
MAX  
UNITS  
SWITCHING CHARACTERISTICS  
Access Time, t  
25  
Full  
25  
-
-
0.5  
-
-
-
-
0.5  
-
-
µs  
µs  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
dB  
pF  
A
1.0  
1.0  
Break-Before Make Delay, t  
25  
-
80  
300  
-
-
25  
-
80  
300  
-
-
OPEN  
Enable Delay (ON), t  
25  
500  
-
ON(EN)  
Full  
25  
-
1000  
-
1000  
Enable Delay (OFF), t  
Settling Time  
-
300  
-
500  
-
300  
-
-
OFF(EN)  
Full  
25  
-
1000  
-
1000  
To 0.1%  
-
1.2  
3.5  
68  
10  
-
-
-
-
-
1.2  
3.5  
68  
10  
-
-
-
-
To 0.01%  
Note 6  
25  
-
-
Off Isolation  
25  
50  
-
50  
-
Channel Input Capacitance, C  
25  
S(OFF)  
Channel Output Capacitance C  
HI-546  
D(OFF)  
25  
25  
25  
25  
25  
-
-
-
-
-
52  
30  
25  
12  
0.1  
-
-
-
-
-
-
-
-
-
-
52  
30  
25  
12  
0.1  
-
-
-
-
-
pF  
pF  
pF  
pF  
pF  
HI-547  
HI-548  
HI-549  
Input to Output Capacitance, C  
DS(OFF)  
DIGITAL INPUT CHARACTERISTICS  
Input Low Threshold, TTL Drive, V  
Full  
Full  
25  
-
4.0  
-
-
-
-
0.8  
-
-
4.0  
-
-
-
-
0.8  
-
V
V
V
AL  
Input High Threshold, V (Note 8)  
AH  
MOS Drive, V (HI-546/547 Only)  
AL  
V
= 10V  
0.8  
0.8  
REF  
8
HI-546, HI-547, HI-548, HI-549  
Electrical Specifications Supplies = +15V, -15V; V  
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V; Unless  
AH AL  
REF  
Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)  
-2  
-5, -9  
TEST  
CONDITIONS  
TEMP  
( C)  
o
PARAMETER  
MIN  
6.0  
-
TYP  
MAX  
-
MIN  
6.0  
-
TYP  
MAX  
-
UNITS  
V
MOS Drive, V (HI-546/547 Only)  
AH  
V
= 10V  
25  
-
-
-
-
REF  
Input Leakage Current (High or Low), I  
Note 5  
Full  
1.0  
1.0  
µA  
A
ANALOG CHANNEL CHARACTERISTICS  
Analog Signal Range, V  
Full  
25  
-15  
-
-
+15  
1.5  
1.8  
7.0  
-
-15  
-
-
+15  
1.8  
2.0  
7.0  
-
V
IN  
On Resistance, r  
Note 2  
1.2  
1.5  
kΩ  
kΩ  
%
ON  
Full  
25  
-
1.5  
-
1.8  
∆r , (Any Two Channels)  
-
-
-
-
ON  
Off Input Leakage Current, I  
Note 3  
Note 3  
25  
-
0.03  
-
0.03  
nA  
nA  
nA  
nA  
nA  
nA  
nA  
nA  
µA  
nA  
nA  
nA  
nA  
nA  
nA  
S(OFF)  
Full  
25  
-
-
50  
-
-
50  
-
Off Output Leakage Current, I  
-
0.1  
-
-
0.1  
D(OFF)  
HI-546  
HI-547  
HI-548  
HI-549  
Full  
Full  
Full  
Full  
25  
-
-
300  
200  
200  
100  
-
-
-
300  
200  
200  
100  
-
-
-
-
-
-
-
-
-
-
-
-
-
I
With Input Overvoltage Applied  
Note 4  
Note 3  
-
4.0  
-
4.0  
D(OFF)  
Full  
25  
-
-
2.0  
-
-
-
-
On Channel Leakage Current, I  
-
0.1  
-
0.1  
-
D(ON)  
HI-546  
HI-547  
HI-548  
HI-549  
Full  
Full  
Full  
Full  
Full  
-
-
-
-
-
-
300  
200  
200  
100  
50  
-
-
-
-
-
-
300  
200  
200  
100  
50  
-
-
-
-
-
-
Differential Off Output Leakage Current  
(HI-547, HI-549 Only)  
-
-
I
DIFF  
POWER SUPPLY CHARACTERISTICS  
Power Dissipation, P  
Current, I+  
Full  
Full  
Full  
-
-
-
7.5  
0.5  
-
-
-
-
7.5  
0.5  
-
mW  
mA  
mA  
D
Note 7  
Note 7  
2.0  
1.0  
2.0  
1.0  
Current, I-  
0.02  
0.02  
NOTES:  
±
2. V  
OUT  
= ±10V, I  
=
100µA.  
OUT  
3. 10nA is the practical lower limit for high speed measurement in the production test environments.  
4. Analog Overvoltage = ±33V.  
o
5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25 C.  
6. V = 0.8V, R = 1K, C = 15pF, V = 7V , f = 100kHz.  
EN  
L
L
S
RMS  
7. V , V = 0V or 4V.  
EN  
A
8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended.  
9
HI-546, HI-547, HI-548, HI-549  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
= Open, Unless Otherwise Specified  
REF  
A
SUPPLY  
AH AL  
100µA  
V
2
IN  
OUT  
r
V
2
V
=
IN  
ON  
100µA  
FIGURE 1A. ON RESISTANCE TEST CIRCUIT  
1.4  
o
1.3  
1.2  
1.1  
125 C  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
o
25 C  
1.0  
0.9  
o
-55 C  
0.8  
0.7  
0.6  
-10  
-8  
-6  
-4  
-2  
0
2
4
6
8
10  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
ANALOG INPUT (V)  
SUPPLY VOLTAGE (±V)  
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY  
VOLTAGE  
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE  
FIGURE 1. ON RESISTANCE  
100nA  
10nA  
1nA  
OFF OUTPUT  
CURRENT  
+0.8V  
EN  
I
ON LEAKAGE  
CURRENT  
D(OFF)  
OUT  
I
D(ON)  
I
D(OFF)  
A
±
±10V  
10V  
OFF INPUT  
100pA  
10pA  
LEAKAGE CURRENT  
I
S(OFF)  
25  
50  
75  
100  
125  
o
TEMPERATURE ( C)  
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE  
FIGURE 2B. I  
TEST CIRCUIT (NOTE 9)  
D(OFF)  
10  
HI-546, HI-547, HI-548, HI-549  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
AH AL REF  
= Open, Unless Otherwise Specified (Continued)  
A
SUPPLY  
OUT  
OUT  
I
A
S(OFF)  
+0.8V  
A
I
D(ON)  
EN  
EN  
±
±10V  
10V  
±
±10V  
10V  
4V  
FIGURE 2C. I  
TEST CIRCUIT (NOTE 9)  
FIGURE 2D. I  
TEST CIRCUIT (NOTE 9)  
D(ON)  
S(OFF)  
NOTE:  
±
±
9. Two measurements per channel: ±10V and 10V. (Two measurements per device for I  
: ±10V and 10V.)  
D(OFF)  
FIGURE 2. LEAKAGE CURRENTS  
18  
ANALOG INPUT  
CURRENT (I  
)
15  
12  
9
5
4
3
2
1
0
IN  
I
I
D(OFF)  
A
A
IN  
6
±V  
IN  
OUTPUT OFF LEAKAGE  
3
CURRENT ID  
(OFF)  
0
15  
18  
21  
24  
27  
30  
33  
36  
ANALOG INPUT OVERVOLTAGE (±V)  
FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF  
LEAKAGE CURRENT vs ANALOG INPUT  
OVER-VOLTAGE  
FIGURE 3B. TEST CIRCUIT  
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS  
±14  
±12  
±10  
±8  
o
-55 C  
o
25 C  
o
125 C  
±6  
A
±V  
IN  
±4  
±2  
0
0
2
4
6
8
10  
12  
14  
VOLTAGE ACROSS SWITCH (±V)  
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE  
FIGURE 4. ON CHANNEL CURRENT  
FIGURE 4B. TEST CIRCUIT  
11  
HI-546, HI-547, HI-548, HI-549  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
= Open, Unless Otherwise Specified (Continued)  
A
SUPPLY AH AL REF  
8
6
4
2
0
+15V/+10V  
+I  
SUPPLY  
A
V+  
±10V/±5V  
A
A
A
A
IN 1  
3
2
1
0
HI-546†  
IN 2  
THRU  
IN 15  
V
= ± 15V  
SUPPLY  
V
50Ω  
A
V
= ± 10V  
SUPPLY  
±
±
IN 16  
10V/ 5V  
EN  
OUT  
V-  
+4V  
GND  
10MΩ  
SUPPLY  
-15V/-10V  
14pF  
-I  
A
1K  
10K  
100K  
1M  
10M  
TOGGLE FREQUENCY (Hz)  
†Similar connection for HI-547/HI-548/HI-549.  
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY  
FIGURE 5. DYNAMIC SUPPLY CURRENT  
FIGURE 5B. TEST CIRCUIT  
+15V  
900  
800  
700  
600  
500  
400  
300  
V
INPUT  
A
2V/DIV.  
V
V
= OPEN FOR LOGIC HIGH LEVEL <
REF  
REF  
= LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V  
ON  
V
V+  
IN 1  
REF  
±10V  
A
A
A
A
3
2
1
0
S
S
ON  
1
16  
IN 2 THRU  
IN 15  
50Ω  
OUTPUT  
0.5V/DIV.  
HI-546†  
±
10V  
IN 16  
EN  
OUT  
+4V  
V-  
GND  
10kΩ  
50pF  
100ns/DIV.  
-15V  
3
4
5
6
7
8
9
10  
11 12 13 14  
15  
LOGIC LEVEL (HIGH) (V)  
†Similar connection for HI-547/HI-548/HI-549.  
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)  
FIGURE 6B. TEST CIRCUIT  
V
INPUT  
A
V
= 4.0V  
2V/DIV.  
AH  
ADDRESS  
DRIVE (V )  
A
50%  
0V  
S
ON  
1
+10V  
OUTPUT  
-10V  
OUTPUT  
5V/DIV.  
10%  
S
ON  
16  
t
A
200ns/DIV.  
FIGURE 6C. MEASUREMENT POINTS  
FIGURE 6D. WAVEFORMS  
FIGURE 6. ACCESS TIME  
12  
HI-546, HI-547, HI-548, HI-549  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V = Open, Unless Otherwise Specified (Continued)  
AH AL REF  
A
SUPPLY  
A
A
3
2
HI-546†  
+5V  
V
= 4V  
AH  
IN 1  
IN 2 THRU  
IN 15  
ADDRESS  
DRIVE (V )  
50Ω  
V
A
A
A
1
0
A
0V  
IN 16  
V
OUT  
OUTPUT  
+4V  
EN  
OUT  
GND  
50pF  
1kΩ  
50%  
50%  
t
OPEN  
†Similar connection for HI-547/HI-548/HI-549  
FIGURE 7A. TEST CIRCUIT  
FIGURE 7B. MEASUREMENT POINTS  
FIGURE 7C. WAVEFORMS  
FIGURE 7. BREAK-BEFORE-MAKE DELAY  
A
A
3
2
HI-546†  
+10V  
IN 1  
V
= 4V  
AH  
ENABLE DRIVE  
(V )  
A
50%  
50%  
IN 2 THRU  
IN16  
A
A
1
0
0V  
V
OUT  
90%  
EN  
OUT  
OUTPUT  
10%  
GND  
V
50pF  
50Ω  
1kΩ  
A
0V  
t
ON(EN)  
t
OFF(EN)  
†Similar connection for HI-547/HI-548/HI-549  
FIGURE 8A. TEST CIRCUIT  
FIGURE 8B. MEASUREMENT POINTS  
13  
HI-546, HI-547, HI-548, HI-549  
o
Test Circuits and Waveforms T = 25 C, V  
= ±15V, V = 4V, V = 0.8V, V  
= Open, Unless Otherwise Specified (Continued)  
A
SUPPLY  
AH  
AL  
REF  
ENABLE  
DRIVE  
2V/DIV.  
DISABLED  
OUTPUT  
2V/DIV.  
ENABLED (S ON)  
1
100ns/DIV.  
FIGURE 8C. WAVEFORMS  
FIGURE 8. ENABLE DELAYS  
14  
HI-546, HI-547, HI-548, HI-549  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
83.9 mils x 159 mils  
Type: Nitride Over Silox  
Nitride Thickness: 3.5kÅ ±1kÅ  
Silox Thickness: 12kÅ ±2kÅ  
METALLIZATION:  
Type: CuAl  
Thickness: 16kÅ ±2kÅ  
WORST CASE CURRENT DENSITY:  
5
2
1.4 x 10 A/cm  
SUBSTRATE POTENTIAL (NOTE):  
TRANSISTOR COUNT:  
-V  
SUPPLY  
485  
PROCESS:  
CMOS-DI  
NOTE: The substrate appears resistive to the -V  
SUPPLY  
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a  
conductor at -V  
potential.  
SUPPLY  
Metallization Mask Layouts  
HI-546  
HI-547  
NC  
V
(14)  
A
A
V
A
A
(17)  
A
A
(17)  
A
1
EN  
(18)  
GND  
(12)  
EN  
(18)  
GND  
(12)  
0
1
2
3
REF  
0
2
REF  
(13)  
(16) (15)  
(14) (13)  
(16) (15)  
IN 1  
(19)  
IN 9  
(11)  
IN 1B  
(11)  
IN 1A  
(19)  
IN 2B  
(10)  
IN 2A  
(20)  
IN 2  
(20)  
IN 10  
(10)  
IN 3  
(21)  
IN 11  
(9)  
IN 3A  
(21)  
IN 3B  
(9)  
IN 4A  
(22)  
IN 4B  
(8)  
IN 4  
(22)  
IN 12  
(8)  
IN 5  
(23)  
IN 13  
(7)  
IN 5A  
(23)  
IN 5B  
(7)  
IN 6  
(24)  
IN 14  
(6)  
IN 6A  
(24)  
IN 6B  
(6)  
IN 7  
(25)  
IN 15  
(5)  
IN 7A  
(25)  
IN 7B  
(5)  
IN 8  
(26)  
IN 16  
(4)  
IN 8A  
(26)  
IN 8B  
(4)  
V- (27)  
OUT (28)  
+V (1)  
NC (2)  
V- (27)  
OUT A (28)  
+V (1)  
OUT B(2)  
15  
HI-546, HI-547, HI-548, HI-549  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
83 mils x 108 mils  
Type: Nitride Over Silox  
Nitride Thickness: 3.5kÅ ±1kÅ  
Silox Thickness: 12kÅ ±2kÅ  
METALLIZATION:  
Type: CuAl  
Thickness: 16kÅ ±2kÅ  
WORST CASE CURRENT DENSITY:  
5
1.4 x 10 A/cm  
SUBSTRATE POTENTIAL (NOTE):  
TRANSISTOR COUNT:  
-V  
SUPPLY  
253  
PROCESS:  
CMOS-DI  
NOTE: The substrate appears resistive to the -V  
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a  
SUPPLY  
conductor at -V  
SUPPLY  
potential.  
Metallization Mask Layouts  
HI-548  
HI-549  
IN 6 IN 7 IN 8  
(11) (10) (9)  
OUT  
(8)  
IN 4 IN 3  
IN 3B IN 4B OUT B  
OUT A IN 4A IN 3A  
(8) (7) (6)  
(7)  
(6)  
(11) (10)  
(9)  
IN 5  
(12)  
IN 2  
(5)  
IN 2B  
(12)  
IN 2A  
(5)  
+V  
(13)  
IN 1  
(4)  
IN 1B  
(13)  
IN 1A  
(4)  
GND  
(14)  
-V  
(3)  
+V  
(14)  
-V  
(3)  
A
2
(15)  
A
A
GND  
(15)  
A
A
0
EN  
(2)  
EN  
(2)  
1
0
1
(16) (1)  
(16) (1)  
16  
HI-546, HI-547, HI-548, HI-549  
17  
HI-546, HI-547, HI-548, HI-549  
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)  
c1 LEAD FINISH  
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)  
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE  
-D-  
E
-A-  
INCHES  
MIN  
MILLIMETERS  
BASE  
(c)  
METAL  
SYMBOL  
MAX  
0.232  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
1.490  
0.610  
MIN  
-
MAX  
5.92  
NOTES  
b1  
A
b
-
-
M
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
0.66  
2
-B-  
b1  
b2  
b3  
c
0.58  
3
SECTION A-A  
bbb  
C A - B  
D
D
S
S
S
1.65  
-
1.14  
4
BASE  
PLANE  
Q
0.46  
2
A
-C-  
SEATING  
PLANE  
c1  
D
0.38  
3
L
α
37.85  
15.49  
5
S1  
b2  
eA  
A A  
e
E
0.500  
12.70  
5
b
C A - B  
eA/2  
aaa M C A - B S D S  
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.600 BSC  
0.300 BSC  
15.24 BSC  
7.62 BSC  
-
ccc  
D
S
M
S
-
NOTES:  
0.125  
0.200  
0.060  
-
3.18  
5.08  
1.52  
-
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.38  
0.13  
6
S1  
7
o
o
o
o
90  
105  
90  
105  
-
α
aaa  
bbb  
ccc  
M
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
2, 3  
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
N
28  
28  
Rev. 0 4/94  
5. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
6. Dimension Q shall be measured from the seating plane to the  
base plane.  
7. Measure dimension S1 at all four corners.  
8. N is the maximum number of terminal positions.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
18  
HI-546, HI-547, HI-548, HI-549  
Dual-In-Line Plastic Packages (PDIP)  
E28.6 (JEDEC MS-011-AB ISSUE B)  
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INCHES  
MILLIMETERS  
INDEX  
AREA  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.250  
-
MIN  
-
MAX  
6.35  
-
NOTES  
-B-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.125  
0.014  
0.030  
0.008  
1.380  
0.005  
0.600  
0.485  
0.39  
3.18  
0.356  
0.77  
0.204  
4
D
E
0.195  
0.022  
0.070  
0.015  
1.565  
-
4.95  
0.558  
1.77  
0.381  
39.7  
-
-
BASE  
PLANE  
A2  
A
-C-  
-
SEATING  
PLANE  
B1  
C
8
L
C
L
-
D1  
B1  
eA  
A1  
A
D1  
e
D
35.1  
5
eC  
C
B
D1  
E
0.13  
15.24  
12.32  
5
eB  
0.010 (0.25) M  
C
B S  
0.625  
0.580  
15.87  
14.73  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and  
Metric dimensions, the inch dimensions control.  
0.100 BSC  
0.600 BSC  
2.54 BSC  
15.24 BSC  
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
-
0.700  
0.200  
-
17.78  
5.08  
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication No. 95.  
L
0.115  
2.93  
4
9
4. Dimensions A, A1 and L are measured with the package seated in  
N
28  
28  
JEDEC seating plane gauge GS-3.  
Rev. 1 12/00  
5. D, D1, and E1 dimensions do not include mold flash or protrusions.  
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).  
e
6. E and  
are measured with the leads constrained to be perpendic-  
A
-C-  
ular to datum  
.
7. e and e are measured at the lead tips with the leads unconstrained.  
B
C
e
must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar  
protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,  
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).  
19  
HI-546, HI-547, HI-548, HI-549  
Plastic Leaded Chip Carrier Packages (PLCC)  
0.042 (1.07)  
0.048 (1.22)  
N28.45 (JEDEC MS-018AB ISSUE A)  
0.042 (1.07)  
0.056 (1.42)  
0.004 (0.10)  
C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE  
PIN (1) IDENTIFIER  
0.025 (0.64)  
0.045 (1.14)  
0.050 (1.27) TP  
INCHES  
MILLIMETERS  
R
C
L
SYMBOL  
MIN  
MAX  
MIN  
4.20  
MAX  
4.57  
NOTES  
A
A1  
D
0.165  
0.090  
0.485  
0.450  
0.191  
0.485  
0.450  
0.191  
0.180  
0.120  
0.495  
0.456  
0.219  
0.495  
0.456  
0.219  
-
2.29  
3.04  
-
-
D2/E2  
D2/E2  
12.32  
11.43  
4.86  
12.57  
11.58  
5.56  
C
L
D1  
D2  
E
3
E1 E  
4, 5  
-
12.32  
11.43  
4.86  
12.57  
11.58  
5.56  
VIEW “A”  
E1  
E2  
N
3
4, 5  
6
0.020 (0.51)  
MIN  
28  
28  
A1  
D1  
D
Rev. 2 11/97  
A
SEATING  
PLANE  
0.020 (0.51) MAX  
3 PLCS  
-C-  
0.026 (0.66)  
0.032 (0.81)  
0.013 (0.33)  
0.021 (0.53)  
0.025 (0.64)  
MIN  
0.045 (1.14)  
MIN  
VIEW “A” TYP.  
NOTES:  
1. Controlling dimension: INCH. Converted millimeter dimensions are  
not necessarily exact.  
2. Dimensions and tolerancing per ANSI Y14.5M-1982.  
3. Dimensions D1 and E1 do not include mold protrusions. Allowable  
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1  
and E1 include mold mismatch and are measured at the extreme  
material condition at the body parting line.  
-C-  
4. To be measured at seating plane  
contact point.  
5. Centerline to be determined where center leads exit plastic body.  
6. “N” is the number of terminal positions.  
20  
HI-546, HI-547, HI-548, HI-549  
Small Outline Plastic Packages (SOIC)  
M28.3 (JEDEC MS-013-AE ISSUE C)  
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE  
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
INCHES  
MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
2.35  
0.10  
0.33  
0.23  
MAX  
2.65  
0.30  
0.51  
0.32  
18.10  
7.60  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0926  
0.0040  
0.013  
0.1043  
0.0118  
0.0200  
0.0125  
-
-
1
2
3
L
9
SEATING PLANE  
A
0.0091  
0.6969  
0.2914  
-
0.7125 17.70  
3
-A-  
o
h x 45  
D
0.2992  
7.40  
4
0.05 BSC  
1.27 BSC  
-
-C-  
α
H
h
0.394  
0.01  
0.419  
0.029  
0.050  
10.00  
0.25  
0.40  
10.65  
0.75  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
0.016  
6
0.25(0.010) M  
C
A M B S  
N
α
28  
28  
7
o
o
o
o
0
8
0
8
-
NOTES:  
Rev. 0 12/93  
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2  
of Publication Number 95.  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusion and gate burrs shall not exceed  
0.15mm (0.006 inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. In-  
terlead flash and protrusions shall not exceed 0.25mm (0.010  
inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual  
index feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater  
above the seating plane, shall not exceed a maximum value of  
0.61mm (0.024 inch)  
10. Controlling dimension: MILLIMETER. Converted inch dimen-  
sions are not necessarily exact.  
21  
HI-546, HI-547, HI-548, HI-549  
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)  
c1 LEAD FINISH  
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)  
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE  
-D-  
E
-A-  
INCHES  
MIN  
MILLIMETERS  
BASE  
(c)  
METAL  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.840  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
21.34  
7.87  
NOTES  
b1  
A
b
-
-
M
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
b1  
b2  
b3  
c
3
SECTION A-A  
bbb  
C A - B  
D
D
S
S
S
-
4
BASE  
PLANE  
Q
2
A
-C-  
SEATING  
PLANE  
c1  
D
3
L
α
5
S1  
b2  
eA  
A A  
e
E
0.220  
5.59  
5
b
C A - B  
eA/2  
aaa M C A - B S D S  
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
D
S
M
S
-
NOTES:  
0.125  
0.200  
0.060  
-
3.18  
5.08  
1.52  
-
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.38  
0.13  
6
S1  
7
o
o
o
o
90  
105  
90  
105  
-
α
aaa  
bbb  
ccc  
M
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
2, 3  
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
N
16  
16  
Rev. 0 4/94  
5. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
6. Dimension Q shall be measured from the seating plane to the  
base plane.  
7. Measure dimension S1 at all four corners.  
8. N is the maximum number of terminal positions.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
22  
HI-546, HI-547, HI-548, HI-549  
Dual-In-Line Plastic Packages (PDIP)  
E16.3 (JEDEC MS-001-BB ISSUE D)  
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INDEX  
AREA  
INCHES  
MILLIMETERS  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.210  
-
MIN  
-
MAX  
5.33  
-
NOTES  
-B-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.115  
0.014  
0.045  
0.008  
0.735  
0.005  
0.300  
0.240  
0.39  
2.93  
0.356  
1.15  
0.204  
18.66  
0.13  
7.62  
6.10  
4
D
E
BASE  
PLANE  
0.195  
0.022  
0.070  
0.014  
0.775  
-
4.95  
0.558  
1.77  
0.355  
19.68  
-
-
A2  
A
-C-  
-
SEATING  
PLANE  
B1  
C
8, 10  
L
C
L
-
D1  
B1  
eA  
A1  
A
D1  
e
D
5
eC  
C
B
D1  
E
5
eB  
0.010 (0.25) M  
C
B S  
0.325  
0.280  
8.25  
7.11  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and  
Metric dimensions, the inch dimensions control.  
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication No. 95.  
e
-
0.430  
0.150  
-
10.92  
3.81  
7
B
L
0.115  
2.93  
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-  
N
16  
16  
DEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or protrusions.  
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).  
e
6. E and  
are measured with the leads constrained to be perpendic-  
A
-C-  
ular to datum  
.
7. e and e are measured at the lead tips with the leads unconstrained.  
B
C
e
must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar  
protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,  
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).  
23  
HI-546, HI-547, HI-548, HI-549  
Plastic Leaded Chip Carrier Packages (PLCC)  
0.042 (1.07)  
0.048 (1.22)  
N20.35 (JEDEC MS-018AA ISSUE A)  
0.042 (1.07)  
0.056 (1.42)  
0.004 (0.10)  
C
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE  
PIN (1) IDENTIFIER  
0.025 (0.64)  
0.045 (1.14)  
0.050 (1.27) TP  
INCHES  
MILLIMETERS  
R
C
L
SYMBOL  
MIN  
MAX  
MIN  
4.20  
2.29  
9.78  
8.89  
3.59  
9.78  
8.89  
3.59  
MAX  
4.57  
NOTES  
A
A1  
D
0.165  
0.090  
0.385  
0.350  
0.141  
0.385  
0.350  
0.141  
0.180  
0.120  
0.395  
0.356  
0.169  
0.395  
0.356  
0.169  
-
3.04  
-
-
D2/E2  
D2/E2  
10.03  
9.04  
C
L
D1  
D2  
E
3
E1 E  
4.29  
4, 5  
-
10.03  
9.04  
VIEW “A”  
E1  
E2  
N
3
4.29  
4, 5  
6
0.020 (0.51)  
MIN  
20  
20  
A1  
D1  
D
Rev. 2 11/97  
A
SEATING  
PLANE  
0.020 (0.51) MAX  
3 PLCS  
-C-  
0.026 (0.66)  
0.032 (0.81)  
0.013 (0.33)  
0.021 (0.53)  
0.025 (0.64)  
MIN  
0.045 (1.14)  
MIN  
VIEW “A” TYP.  
NOTES:  
1. Controllingdimension:INCH. Convertedmillimeterdimensionsare  
not necessarily exact.  
2. Dimensions and tolerancing per ANSI Y14.5M-1982.  
3. Dimensions D1 and E1 do not include mold protrusions. Allowable  
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1  
and E1 include mold mismatch and are measured at the extreme  
material condition at the body parting line.  
4. To be measured at seating plane -C- contact point.  
5. Centerline to be determined where center leads exit plastic body.  
6. “N” is the number of terminal positions.  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
24  

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