HI7190IBZ中文资料_数据手册_规格书

HI7190

®

Data Sheet

June 27, 2006

FN3612.10

24-Bit, High Precision, Sigma Delta A/D

Converter

Features

• 22-Bit Resolution with No Missing Code

• 0.0007% Integral Non-Linearity (Typ)

• 20mV to ±2.5V Full Scale Input Ranges

• Internal PGIA with Gains of 1 to 128

• Serial Data I/O Interface, SPI Compatible

• Differential Analog and Reference Inputs

• Internal or System Calibration

The Intersil HI7190 is a monolithic instrumentation, sigma

delta A/D converter which operates from ±5V supplies. Both

the signal and reference inputs are fully differential for

maximum flexibility and performance. An internal

Programmable Gain Instrumentation Amplifier (PGIA)

provides input gains from 1 to 128 eliminating the need for

external pre-amplifiers. The on-demand converter auto-

calibrate function is capable of removing offset and gain

errors existing in external and internal circuitry. The on-board

user programmable digital filter provides over 120dB of

60/50Hz noise rejection and allows fine tuning of resolution

and conversion speed over a wide dynamic range. The

HI7190 and HI7191 are functionally the same device, but the

HI7190 has tighter linearity specifications.

• 120dB Rejection of 60/50Hz Line Noise

• Settling Time of 4 Conversions (Max) for a Step Input

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

The HI7190 contains a serial I/O port and is compatible with

most synchronous transfer formats including both the

Motorola 6805/11 series SPI and Intel 8051 series SSR

protocols. A sophisticated set of commands gives the user

control over calibration, PGIA gain, device selection, standby

mode, and several other features. The On-chip Calibration

Registers allow the user to read and write calibration data.

• Process Control and Measurement

• Industrial Weight Scales

• Part Counting Scales

• Laboratory Instrumentation

• Seismic Monitoring

• Magnetic Field Monitoring

• Additional Reference Literature

Pinout

HI7190

20 LD SOIC, PDIP

TOP VIEW

- Technical Brief, TB348 “HI7190/1 Negative Full Scale

Error vs Conversion Frequency”

- Application Note, AN9504 “A Brief Intro to Sigma Delta

Conversion”

1

2

MODE

SYNC

20

19

SCLK

SDO

- Technical Brief, TB329 “Intersil Sigma Delta Calibration

Technique”

SDIO

CS

3

18 RESET

4

17 OSC

16 OSC

1

2

- Application Note, AN9505 “Using the HI7190 Evaluation

Kit”

DRDY

DGND

5

6

15 DV

DD

- Technical Brief, TB331 “Using the HI7190 Serial

Interface”

AV

V

7

14

AGND

SS

8

13 AV

DD

RLO

- Application Note, AN9527 “Interfacing HI7190 to a

Microcontroller”

9

12

V

RHI

INHI

V

10

11 V

INLO

CM

- Application Note, AN9532 “Using HI7190 in a

Multiplexed System”

- Application Note, AN9601 “Using HI7190 with a Single

+5V Supply”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

HI7190

Ordering Information

TEMP.

PART

NUMBER

PART

MARKING

RANGE

(°C)

PKG.

DWG. #

PACKAGE

HI7190IP

-40 to 85 20 Ld PDIP

E20.3

HI7190IPZ

-40 to 85 20 Ld PDIP*

(Pb-free)

HI7190IB

-40 to 85 20 Ld SOIC

M20.3

HI7190IBZ

(Note)

HI7190IBZ

-40 to 85 20 Ld SOIC

(Pb-free)

HI7190IBZ-T HI7190IBZ

(Note)

-40 to 85 20 Ld SOIC

Tape and Reel

(Pb-free)

M20.3

HI7190EVAL Evaluation Kit

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

Functional Block Diagram

V

RLO

RHI

AV

DD

REFERENCE

INPUTS

TRANSDUCER

BURN-OUT

CURRENT

∑ − Δ

MODULATOR

PGIA

DIGITAL FILTER

V

INHI

∑

∫

1

INLO

1-BIT

D/A

V

CM

CONTROL AND SERIAL INTERFACE UNIT

CONTROL REGISTER

SERIAL INTERFACE

UNIT

CLOCK

GENERATOR

OSC

DRDY RESET SYNC

CS

MODE

S

SDIO SDO

CLK

1

2

FN3612.10

June 27, 2006

2

HI7190

Typical Application Schematic

10MHz

17

16

15

OSC OSC

1

2

13

12

+5V

DV

AV

V

DD

+5V

+

DD

+

4.7μF

0.1μF

1

0.1μF

SCLK

SDIO

INPUT

INHI

+

3

2

11

10

DATA I/O

V

INLO

CM

-

SDO

DATA OUT

R

1

19

4

SYNC

CS

SYNC

CS

9

8

+2.5V

REFERENCE

V

RHI

RLO

5

DRDY

7

18

AV

SS

-5V

RESET

4.7μF

+

20

MODE

0.1μF

AGND

14

DGND

6

FN3612.10

June 27, 2006

3

HI7190

Absolute Maximum Ratings

Thermal Information

Supply Voltage

Thermal Resistance (Typical, Note 1)

θ_JA(°C/W)

AV

to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V

DD

AV to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

125

75

SS

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V

DD

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AV to AV

Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DV

ESD Tolerance (No Damage)

SS

DD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40° C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications AV = +5V, AV = -5V, DV = +5V, V

= +2.5V, V = AGND = 0V, V

RLO CM

= AGND,

DD

SS

DD

RHI

PGIA Gain = 1, OSC = 10MHz, Bipolar Input Range Selected, f = 10Hz

IN

N

PARAMETER

SYSTEM PERFORMANCE

Integral Non-Linearity, INL

Differential Non-Linearity

TEST CONDITIONS

MIN

TYP

MAX

UNITS

End Point Line Method (Notes 3, 5, 6)

-

±0.0007

±0.0015

%FS

(Note 2)

No Missing codes to 22-Bits

LSB

Offset Error, V

See Table 1

-

1

-

OS

Offset Error Drift

V

= V

(Notes 3, 8)

-

μV/°C

INHI

INLO

Full Scale Error, FSE

- V

= +2.5V (Notes 3, 5, 8, 10)

-

INLO

Noise, e

See Table 1

= 0V, V

-

N

Common Mode Rejection Ratio, CMRR

Normal Mode 50Hz Rejection

Normal Mode 60Hz Rejection

Step Response Settling Time

ANALOG INPUTS

V

= V from -2V to +2V

INLO

70

-

dB

CM

INHI

Filter Notch = 10Hz, 25Hz, 50Hz (Note 2)

Filter Notch = 10Hz, 30Hz, 60Hz (Note 2)

120

-

dB

2

4

Conversions

Input Voltage Range

Unipolar Mode (Note 9)

Bipolar Mode (Note 9)

(Note 2)

0

-

V

REF

Input Voltage Range

- V

-

REF

AV

Common Mode Input Range

-

AV

V

SS

DD

Input Leakage Current, I

V

= AV (Note 2)

DD

-

1.0

nA

pF

V

IN

Input Capacitance, C

-

5.0

-

IN

Reference Voltage Range, V

2.5

5

REF

(V

= V

RHI

- V

)

RLO

REF

Transducer Burn-Out Current, I

-

200

-

nA

BO

CALIBRATION LIMITS

Positive Full Scale Calibration Limit

Negative Full Scale Calibration Limit

Offset Calibration Limit

Input Span

-

1.2(V

2.4(V

/Gain)

-

REF

0.2(V

/Gain)

REF

DIGITAL INPUTS

Input Logic High Voltage, V

(Note 11)

2.0

-

V

IH

Input Logic Low Voltage, V

-

0.8

10

IL

Input Logic Current, I

V

= 0V, +5V

IN

1.0

μA

I

FN3612.10

June 27, 2006

4

HI7190

Electrical Specifications AV = +5V, AV = -5V, DV = +5V, V

= +2.5V, V

RLO

= AGND = 0V, V = AGND,

CM

DD

SS

DD

RHI

PGIA Gain = 1, OSC = 10MHz, Bipolar Input Range Selected, f = 10Hz (Continued)

IN

N

PARAMETER

Input Capacitance, C

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

= 0V

IN

-

5.0

-

pF

IN

DIGITAL OUTPUTS

Output Logic High Voltage, V

I

= -100μA (Note 7)

2.4

-

V

OH

OL

OUT

Output Logic Low Voltage, V

= 3mA (Note 7)

= 0V, +5V (Note 7)

0.4

10

Output Three-State Leakage Current,

V

-10

1

μA

OUT

I

OZ

Digital Output Capacitance, C

-

10

-

pF

OUT

TIMING CHARACTERISTICS

SCLK Minimum Cycle Time, t

200

50

-

ns

SCLK

SCLK Minimum Pulse Width, t

SCLKPW

CS to SCLK Precharge Time, t

50

PRE

DRDY Minimum High Pulse Width

(Notes 2, 7)

500

50

Data Setup to SCLK Rising Edge (Write),

t

DSU

Data Hold from SCLK Rising Edge

(Write), t

0

-

ns

DHLD

Data Read Access from Instruction Byte (Note 7)

Write, t

40

-

ACC

Read Bit Valid from SCLK Falling Edge, (Note 7)

-

t

DV

Last Data Transfer to Data Ready

Inactive, t

(Note 7)

-

35

DRDY

RESET Low Pulse Width

SYNC Low Pulse Width

(Note 2)

100

0.1

-

ns

Oscillator Clock Frequency

Output Rise/Fall Time

10

30

1

MHz

ns

Input Rise/Fall Time

-

μs

POWER SUPPLY CHARACTERISTICS

IAV

-

1.5

2.0

3.0

32.5

-

mA

mW

dB

DD

SS

IDV

SCLK = 4MHz

SB = ‘0’

-

DD

Power Dissipation, Active PD

15

5

A

Power Dissipation, Standby PD

SB = ‘1’

S

PSRR

(Note 3)

-70

-

NOTES:

2. Parameter guaranteed by design or characterization, not production tested.

3. Applies to both bipolar and unipolar input ranges.

4. These errors can be removed by re-calibrating at the desired operating temperature.

5. Applies after system calibration.

6. Fully differential input signal source is used.

7. See Load Test Circuit, Figure 4, R1 = 10kΩ, C = 50pF.

L

8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.

9. V

= V

- V

RLO.

REF

10. These errors are on the order of the output noise shown in Table 1.

11. All inputs except OSC . The OSC input V is 3.5V minimum.

RHI

1

IH

FN3612.10

June 27, 2006

5

HI7190

Timing Diagrams

t

SCLK

t

PRE

CS

t

DSU

t

SCLKPW

SCLK

SDIO

t

DHLD

1ST BIT

2ND BIT

FIGURE 1. DATA WRITE TO HI7190

CS

SCLK

SDIO

SDO

1ST BIT

2ND BIT

t

ACC

t

DV

FIGURE 2. DATA READ FROM HI7190

t

DRDY

CS

SCLK

SDIO

1

5

6

7

8

FIGURE 3. DATA READ FROM HI7190

FN3612.10

June 27, 2006

6

HI7190

Pin Descriptions

20 LEAD

DIP, SOIC

PIN NAME

DESCRIPTION

1

SCLK

Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the

falling edge.

2

3

SDO

Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the

Motorola Serial Peripheral Interface.

SDIO

Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial

Interface using a 2-wire serial protocol.

4

5

CS

Chip Select Input. Used to select the HI7190 for a serial data transfer cycle. This line can be tied to DGND.

An Active Low Interrupt indicating that a new data word is available for reading.

Digital Supply Ground.

DRDY

DGND

6

7

AV

Negative Analog Power Supply (-5V).

SS

8

V

External Reference Input. Should be negative referenced to V

.

RHI

RLO

9

V

External Reference Input. Should be positive referenced to V

.

RLO

RHI

10

11

12

V

Common Mode Input. Should be set to halfway between AV

Analog Input LO. Negative input of the PGIA.

and AV

.

SS

CM

DD

V

INLO

V

Analog Input HI. Positive input of the PGIA. The V input is connected to a current source that can be used to check

INHI

the condition of an external transducer. This current source is controlled via the Control Register.

13

14

15

16

17

AV

Positive Analog Power Supply (+5V).

DD

AGND

DV

Analog Supply Ground.

Positive Digital Supply (+5V).

DD

OSC

Used to connect a crystal source between OSC and OSC . Leave open otherwise.

1 2

2

1

Oscillator Clock Input for the device. A crystal connected between OSC and OSC will provide a clock to the device,

1

2

or an external oscillator can drive OSC . The oscillator frequency should be 10MHz (Typ).

1

18

19

20

RESET

SYNC

MODE

Active Low Reset Pin. Used to initialize the HI7190 registers, filter and state machines.

Active Low Sync Input. Used to control the synchronization of a number of HI7190s. A logic ‘0’ initializes the converter.

Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking

(Mode = 0) for the Serial Port.

Load Test Circuit

V

1

R

1

DUT

C

(INCLUDES STRAY

CAPACITANCE)

L

FIGURE 4.

ESD Test Circuits

R

HUMAN BODY

R

1

2

R

1

C

R

= 100pF

= 10MΩ

= 1.5kΩ

ESD

1

2

CHARGED DEVICE MODEL

R

= 1GΩ

= 1Ω

DUT

1

R

2

±

V

2

±

V

DUT

C

ESD

MACHINE MODEL

= 200pF

DIELECTRIC

C

ESD

R

= 10MΩ

= 0Ω

1

2

FIGURE 5A.

FIGURE 5B.

FN3612.10

June 27, 2006

7

HI7190

TABLE 1. NOISE PERFORMANCE WITH INPUTS CONNECTED TO ANALOG GROUND

P-P NOISE RMS NOISE

HERTZ

GAIN = 16

10

SNR

ENOB

(μV)

HERTZ

GAIN = 1

10

SNR

ENOB

(μV)

120.1

114.8

113.5

111.0

109.6

105.5

95.2

19.7

18.8

18.6

18.1

17.9

17.2

15.5

14.5

13.6

10.1

39.8

73.4

6.0

11.1

132.3

129.5

127.7

126.3

125.6

122.4

107.7

98.1

21.7

21.2

20.9

20.7

20.6

20.0

17.6

16.0

13.9

11.1

9.8

13.6

1.5

2.1

25

30

85.1

12.9

30

16.6

2.5

50

114.4

134.0

214.8

699.1

1417.7

2686.0

30110.0

17.3

50

19.5

3.0

60

20.3

60

21.2

3.2

100

32.5

100

250

500

1000

2000

GAIN = 2

10

30.7

4.6

250

105.9

214.8

407.0

4562.1

166.7

505.3

2101.8

14661.6

25.3

76.6

318.5

2221.4

500

89.1

1000

2000

GAIN = 32

10

83.5

85.7

62.6

68.8

113.2

109.0

108.2

104.7

105.0

102.3

93.4

18.5

17.8

17.7

17.1

16.7

15.2

14.2

12.7

9.2

88.8

142.7

157.4

235.8

227.8

310.5

861.1

1782.7

4990.4

57311.1

13.5

21.6

129.2

125.7

124.5

123.4

122.5

118.1

106.1

96.9

21.2

20.6

20.4

20.2

20.1

19.3

17.3

15.8

13.7

11.0

14.0

20.9

2.1

3.2

25

30

23.8

30

24.1

3.7

50

35.7

50

27.3

4.1

60

34.5

60

30.3

4.6

100

47.0

100

250

500

1000

2000

GAIN = 4

10

50.0

7.6

250

130.5

270.1

756.1

8683.5

199.5

580.1

2435.6

16469.7

30.2

87.9

369.0

2495.4

500

87.1

1000

2000

GAIN = 64

10

78.2

84.4

57.0

67.8

106.7

102.9

101.9

98.5

98.9

96.3

85.5

78.1

66.7

50.5

17.4

16.8

16.6

16.1

15.7

13.9

12.7

10.8

8.1

186.2

288.4

28.2

43.7

125.9

123.1

121.8

119.9

116.1

105.7

96.6

20.6

20.1

19.9

19.6

19.0

17.3

15.8

13.7

11.0

20.5

28.4

3.1

4.3

25

30

325.8

49.4

30

32.8

5.0

50

479.8

72.7

50

40.9

6.2

60

459.8

69.7

60

40.9

6.2

100

620.2

94.0

100

250

500

1000

2000

GAIN = 8

10

63.2

9.6

250

2133.5

5025.0

18693.5

120163.0

323.3

761.4

2832.3

18206.5

209.7

597.8

2469.5

15656.1

31.8

90.6

374.2

2372.1

500

1000

2000

GAIN = 128

10

84.3

68.2

101.1

96.0

95.2

93.2

92.2

91.4

79.4

71.8

60.1

44.8

16.5

15.7

15.5

15.2

15.0

14.9

12.9

11.6

9.7

356.5

638.3

54.0

96.7

124.7

120.6

119.2

117.5

116.8

112.1

101.4

95.3

20.4

19.7

19.5

19.2

19.1

18.3

16.5

15.5

13.5

11.1

23.4

37.8

3.5

5.7

25

30

704.8

106.8

133.7

151.0

164.6

658.5

1581.7

6048.9

35339.1

30

44.3

6.7

50

882.2

50

53.8

8.2

60

996.7

60

58.6

8.9

100

1086.6

4346.4

10439.2

39923.0

233238.2

100

250

500

1000

2000

100.0

345.2

691.1

2838.6

15494.7

15.2

52.3

104.7

430.1

2347.7

250

500

1000

2000

83.1

7.1

68.3

FN3612.10

June 27, 2006

8

HI7190

noise and, in this case, the output noise tends to decrease

with increasing gain.

Definitions

Integral Non-Linearity, INL, is the maximum deviation of

any digital code from a straight line passing through the

endpoints of the transfer function. The endpoints of the

transfer function are zero scale (a point 0.5 LSB below the

first code transition 000...000 and 000...001) and full scale (a

point 0.5 LSB above the last code transition 111...110 to

111...111).

Since the output noise comes from two sources, the effective

resolution of the device (i.e., the ratio of the input full scale to

the output RMS noise) does not remain constant with

increasing gain or with increasing bandwidth. It is possible to

do post-filtering (such as brick wall filtering) on the data to

improve the overall resolution for a given -3dB frequency

and also to further reduce the output noise.

Differential Non-Linearity, DNL, is the deviation from the

actual difference between midpoints and the ideal difference

between midpoints (1 LSB) for adjacent codes. If this

difference is equal to or more negative than 1 LSB, a code

will be missed.

Circuit Description

The HI7190 is a monolithic, sigma delta A/D converter which

operates from ±5V supplies and is intended for

measurement of wide dynamic range, low frequency signals.

It contains a Programmable Gain Instrumentation Amplifier

(PGIA), sigma delta ADC, digital filter, bidirectional serial port

(compatible with many industry standard protocols), clock

oscillator, and an on-chip controller.

Offset Error, V , is the deviation of the first code transition

OS

from the ideal input voltage (V - 0.5 LSB). This error can

IN

be calibrated to the order of the noise level shown in Table 1.

Full Scale Error, FSE, is the deviation of the last code

transition from the ideal input full scale voltage

The signal and reference inputs are fully differential for

(V - + V

/Gain - 1.5 LSB). This error can be calibrated

IN

REF

maximum flexibility and performance. Normally V

and

RHI

are tied to +2.5V and AGND respectively. This allows

to the order of the noise level shown in Table 1.

V

RLO

for input ranges of 2.5V and 5V when operating in the

unipolar and bipolar modes respectively (assuming the PGIA

is configured for a gain of 1). The internal PGIA provides

input gains from 1 to 128 and eliminates the need for

external pre-amplifiers. This means the device will convert

signals ranging from 0V to +20mV and 0V to +2.5V when

operating in the unipolar mode or signals in the range of

±20mV to ±2.5V when operating in the bipolar mode.

Input Span, defines the minimum and maximum input

voltages the device can handle while still calibrating properly

for gain.

Noise, e , Table 1 shows the peak-to-peak and RMS noise

N

for typical notch and -3dB frequencies. The device

programming was for bipolar input with a V_REFof +2.5V. This

implies the input range is 5V. The analysis was performed on

100 conversions with the peak-to-peak output noise being

the difference between the maximum and minimum readings

over a rolling 10 conversion window. The equation to convert

the peak-to-peak noise data to ENOB is:

The input signal is continuously sampled at the input to the

HI7190 at a clock rate set by the oscillator frequency and the

selected gain. This signal then passes through the sigma

delta modulator (which includes the PGIA) and emerges as a

pulse train whose code density contains the analog signal

ENOB = Log (V /V

FS NRMS

)

2

3

information. The output of the modulator is fed into the sinc

where: V = 5V, V

FS NRMS

= V

/CF and

NP-P

digital low pass filter. The filter output passes into the

calibration block where offset and gain errors are removed.

The calibrated data is then coded (2’s complement, offset

binary or binary) before being stored in the Data Output

Register. The Data Output Register update rate is

determined by the first notch frequency of the digital filter.

This first notch frequency is programmed into HI7190 via the

Control Register and has a range of 10Hz to 1.953kHz which

corresponds to -3dB frequencies of 2.62Hz and 512Hz

respectively.

CF = 6.6 (Empirical Crest Factor)

The noise from the part comes from two sources, the

quantization noise from the analog-to-digital conversion

process and device noise. Device noise (or Wideband

Noise) is independent of gain and essentially flat across the

frequency spectrum. Quantization noise is ratiometric to

input full scale (and hence gain) and its frequency response

is shaped by the modulator.

Looking at Table 1, as the cutoff frequency increases the

output noise increases. This is due to more of the

Output data coding on the HI7190 is programmable via the

Control Register. When operating in bipolar mode, data

output can be either 2’s complement or offset binary. In

unipolar mode output is binary.

quantization noise of the part coming through to the output

and, hence, the output noise increases with increasing -3dB

frequencies. For the lower notch settings, the output noise is

dominated by the device noise and, hence, altering the gain

has little effect on the output noise. At higher notch

The DRDY signal is used to alert the user that new output

data is available. Converted data is read via the HI7190

serial I/O port which is compatible with most synchronous

transfer formats including both the Motorola 6805/11 series

frequencies, the quantization noise dominates the output

FN3612.10

June 27, 2006

9

HI7190

SPI and Intel 8051 series SSR protocols. Data Integrity is

always maintained at the HI7190 output port. This means

that if a data read of conversion N is begun but not finished

before the next conversion (conversion N + 1) is complete,

the DRDY line remains active (low) and the data being read

is not overwritten.

If the device is written to the conversion mode, a new

calibration is NOT performed (A new calibration is

recommended any time data is written to the Control

Register.). In either case, DRDY goes low when valid data is

available at the output.

If a single data byte is written to byte 0 of the Control

Register, the device assumes the gain has NOT been

changed. It is up to the user to re-calibrate the device if the

gain is changed in this manner. For this reason it is

recommended that the entire Control Register be written

when changing the gain of the device. This ensures that the

part is re-calibrated (if in a calibration mode) before the

DRDY output goes low indicating that valid data is available.

The HI7190 provides many calibration modes that can be

initiated at any time by writing to the Control Register. The

device can perform system calibration where external

components are included with the HI7190 in the calibration

loop or self-calibration where only the HI7190 itself is in the

calibration loop. The On-chip Calibration Registers are

read/write registers which allow the user to read calibration

coefficients as well as write previously determined

calibration coefficients.

The calibration registers can be read via the serial interface

at any time. However, care must be taken when writing data

to the calibration registers. If the HI7190 is internally

updating any calibration register the user can not write to

that calibration register. See the Operational Modes section

for details on which calibration registers are updated for the

various modes.

Circuit Operation

The analog and digital supplies and grounds are separate

on the HI7190 to minimize digital noise coupling into the

analog circuitry. Nominal supply voltages are AV

= +5V,

DD

= -5V. If the same supply is used

DV

= +5V, and AV

DD

for AV

SS

it is imperative that the supply is

DD

Since access to the calibration registers is asynchronous to the

conversion process the user is cautioned that new calibration

data may not be used on the very next set of “valid” data after a

calibration register write. It is guaranteed that the new data will

take effect on the second set of output data. Non-calibrated

data can be obtained from the device by writing 000000 (h) to

the Offset Calibration Register, 800000 (h) to the Positive Full

Scale Calibration Register, and 800000 (h) to the Negative Full

Scale Calibration Register. This sets the offset correction factor

to 0 and the positive and negative gain slope factors to 1.

and DV

DD

separately decoupled to the AV

and DV

pins on the

DD

HI7190. Separate analog and digital ground planes should

be maintained on the system board and the grounds should

be tied together back at the power supply.

When the HI7190 is powered up it needs to be reset by

pulling the RESET line low. The reset sets the internal

registers of the HI7190 as shown in Table 2 and puts the part

in the bipolar mode with a gain of 1 and offset binary coding.

The filter notch of the digital filter is set at 30Hz while the I/O

is set up for bidirectional I/O (data is read and written on the

SDIO line and SDO is three-stated), descending byte order,

and MSB first data format. A self calibration is performed

before the device begins converting. DRDY goes low when

valid data is available at the output.

If several HI7190s share a system master clock the SYNC

pin can be used to synchronize their operation. A common

SYNC input to multiple devices will synchronize operation

such that all output registers are updated simultaneously. Of

course the SYNC pin would normally be activated only after

each HI7190 has been calibrated or has had calibration

coefficients written to it.

TABLE 2. REGISTER RESET VALUES

REGISTER

Data Output Register

VALUE (HEX)

XXXX (Undefined)

28B300

The SYNC pin can also be used to control the HI7190 when

an external multiplexer is used with a single HI7190. The

SYNC pin in this application can be used to guarantee a

maximum settling time of 3 conversion periods when

switching channels on the multiplexer.

Control Register

Offset Calibration Register

Positive Full Scale Calibration Register

Self Calibration Value

Analog Section Description

Negative Full Scale Calibration Register Self Calibration Value

Figure 6 shows a simplified block diagram of the analog

modulator front end of a sigma delta A/D Converter. The

The configuration of the HI7190 is changed by writing new

setup data to the Control Register. Whenever data is written

to byte 2 and/or byte 1 of the Control Register the part

assumes that a critical setup parameter is being changed

which means that DRDY goes high and the device is re-

synchronized. If the configuration is changed such that the

device is in any one of the calibration modes, a new

calibration is performed before normal conversions continue.

input signal V comes into a summing junction (the PGIA in

IN

this case) where the previous modulator output is subtracted

from it. The resulting signal is then integrated and the output

of the integrator goes into the comparator. The output of the

comparator is then fed back via a 1-bit DAC to the summing

FN3612.10

June 27, 2006

10

HI7190

junction. The feedback loop forces the average of the fed

back signal to be equal to the input signal V

Programmable Gain Instrumentation Amplifier

.

IN

The Programmable Gain Instrumentation Amplifier allows the

user to directly interface low level sensors and bridges directly

to the HI7190. The PGIA has 4 selectable gain options of 1, 2,

4, 8 which are implemented by multiple sampling of the input

signal. Input signals can be gained up further to 16, 32, 64 or

128. These higher gains are implemented in the digital section

of the design to maintain a high signal to noise ratio through

the front end amplifiers. The gain is digitally programmable in

the Control Register via the serial interface. For optimum

PGIA

INTEGRATOR

COMPARATOR

+

V

∑

∫

+

IN

-

DAC

V

RHI

RLO

PGIA performance the V

of the analog supplies.

pin should be tied to the mid point

CM

FIGURE 6. SIMPLE MODULATOR BLOCK DIAGRAM

Differential Reference Input

Analog Inputs

The reference inputs of the of the HI7190, V

and V ,

RLO

The analog input on the HI7190 is a fully differential input

with programmable gain capabilities. The input accepts both

unipolar and bipolar input signals and gains range from 1 to

RHI

provide a differential reference input capability. The nominal

differential voltage (V = V - V ) is +2.5V and the

REF

RHI

RLO

common mode voltage cab be anywhere between AV and

128. The common mode range of this input is from AV to

SS

AV . Larger values of V

DD

can be used without

AV

DD

provided that the absolute value of the analog input

REF

degradation in performance with the maximum reference

voltage being V = +5V. Smaller values of V can also

voltage lies within the power supplies. The input impedance

of the HI7190 is dependent upon the modulator input

sampling rate and the sampling rate varies with the selected

PGIA gain. Table 3 shows the sampling rates and input

impedances for the different gain settings of the HI7190.

Note that this table is valid only for a 10MHz master clock. If

the input clock frequency is changed, then the input

impedance will change accordingly. The equation used to

calculate the input impedance is:

REF

be used but performance will be degraded since the LSB

size is reduced.

The full scale range of the HI7190 is defined as:

FSR

= 2 x V

/GAIN

BIPOLAR

REF

= V /GAIN

REF

FSR

UNIPOLAR

and V

must always be greater than V for proper

RLO

RHI

Z

= 1/(C x f ),

IN

S

operation of the device.

where C is the nominal input capacitance (8pF) and f is

the modulator sampling rate.

in

S

The reference inputs provide a high impedance dynamic

load similar to the analog inputs and the effective input

impedance for the reference inputs can be calculated in the

same manner as it is for the analog input impedance. The

TABLE 3. EFFECTIVE INPUT IMPEDANCE vs GAIN

SAMPLING RATE INPUT IMPEDANCE

only difference in the calculation is that C for the reference

GAIN

(kHz)

78.125

156.25

312.5

625

(MΩ)

IN

inputs is 10.67pF. Therefore, the input impedance range for

the reference inputs is from 149kΩ in a gain of 8 or higher

mode to 833kΩ in the gain of 1 mode.

1

1.6

2

0.8

4

0.4

V

Input

CM

The voltage at the V

8, 16, 32, 64, 128

0.2

input is the voltage that the internal

CM

analog circuitry is referenced to and should always be tied to

the midpoint of the AV and AV supplies. This point

Bipolar/Unipolar Input Ranges

DD

SS

provides a common mode input voltage for the internal

operational amplifiers and must be driven from a low noise,

low impedance source if it is not tied to analog ground.

Failure to do so will result in degraded HI7190 performance.

The input on the HI7190 can accept either unipolar or bipolar

input voltages. Bipolar or unipolar options are chosen by

programming the B/U bit of the Control Register.

Programming the part for either unipolar or bipolar operation

does not change the input signal conditioning.

It is recommended that V

be tied to analog ground when

CM

= +5V and AV = -5V supplies.

operating off of AV

DD

SS

V also determines the headroom at the upper and lower

CM

The inputs are differential, and as a result are referenced to the

voltage on the V

input. For example, if V

is +1.25V

INLO

ends of the power supplies which is limited by the common

mode input range where the internal operational amplifiers

remain in the linear, high gain region of operation. The

and the HI7190 is configured for unipolar operation with a gain

of 1 and a V of +2.5V, the input voltage range on the V

REF INHI

input is +1.25V to +3.75V. If V

is +1.25V and the HI7190 is

INLO

configured for bipolar mode with gain of 1 and a V

HI7190 is designed to have a range of AV +1.8V < V

SS CM

<

of +2.5V,

REF

input is -1.25V to +3.75V.

the analog input range on the V

INHI

FN3612.10

June 27, 2006

11

HI7190

AV

DD

- 1.8V. Exceeding this range on the V

CM

pin will

the conversion. It can not, however, remove noise present

on the analog signal prior to the ADC (which an analog filter

can).

compromise the device performance.

Transducer Burn-Out Current Source

One problem with the modulator/digital filter combination is

that excursions outside the full scale range of the device

could cause the modulator and digital filter to saturate. This

device has headroom built in to the modulator and digital

filter which tolerates signal deviations up to 33% outside of

the full scale range of the device. If noise spikes can drive

the input signal outside of this extended range, it is

recommended that an input analog filter is used or the

overall input signal level is reduced.

The V_INHIinput of the HI7190 contains a 500nA (Typ) current

source which can be turned on/off via the Control Register.

This current source can be used in checking whether a

transducer has burnt-out or become open before attempting

to take measurements on that channel. When the current

source is turned on an additional offset will be created

indicating the presence of a transducer. The current source is

controlled by the BO bit (Bit 4) in the Control Register and is

disabled on power up. See Figure 7 for an applications circuit.

Low Pass Decimation Filter

HI7190

The digital low-pass filter is a Hogenauer (sinc³) decimating

filter. This filter was chosen because it is a cost effective low

pass decimating filter that minimizes the need for internal

multipliers and extensive storage and is most effective when

used with high sampling or oversampling rates. Figure 9

AV

DD

RATIOMETRIC

CONFIGURATION

CURRENT

SOURCE

LOAD CELL

shows the frequency characteristics of the filter where f is

C

V

RHI

the -3dB frequency of the input signal and f is the

N

V

RLO

programmed notch frequency. The analog modulator sends

a one bit data stream to the filter at a rate of that is

determined by:

V

INHI

f

= f

/128

MODULATOR

OSC

f

= 78.125kHz for f

= 10MHz.

V

OSC

INLO

The filter then converts the serial modulator data into 40-bit

words for processing by the Hogenauer filter. The data is

decimated in the filter at a rate determined by the CODE

word FP10-FP0 (programed by the user into the Control

Register) and the external clock rate. The equation is:

AV

SS

FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT

Digital Section Description

f

= f

/(512 x CODE).

OSC

NOTCH

A block diagram of the digital section of the HI7190 is shown

in Figure 8. This section includes a low pass decimation

filter, conversion controller, calibration logic, serial interface,

and clock generator.

The Control Register has 11 bits that select the filter cutoff

frequency and the first notch of the filter. The output data

update rate is equal to the notch frequency. The notch

frequency sets the Nyquist sampling rate of the device while

the -3dB point of the filter determines the frequency

MODULATOR

OSC

CLOCK

GENERATOR

2

1

CLOCK

spectrum of interest (f ). The FP bits have a usable range of

S

10 through 2047 where 10 yields a 1.953kHz Nyquist rate.

The Hogenauer filter contains alias components that reflect

around the notch frequency. If the spectrum of the frequency

of interest reaches the alias component, the data has been

aliased and therefore undersampled.

SDO

CALIBRATION

AND CONTROL

SERIAL I/O

DIGITAL

FILTER

SDIO

SCLK

CS

DRDY

Filter Characteristics

Please note: We have recently discovered a

performance anomaly with the HI7190. The problem

occurs when the digital code for the notch filter is

programmed within certain frequencies. We believe the

error is caused by the calibration logic and the digital

notch code NOT the absolute frequency. The error is

seen when the user applies mid-scale (0V input, Bipolar

mode). With this input, the expected digital output

SYNC

RESET

FIGURE 8. DIGITAL SECTION BLOCK DIAGRAM

Digital Filtering

One advantage of digital filtering is that it occurs after the

conversion process and can remove noise introduced during

FN3612.10

June 27, 2006

12

HI7190

should be mid-scale (800000 ). Instead, there is a small

clock frequency and gain, determines the allotted time for the

input capacitor to charge. The addition of external components

may cause the charge time of the capacitor to increase beyond

the allotted time. The result of the input not settling to the proper

value is a system gain error which can be eliminated by system

calibration of the HI7190.

h

probability, of an erroneous negative full scale (000000 )

h

output. Refer to Technical Brief TB348 for complete

details.

The FP10 to FP0 bits programmed into the Control Register

determine the cutoff (or notch) frequency of the digital filter.

The allowable code range is 00A . This corresponds to a

Clocking/Oscillators

H

maximum and minimum cutoff frequency of 1.953kHz and

10Hz, respectively when operating at a clock frequency of

10MHz. If a 1MHz clock is used then the maximum and

minimum cutoff frequencies become 195.3kHz and 1Hz,

The master clock into the HI7190 can be supplied by either a

crystal connected between the OSC and OSC pins as

1

2

shown in Figure 10A or a CMOS compatible clock signal

connected to the OSC pin as shown in Figure 10B. The

1

3

respectively. A plot of the (sinx/x) digital filter characteristics

input sampling frequency, modulator sampling frequency,

filter -3dB frequency, output update rate, and calibration time

is shown in Figure 9. This filter provides greater than 120dB

of 50Hz or 60Hz rejection. Changing the clock frequency or

the programming of the FP bits does not change the shape

of the filter characteristics, it merely shifts the notch

frequency. This low pass digital filter at the output of the

converter has an accompanying settling time for step inputs

just as a low pass analog filter does. New data takes

between 3 and 4 conversion periods to settle and update on

are all directly related to the master clock frequency, f

.

OSC

For example, if a 1MHz clock is used instead of a 10MHz

clock, what is normally a 10Hz conversion rate becomes a

1Hz conversion rate. Lowering the clock frequency will also

lower the amount of current drawn from the power supplies.

Please note that the HI7190 specifications are written for a

10MHz clock only.

the serial port with a conversion period t

being equal to

CONV

1/f .

N

10MHz

17

OSC

16

OSC

0

ALIAS BAND

±f

1

2

f

N

C

HI7190

-20

-40

FIGURE 10A.

-60

-80

10MHz

NO

CONNECTION

-100

-120

17

OSC

16

OSC

1

2

HI7190

f

2f

3f

4f

N

C

N

FREQUENCY (Hz)

FIGURE 10B.

FIGURE 10. OSCILLATOR CONFIGURATIONS

FIGURE 9. LOW PASS FILTER FREQUENCY CHARACTERISTICS

Input Filtering

The digital filter does not provide rejection at integer

multiples of the modulator sampling frequency. This implies

that there are frequency bands where noise passes to the

output without attenuation. For most cases this is not a

problem because the high oversampling rate and noise

shaping characteristics of the modulator cause this noise to

become a small portion of the broadband noise which is

filtered. However, if an anti-alias filter is necessary a single

pole RC filter is usually sufficient.

Operational Modes

The HI7190 contains several operational modes including

calibration modes for cancelling offset and gain errors of

both internal and external circuitry. A calibration routine

should be initiated whenever there is a change in the

ambient operating temperature or supply voltage. Calibration

should also be initiated if there is a change in the gain, filter

notch, bipolar, or unipolar input range. Non-calibrated data

can be obtained from the device by writing 000000 to the

Offset Calibration Register, 800000 (h) to the Positive Full

Scale Calibration Register, and 800000 (h) to the Negative

Full Scale Calibration Register. This sets the offset

correction factor to 0 and both the positive and negative gain

slope factors to 1.

If an input filter is used the user must be careful that the source

impedance of the filter is low enough not to cause gain errors in

the system. The DC input impedance at the inputs is > 1GΩ but

it is a dynamic load that changes with clock frequency and

selected gain. The input sample rate, also dependent upon

FN3612.10

June 27, 2006

13

HI7190

The HI7190 offers several different modes of Self-Calibration

and System Calibration. For calibration to occur, the on-chip

microcontroller must convert the modulator output for three

different input conditions - “zero-scale,” “positive full scale,”

and “negative full scale”. With these readings, the HI7190

can null any offset errors and calculate the gain slope factor

for the transfer function of the converter. It is imperative that

the zero-scale calibration be performed before either of the

gain calibrations. However, the order of the gain calibrations

is not important.

HI7190 then takes 3 conversion cycles to sample the data

and update the Positive Full Scale Calibration Register. Next

the polarity of the reference voltage across the modulator

input terminals is reversed and after 3 conversion cycles the

Negative Full Scale Calibration Register is updated. The

values stored in the Positive and Negative Full Scale

Calibration Registers correct for any internal gain errors in

the A/D transfer function. After 3 more conversion cycles the

DRDY line will activate signaling that the calibration is

complete and valid data is present in the Data Output

Register.

The calibration modes are user selectable in the Control

Register by using the MD bits (MD2-MD0) as shown in

Table 4. DRDY will go low indicating that the calibration is

complete and there is valid data at the output.

System Offset Calibration Mode

The System Offset Calibration Mode is a single step process

that allows the user to lump offset errors of external circuitry

and the internal errors of the HI7190 together and null them

out. This mode will convert the external differential signal

TABLE 4. HI7190 OPERATIONAL MODES

MD2

MD1

MD0

OPERATIONAL MODE

Conversion

applied to the V inputs and then store that value in the

IN

Offset Calibration Register. The user must apply the zero

point or offset voltage to the HI7190 analog inputs and allow

the signal to settle before selecting this mode. After 4

conversion periods the DRDY line will activate signaling that

the calibration is complete and valid data is present in the

Data Output Register.

0

1

0

1

0

1

0

1

0

1

Self Calibration (Gain of 1 only)

System Offset Calibration

System Positive Full Scale Calibration

System Negative Full Scale Calibration

System Positive Full Scale Calibration Mode

System Offset/Internal Gain Calibration

(Gain of 1 only)

The System Positive Full Scale Calibration Mode is a single

step process that allows the user to lump gain errors of

external circuitry and the internal errors of the HI7190

together and null them out. This mode will convert the

1

0

1

System Gain Calibration

Reserved

external differential signal applied to the V inputs and

IN

Conversion Mode

For Conversion Mode operation the HI7190 converts the

differential voltage between V and V . From

switching into this mode it takes 3 conversion periods (3 x

1/f ) for DRDY to go low and new data to be valid. No

N

calibration coefficients are generated when operating in

Conversion Mode as data is calibrated using the existing

calibration coefficients.

stores the converted value in the Positive Full Scale

Calibration Register. The user must apply the +Full Scale

voltage to the HI7190 analog inputs and allow the signal to

settle before selecting this mode. After 4 conversion periods

the DRDY line will activate signaling the calibration is

complete and valid data is present in the Data Output

Register.

INHI

INLO

System Negative Full Scale Calibration Mode

Self-Calibration Mode

The System Negative Full Scale Calibration Mode is a

single-step process that allows the user to lump gain errors

of external circuitry and the internal errors of the HI7190

together and null them out. This mode will convert the

Please note: Self-calibration is only valid when operating in a

gain of one. In addition, the offset and gain errors are not

reduced as with the full system calibration.

The Self-Calibration Mode is a three step process that

updates the Offset Calibration Register, the Positive Full

Scale Calibration Register, and the Negative Full Scale

Calibration Register. In this mode an internal offset

calibration is done by disconnecting the external inputs and

shorting the inputs of the PGIA together. After 3 conversion

periods the Offset Calibration Register is updated with the

value that corrects any internal offset errors.

external differential signal applied to the V inputs and

IN

stores the converted value in the Negative Full Scale

Calibration Register. The user must apply the -Full Scale

voltage to the HI7190 analog inputs and allow the signal to

settle before selecting this mode. After 4 conversion periods

the DRDY line will activate signaling the calibration is

complete and valid data is present in the Data Output

Register.

After the offset calibration is completed, the Positive and

Negative Full Scale Calibration Registers are updated. The

inputs V

and V are disconnected and the external

INHI

INLO

reference is applied across the modulator inputs. The

FN3612.10

June 27, 2006

14

HI7190

value of 0.2 x V

/GAIN, the offset must be less than 1 x

System Offset/Internal Gain Calibration Mode

REF

/GAIN. In bipolar mode the span is equidistant around

V

REF

the voltage used for the zero scale point. For this mode the

offset plus half the span cannot exceed 1.2 x V /GAIN. If

Please note: System Offset/Internal Gain is only valid when

operating in a gain of one. In addition, the offset and gain errors

are not reduced as with the full system calibration.

REF

/GAIN, then the offset can not be

the span is at ±0.2 x V

greater than ±2 x V

REF

The System Offset/Internal Gain Calibration Mode is a single

step process that updates the Offset Calibration Register,

the Positive Full Scale Calibration Register, and the

/GAIN.

REF

Serial Interface

Negative Full Scale Calibration Register. First the external

The HI7190 has a flexible, synchronous serial communication

port to allow easy interfacing to many industry standard

microcontrollers and microprocessors. The serial I/O is

compatible with most synchronous transfer formats, including

both the Motorola 6805/11 SPI and Intel 8051 SSR protocols.

The Serial Interface is a flexible 2-wire or 3-wire hardware

interface where the HI7190 can be configured to read and

write on a single bidirectional line (SDIO) or configured for

writing on SDIO and reading on the SDO line.

differential signal applied to the V inputs is converted and

IN

that value is stored in the Offset Calibration Register. The

user must apply the zero point or offset voltage to the

HI7190 analog inputs and allow the signal to settle before

selecting this mode.

After this is completed the Positive and Negative Full Scale

Calibration Registers are updated. The inputs V

and V

INHI

INLO

are disconnected and the external reference is switched in. The

HI7190 then takes 3 conversion cycles to sample the data and

update the Positive Full Scale Calibration Register. Next the

The interface is byte organized with each register byte

having a specific address and single or multiple byte

transfers are supported. In addition, the interface allows

flexibility as to the byte and bit access order. That is, the user

can specify MSB/LSB first bit positioning and can access

bytes in ascending/descending order from any byte position.

polarity of the reference voltage across the V

and V

INHI

INLO

terminals is reversed and after 3 conversion cycles the

Negative Full Calibration Register is updated. The values

stored in the Positive and Negative Full Scale Calibration

Registers correct for any internal gain errors in the A/D transfer

function. After 3 more conversion cycles, the DRDY line will

activate signaling that the calibration is complete and valid data

is present in the Data Output Register.

The serial interface allows the user to communicate with 5

registers that control the operation of the device.

Data Output Register - a 24-bit, read only register

containing the conversion results.

System Gain Calibration Mode

Control Register - a 24-bit, read/write register containing

the setup and operating modes of the device.

The Gain Calibration Mode is a single step process that

updates the Positive and Negative Full Scale Calibration

Registers. This mode will convert the external differential

Offset Calibration Register - a 24-bit, read/write register

used for calibrating the zero point of the converter or system.

signal applied to the V inputs and then store that value in

IN

the Negative Full Scale Calibration Register. Then the

polarity of the input is reversed internally and another

conversion is performed. This conversion result is written to

the Positive Full Scale Calibration Register. The user must

apply the +Full Scale voltage to the HI7190 analog inputs

and allow the signal to settle before selecting this mode.

After 1 more conversion period the DRDY line will activate

signaling the calibration is complete and valid data is present

in the data output register.

Positive Full Scale Calibration Register - a 24-bit,

read/write register used for calibrating the Positive Full Scale

point of the converter or system.

Negative Full Scale Calibration Register - a 24-bit,

read/write register used for calibrating the Negative Full

Scale point of the converter or system.

Two clock modes are supported. The HI7190 can accept the

serial interface clock (SCLK) as an input from the system or

generate the SCLK signal as an output. If the MODE pin is

logic low the HI7190 is in external clocking mode and the

SCLK pin is configured as an input. In this mode the user

supplies the serial interface clock and all interface timing

specifications are synchronous to this input. If the MODE pin

is logic high the HI7190 is in self-clocking mode and the

SCLK pin is configured as an output. In self-clocking mode,

Reserved

This mode is not used in the HI7190 and should not be

selected. There is no internal detection logic to keep this

condition from being selected and care should be taken not

to assert this bit combination.

Offset and Span Limits

There are limits to the amount of offset and gain which can

be adjusted out for the HI7190. For both bipolar and unipolar

modes the minimum and maximum input spans are

SCLK runs at F

= OSC /8 and stalls high at byte

SCLK

1

boundaries. SCLK does NOT have the capability to stall low

in this mode. All interface timing specifications are

synchronous to the SCLK output.

0.2 x V

/GAIN and 1.2 x V

/GAIN respectively.

REF

In the unipolar mode the offset plus the span cannot exceed

Normal operation in self-clocking mode is as follows (See

Figure 12): CS is sampled low on falling OSC edges. The

1

the 1.2 x V

/GAIN limit. So, if the span is at its minimum

REF

FN3612.10

June 27, 2006

15

HI7190

first SCLK transition output is delayed 29 OSC cycles from

case of CS inactive during the clock stall time it takes 1 OSC

cycle plus prop delay (Max) for the outputs to be disabled.

1

the next rising OSC . SCLK transitions eight times and then

1

stalls high for 28 OSC cycles. After this stall period is

1

I/O Port Pin Descriptions

completed SCLK will again transition eight times and stall

high. This sequence will repeat continuously while CS is

active.

The serial I/O port is a bidirectional port which is used to

read the data register and read or write the control register

and calibration registers. The port contains two data lines, a

synchronous clock, and a status flag. Figure 11 shows a

diagram of the serial interface lines.

The extra OSC cycle required when coming out of the CS

1

inactive state is a one clock cycle latency required to

properly sample the CS input. Note that the normal stall at

byte boundaries is 28 OSC cycles thus giving a SCLK rising

to rising edge stall period of 32 OSC cycles.

1

DATA OUT

BIDIRECTIONAL DATA

PORT CLOCK

SDO

1

SDIO

SCLK

CS

HI7190

The affects of CS on the I/O are different for self-clocking

mode (MODE = 1) than for external mode (MODE = 0). For

external clocking mode CS inactive disables the I/O state

machine, effectively freezing the state of the I/O cycle. That

is, an I/O cycle can be interrupted using chip select and the

HI7190 will continue with that I/O cycle when re-enabled via

CS. SCLK can continue toggling while CS is inactive. If CS

goes inactive during an I/O cycle, it is up to the user to

ensure that the state of SCLK is identical when reactivating

CS as to what it was when CS went inactive. For read

operations in external clocking mode, the output will go

three-state immediately upon deactivation of CS.

CHIP SELECT

DEVICE STATUS

CLOCK MODE

DRDY

MODE

FIGURE 11. HI7190 SERIAL INTERFACE

SDO - Serial Data out. Data is read from this line using those

protocols with separate lines for transmitting and receiving

data. An example of such a standard is the Motorola Serial

Peripheral Interface (SPI) using the 68HC05 and 68HC11

family of microcontrollers, or other similar processors. In the

case of using bidirectional data transfer on SDIO, SDO does

not output data and is set in a high impedance state.

For self-clocking mode (MODE = 1), the affects of CS are

different. If CS transitions high (inactive) during the period

when data is being transferred (any non stall time) the HI7190

will complete the data transfer to the byte boundary. That is,

once SCLK begins the eight transition sequence, it will always

complete the eight cycles. If CS remains inactive after the byte

has been transferred it will be sampled and SCLK will remain

stalled high indefinitely. If CS has returned to active low before

the data byte transfer period is completed the HI7190 acts as

if CS was active during the entire transfer period.

SDIO - Serial Data in or out. Data is always written to the

device on this line. However, this line can be used as a

bidirectional data line. This is done by properly setting up the

Control Register. Bidirectional data transfer on this line can

be used with Intel standard serial interfaces (SSR, Mode 0)

in MCS51 and MCS96 family of microcontrollers, or other

similar processors.

SCLK - Serial clock. The serial clock pin is used to

synchronize data to and from the HI7190 and to run the port

state machines. In Synchronous External Clock Mode, SCLK

is configured as an input, is supplied by the user, and can

run up to a 5MHz rate. In Synchronous Self Clocking Mode,

It is important to realize that the user can interrupt a data

transfer on byte boundaries. That is, if the Instruction

Register calls for a 3 byte transfer and CS is inactive after

only one byte has been transferred, the HI7190, when

reactivated, will continue with the remaining two bytes before

looking for the next Instruction Register write cycle.

SCLK is configured as an output and runs at OSC /8.

1

CS - Chip select. This signal is an active low input that allows

more than one device on the same serial communication lines.

The SDO and SDIO will go to a high impedance state when this

signal is high. If driven high during any communication cycle,

that cycle will be suspended until CS reactivation. Chip select

can be tied low in systems that maintain control of SCLK.

Note that the outputs will NOT go three-state immediately upon

CS inactive for read operations in self-clocking mode. In the

case of CS going inactive during a read cycle the outputs

remain driving until after the last data bit is transferred. In the

29

33

37

41

89

45

121

125

OSC

1

CS

SCLK

FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE

FN3612.10

June 27, 2006

16

HI7190

DRDY - Data Ready. This is an output status flag from the

device to signal that the Data Output Register has been

updated with the new conversion result. DRDY is useful as an

edge or level sensitive interrupt signal to a microprocessor or

microcontroller. DRDY low indicates that new data is available

at the Data Output Register. DRDY will return high upon

completion of a complete Data Output Register read cycle.

The second combination is to set both the BD and MSB bits

to 1. This sets up the interface for ascending byte order and

LSB first format. When this combination is used the user

should always write the Instruction Register such that the

starting byte is the least significant byte address. For

example, read three bytes of DR starting with the least

significant byte. The first byte read will be the least

significant in LSB to MSB format. The next byte will be the

next greater significant (recall ascending byte order) again in

LSB to MSB order. The last byte will be the next greater

significant byte in LSB to MSB order. The entire word was

read MSB to LSB format.

MODE - Mode. This input is used to select between

Synchronous Self Clocking Mode (‘1’) or the Synchronous

External Clocking Mode (‘0’). When this pin is tied to V

the

DD

serial port is configured in the Synchronous Self Clocking

mode where the synchronous shift clock (SCLK) for the serial

port is generated by the HI7190 and has a frequency of

After completion of each communication cycle, The HI7190

interface enters a standby mode while waiting to receive a

new instruction byte.

OSC /8. When the pin is tied to DGND the serial port is

1

configured for the Synchronous External Clocking Mode

where the synchronous shift clock for the serial port is

generated by an external device up to a maximum frequency

of 5MHz.

CS

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE 3

INSTRUCTION

BYTE

Programming the Serial Interface

SDIO

It is useful to think of the HI7190 interface in terms of

communication cycles. Each communication cycle happens

in 2 phases. The first phase of every communication cycle

is the writing of an instruction byte. The second phase is

the data transfer as described by the instruction byte. It is

important to note that phase 2 of the communication cycle

can be a single byte or a multi-byte transfer of data. For

example, the 3-byte Data Output Register can be read

using one multi-byte communication cycle rather than three

single-byte communication cycles. It is up to the user to

maintain synchronism with respect to data transfers. If the

system processor “gets lost” the only way to recover is to

reset the HI7190. Figures 13A and 13B show both a 2-wire

and a 3-wire data transfer.

INSTRUCTION

CYCLE

DATA TRANSFER

FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER

CS

INSTRUCTION

BYTE

SDIO

DATA

INSTRUCTION

CYCLE

BYTE 1

BYTE 2

BYTE 3

SDO

Several formats are available for reading from and writing to

the HI7190 registers in both the 2-wire and 3-wire protocols.

A portion of these formats is controlled by the CR<2:1> (BD

and MSB) bits which control the byte direction and bit order

of a data transfer respectively. These two bits can be written

in any combination but only the two most useful will be

discussed here.

DATA TRANSFER

FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER

Instruction Byte Phase

The instruction byte phase initiates a data transfer

sequence. The processor writes an 8-bit byte (Instruction

Byte) to the Instruction Register. The instruction byte informs

the HI7190 about the Data transfer phase activities and

includes the following information:

The first combination is to reset both the BD and MSB bits

(BD = 0, MSB = 0). This sets up the interface for descending

byte order and MSB first format. When this combination is

used the user should always write the Instruction Register

such that the starting byte is the most significant byte

address. For example, read three bytes of DR starting with

the most significant byte. The first byte read will be the most

significant in MSB to LSB format. The next byte will be the

next least significant (recall descending byte order) again in

MSB to LSB order. The last byte will be the next lesser

significant byte in MSB to LSB order. The entire word was

read MSB to LSB format.

• Read or Write cycle

• Number of Bytes to be transferred

• Which register and starting byte to be accessed

Data Transfer Phase

In the data transfer phase, data transfer takes place as set

by the Instruction Register contents. See Write Operation

and Read Operation sections for detailed descriptions.

FN3612.10

June 27, 2006

17

HI7190

TABLE 6. INTERNAL DATA ACCESS DECODE STARTING

BYTE (Continued)

Instruction Register

The Instruction Register is an 8-bit register which is used

during a communications cycle for setting up read/write

operations.

FSC A3 A2 A1 A0

DESCRIPTION

1

0

1

0

1

0

Negative Full Scale Cal Register, Byte 0

Negative Full Scale Cal Register, Byte 1

Negative Full Scale Cal Register, Byte 2

INSTRUCTION REGISTER

MSB

6

5

4

3

2

1

LSB

R/W

MB1

MB0

FSC

A3

A2

A1

A0

Write Operation

R/W - Bit 7 of the Instruction Register determines whether a

read or write operation will be done following the instruction

byte load. 0 = READ, 1 = WRITE.

Data can be written to the Control Register, Offset

Calibration Register, Positive Full Scale Calibration Register,

and the Negative Full Scale Calibration Register. Write

operations are done using the SDIO, CS and SCLK lines

only, as all data is written into the HI7190 via the SDIO line

even when using the 3-wire configuration. Figures 14 and 15

show typical write timing diagrams.

MB1, MB0 - Bits 6 and 5 of the Instruction Register

determine the number of bytes that will be accessed

following the instruction byte load. See Table 5 for the

number of bytes to transfer in the transfer cycle.

The communication cycle is started by asserting the CS line

low and starting the clock from its idle state. To assert a write

cycle, during the instruction phase of the communication

cycle, the Instruction Byte should be set to a write transfer

(R/W = 1).

TABLE 5. MULTIPLE BYTE ACCESS BITS

MB1

MB0

DESCRIPTION

Transfer 1 Byte

0

1

0

1

0

1

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

When writing to the serial port, data is latched into the

HI7190 on the rising edge of SCLK. Data can then be

changed on the falling edge of SCLK. Data can also be

changed on the rising edge of SCLK due to the 0ns hold time

required on the data. This is useful in pipelined applications

where the data is latched on the rising edge of the clock.

FSC - Bit 4 is used to determine whether a Positive Full Scale

Calibration Register I/O transfer (FSC = 0) or a Negative Full

Scale Calibration Register I/O transfer (FSC = 1) is being

performed (see Table 6).

Read Operation - 3-Wire Transfer

Data can be read from the Data Output Register, Control

Register, Offset Calibration Register, Positive Full Scale

Calibration Register, and the Negative Full Scale Calibration

Register. When configured in 3-wire transfer mode, read

operations are done using the SDIO, SDO, CS and SCLK

lines. All data is read via the SDO line. Figures 16 and 17

show typical 3-wire read timing diagrams.

A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction

Register determine which internal register will be accessed

while bits 1 and 0 (A1 and A0) determine which byte of that

register will be accessed first. See Table 6 for the address

decode.

TABLE 6. INTERNAL DATA ACCESS DECODE STARTING

BYTE

The communication cycle is started by asserting the CS line

and starting the clock from its idle state. To assert a read

cycle, during the instruction phase of the communication

cycle, the Instruction Byte should be set to a read transfer

(R/W = 0).

FSC A3 A2 A1 A0

DESCRIPTION

Data Output Register, Byte 0

Data Output Register, Byte 1

Data Output Register, Byte 2

Control Register, Byte 0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

When reading the serial port, data is driven out of the HI7190

on the falling edge of SCLK. Data can be registered

externally on the next rising edge of SCLK.

Control Register, Byte 1

Read Operation - 2-Wire Transfer

Control Register, Byte 2

Data can be read from the Data Output Register, Control

Register, Offset Calibration Register, Positive Full Scale

Calibration Register, and the Negative Full Scale Calibration

Register. When configured in two-wire transfer mode, read

operations are done using the SDIO, CS and SCLK lines. All

data is read via the SDIO line. Figures 18 and 19 show

typical 2-wire read timing diagrams.

Offset Cal Register, Byte 0

Offset Cal Register, Byte 1

Offset Cal Register, Byte 2

Positive Full Scale Cal Register, Byte 0

Positive Full Scale Cal Register, Byte 1

Positive Full Scale Cal Register, Byte 2

0

FN3612.10

June 27, 2006

18

HI7190

The communication cycle is started by asserting the CS line

and starting the clock from its idle state. To assert a read cycle,

during the instruction phase of the communication cycle, the

Instruction Byte should be set to a read transfer (R/W = 0).

BYTE 2

MSB

22

21

20

19

18

17

16

D23

D22

D21

D20

D19

D18

D17

D16

When reading the serial port, data is driven out of the HI7190

on the falling edge of SCLK. Data can be registered

externally on the next rising edge of SCLK.

BYTE 1

15

14

13

12

11

10

9

8

D15

D14

D13

D12

D11

D10

D9

D8

Detailed Register Descriptions

Data Output Register

BYTE 0

The Data Output Register contains 24 bits of converted data.

This register is a read only register.

7

6

5

4

3

2

1

LSB

D7

D6

D5

D4

D3

D2

D1

D0

IR WRITE PHASE

CS

DATA TRANSFER PHASE - TWO-BYTE WRITE

SCLK

I0

I1

I2

I3

I4

I5

I6

I7

B0

B1 B2

B3 B4

B5

B6 B7

B8 B9 B10 B11 B12 B13 B14 B15

SDIO

SDO

THREE-STATE

FIGURE 14. DATA WRITE CYCLE, SCLK IDLE LOW

IR WRITE PHASE

DATA TRANSFER PHASE - TWO-BYTE WRITE

CS

SCLK

B15

B0

B1 B2 B3 B4 B5 B6

B7

B8 B9 B10 B11 B12 B13 B14

I0

I1

I2

I3

I4

I5

I6

I7

SDIO

SDO

THREE-STATE

FIGURE 15. DATA WRITE CYCLE, SCLK IDLE HIGH

IR WRITE PHASE

DATA TRANSFER PHASE - TWO-BYTE READ

CS

SCLK

I0

I1

I2

I3

I4

I5

I6

I7

SDIO

SDO

B15

B8

B1 B2 B3 B4 B5

B9 B10 B11 B12 B13 B14

B0

B6 B7

FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW

FN3612.10

June 27, 2006

19

HI7190

IR WRITE PHASE

DATA TRANSFER PHASE - TWO-BYTE READ

CS

SCLK

SDIO

SDO

I0

I1

I2

I3

I4

I5

I6

I7

B15

B0

B1 B2 B3 B4 B5 B6

B7

B8 B9 B10 B11 B12 B13 B14

FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH

IR WRITE PHASE

DATA TRANSFER PHASE - TWO-BYTE READ

CS

SCLK

B15

I0

I1

I2

I3

I4

I5

I6

I7

B0

B1 B2

B3 B4 B5

B6 B7

B8

B9 B10 B11 B12 B13 B14

SDIO

SDO

THREE-STATE

FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW

IR WRITE PHASE

DATA TRANSFER PHASE - TWO-BYTE READ

CS

SCLK

B15

I0

I1

I2

I3

I4

I5

I6

I7

B0

B1 B2

B3 B4 B5

B6

B7

B8

B9 B10 B11 B12 B13 B14

SDIO

SDO

THREE-STATE

FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH

DC - Bit 23 is the Data Coding Bit used to select between

two’s complementary and offset binary data coding. When

this bit is set (DC = 1) the data in the Data Output Register

will be two’s complement. When cleared (DC = 0) this data

will be offset binary. When operating in the unipolar mode

the output data is available in straight binary only (the DC bit

is ignored). This bit is cleared after a RESET is applied to the

part.

Control Register

The Control Register contains 24-bits to control the various

sections of the HI7190. This register is a read/write

register.

BYTE 2

MSB

22

21

20

19

18

17

16

DC

FP10

FP9

FP8

FP7

FP6

FP5

FP4

FP10 through FP0 - Bits 22 through 12 are the Filter

programming bits that determine the frequency response of

the digital filter. These bits determine the filter cutoff

frequency, the position of the first notch and the data rate of

the HI7190. The first notch of the filter is equal to the

decimation rate and can be determined by the formula:

BYTE 1

15

14

13

12

11

10

9

8

FP3

FP2

FP1

FP0

MD2

MD1

MD0

B/U

f

= f

/(512 x CODE)

OSC

NOTCH

BYTE 0

where CODE is the decimal equivalent of the value in FP10

through FP0. The values that can be programmed into these

bits are 10 to 2047 decimal, which allows a conversion rate

range of 9.54Hz to 1.953kHz when using a 10MHz clock.

7

6

5

4

3

2

1

LSB

G2

G1

G0

BO

SB

BD

MSB

SDL

FN3612.10

June 27, 2006

20

HI7190

Changing the filter notch frequency, as well as the selected

gain, impacts resolution. The output data rate (or effective

conversion time) for the device is equal to the frequency

selected for the first notch to the filter. For example, if the

first notch of the filter is selected at 50Hz then a new word is

available at a 50Hz rate or every 20ms. If the first notch is at

1kHz a new word is available every 1ms.

can be used to detect the presence of an external

connection to V . This bit is cleared after a RESET is

INHI

applied to the part.

SB - Bit 3 is the Standby Mode enable bit used to put the

HI7190 in a lower power/standby mode. When this bit is set

(SB = 1) the filter nodes are halted, the DRDY line is set high

and the modulator clock is disabled. When this bit is cleared

the HI7190 begins operation as described by the contents of

the Control Register. For example, if the Control Register is

programmed for Self Calibration Mode and a notch

frequency to 10Hz, the HI7190 will perform the self

calibration before providing the data at the 10Hz rate. This

bit is cleared after a RESET is applied to the part.

The settling-time of the converter to a full scale step input

change is between 3 and 4 times the data rate. For example,

with the first filter notch at 50Hz, the worst case settling time

to a full scale step input change is 80ms. If the first notch is

1kHz, the settling time to a full scale input step is 4ms

maximum.

The -3dB frequency is determined by the programmed first

notch frequency according to the relationship:

BD - Bit 2 is the Byte Direction bit used to select the multi-

byte access ordering. The bit determines the either

ascending or descending order access for the multi-byte

registers. When set (BD = 1) the user can access multi-byte

registers in ascending byte order and when cleared (BD = 0)

the multi-byte registers are accessed in descending byte

order. This bit is cleared after a RESET is applied to the part.

f

= 0.262 x f

.

NOTCH

-3dB

MD2 through MD0 - Bits 11 through 9 are the Operational

Modes of the converter. See Table 4 for the Operational

Modes description. After a RESET is applied to the part

these bits are set to the self calibration mode.

MSB - Bit 1 is used to select whether a serial data transfer is

MSB or LSB first. This bit allows the user to change the

order that data can be transmitted or received by the

HI7190. When this bit is cleared (MSB = 0) the MSB is the

first bit in a serial data transfer. If set (MSB = 1), the LSB is

the first bit transferred in the serial data stream. This bit is

cleared after a RESET is applied to the part.

B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is

set the HI7190 is configured for bipolar operation. When this

bit is reset the part is in unipolar mode. This bit is set after a

RESET is applied to the part.

G2 through G0 - Bits 7 through 5 select the gain of the input

analog signal. The gain is accomplished through a

programmable gain instrumentation amplifier that gains up

incoming signals from 1 to 8. This is achieved by using a

switched capacitor voltage multiplier network preceding the

modulator. The higher gains (i.e., 16 to 128) are achieved

through a combination of a PGIA gain of 8 and a digital

multiply after the digital filter (see Table 7). The gain will

affect noise and Signal to Noise Ratio of the conversion.

These bits are cleared to a gain of 1 (G2, G1, G0 = 000) after

a RESET is applied to the part.

SDL - Bit 0 is the Serial Data Line control bit. This bit selects

the transfer protocol of the serial interface. When this bit is

cleared (SDL = 0), both read and write data transfers are

done using the SDIO line. When set (SDL = 1), write

transfers are done on the SDIO line and read transfers are

done on the SDO line. This bit is cleared after a RESET is

applied to the part.

Reading the Data Output Register

The HI7190 generates an active low interrupt (DRDY)

indicating valid conversion results are available for reading.

At this time the Data Output Register contains the latest

conversion result available from the HI7190. Data integrity is

maintained at the serial output port but it is possible to miss

a conversion result if the Data Output Register is not read

within a given period of time. Maintaining data integrity

means that if a Data Output Register read of conversion N is

begun but not finished before the next conversion

TABLE 7. GAIN SELECT BITS

G2

0

G1

0

G0

0

GAIN

1

GAIN ACHIEVED

PGIA = 1, Filter Multiply = 1

PGIA = 2, Filter Multiply = 1

PGIA = 4, Filter Multiply = 1

PGIA = 8, Filter Multiply = 1

PGIA = 8, Filter Multiply = 2

PGIA = 8, Filter Multiply = 4

PGIA = 8, Filter Multiply = 8

PGIA = 8, Filter Multiply = 16

0

1

2

0

1

0

4

0

1

8

1

0

16

32

64

128

(conversion N + 1) is complete, the DRDY line remains

active low and the data being read is not overwritten.

1

0

1

0

In addition to the Data Output Register, the HI7190 has a

one conversion result storage buffer. No conversion results

will be lost if the following constraints are met.

1

BO - Bit 4 is the Transducer Burn-Out Current source enable

1) A Data Output Register read cycle is started for a given

bit. When this bit is set (BO = 1) the burn-out current source

conversion (conversion X) 1/f - (128*1/f

) after DRDY

initially goes active low. Failure to start the read cycle may

N

OSC

connected to V

internally is enabled. This current source

INHI

FN3612.10

June 27, 2006

21

HI7190

result in conversion X + 1 data overwriting conversion X

Positive Full Scale Calibration Register

results. For example, with f

read cycle must start within 1/2000 - 128(1/10 ) = 487μs

after DRDY went low.

= 10MHz, f = 2kHz, the

OSC

N

The Positive Full Scale Calibration Register is a 24-bit

register containing the Positive Full Scale correction

coefficient. This coefficient is used to determine the positive

gain slope factor. This register is indeterminate on power-up

but will contain a Self Calibration correction coefficient after

a RESET has been applied.

6

2) The Data Output Register read cycle for conversion X

must be completed within 2(1/f )-1440(1/f

initially goes active low. If the read cycle for conversion X is

not complete within this time the results of conversion X + 1

are lost and results from conversion X + 2 are now stored in

the data output word buffer.

) after DRDY

N

OSC

BYTE 2

MSB

22

21

20

19

18

17

16

P23

P22

P21

P20

P19

P18

P17

P16

Completing the Data Output Register read cycle inactivates

the DRDY interrupt. If the one word data output buffer is full

when this read is complete this data will be immediately

transferred to the Data Output Register and a new DRDY

interrupt will be issued after the minimum DRDY pulse high

time is met.

BYTE 1

15

14

13

12

11

10

9

8

P15

P14

P13

P12

P11

P10

P9

P8

Writing the Control Register

If data is written to byte 2 and/or byte 1 of the Control

Register the DRDY output is taken high and the device re-

calibrates if written to a calibration mode. This action is taken

because it is assumed that by writing byte 2 or byte 1 that

the user either reprogrammed the filter or changed modes of

the part. However, if a single data byte is written to byte 0, it

is assumed that the gain has NOT been changed. It is up to

the user to re-calibrate the HI7190 after the gain has been

changed by this method. It is recommended that the entire

Control Register be written to when changing the selected

gain. This ensures that the part is re-calibrated before the

DRDY signal goes low indicating valid data is available.

BYTE 0

7

6

5

4

3

2

1

LSB

P7

P6

P5

P4

P3

P2

P1

P0

Negative Full Scale Calibration Register

The Negative Full Scale Calibration Register is a 24-bit

register containing the Negative Full Scale correction

coefficient. This coefficient is used to determine the negative

gain slope factor. This register is indeterminate on power-up

but will contain a Self Calibration correction coefficient after

a RESET has been applied.

BYTE 2

Offset Calibration Register

MSB

22

21

20

19

18

17

16

The Offset Calibration Register is a 24-bit register containing

the offset correction factor. This register is indeterminate on

power-up but will contain a Self Calibration correction value

after a RESET has been applied.

N23

N22

N21

N20

N19

N18

N17

N16

BYTE 1

BYTE 2

15

14

13

12

11

10

9

8

MSB

22

21

20

19

18

17

16

N15

N14

N13

N12

N11

N10

N9

N8

O23

O22

O21

O20

O19

O18

O17

O16

BYTE 0

BYTE 1

7

6

5

4

3

2

1

LSB

15

14

13

12

11

10

9

8

N7

N6

N5

N4

N3

N2

N1

N0

O15

O14

O13

O12

O11

O10

O9

O8

BYTE 0

7

6

5

4

3

2

1

LSB

O7

O6

O5

O4

O3

O2

O1

O0

The Offset Calibration Register holds the value that corrects

the filter output data to all 0’s when the analog input is 0V.

FN3612.10

June 27, 2006

22

HI7190

SUBSTRATE POTENTIAL (POWERED UP)

AV

Die Characteristics

SS

DIE DIMENSIONS

PASSIVATION

3550μm x 6340μm

Type: Sandwich

Thickness:Nitride 8kÅ

USG 1kÅ

METALLIZATION

Type: AlSiCu

Thickness:Metal 2, 16kÅ

Metal 1, 6kÅ

Metallization Mask Layout

HI7190

OSC

CS

1

DRDY

DGND

OSC

2

DV

DD

AV

SS

AGND

FN3612.10

June 27, 2006

23

HI7190

Dual-In-Line Plastic Packages (PDIP)

N

E20.3 (JEDEC MS-001-AD ISSUE D)

E1

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INDEX

AREA

1 2

3

N/2

INCHES

MILLIMETERS

-B-

-C-

SYMBOL

MIN

MAX

0.210

-

MIN

-

MAX

5.33

-

NOTES

-A-

A

A1

A2

B

-

4

D

E

0.015

0.115

0.014

0.045

0.008

0.980

0.005

0.300

0.240

0.39

2.93

0.356

1.55

0.204

24.89

0.13

7.62

6.10

4

BASE

PLANE

A2

A

0.195

0.022

0.070

0.014

1.060

-

4.95

0.558

1.77

0.355

26.9

-

SEATING

PLANE

-

L

C

L

B1

C

8

D1

B1

e_A

A1

A

D1

-

e

e_C

C

B

D

5

e_B

0.010 (0.25) M

C

B S

D1

E

5

0.325

0.280

8.25

7.11

6

E1

e

5

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

-

e

6

A

B

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

-

0.430

0.150

-

10.92

3.81

7

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication No. 95.

L

0.115

2.93

4

9

4. Dimensions A, A1 and L are measured with the package seated in

N

20

JEDEC seating plane gauge GS-3.

Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

e

6. E and

dicular to datum

7. e and e are measured at the lead tips with the leads uncon-

are measured with the leads constrained to be perpen-

A

-C-

.

B

C

strained. e must be zero or greater.

C

8. B1 maximum dimensions do not include dambar protrusions. Dam-

bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

FN3612.10

June 27, 2006

24

HI7190

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

N

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

M

B

0.25(0.010)

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.35

0.23

MAX

2.65

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.014

0.1043

0.0118

0.019

-

0.30

-

1

2

3

L

0.49

9

SEATING PLANE

A

0.0091

0.4961

0.2914

0.0125

0.32

-

-A-

0.5118 12.60

13.00

7.60

3

D

h x 45°

0.2992

7.40

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

M

S

B

0.25(0.010)

C

A

N

α

20

7

0°

8°

0°

8°

-

NOTES:

Rev. 2 6/05

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN3612.10

June 27, 2006

25

型号	制造商	描述	替代类型	文档
HI7190IB	INTERSIL	null24-Bit, High Precision, Sigma Delta A/D Converter	完全替代
HI7190IBZ-T	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	完全替代

型号	制造商	描述	价格	文档
HI7190IBZ-T	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7190IJ	RENESAS	24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20	获取价格
HI7190IP	INTERSIL	null24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7190IPZ	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7190_06	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7191	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7191	RENESAS	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7191IB	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格
HI7191IB-T	RENESAS	1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20, PLASTIC, MS-013-AC, SOIC-20	获取价格
HI7191IBZ	INTERSIL	24-Bit, High Precision, Sigma Delta A/D Converter	获取价格

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