HCTS164DMSR_技术文档

TM

HCTS164MS

Radiation Hardened

8-Bit Serial-In/Parallel-Out Shift Register

August 1995

Features

Pinouts

• 3 Micron Radiation Hardened CMOS SOS

14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T14

• Total Dose 200K RAD (Si)

TOP VIEW

12

• Dose Rate Survivability >10 RAD (Si)/s (20ns Pulse)

10

• Dose Rate Upset >10 RAD (Si)/s (20ns Pulse)

DS1

DS2

Q0

VCC

Q7

1

2

3

4

5

6

7

14

13

-9

• Single Event Ray Upset Rate < 2 x 10 Errors/Bit Day

(Typ)

12 Q6

2

• LET Threshold >100 MEV-cm /mg

Q1

Q5

Q4

MR

CP

11

10

9

• Latch-Up-Free Under Any Conditions

Q2

o

• Military Temperature Range: -55 C to +125 C

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

Q3

GND

8

• Input Logic Levels

-VIL = 0.8 VCC (Max)

-VIH = VCC/2 (Min)

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835, CDFP3-F14

TOP VIEW

• Input Current Levels Ii ≤5µA at VOL, VOH

DS1

DS2

Q0

VCC

Q7

1

2

3

4

5

6

7

14

13

12

11

10

9

Description

Q6

The Intersil HCTS164MS is a radiation hardened 8-bit Serial-In/

Parallel-Out Shift Register with asynchronous reset.

Q1

Q5

Q2

Q4

The HCTS164MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

Q3

MR

CP

GND

8

Ordering Information

PART NUMBER

HCTS164DMSR

TEMPERATURE RANGE

-55^oC to +125^oC

+25^oC

SCREENING LEVEL

Intersil Class S Equivalent

Sample

PACKAGE

14 Lead SBDIP

HCTS164KMSR

14 Lead Ceramic Flatpack

14 Lead SBDIP

HCTS164D/Sample

HCTS164K/Sample

HCTS164HMSR

+25^oC

Sample

14 Lead Ceramic Flatpack

Die

Truth Table

INPUTS

OUTPUTS

OPERATING

MODE

MR

L

CP

DS1†

DS2†

Q0

L

Q1-Q7

L-L

Reset (Clear)

Shift

X

L

X

L

H

L

q0 -q6

q0 - q6

H

L

H

L

H

L

H

H = High Voltage Level

L = Low Voltage Level

= LOW-to-HIGH clock transition

q = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition

† = DS1 and DS2 inputs must be at state one setup prior to CP (rising edge)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

FN 3386.1

Spec Number 518613

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

1

HCTS164MS

Functional Diagram

CP

DS1

DS2

CL

R

CL

R

CL

R

CL

R

CL

R

CL

R

CL

R

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

R

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Spec Number 518613

2

Specifications HCTS164MS

Absolute Maximum Ratings

Reliability Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG). . . . . . . . . . . -65^oC to +150^oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +265^oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175^oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance

θ_JA

θ_JC

SBDIP Package. . . . . . . . . . . . . . . . . . . .

74^oC/W

24^oC/W

Ceramic Flatpack Package . . . . . . . . . . . 116^oC/W 30^oC/W

Maximum Package Power Dissipation at +125^oAmbient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . .0.43W

If device power exceeds package dissipation capability provide heat

sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/^oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/^oC

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent

damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed

under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . 100ns/V Max

Operating Temperature Range (T_A). . . . . . . . . . . . -55^oC to +125^oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V

Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . VCC to VCC/2V

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

A SUB-

LIMITS

(NOTE 1)

PARAMETERS

SYMBOL

CONDITIONS

GROUPS

TEMPERATURE

+25^oC

MIN

MAX

UNITS

µA

Supply Current

ICC

VCC = 5.5V,

1

-

40

VIN = VCC or GND

2, 3

1

+125^oC, -55^oC

+25^oC

-

750

µA

Output Current

(Sink)

IOL

IOH

VOL

VCC = VIH = 4.5V,

VOUT = 0.4V, VIL = 0V

(Note 2)

4.8

4.0

-

mA

2, 3

+125^oC, -55^oC

mA

Output Current

(Source)

VCC = VIH = 4.5V,

VOUT = VCC -0.4V,

VIL = 0V (Note 2)

1

+25^oC

-4.8

-4.0

-

mA

2, 3

+125^oC, -55^oC

Output Voltage Low

VCC = 4.5V, VIH = 2.25V,

IOL = 50µA, VIL = 0.8V

1, 2, 3

+25^oC, +125^oC, -55^oC

-

0.1

-

V

VCC = 5.5V, VIH = 2.75V,

IOL = 50µA, VIL = 0.8V

Output Voltage High

VOH

VCC = 4.5V, VIH = 2.25V,

IOH = -50µA, VIL = 0.8V

VCC

-0.1

VCC = 5.5V, VIH = 2.75V,

IOH = -50µA, VIL = 0.8V

VCC

-0.1

-

Input Leakage

Current

IIN

FN

VCC = 5.5V, VIN = VCC or

GND

1

+25^oC

-

±0.5

±5.0

-

µA

-

2, 3

+125^oC, -55^oC

Noise Immunity

Functional Test

VCC = 4.5V, VIH = 2.25V,

VIL = 0.8V (Note 2)

7, 8A, 8B

+25^oC, +125^oC, -55^oC

NOTES:

1. All voltages reference to device GND.

2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.

Spec Number 518613

3

Specifications HCTS164MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

LIMITS

(NOTES 1, 2)

A SUB-

PARAMETER

CP to Qn

SYMBOL

CONDITIONS

GROUPS

TEMPERATURE

+25^oC

MIN

MAX

26

UNITS

ns

TPLH

VCC = 4.5V

9

2

VCC = 4.5V

10, 11

9

+125^oC, -55^oC

+25^oC

33

ns

CP to Qn

MR to Qn

NOTES:

TPHL

33

ns

10, 11

9

+125^oC, -55^oC

+25^oC

40

ns

34

ns

10, 11

+125^oC, -55^oC

42

ns

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3.0V.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

(NOTE 1)

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

+25^oC

MIN

MAX

135

210

10

UNITS

pF

Capacitance Power

Dissipation

CPD

VCC = 5.0V, f = 1MHz

1

-

+125^oC, -55^oC

+25^oC

pF

Input Capacitance

Output Transition Time

NOTE:

CIN

VCC = 5.0V, f = 1MHz

VCC = 4.5V

pF

+125^oC, -55^oC

+25^oC

10

pF

TTHL

TTLH

15

ns

+125^oC, -55^oC

22

ns

1. The parameters listed in Table 3 are controlled via design or process parameters. Minimum and Maximum Limits are guaranteed, but not

directly tested. These parameters are characterized upon initial design release and upon design changes which affect these character-

istics.

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

200K RAD

LIMITS

(NOTES 1, 2)

PARAMETERS

Quiescent Current

SYMBOL

ICC

CONDITIONS

TEMP

+25^oC

MIN

-

MAX

0.75

-

UNITS

mA

VCC = 5.5V, VIN = VCC or GND

Output Current (Sink)

Output Current (Source)

Output Voltage Low

Output Voltage High

Input Leakage Current

IOL

VCC = 4.5V, VIN = VCC or GND, VOUT =

0.4V

4.0

mA

IOH

VOL

VOH

VCC = 4.5V, VIN = VCC or GND, VOUT =

VCC -0.4V

+25^oC

-4.0

-

0.1

-

mA

V

VCC = 4.5V and 5.5V, VIH = VCC/2,

VIL = 0.8V, IOL = 50µA

VCC = 4.5V and 5.5V, VIH = VCC/2,

VIL = 0.8V, IOH = -50µA

VCC

-0.1

V

IIN

FN

VCC = 5.5V, VIN = VCC or GND

+25^oC

-

±5

µA

Noise Immunity

Functional Test

VCC = 4.5V, VIH = VCC/2, VIL = 0.8V,

(Note 3)

-

Spec Number 518613

4

Specifications HCTS164MS

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

200K RAD

LIMITS

(NOTES 1, 2)

PARAMETERS

CP to Qn

SYMBOL

TPLH

CONDITIONS

TEMP

+25^oC

MIN

MAX

33

UNITS

ns

VCC = 4.5V

2

CP to Qn

MR to Qn

NOTES:

TPHL

40

ns

TPHL

42

ns

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

3. For functional tests VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25^oC)

GROUP B

PARAMETER

SUBGROUP

DELTA LIMIT

ICC

5

12µA

IOL/IOH

-15% of 0 Hour

TABLE 6. APPLICABLE SUBGROUPS

GROUP A SUBGROUPS

CONFORMANCE GROUPS

METHOD

100%/5004

Sample/5005

READ AND RECORD

ICC, IOL/H

Initial Test (Preburn-In)

1, 7, 9

Interim Test 1 (Postburn-In)

Interim Test 2 (Postburn-In)

PDA

ICC, IOL/H

1, 7, 9

1, 7, 9, Deltas

1, 7, 9

Interim Test 3 (Postburn-In)

PDA

ICC, IOL/H

1, 7, 9, Deltas

2, 3, 8A, 8B, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

1, 7, 9

Final Test

Group A (Note 1)

Group B

Subgroup B-5

Subgroup B-6

Subgroups 1, 2, 3, 9, 10, 11

Group D

NOTE:

1, 7, 9

1. Alternate Group A Testing in accordance with Method 5005 of MIL-STD-883 may be exercised.

TABLE 7. TOTAL DOSE IRRADIATION

TEST

READ AND RECORD

CONFORMANCE

GROUPS

Group E Subgroup 2

NOTE:

METHOD

PRE RAD

POST RAD

PRE RAD

1, 9

POST RAD

5005

1, 7, 9

Table 4

Table 4 (Note 1)

1. Except FN Test which will be performed 100% Go/No-Go.

Spec Number 518613

5

Specifications HCTS164MS

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

OSCILLATOR

OPEN

STATIC BURN-IN I TEST CONNECTIONS (Note 1)

3 - 6, 10 - 13 1, 2, 7 - 9

STATIC BURN-IN II TEST CONNECTIONS (Note 1)

3 - 6, 10 - 13

DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)

3 - 6, 10 - 13

GROUND

1/2 VCC = 3V ±0.5V

VCC = 6V ±0.5V

14

50kHz

25kHz

-

7

1, 2, 8, 9, 14

9, 14

-

7

8

1, 2

NOTES:

1. Each pin except VCC and GND will have a resistor of 10KΩ ±5% for static burn-in.

2. Each pin except VCC and GND will have a resistor of 1KΩ ±5% for dynamic burn-in.

TABLE 9. IRRADIATION TEST CONNECTIONS

OPEN

GROUND

VCC = 5V ±0.5V

3 - 6, 10 - 13

7

1, 2, 8, 9, 14

NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ±5% for Irradiation Testing.

Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.

AC Timing Diagrams and Load Circuit

DUT

TEST

POINT

VIH

INPUT

VS

VIL

CL

RL

TPLH

TPHL

VOH

VOL

VOH

VOL

VS

OUTPUT

CL = 50pF

RL = 500Ω

TTLH

TTHL

80%

20%

OUTPUT

AC VOLTAGE LEVELS

PARAMETER

VCC

HCTS

4.50

3.0

1.3

0

UNITS

V

VIH

VS

VIL

GND

0

Spec Number 518613

6

HCTS164MS

Die Characteristics

WORST CASE CURRENT DENSITY:

< 2.0 x 10 A/cm

DIE DIMENSIONS:

95 mils x 95 mils

5

2

2.380mm x 2.410mm

BOND PAD SIZE:

100µm x 100µm

4 mils x 4 mils

METALLIZATION:

Type: AlSi

Metal Thickness: 11kÅ ±1kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 13kÅ ±2.6kÅ

Metallization Mask Layout

HCTS164MS

DS2

(2)

DS1

(1)

VCC

(14)

Q7

Q6

(13)

(12)

Q0 (3)

Q1 (4)

NC

(11) Q5

NC

(10) Q4

(5)

Q2

(6)

(7)

(8)

(9)

(MR)

Q3

GND

CP

Spec Number 518613

7

HCTS164MS

Intersil Space Level Product Flow - MS

Wafer Lot Acceptance, All Lots (including SEM);

100% Interim Electrical Test (T1)

Method 5007

100% Delta Calculation (T0-T1)

Gamma Radiation Verification, Each Wafer, 4 Samples/

Wafer, 0 Rejects, Method 1019

100% Static Burn-In 2, Method 1015, Condition A or B, 24

o

Hours Minimum, + 125 C Minimum

100% Nondestructive Bond Pull, Method 2023

Sample Wire Bond Pull Monitor, Method 2011

Sample Die Shear Monitor, Method 2019 or 2027

100% Internal Visual Inspection - Method 2010, Condition A

100% Interim Electrical Test 2 (T2)

100% Delta Calculation (T0-T2)

100% PDA 1, Method 5004 (see Notes 1, 2)

o

100% Dynamic Burn-In, Condition D, 240 Hours, +125 C or

100% Temperature Cycling, Method 1010, Condition C,

10 Cycles

Equivalent per Method 1015

100% Interim Electrical Test 3 (T3)

100% Delta Calculation (T0-T3)

100% Constant Acceleration Method 2001, Condition per

Method 5004

100% PDA 2, Method 5004 (see Note 2)

100% Final Electrical Test

100% PIND, Method 2020, Condition A

100% External Visual

100% Fine/Gross Leak, Method 1014

100% Radiographic, Method 2012 (see Note 3)

100% External Visual, Method 2009

Sample Group A, Method 5005 (see Note 4)

100% Data Package Generation (see Note 5)

100% Serialization

100% Initial Electrical Test (T0)

100% Static Burn-In 1, Method 1015, Condition A or B,

o

24 Hours Minimum, +125 C minimum

NOTES:

1. Failures from Interim Electrical Test 1 and 2 are combined for determining PDA 1.

2. Failures from subgroups 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the

failures from subgroup 7.

3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.

4. Alternate Group A as allowed by MIL-STD-883, Method 5005 may be performed.

5. Data package contains:

• Cover Sheet (Intersil name and/or logo, PO #, customer part #, lot date code, Intersil part #, lot #, quantity).

• Wafer lot acceptance report (Method 5007). Includes reproductions of SEM photos with % step coverage. GAMMA Radiation Report. Con-

tains cover page, disposition, rad dose, Lot #, test package used, specifications #s, test equipment, etc. radiation read and record data on

file at Intersil.

• X- Ray report and film. Includes pentrameter measurements.

• Screening, electrical, and group A attributes (screening attributes begin after package seal).

• Lot serial number sheet (good units serial # and lot #).

• Variables data (all delta operations). Data is identified by serial number. The data header includes lot # and date of test.

• The Certification of Conformance is part of the shipping invoice and is not part of the data book. The Certificate of Conformance is signed

by an authorized quality representative.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation

7585 Irvine Center Drive

Suite 100

Irvine, CA 92618

TEL: (949) 341-7000

FAX: (949) 341-7123

EUROPE

ASIA

Intersil Corporation

2401 Palm Bay Rd.

Palm Bay, FL 32905

TEL: (321) 724-7000

FAX: (321) 724-7946

Intersil Europe Sarl

Ave. William Graisse, 3

1006 Lausanne

Switzerland

TEL: +41 21 6140560

FAX: +41 21 6140579

Unit 1804 18/F Guangdong Water Building

83 Austin Road

TST, Kowloon Hong Kong

TEL: +852 2723 6339

FAX: +852 2730 1433

Spec Number 518613

8


型号：	HCTS164DMSR
厂家：	Intersil
描述：	Radiation Hardened 8-Bit Serial-In/Parallel-Out Shift Register 抗辐射的8位串行输入/并行输出移位寄存器移位寄存器触发器逻辑集成电路 CD
文件：	总8页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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