HCA10014 [INTERSIL]
15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output; 15MHz的，采用BiMOS与MOSFET的输入运算放大器/ CMOS输出
| 型号： | HCA10014 |
| 厂家： | 
Intersil |
| 描述： | 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output |
| 文件： | 总17页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCA10014
Data Sheet
August 1999
File Number 4769
15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
Features
• MOSFET Input Stage Provides:
12
HCA10014 op amp combines the advantage of both CMOS
and bipolar transistors.
- Very High Z = 1.5TΩ (1.5 x 10 Ω) (Typ)
I
- Very Low I
I
15V Operation. . . . . . . . . . . . . . . . . . . . . . . . . 5pA (Typ)
5V Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ)
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common mode input voltage capability down to
0.5V below the negative supply terminal, an important
attribute in single supply applications.
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
A CMOS transistor pair, capable of swinging the output
voltage to within 10mV of either supply voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample and Hold Amplifiers
• Long Duration Timers/Monostables
The HCA10014 operates at supply voltages ranging from 5V
to 16V, (±2.5V to ±8V). It can be phase compensated with a
single external capacitor, and have terminals for adjustment
of offset voltage for applications requiring offset null
capability. Terminal provisions are also made to permit
strobing of the output stage.
• High Input Impedance Comparators
(Ideal Interface with Digital CMOS)
• High Input Impedance Wideband Amplifiers
Pinout
• Voltage Followers (e.g., Follower for Single Supply D/A
Converter)
HCA10014
(SOIC)
TOP VIEW
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
• Peak Detectors
OFFSET
1
2
3
4
8
7
6
5
STROBE
V+
NULL
• Single Supply Full Wave Precision Rectifiers
• Photo Diode Sensor Amplifiers
INV.
INPUT
NON-INV.
INPUT
-
+
OUTPUT
V-
OFFSET
NULL
Ordering Information
PART NO.
(BRAND)
TEMP.
RANGE ( C)
o
PACKAGE
PKG. NO.
HCA10014
-55 to 125 8 Ld SOIC
M8.15
Tape and Reel
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HCA10014
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
θ
( C/W)
JA
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
o
Maximum Junction Temperature (Metal Can Package) . . . . . . .175 C
o
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50 C to 125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, V+ = 15V, V- = 0V, Unless Otherwise Specified
A
TEST
PARAMETER
Input Offset Voltage
SYMBOL
|V
CONDITIONS
MIN
TYP
8
MAX
15
-
UNITS
|
V
= ±7.5V
-
mV
IO
S
o
Input Offset Voltage Temperature Drift
Input Offset Current
∆V /∆T
IO
-
10
µV/ C
|I
|
V
V
= ±7.5V
= ±7.5V
-
0.5
5
30
50
-
pA
pA
kV/V
dB
dB
V
IO
S
S
Input Current
I
-
50
94
70
0
I
Large Signal Voltage Gain
A
V
= 10V , R = 2kΩ
P-P
320
110
90
OL
O
L
-
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Maximum Output Voltage
CMRR
-
V
-0.5 to 12
32
10
320
-
ICR
∆V /∆V
IO
V
= ±7.5V
S
-
µV/V
V
S
V
+
R
= 2kΩ
= 2kΩ
= ∞
12
-
13.3
0.002
15
OM
L
L
L
L
V
-
R
R
R
0.01
-
V
OM
V
+
-
14.99
-
V
OM
V
= ∞
0
0.01
45
45
15
3
V
OM
Maximum Output Current
Supply Current
I
I
+ (Source) at V = 0V
12
12
-
22
mA
mA
mA
mA
OM
O
- (Sink) at V = 15V
20
OM
O
I+
I+
V
= 7.5V, R = ∞
10
O
L
V
= 0V, R = ∞
-
2
O
L
2
HCA10014
o
Electrical Specifications Typical Values Intended Only for Design Guidance, V
= ±7.5V, T = 25 C
A
SUPPLY
Unless Otherwise Specified
PARAMETER
Input Offset Voltage Adjustment Range
Input Resistance
SYMBOL
TEST CONDITIONS
TYP
±22
1.5
4.3
23
UNITS
mV
10kΩ Across Terminals 4 and 5 or 4 and 1
R
C
TΩ
I
I
Input Capacitance
f = 1MHz
pF
Equivalent Input Noise Voltage
e
BW = 0.2MHz, R = 1MΩ (Note 3)
µV
N
T
S
Open Loop Unity Gain Crossover Frequency
(for Unity Gain Stability ≥47pF Required)
f
C
C
= 0
15
MHz
MHz
C
C
= 47pF
4
Slew Rate:
Open Loop
SR
C
C
C
= 0
30
10
V/µs
V/µs
C
C
C
Closed Loop
= 56pF
Transient Response:
Rise Time
= 56pF, C = 25pF, R = 2kΩ (Voltage Follower)
L L
t
0.09
10
µs
%
r
Overshoot
OS
Settling Time (To <0.1%, V = 4V
IN
)
t
1.2
µs
P-P
S
NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of R up to 10MΩ.
S
3
HCA10014
Typical Performance Curves
120
100
150
AOL
SUPPLY VOLTAGE: V+ = 15V; V- = 0
LOAD RESISTANCE = 2kΩ
o
T
= 25 C
A
140
4
φ OL
-100
3
1
130
120
110
100
90
80
60
40
20
0
2
2
3
-200
-300
1
4
80
1
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
-100
-50
0
50
100
FREQUENCY (Hz)
o
TEMPERATURE ( C)
1 - C = 9pF, C = 0pF, R = ∞ 3 - C = 30pF, C = 47pF, R = 2kΩ
L
C
L
L
C
L
2 - C = 30pF, C = 15pF, R = 2kΩ
4 - C = 30pF, C = 150pF, R = 2kΩ
L C L
L
C
L
FIGURE 1. OPEN LOOP GAIN vs TEMPERATURE
FIGURE 2. OPEN LOOP RESPONSE
17.5
14
LOAD RESISTANCE =
∞
OUTPUT VOLTAGE = V+/2
V- = 0
o
T
= 25 C
o
A
T
= -55 C
12
10
8
A
12.5
10
7.5
5
OUTPUT VOLTAGE BALANCED = V+/2
V- = 0
o
25 C
o
125 C
6
4
OUTPUT VOLTAGE HIGH = V+
OR LOW = V-
2.5
0
2
0
0
2
4
6
8
10
12
14
16
4
6
8
10
12
14
16
18
TOTAL SUPPLY VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
50
50
NEGATIVE SUPPLY VOLTAGE = 0V
NEGATIVE SUPPLY VOLTAGE = 0V
15V
o
15V
T
= 25 C
o
A
10V
T
= 25 C
A
10
10
10V
POSITIVE SUPPLY VOLTAGE = 5V
POSITIVE SUPPLY VOLTAGE = 5V
1
1
0.1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
1.0
10
100
0.001
0.01
0.1
1
10
100
MAGNITUDE OF LOAD CURRENT (mA)
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 5. VOLTAGE ACROSS PMOS OUTPUT
FIGURE 6. VOLTAGE ACROSS NMOS OUTPUT
TRANSISTOR (Q ) vs LOAD CURRENT
TRANSISTOR (Q ) vs LOAD CURRENT
8
12
4
HCA10014
Schematic Diagram
V+
CURRENT SOURCE FOR
Q AND Q
“CURRENT SOURCE
LOAD” FOR Q
7
BIAS CIRCUIT
11
6
7
Q
Q
Q
3
1
2
D
D
D
D
1
2
3
4
Z
8.3V
1
Q
Q
5
4
R
1
40kΩ
R
2
5kΩ
SECOND
STAGE
INPUT STAGE
D
D
D
D
8
5
6
7
(NOTE 4)
NON-INV.
INPUT
OUTPUT
STAGE
3
+
INV.-INPUT
Q
Q
8
Q
Q
OUTPUT
6
7
2
-
6
R
R
4
3
1kΩ
1kΩ
Q
Q
10
9
12
Q
11
R
1kΩ
R
1kΩ
5
6
V-
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
NOTE:
4. Diodes D through D provide gate-oxide protection for MOSFET input stage.
5
8
Application Information
ohmic load resistance presented to the amplifier is very high
(e.g., when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Circuit Description
Figure 7 is a block diagram of the HCA10014. The input
terminals may be operated down to 0.5V below the negative
supply rail, and the output can be swung very close to either
supply rail in many applications. Consequently, the
HCA10014 is ideal for single supply operation. Three
Class A amplifier stages, having the individual gain
capability and current consumption shown in Figure 7,
provide the total gain of the HCA10014. A biasing circuit
provides two potentials for common use in the first and
second stages. Terminal 8 can be used both for phase
compensation and to strobe the output stage into
quiescence. When Terminal 8 is tied to the negative supply
rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of
essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
Input Stage
The circuit is shown in the schematic diagram. It consists of
a differential input stage using PMOS field effect transistors
(Q , Q ) working into a mirror pair of bipolar transistors (Q ,
6
7
9
Q
) functioning as load resistors together with resistors R
10
3
through R . The mirror pair transistors also function as a
6
differential to single ended converter to provide base drive to
the second stage bipolar transistor (Q ). Offset nulling,
11
when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade connected
PMOS transistors Q , Q are the constant current source for
2
4
the input stage. The biasing circuit for the constant current
source is subsequently described. The small diodes D
5
5
HCA10014
through D provide gate oxide protection against high
voltage transients, including static electricity during handling
At total supply voltages somewhat less than 8.3V, zener
diode Z becomes nonconductive and the potential,
8
1
for Q and Q .
developed across series connected R , D -D , and Q ,
6
7
1 1 4 1
varies directly with variations in supply voltage.
Consequently, the gate bias for Q , Q and Q , Q varies in
V+
7
4
5
2
3
HCA10014
accordance with supply voltage variations. This variation
results in deterioration of the power supply rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
200µA
BIAS CKT.
200µA
1.35mA
8mA
(NOTE 5)
0mA
(NOTE 6)
+
3
OUTPUT
6
Output Stage
A
≈
A
30X
≈
V
V
INPUT
A
≈ 5X
V
6000X
The output stage consists of a drain loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 8. Typical op amp
loads are readily driven by the output stage. Because large
signal excursions are nonlinear, requiring feedback for good
waveform reproduction, transient delays may be
2
-
V-
4
C
C
5
1
8
STROBE
COMPENSATION
(WHEN REQUIRED)
OFFSET
NULL
NOTES:
5. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
6. Total supply voltage (for indicated voltage gains) = 15V with
output terminal driven to either supply rail.
NOTE:
FIGURE 7. BLOCK DIAGRAM OF THE HCA10014
7. ForgeneralinformationonthecharacteristicsofCMOStransistor
pairs in linear circuit applications, see Document # 619, data
sheet on CA3600E “CMOS Transistor Array”.
Second Stage
Most of the voltage gain is provided by the second amplifier
17.5
stage, consisting of bipolar transistor Q and its cascade
11
SUPPLY VOLTAGE: V+ = 15, V- = 0V
o
T
= 25 C
connected load resistance provided by PMOS transistors Q
A
3
15
LOAD RESISTANCE = 5kΩ
2kΩ
and Q . The source of bias potentials for these PMOS
5
12.5
transistors is subsequently described. Miller Effect
1kΩ
500Ω
compensation (roll off) is accomplished by simply connecting
a small capacitor between Terminals 1 and 8. A 47pF
capacitor provides sufficient compensation for stable unity
gain operation in most applications.
10
7.5
5
Bias Source Circuit
2.5
0
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z serve to establish a voltage of 8.3V
1
across the series connected circuit, consisting of resistor R ,
0
2.5
5
7.5
10
12.5
15 17.5
20 22.5
1
diodes D through D , and PMOS transistor Q . A tap at the
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
1
4
1
junction of resistor R and diode D provides a gate bias
1
4
FIGURE 8. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
potential of about 4.5V for PMOS transistors Q and Q with
4
5
respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q with respect to
1
Input Current Variation with Common Mode Input
Voltage
Terminal 7 to provide gate bias for PMOS transistors Q and
2
Q . It should be noted that Q is “mirror connected (see
3
1
Note 7)” to both Q and Q . Since transistors Q , Q , Q are
designed to be identical, the approximately 200µA current in
As shown in the Table of Electrical Specifications, the input
o
2
3
1
2
3
current for the HCA10014 is typically 5pA at T = 25 C when
A
Q establishes a similar current in Q and Q as constant
current sources for both the first and second amplifier
stages, respectively.
Terminals 2 and 3 are at a common mode potential of +7.5V
with respect to negative supply Terminal 4. Figure 9 contains
data showing the variation of input current as a function of
1
2
3
6
HCA10014
o
common mode input voltage at T = 25 C. These data show
A
4000
1000
V
= ±7.5V
S
that circuit designers can advantageously exploit these
characteristics to design circuits which typically require an
input current of less than 1pA, provided the common mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the
finite resistance of the glass terminal-to-case insulator of the
metal can package also contributes an increment of leakage
current, there are useful compensating factors.
100
10
1
10
o
= 25 C
-80 -60 -40 -20
0
20 40
60 80 100 120 140
o
T
A
TEMPERATURE ( C)
15V
TO
5V
FIGURE 10. INPUT CURRENT vs TEMPERATURE
7.5
5
V+
7
Input Offset Voltage (VIO) Variation with DC Bias
and Device Operating Life
2
3
6
PA
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate source bias potential is
applied to the device for extended time periods. The
8
2.5
0
V
IN
5
4
0V
TO
-10V
magnitude of the change is increased at high temperatures.
Users should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias
voltage applied across Terminals 2 and 3. Figure 11 shows
typical data pertinent to shifts in offset voltage encountered
with devices during life testing. At lower temperatures (metal
V-
-1
0
1
2
3
4
6
7
INPUT CURRENT (pA)
FIGURE 9. INPUT CURRENT vs COMMON-MODE VOLTAGE
o
Offset Nulling
can and plastic), for example at 85 C, this change in voltage
Offset voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset null adjustment usually can be
effected with the slider arm positioned in the midpoint of the
potentiometer’s total range.
is considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2V
differential voltage
DC
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
Input Current Variation with Temperature
The input current of the HCA10014 circuit is typically 5pA at
25 C. The major portion of this input current is due to
7
o
leakage current through the gate protective diodes in the
input circuit. As with any semiconductor junction device,
including op amps with a junction FET input stage, the
6
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
5
OUTPUT STAGE TOGGLED
o
leakage current approximately doubles for every 10 C
4
3
increase in temperature. Figure 10 provides data on the
typical variation of input bias current as a function of
temperature.
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
1
OUTPUT VOLTAGE = V+ /2
0
0
500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)
FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
7
HCA10014
V+
7
V+
7
3
2
+
-
3
2
+
-
Q
Q
8
Q
Q
8
6
6
12
R
12
L
R
L
4
4
8
V-
8
FIGURE 12A. DUAL POWER SUPPLY OPERATION
FIGURE 12B. SINGLE POWER SUPPLY OPERATION
FIGURE 12. OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
R = ∞ by pulling the potential of Terminal 8 down to that of
Power Supply Considerations
L
Terminal 4.
Because the HCA10014 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 12A and 12B show
connections for both dual and single supply operation.
Let it now be assumed that a load resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 12B. Let it be assumed again
that the input terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q must now supply quiescent current to both R
and transistor Q , it should be apparent that under these
conditions the supply current must increase as an inverse
function of the R magnitude. Figure 5 shows the voltage
Dual Supply Operation - When the output voltage at
Terminal 6 is 0V, the currents supplied by the two power
8
L
12
supplies are equal. When the gate terminals of Q and Q
8
12
are driven increasingly positive with respect to ground,
L
current flow through Q (from the negative supply) to the
12
drop across PMOS transistor Q as a function of load
8
load is increased and current flow through Q (from the
8
positive supply) decreases correspondingly. When the gate
current at several supply voltages. Figure 8 shows the
voltage transfer characteristics of the output stage for
several values of load resistance.
terminals of Q and Q are driven increasingly negative
8
12
with respect to ground, current flow through Q is increased
8
and current flow through Q is decreased accordingly.
12
Wideband Noise
Single Supply Operation - Initially, let it be assumed that
From the standpoint of low noise performance
considerations, the use of the HCA10014 is most
the value of R is very high (or disconnected), and that the
L
input terminal bias (Terminals 2 and 3) is such that the
output terminal (No. 6) voltage is at V+/2, i.e., the voltage
advantageous in applications where the source resistance
of the input signal is on the order of 1MΩ or more. In this
case, the total input referred noise voltage is typically only
23µV when the test circuit amplifier of Figure 13 is
operated at a total supply voltage of 15V. This value of total
input referred noise remains essentially constant, even
though the value of source resistance is raised by an order
of magnitude. This characteristic is due to the fact that
reactance of the input capacitance becomes a significant
factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1MΩ, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.
drops across Q and Q are of equal magnitude. Figure 4
8
12
shows typical quiescent supply current vs supply voltage for
the HCA10014 operated under these conditions. Since the
output stage is operating as a Class A amplifier, the supply
current will remain constant under dynamic operating
conditions as long as the transistors are operated in the
linear portion of their voltage transfer characteristics (see
Figure 8). If either Q or Q are swung out of their linear
8
12
regions toward cutoff (a nonlinear region), there will be a
corresponding reduction in supply current. In the extreme
case, e.g., with Terminal 8 swung down to ground potential
(or tied to ground), NMOS transistor Q is completely cut
12
off and the supply current to series connected transistors
Q , Q goes essentially to zero. The two preceding stages,
8
12
however, continue to draw modest supply current (see the
lower curve in Figure 4) even though the output stage is
strobed off. Figure 12A shows a dual supply arrangement for
the output stage that can also be strobed off, assuming
8
HCA10014
The circuit uses an R/2R voltage ladder network, with the
+7.5V
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single pole double throw switch to
terminate an arm of the R/2R network at either the positive
or negative power supply terminal. The resistor ladder is an
assembly of 1% tolerance metal oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.
0.01µF
R
s
7
4
+
-
3
2
NOISE
VOLTAGE
OUTPUT
1MΩ
6
8
30.1kΩ
1
0.01
µF
47pF -7.5V
A single 15V supply provides a positive bus for the follower
amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line
voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
BW (-3dB) = 200kHz
1kΩ
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)
FIGURE 13. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Single Supply, Absolute Value, Ideal Full Wave
Rectifier
Operational amplifiers with very high input resistances are
particularly suited to service as voltage followers. Figure 14
shows the circuit of a classical voltage follower, together with
pertinent waveforms in a split supply configuration.
An absolute value circuit is shown in Figure 17. During
positive excursions, the input signal is fed through the
feedback network directly to the output. Simultaneously, the
positive excursion of the input signal also drives the output
terminal (No. 6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the HCA10014 functions as a
A voltage follower, operated from a single supply, is shown in
Figure 15, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 15A with
input signal ramping. The waveforms in Figure 15B show
that the follower does not lose its input to output phase
sense, even though the input is being swung 7.5V below
ground potential. This unique characteristic is an important
attribute in both operational amplifier and comparator
applications. Figure 15B also shows the manner in which the
CMOS output stage permits the output signal to swing down
to the negative supply rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of the HCA10014
in a single supply voltage follower application.
normal inverting amplifier with a gain equal to -R /R . When
2
1
the equality of the two equations shown in Figure 17 is
satisfied, the full wave output is symmetrical.
Peak Detectors
Peak detector circuits are easily implemented, as illustrated
in Figure 18 for both the peak positive and the peak negative
circuit. It should be noted that with large signal inputs, the
bandwidth of the peak negative circuit is much less than that
of the peak positive circuit. The second stage of the
HCA10014 limits the bandwidth in this case. Negative going
output signal excursion requires a positive going signal
9-Bit CMOS DAC
excursion at the collector of transistor Q , which is loaded
11
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 16. This system combines the concepts of
multiple switch CMOS lCs, a low cost ladder network of
discrete metal oxide film resistors, a HCA10014 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 16.
by the intrinsic capacitance of the associated circuitry in this
mode. On the other hand, during a negative going signal
excursion at the collector of Q , the transistor functions in
11
an active “pull down” mode so that the intrinsic capacitance
can be discharged more expeditiously.
9
HCA10014
+7.5V
0.01µF
7
+
-
3
2
10kΩ
6
2kΩ
4
8
1
0.01µF
25pF
-7.5V
C
= 56pF
C
2kΩ
BW (-3dB) = 4MHz
0.1µF
SR = 10V/µs
Top Trace: Output
Center Trace: Input
Top Trace: Output Signal; 2V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal; 2V/Div., 5µs/Div.
FIGURE 14A. SMALL SIGNAL RESPONSE (50mV/DIV.,
200ns/DIV.)
FIGURE 14B. INPUT OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 14. SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
10
HCA10014
+15V
0.01µF
7
3
2
+
-
10kΩ
6
4
5
1
100kΩ
8
56pF
OFFSET
ADJUST
2kΩ
0.1µF
Top Trace: Output; 5V/Div., 200µs/Div.
Bottom Trace: Input Signal; 5V/Div., 200µs/Div.
FIGURE 15A. OUTPUT WAVEFORM WITH INPUT SIGNAL
FIGURE 15B. OUTPUT WAVEFORM WITH GROUND
REFERENCE SINEWAVE INPUT
RAMPING (2V/DIV., 500µs/DIV.)
FIGURE 15. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SINGLE SUPPLY D/A
CONVERTER; SEE FIGURE 9 IN AN6080)
11
HCA10014
10V LOGIC INPUTS
+10.010V
REQUIRED
RATIO MATCH
LSB
9
MSB
1
BIT
14
11
2
8
3
7
6
6
5
3
4
3
6
2
3
STANDARD
±0.1%
±0.2%
±0.4%
±0.8%
1
2
3
4
5
6
10
10
10
CD4007A
CD4007A
“SWITCHES”
CD4007A
6 - 9
±1% ABS
“SWITCHES”
“SWITCHES”
NOTE: All resistances are in ohms.
9
7
4
13
8
1
5
13
8
1
12
806K
13
8
1
5
12
12
5
(4)
(8)
(2)
1%
806K
1%
806K 402K 200K
100K
1%
806K 806K 806K
1% 1% 1%
806K
1%
1%
1%
1%
806K
1%
750K
1%
806K
1%
PARALLELED
RESISTORS
10K
+15V
7
VOLTAGE
REGULATOR
62
+15V
3
+
1
6
OUTPUT
VOLTAGE
FOLLOWER
2
+10.010V
HCA10014
-
6
CA3085
8
2
4
LOAD
3
22.1k
1%
5
1
8
7
REGULATED
VOLTAGE
ADJ
+
-
4
2µF
25V
56pF
100K
OFFSET
NULL
1K
0.001µF
3.83k
1%
2K
0.1µF
FIGURE 16. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND HCA10014
R
2
+15V
2kΩ
0.01
µF
R
1
7
4
-
2
3
4kΩ
HCA10014
+
6
1N914
5.1kΩ
5
0V
0V
1
8
R
3
PEAK
ADJUST
2kΩ
100kΩ
OFFSET
ADJUST
20pF
R
2
R
1
R
3
------
-------------------------------------
1
Gain =
= X =
X + X
R
+ R + R
2 3
2
R
2KΩ
4kΩ
2
----------- ------
For X = 0.5:
=
------------------
R
= R
3
1
R
1
1 - X
Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
Time base on both traces: 0.2ms/Div.
0.75
-----------
0.5
R = 4kΩ
= 6kΩ
3
20V
Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
P-P
1V
P-P
FIGURE 17. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
12
HCA10014
6V
INPUT;
6V INPUT;
P-P
P-P
BW (-3dB) = 1.3MHz
0.3V INPUT;
+7.5V
+7.5V
BW (-3dB) = 360kHz
0.3V INPUT;
P-P
P-P
0.01µF
0.01µF
BW (-3dB) = 240kHz
BW (-3dB) = 320kHz
7
7
+DC
OUTPUT
-DC
OUTPUT
+
+
3
2
3
2
10kΩ
10kΩ
HCA10014
-
HCA10014
-
6
6
1N914
1N914
4
4
+
-
-
100
kΩ
100
kΩ
5µF
5µF
+
0.01µF
0.01µF
-7.5V
-7.5V
2kΩ
2kΩ
FIGURE 18A. PEAK POSITIVE DETECTOR CIRCUIT
FIGURE 18B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 18. PEAK DETECTOR CIRCUITS
CURRENT
LIMIT
ADJ
3Ω
+
R
2
1kΩ
IC
1kΩ
3
Q
CA3086
10
5
13
14
12
7
3
Q
Q
Q
Q
1
4
3
2
9
8
6
2
4
11
1
5
+
OUTPUT
0 TO 13V
AT
20kΩ
1kΩ
390Ω
56pF
40mA
+
5µF
2.2kΩ
25V
0.01µF
-
ERROR
AMPLIFIER
1
+
8
25µF
IC
2
-
7
+20V
INPUT
11
2
3
1, 2
10
9
CA3086
-
HCA10014
+
Q
Q
6
1
4
3
IC1
5
8, 7
30kΩ
Q
Q
2
3
4
14
13
Q
5
4
6
100kΩ
R
50kΩ
1
12
VOLTAGE
ADJUST
0.01µF
62kΩ
-
-
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz
FIGURE 19. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
13
HCA10014
2N3055
1Ω
Q
2
+
+
10kΩ
2N2102
1kΩ
CURRENT
LIMIT
Q
1
4.3kΩ
1W
ADJUST
Q
3
3.3kΩ
1W
2N5294
+
-
43kΩ
+
-
1000pF
100µF
100µF
2.2kΩ
1
ERROR
AMPLIFIER
OUTPUT:
0.1 TO 50V
AT 1A
+55V
INPUT
+
-
8
5µF
IC
2
7
2N2102
3
+
CA3086
10, 11 1, 2
10kΩ
6
HCA10014
Q
Q
4
1
14
9
3
5
Q
-
2
5
IC
1
Q
4
8, 7
12
4
13
Q
Q
3
2
8.2kΩ
6
4
50kΩ
1kΩ
62kΩ
VOLTAGE
ADJUST
-
-
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µV
UP TO 100kHz
RMS
FIGURE 20. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
connected series pass transistors Q , Q . Transistor Q
3
Error Amplifier in Regulated Power Supplies
1
2
functions in the previously described current limiting circuit.
The HCA10014 is an ideal choice for error amplifier service
in regulated power supplies since it can function as an error
amplifier when the regulated output voltage is required to
approach zero. Figure 19 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
Multivibrators
The exceptionally high input resistance presented by the
HCA10014 is an attractive feature for multivibrator circuit
design because it permits the use of timing circuits with high
R/C ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
13V. Q and Q in lC (a CA3086 transistor array lC)
3
4
2
function as zeners to provide the supply voltage for
comparator IC . Q , Q , and Q in IC are configured as a
“on” and “off” periods, is shown in Figure 21. Resistors R
1
1
1
2
5
2
and R are used to bias the HCA10014 to the midpoint of
2
low impedance, temperature compensated source of
adjustable reference voltage for the error amplifier.
the supply voltage and R is the feedback resistor. The pulse
3
repetition rate is selected by positioning S to the desired
1
Transistors Q , Q , Q , and Q in lC (another CA3086
1
2
3
4
3
position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.
transistor array lC) are connected in parallel as the series
pass element. Transistor Q in lC functions as a current
5
3
limiting device by diverting base drive from the series pass
transistors, in accordance with the adjustment of resistor R .
2
Function Generator
Figure 22 contains a schematic diagram of a function
generator using the HCA10014 in the integrator and
threshold detector functions. This circuit generates a
triangular or square wave output that can be swept over a
1,000,000:1 range (0.1Hz to 100kHz) by means of a single
Figure 20 contains the schematic diagram of a regulated
power supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC ) and circuitry
1
associated with lC function as previously described,
2
control, R . A voltage control input is also available for
1
although the output of lC is boosted by a discrete transistor
1
remote sweep control.
(Q ) to provide adequate base drive for the Darlington
4
14
HCA10014
The heart of the frequency determining system is an
operational transconductance amplifier (OTA) (see Note 9),
lC , operated as a voltage controlled current source. The
+15V
1
0.01µF
output, I , is a current applied directly to the integrating
O
ON-PERIOD
ADJUST
1MΩ
OFF-PERIOD
capacitor, C , in the feedback loop of the integrator lC ,
1
2
ADJUST
1MΩ
R
1
using a HCA10014, to provide the triangular wave output.
100kΩ
Potentiometer R is used to adjust the circuit for slope
symmetry of positive going and negative going signal
excursions.
2
2kΩ
2kΩ
R
3
100kΩ
Another HCA10014, IC , is used as a controlled switch to
3
7
4
set the excursion limits of the triangular output from the
3
2
+
integrator circuit. Capacitor C is a “peaking adjustment” to
2
6
HCA10014
-
optimize the high frequency square wave performance of the
circuit.
S
1µF
0.1µF
1
OUTPUT
R
2
100kΩ
2kΩ
Potentiometer R is adjustable to perfect the “amplitude
3
symmetry” of the square wave output signals. Output from
0.001µF
0.01µF
the threshold detector is fed back via resistor R to the input
4
of lC so as to toggle the current source from plus to minus
1
in generating the linear triangular wave.
Frequency Range:
Position of S
Pulse Period
1
Operation with Output Stage Power Booster
0.001µF 4µs to 1ms
The current sourcing and sinking capability of the
0.01µF 40µs to 10ms
0.1µF 0.4ms to 100ms
1µF 4ms to 1s
HCA10014 output stage is easily supplemented to provide
power boost capability. In the circuit of Figure 23, three
CMOS transistor pairs in a single CA3600E (see Note 11) lC
array are shown parallel connected with the output stage in
the HCA10014. In the Class A mode of CA3600E shown, a
typical device consumes 20mA of supply current at 15V
operation. This arrangement boosts the current handling
capability of the output stage by about 2.5X.
FIGURE 21. PULSE GENERATOR (ASTABLE
MULTIVIBRATOR) WITH PROVISIONS FOR
INDEPENDENT CONTROL OF “ON” AND “OFF”
PERIODS
The amplifier circuit in Figure 23 employs feedback to
establish a closed loop gain of 48dB. The typical large signal
bandwidth (-3dB) is 50kHz.
NOTE:
8. See Document # 619 (CA3600E) for technical information.
15
HCA10014
R
4
INTEGRATOR
270kΩ
VOLTAGE CONTROLLED
CURRENT SOURCE
C
1
THRESHOLD
DETECTOR
HIGH FREQ.
ADJUST
3 - 30pF
+7.5V
100pF
+7.5V
150kΩ
7
IC
1
+7.5V
IC
2
7
I
3
O
+
-
IC
3
C
2
7
3kΩ
-
2
3
6
3kΩ
+
2
3
2
HCA10014
+
CA3080A (NOTE 9)
6
39kΩ
4
HCA10014
-
6
4
5
+7.5V
-7.5V
8
10MΩ
4
5
1
+7.5V
R
2
-7.5V
1
100kΩ
22kΩ
SLOPE
R
3
10kΩ
SYMMETRY
ADJUST
56pF
100kΩ
FREQUENCY
ADJUST
(100kHz MAX)
-7.5V
AMPLITUDE
SYMMETRY
ADJUST
VOLTAGE
R
1
CONTROLLED
INPUT
10kΩ
-7.5V
-7.5V
NOTE:
9. See Document # 475 (CA3080/CA3080A) and AN6668 for technical information.
FIGURE 22. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
+15V
0.01µF
14
2
11
1MΩ
CA3600E
(NOTE 11)
1µF
Q
Q
Q
P3
P1
P2
7
750kΩ
2kΩ
3
2
+
13
3
1
HCA10014
-
6
INPUT
500µF
1µF
8
6
10
12
4
R
= 100Ω
L
(P = 150mW
O
AT THD = 10%)
8
5
A
V(CL)
= 48dB
Q
Q
Q
N3
N1
N2
LARGE SIGNAL
BW (-3 dB) = 50kHz
7
4
9
510kΩ
NOTES:
10. Transistors Q , Q , Q and Q , Q , Q are parallel connected with Q and Q , respectively, of the HCA10014.
P1 P2 P3
N1 N2 N3
8
12
11. See Document # 619 (CA3600E).
FIGURE 23. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE HCA10014
16
HCA10014
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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17
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