HC9P5509B-5 [INTERSIL]
ITU CO/Loop Carrier SLIC; ITU CO /环路载波SLIC
| 型号： | HC9P5509B-5 |
| 厂家： | 
Intersil |
| 描述： | ITU CO/Loop Carrier SLIC |
| 文件： | 总9页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC-5509B
®
Augus t 2003
FN2799.8
ITU CO/Loop Carrier SLIC
Features
The HC-5509B telephone Subscriber Line Interface Circuit
integrates most of the BORSCHT functions on a monolithic
IC. The device is manufactured in a Dielectric Isolation (DI)
process and is designed for use as a high voltage interface
between the traditional telephone subscriber pair (Tip and
Ring) and the low voltage filtering and coding/decoding
functions of the line card. Together with a secondary
protection diode bridge and “feed” resistors, the device will
withstand 1000V lightning induced surges, in plastic
packages. The SLIC also maintains specified transmission
performance in the presence of externally induced
longitudinal currents. The BORSCHT functions that the SLIC
provides are:
• DI Monolithic High Voltage Process
• Compatible with Worldwide PBX and CO Performance
Requirements
• Controlled Supply of Battery Feed Current with
Programmable Current Limit
• Operates with 5V Positive Supply (V +)
B
• Internal Ring Relay Driver and a Utility Relay Driver
• High Impedance Mode for Subscriber Loop
• High Temperature Alarm Output
• Low Power Consumption During Standby Functions
• Switch Hook, Ground Key, and Ring Trip Detection
• Selective Power Denial to Subscriber
Battery Feed with Subscriber Loop Current Limiting
• Overvoltage Protection
• Voice Path Active During Power Denial
• Ring Relay Driver
• On-Chip Op Amp for 2-Wire Impedance Matching
• Supervisory Signaling Functions
• Hybrid Functions (with External Op Amp)
• Test (or Battery Reversal) Relay Driver
Applications
• Solid State Line Interface Circuit for PBX or Central Office
Systems, Digital Loop Carrier Systems
In addition, the SLIC provides selective denial of power to
subscriber loops, a programmable subscriber loop current
limit from 20mA to 60mA, a thermal shutdown with an alarm
output and line fault protection. Switch hook detection, ring
trip detection and ground key detection functions are also
incorporated in the SLIC device.
• Hotel/Motel Switching Systems
• Direct Inward Dialing (DID) Trunks
• Voice Messaging PBXs
• High Voltage 2-Wire/4-Wire, 4-Wire/2-Wire Hybrid
The HC-5509B SLIC is ideally suited for line card designs in
PBX and CO systems, replacing traditional transformer
solutions.
• Related Literature
- AN9607, Impedance Matching Design Equations
- AN9628, AC Voltage Gain
- AN9608, Implementing Pulse Metering
Part Number Information
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
PART
TEMP.
PKG. DWG.
#
o
NUMBER
RANGE ( C)
PACKAGE
HC9P5509B-5
0 to 75
28 Ld SOIC
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HC-5509B
Absolute Maximum Ratings (Note 1)
Thermal Information
o
o
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 15V
Maximum Supply Voltages
Thermal Resistance (Typical, Note 3)
SOIC Package . . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
72
N/A
o
(V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
B+
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150 C
Storage Temperature Range. . . . . . . . . . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
(V )-(V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
B+ B-
o
(For SMD; SOIC - Lead Tips Only)
Operating Conditions
Operating Temperature Range
HC-5509B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Die Characteristics
o
o
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Positive Power Supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
B+
Negative Power Supply (V ) . . . . . . . . . . . . . . . . . . . .-42V to -58V
B-
Loop Resistance (R ) . . . . . . . . . . . . . . . . .200Ω to 1750Ω (Note 2)
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. May Be Extended to 1900Ω With Application Circuit.
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are Over Operating
A
Temperature Range, V - = -48V, V + = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
B
B
2-Wire Terminating Impedance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC TRANSMISSION PARAMETERS
RX Input Impedance
300Hz to 3.4kHz (Note 4)
300Hz to 3.4kHz (Note 4)
-
-
100
-
20
-
kΩ
TX Output Impedance
-
-
Ω
4-Wire Input Overload Level
300Hz to 3.4kHz R = 1200Ω,
1.5
V
PEAK
L
600Ω Reference
2-Wire Return Loss
SRL LO
Matched for 600Ω (Note 4)
26
30
30
58
35
40
40
63
-
-
-
-
dB
dB
dB
dB
ERL
SRL HI
2-Wire Longitudinal to Metallic Balance
Off Hook
Per ANSI/IEEE STD 455-1976 (Note 4) 300Hz to
3400Hz
4-Wire Longitudinal Balance
Off Hook
300Hz to 3400Hz (Note 4)
50
55
-
dB
Low Frequency Longitudinal Balance
R.E.A. Test Circuit
o
-
-
-
-
-
-
-67
23
30
dBmp
I
I
= 40mA, T = 25 C (Note 4)
A
dBrnC
LINE
o
Longitudinal Current Capability
= 40mA, T = 25 C (Note 4)
mA
RMS
LINE
A
Insertion Loss
2-Wire/4-Wire
0dBm at 1kHz, Referenced 600Ω
-
-
-
-
±0.05
±0.05
-
±0.2
±0.2
dB
4-Wire/2-Wire
4-Wire/4-Wire
dB
dB
dB
±0.2
Frequency Response
300Hz to 3400Hz (Note 4) Referenced to
±0.02
±0.05
Absolute Level at 1kHz, 0dBm Referenced 600Ω
Level Linearity
Referenced to -10dBm (Note 4)
+3 to -40dBm
2-Wire to 4-Wire and 4-Wire to 2-Wire
-
-
-
-
-
-
±0.05
±0.1
±0.3
dB
dB
dB
-40 to -50dBm
-50 to -55dBm
2
HC-5509B
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are Over Operating
A
Temperature Range, V - = -48V, V + = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
B
B
2-Wire Terminating Impedance (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Absolute Delay
2-Wire/4-Wire
(Note 4)
300Hz to 3400Hz
-
-
-
-
-
-
-
1
1
µs
µs
µs
dB
dB
4-Wire/2-Wire
4-Wire/4-Wire
300Hz to 3400Hz
300Hz to 3400Hz
(Note 4) See Figure 1
-
1.5
-
Transhybrid Loss, THL
40
-
Total Harmonic Distortion
Reference Level 0dBm at 600Ω
-52
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire
300Hz to 3400Hz (Note 4)
Idle Channel Noise
2-Wire and 4-Wire
(Note 4)
C-Message
-
-
-
-
-
-
5
dBrnC
dBmp
dBrn
Psophometric
3kHz Flat
-85
15
Power Supply Rejection Ratio
(Note 4)
30Hz to 200Hz, R = 600Ω
V
V
V
V
V
V
V
V
to 2-Wire
to 4-Wire
to 2-Wire
to 4-Wire
to 4-Wire
to 2-Wire
to 4-Wire
to 4-Wire
20
20
20
20
30
30
20
20
50
29
29
29
29
-
-
dB
dB
dB
dB
dB
dB
dB
dB
µs
L
B+
B+
B-
B-
B+
B-
B-
B-
-
-
-
(Note 4)
-
200Hz to 16kHz, R = 600Ω
L
-
-
25
25
-
-
-
Ring Sync Pulse Width
500
DC PARAMETERS
Loop Current Programming
Limit Range
20
10
-
-
-
60
-
mA
%
Accuracy
Loop Current During Power Denial
R
= 200Ω
±3
±5
mA
L
Fault Currents
TIP to Ground
-
30
60
90
12
10
-
-
-
mA
mA
mA
mA
mA
RING to Ground
-
TIP and RING to Ground
Switch Hook Detection Threshold
Ground Key Detection Threshold
Thermal ALARM Output
Ring Trip Detection Threshold
Ring Trip Detection Period
Dial Pulse Distortion
-
-
-
15
-
-
o
Safe Operating Die Temperature Exceeded
= 105V , f = 20Hz
140
160
-
C
V
-
-
-
10
100
0.1
mA
ms
ms
RING
RMS RING
150
0.5
Relay Driver Outputs
On Voltage V
OL
I
(PR) = 60mA, I (RD) = 30mA
OL
-
-
0.2
0.5
V
OL
Off Leakage Current
V
= 13.2V
±10
±100
µA
OH
TTL/CMOS Logic Inputs (F0, F1, RS, TEST, PRI)
Logic ‘0’ V
Logic ‘1’ V
-
2.0
-
-
-
-
0.8
5.5
V
V
IL
IH
Input Current (F0, F1, RS, TEST, PRI)
0V ≤ V ≤ 5V
IN
±100
µA
3
HC-5509B
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are Over Operating
A
Temperature Range, V - = -48V, V + = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
B
B
2-Wire Terminating Impedance (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Logic Outputs
Logic ‘0’ V
I
I
= 800µA
-
2.7
-
0.1
0.5
V
V
OL
LOAD
LOAD
Logic ‘1’ V
= 40µA
-
-
-
OH
Power Dissipation On Hook
I +
Relay Drivers Off
200
mW
mA
mA
V
V
= 5.25V, V = -58V, R
B-
= ∞
= ∞
-
-
-
6
-
B
B+
B+
LOOP
I -
B
= 5.25V, V - = -58V, R
-6
B
LOOP
UNCOMMITTED OP AMP PARAMETERS
Input Offset Voltage
-
-
-
-
-
±5
±10
1
-
-
-
-
-
mV
nA
Input Offset Current
Differential Input Resistance
Output Voltage Swing
Small Signal GBW
(Note 4)
= 10kΩ
MΩ
R
±3
1
V
L
P-P
MHz
(Note 4)
NOTE:
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
Pin Des criptions
SOIC
SYMBOL
DESCRIPTION
1
AG
(Note 5)
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and receive input
terminals.
2
3
V +
Positive Voltage Source - most positive supply.
B
C
Capacitor #C - An external capacitor to be connected between this terminal and analog ground. Required for proper
1
1
operation of the loop current limiting function.
4
F1
Function Address #1 - A TTL and CMOS compatible input used with F0 function address line to externally select logic
functions. The three selectable functions are mutually exclusive. See Truth Table. F1 should be toggled high after power
is applied.
5
6
F0
Function Address #0 - A TTL and CMOS compatible input used with F1 function address line to externally select logic
functions. The three selectable functions are mutually exclusive. See Truth Table.
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock is arranged such that a positive pulse (50µs -
500µs) occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected
systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive
going zero crossing. This ensures that the ring delay activates and deactivates when the instantaneous ring voltage is
near zero. If synchronization is not required, the pin should be tied to 5.
7
8
9
SHD
GKD
TST
Switch Hook Detection - An active low LS, TTL-compatible logic output. A line supervisory output.
Ground Key Detection - An active low LS, TTL-compatible logic output. A line supervisory output.
A TTL logic input. A low on this pin will set a latch and keep the SLIC in a power down mode until the proper F1, F0
state is set and will keep ALM low. See Truth Table.
10
ALM
An LS TTL-compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded. When TST is forced low by an external control signal, ALM is latched low until the
proper F1, F0 state and TST input is brought high. The ALM can be tied directly to the TST pin to power down the part
when a thermal fault is detected and then reset with F0, F1. See Truth Table. It is possible to ignore transient thermal
overload conditions in the SLIC by delaying the response to the TST pin from the ALM. Care must be exercised in
attempting this as continued thermal overstress may reduced component life.
11
12
13
I
Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider.
The analog output of the spare operational amplifier.
LMT
OUT1
-IN1
The inverting analog input of the spare operational amplifier.
4
HC-5509B
Pin Des criptions (Continued)
SOIC
SYMBOL
DESCRIPTION
14
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor and ring relay
contact. Functions with the RING terminal to receive voice signals from the telephone and for loop monitoring purpose.
15
16
17
18
RING
RFS
An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions
with the TIP terminal to receive voice signals from the telephone and for loop monitoring purposes.
Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected ringing the ring signal
at this node is isolated from RF via the ring relay. For Tip injected ringing, the RF and RFS pins must be shorted.
V
Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and
Ring Feed amplifiers differentially.
RX
C
Capacitor #C - An external capacitor to be connected between this terminal and ground. It prevents false ring trip
2
2
detection from occurring when longitudinal currents are induced onto the subscriber loop from power lines and other
noise sources. This capacitor should be nonpolarized.
19
V
Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and
RING. Transhybrid balancing must be performed beyond this output to completely implement 2-Wire to 4-Wire conversion.
This output is referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling
to the next stage is necessary.
TX
20
21
22
PRI
PR
A TTL compatible input used to control PR. PRI active High = PR active low.
An active low open collector output. Can be used to drive a Polarity Reversal Relay.
DG
Digital Ground - To be connected to zero potential. Serves as a reference for all digital inputs and outputs on the SLIC.
(Note 5)
23
24
RD
Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing signals onto the 2-
Wire line.
V
Feedback input to the tip feed amplifier; may be used in conjunction with transmit output signal and the spare op amp
to accommodate 2-Wire line impedance matching.
FB
25
26
27
28
TF
RF
Tip Feed - A low impedance analog output connected to the TIP terminal through a feed resistor.
Ring Feed - A low impedance analog output connected to the RING terminal through a feed resistor.
The battery voltage source. The most negative supply.
V -
B
BG
(Note 5)
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground
terminal.
NOTE:
5. All grounds (AG, BG, and DG) must be applied before V + or V -. Failure to do so may result in premature failure of the part. If a user wishes
B
B
to run separate grounds off a line card, the AG must be applied first.
5
HC-5509B
Pinout
HC-5509B (SOIC)
TRUTH TABLE
TOP VIEW
F1
0
F0
0
ACTION
AG
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BG
VB-
RF
Normal Loop Feed
VB+
0
1
RD Active (Ringing)
C
1
3
1
0
Power Down Latch RESET
Power On RESET
F1
4
TF
1
0
5
F0
RS
VFB
RD
DG
1
1
Loop Power Denial Active
6
7
SHD
GKD
TST
ALM
8
PR
9
PRI
10
11
12
VTX
C
2
I
LMT
OUT 1
VRX
RFS
RING
-IN 1 13
14
TIP
Functional Diagram
SOIC
R
-IN 1
VRX
17
OUT 1
12
VFB
24
VTX
19
DG
AG
VB+
13
2
22
1
R
28
27
25
-
BG
TF
TF
2R
-
+
+
OP AMP
BIAS
NETWORK
R/2
2R
2R
VB-
RF
1
4
5
R
R
R
F1
F0
RS
-
SHD
TA
SH
14
6
TIP
+
R
2R
THERM
LTD
TSD
9
TST
PRI
4.5K
20
21
23
7
25K
100K
100K
100K
100K
RTD
GKD
15
GK
PR
RING
RFS
-
90K
LA
+
RD
25K
16
FAULT
DET
SHD
GKD
ALM
4.5K
8
90K
RFC
90K
10
-
26
90K
-
RF
RF
RF
11
2
VB/2
REF
+
GM
+
R = 108kΩ
18
3
C1
C2
I
LMT
6
HC-5509B
TABLE 1.
Overvoltage Protection and Longitudinal
Current Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
PERFORMANCE
(MAX)
PARAMETER TEST CONDITION
UNITS
Longitudinal
Surge
10µs Rise/
1000µs Fall
±1000 (Plastic)
±1000 (Plastic)
±1000 (Plastic)
V
PEAK
Metallic Surge
10µs Rise/
1000µs Fall
V
V
PEAK
PEAK
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
T/GND, R/GND 10µs Rise/
1000µs Fall
maximum or 30mA
, 15mA
per leg, without any
RMS
RMS
performance degradation.
50/60Hz Current
T/GND,
R/GND
11 Cycles,
Limited to 10A
700 (Plastic)
V
RMS
RMS
Logic Diagram
RS
2
TTL TO I L
RELAY
DRIVER
RD
2
TTL TO I L
F0
2
I L TO TTL
GKD
GK
2
I L TO TTL
SHD
THERMAL
SHUT DOWN
2
I L TO TTL
2
TTL TO I L
ALM
F1
PD
SH
THERMAL
SHUT
DOWN
LATCH
TO BIAS
NETWORK
2
TTL TO I L
TEST
INJ
A
A
B
B
C
C
KEY
7
HC-5509B
Typical Applications
5V
SYSTEM CONTROLLER
5V
K
1
SHD GKD PRI RS TEST F1 ALARM F0
RD
R
C
S1
S1
K
2
PR
K
R
L2
1A
TIP
TIP
I
LIMIT
R
R
B2
B1
V
+
RX
SECONDARY
PROTECTION
(NOTE 8)
FROM PCM
FILTER/CODER
R
L1
V
FB
V -
B
C
AC
C
5
SLIC
HC-5509B
V
TX
PRIMARY
PROTECTION
K
RF
-IN1
R
C
S2
S2
RF
K
IB
K
Z0
RFS
OUT1
TO HYBRID
BALANCE
NETWORK
V
RING
R
B4
R
B3
150V
(MAX)
PEAK
RING
RING
V -
BG
C
DG AG
V +
C
B
1
B
2
PTC
Z
1
C
C
4
3
5V
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C = 0.5µF, 30V.
R
R
, R ; Current Limit Setting Resistors:
L2
1
L1
C = 1.0µF ±10%, 20V (for other values of C , refer to
+ R > 90kΩ → offset.
L2
2
2
L1
AN9667).
I
= (0.6) (R + R )/(200 x R ), R typically 100kΩ.
L1 L2 L2 L1
LIMIT
C = 0.01µF, 100V, ±20%.
3
K
= 20kΩ, RF = 2(R + R ), K = Scaling Factor = 100).
B2 B4
RF
C = 0.01µF, 100V, ±20%.
4
R
= R = R = R = 50Ω (1% absolute, matching
B2 B3 B4
B1
requirements covered in a Tech Brief).
C = 0.01µF, 100V, ±20%.
5
C
= 0.5µF, 20V.
R
C
= R = 1kΩ, typically.
S2
AC
S1
KZ = 60kΩ, (Z = 600Ω, K = Scaling Factor = 100).
= C = 0.1µF, 200V typically, depending on V and
S2 Ring
0
0
S1
line length.
Z = 150V to 200V transient protector. PTC used as ring
1
generator ballast.
8
HC-5509B
Small Outline Plas tic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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