HC5526IM [INTERSIL]
ITU CO/PABX SLIC with Low Power Standby; ITU CO / PABX SLIC与低功耗待机
| 型号： | HC5526IM |
| 厂家： | 
Intersil |
| 描述： | ITU CO/PABX SLIC with Low Power Standby |
| 文件： | 总18页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC5526
Data Sheet
October 1998
File Number 4151.6
ITU CO/PABX SLIC with Low Power
Standby
Features
• DI Monolithic High Voltage Process
The HC5526 is a subscriber line interface circuit that is
compliant with CCITT standards. Enhancements include
immunity to circuit latch-up during hot plug and absence of
false signaling in the presence of longitudinal currents.
• Programmable Current Feed (20mA to 60mA)
• Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
• Ground Key and Ring Trip Detection
• Compatible with Ericsson’s PBL3764
• Thermal Shutdown
The HC5526 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with Junction Isolated (JI) ICs. The elimination of the
leakage currents results in improved circuit performance for
wide temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5526 ideally
suited for use in harsh outdoor environments.
• On-Hook Transmission
• Wide Battery Voltage Range (-24V to -58V)
• Low Standby Power
• Meets CCITT Transmission Requirements
o
o
• -40 C to 85 C Ambient Temperature Range
Ordering Information
Applications
• On-Premises (ONS)
• Key Systems
• PBX
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
28 Ld PLCC
22 Ld PDIP
28 Ld PLCC
22 Ld PDIP
HC5526CM
HC5526CP
HC5526IM
HC5526IP
0 to 70
0 to 70
N28.45
E22.4
-40 to 85
-40 to 85
N28.45
E22.4
• Related Literature
- AN9537, Operation of the HC5513/26 Evaluation Board
Block Diagram
RING RELAY
DRIVER
4-WIRE
RINGRLY
V
INTERFACE
TX
VF SIGNAL
PATH
RSN
DT
DR
RING TRIP
DETECTOR
TIP
RING
2-WIRE
LOOP CURRENT
E0
INTERFACE
DETECTOR
HPT
HPR
E1
C1
GROUND KEY
DETECTOR
DIGITAL
MULTIPLEXER
C2
V
BAT
V
CC
DET
V
BIAS
EE
R
R
D
AGND
BGND
DC
RSG
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
57
HC5526
Absolute Maximum Ratings
Thermal Information
o
o
o
Operating Temperature Range . . . . . . . . . . . . . . . . -40 C to 110 C
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
o
o
Power Supply (-40 C ≤ T ≤ 85 C)
A
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . .
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . .
53
53
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
Supply Voltage V to GND. . . . . . . . . . . . . . . . . . . . .-7V to 0.5V
EE
CC
o
Continuous Dissipation at 70 C
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . .-70V to 0.5V
BAT
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
Ground
o
Voltage between AGND and BGND . . . . . . . . . . . . . -0.3V to 0.3V
Relay Driver
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . 0V to V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Ring Trip Comparator
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Package Power Dissipation at 70 C, t < 100ms, t
> 1s
REP
22 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/ C
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/ C
Maximum Junction Temperature Range. . . . . . . . . . -40 C to 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
75V
BAT
o
o
o
to 0V
BAT
o
o
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA
o
o
Digital Inputs, Outputs (C1, C2, E0, E1, DET)
o
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . 0V to V
Output Current (DET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
CC
CC
(PLCC - Lead Tips Only)
o
o
Tipx and Ringx Terminals (-40 C ≤ T ≤ 85 C)
A
Die Characteristics
Tipx or Ringx Voltage, Continuous (Referenced to GND) V
to 2V
BAT
-20V to 5V
Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes
Tipx or Ringx, Pulse < 10ms, T
> 10s . . . . . .V
REP
BAT
Tipx or Ringx, Pulse < 10µs, T
Tipx or Ringx, Pulse < 250ns, T
> 10s . . . . V
-40V to 10V
-70V to 15V
REP
BAT
> 10s. . . . V
REP
BAT
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
CONDITIONS
MIN
-40
TYP
MAX
100
UNITS
o
Case Temperature
-
-
-
-
C
o
o
V
V
V
with Respect to AGND
0 C to 70 C
4.75
-5.25
-58
5.25
-4.75
-24
V
V
V
CC
o
o
with Respect to AGND
0 C to 70 C
EE
o
o
with Respect to BGND
0 C to 70 C
BAT
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V
= -28V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
A
R
CC
EE
BAT
= 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
DC L
= 39kΩ, R
= ∞, R = R = 0Ω, C
D
SG
F1 F2
HP
pin number references in the figures refer to the 28 lead PLCC package.
PARAMETER
CONDITIONS
MIN
3.1
-
TYP
-
MAX
-
UNITS
Overload Level
1% THD, Z = 600Ω, (Note 2, Figure 1)
V
L
PEAK
Longitudinal Impedance (Tip/Ring)
0 < f < 100Hz (Note 3, Figure 2)
20
35
Ω/Wire
A
V
T
TX
TIP
27
1V
RMS
19
0 < f < 100Hz
V
TX
TIP
27
V
T
300Ω
E
L
19
C
R
T
600kΩ
R
L
R
T
2.16µF
600Ω
V
600kΩ
300Ω
TRO
V
R
R
RX
I
DCMET
23mA
A
E
R
RING
28
RSN
16
RX
R
RX
300kΩ
RING
28
RSN
16
LZ = V /A
LZ = V /A
R
300kΩ
T
T
T
R
R
FIGURE 2. LONGITUDINAL IMPEDANCE
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
58
HC5526
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V
= -28V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
A
R
CC
EE
BAT
= 10nF, C
DC1
DC2
= 39kΩ, R
= ∞, R = R = 0Ω, C
D
SG
F1 F2 HP
DC
L
pin number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active)
CONDITIONS
MIN
TYP
MAX
UNITS
No False Detections (Loop Current),
LB > 45dB (Note 4, Figure 3A)
-
-
-
-
20
5
mA-
/Wire
PEAK
mA-
/Wire
On-Hook (Standby), R = ∞
No False Detections (Loop Current)
(Note 5, Figure 3B)
L
PEAK
368Ω
368Ω
TIP
27
RSN
16
TIP
27
RSN
16
A
A
2.16µF
E
L
C
39kΩ
39kΩ
C
R
R
DC1
E
R
D
R
D
DC1
L
41.2kΩ
41.2kΩ
-5V
-5V
A
2.16µF
2.16µF
C
C
R
C
DC
DC2
DC
R
DC2
R
A
RING
28
R
RING
28
DC
14
DC
14
41.2kΩ
368Ω
368Ω
1.5µF
1.5µF
41.2kΩ
DET
DET
FIGURE 3A. OFF-HOOK
FIGURE 3B. ON-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic
IEEE 455 - 1985, R , R = 368Ω,
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
53
53
50
60
60
55
-
-
-
dB
LR LT
Longitudinal to Metallic
Metallic to Longitudinal
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
dB
dB
LR LT
(Note 6, Figure 4)
FCC Part 68, Para 68.310
0.2kHz < f < 1.0kHz
1.0kHz < f < 4.0kHz (Note 7)
50
53
50
55
60
55
-
-
-
dB
dB
dB
Longitudinal to 4-Wire
Metallic to Longitudinal
0.2kHz < f < 4.0kHz (Note 8, Figure 4)
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
LR LT
(Note 9, Figure 5)
4-Wire to Longitudinal
0.2kHz < f < 4.0kHz (Note 10, Figure 5)
50
55
-
dB
R
LT
R
LT
V
19
TIP
27
TX
V
19
TIP
27
TX
300Ω
2.16µF
E
L
E
R
T
600kΩ
TR
C
R
T
V
V
TR
TX
600kΩ
C
2.16µF
V
L
E
RX
R
R
LR
RX
R
RX
RING
28
RSN
16
RSN
16
RING
28
300Ω
300kΩ
R
LR
300kΩ
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
2-Wire Return Loss
= 20nF
0.2kHz to 0.5kHz (Note 11, Figure 6)
0.5kHz to 1.0kHz (Note 11, Figure 6)
1.0kHz to 3.4kHz (Note 11, Figure 6)
25
27
23
-
-
-
-
-
-
dB
dB
dB
C
HP
59
HC5526
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V
= -28V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
A
R
CC
EE
BAT
= 10nF, C
DC1
DC2
= 39kΩ, R
= ∞, R = R = 0Ω, C
D
SG
F1 F2 HP
DC
L
pin number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
TIP IDLE VOLTAGE
Active, I = 0
CONDITIONS
MIN
TYP
MAX
UNITS
-
-
-4
-
-
V
V
L
Standby, I = 0
L
<0
RING IDLE VOLTAGE
Active, I = 0
-
-
-24
-
-
V
V
L
Standby, I = 0
L
>-28
4-WIRE TRANSMIT PORT (V
)
TX
Overload Level
Z > 20kΩ, 1% THD (Note 12, Figure 7)
3.1
-60
-
-
-
-
V
L
PEAK
Output Offset Voltage
E
= 0, Z = ∞ (Note 13, Figure 7)
60
mV
G
L
Output Impedance (Guaranteed by Design)
2- to 4-Wire (Metallic to V ) Voltage Gain
0.2kHz < f < 03.4kHz
0.3kHz < f < 03.4kHz (Note 14, Figure 7)
2.16µF
5
20
Ω
0.98
1.0
1.02
V/V
TX
Z
D
TIP
27
V
V
19
TX
TIP
27
TX
R
L
C
19
600Ω
V
R
R
TR
R
V
T
M
Z
R
600kΩ
T
V
V
TXO
TX
V
Z
L
S
I
600kΩ
DCMET
23mA
E
G
IN
R
R
RX
RX
RING RSN
28 16
RING
28
RSN
16
R
300kΩ
300kΩ
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage
I
= 0mA
-
-
0
-
-
V
RSN
R
Sum Node Impedance (Guaranteed by
0.3kHz < f < 3.4kHz
20
Ω
X
Design)
Current Gain-RSN to Metallic
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
0.3kHz < f < 3.4kHz (Note 15, Figure 8)
980
1000
1020
Ratio
0dBm at 1.0kHz, E = 0V,
RX
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
-0.2
-0.2
-0.2
-
-
-
0.2
0.2
0.2
dB
dB
dB
4-Wire to 2-Wire
4-Wire to 4-Wire
0dBm at 1.0kHz, E = 0V,
G
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
0dBm at 1.0kHz, E = 0V,
G
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz (Note 19, Figure 9)
0dBm, 1kHz (Note 20, Figure 9)
-0.2
-0.2
-
-
0.2
0.2
dB
dB
4-Wire to 2-Wire
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
-40dBm to +3dBm (Note 21, Figure 9)
-55dBm to -40dBm (Note 21, Figure 9)
-40dBm to +3dBm (Note 22, Figure 9)
-0.1
-
-
±0.03
-
0.1
-
dB
dB
dB
2-Wire to 4-Wire
4-Wire to 2-Wire
-0.1
0.1
60
HC5526
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V
= -28V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
A
R
CC
EE
BAT
= 10nF, C
DC1
DC2
= 39kΩ, R
= ∞, R = R = 0Ω, C
D
SG
F1 F2 HP
DC
L
pin number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4-Wire to 2-Wire
-55dBm to -40dBm (Note 22, Figure 9)
-
±0.03
-
dB
GRX = ((V
- V )(300k))/(-3)(600)
TR1 TR2
Where: V
and V
is the Tip to Ring Voltage with V
is the Tip to Ring Voltage with V
= 0V
TR1
TR2
RSN
RSN
= -3V
V
V
= 0V
RSN
RSN
C
TIP
27
V
R
TX
RX
= -3V
R
L
19
TIP
27
RSN
16
600Ω
R
T
300kΩ
600kΩ
V
TX
R
I
V
R
L
DCMET
TR
DC1
600Ω
41.2kΩ
V
TR
E
G
E
RX
R
RX
1/ωC << R
C
L
R
RING RSN
28 16
DC
DC2
300kΩ
RING
28
R
DC
14
1.5µF
41.2kΩ
FIGURE 8. CURRENT GAIN-RSN TO METALLIC
FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS, GAIN
TRACKING AND HARMONIC DISTORTION
NOISE
Idle Channel Noise at 2-Wire
Idle Channel Noise at 4-Wire
HARMONIC DISTORTION
2-Wire to 4-Wire
C-Message Weighting (Note 23, Figure 10)
C-Message Weighting (Note 24, Figure 10)
-
-
10
10
-
-
dBrnC
dBrnC
0dBm, 1kHz (Note 25, Figure 7)
-
-
-65
-65
-54
-54
dB
dB
4-Wire to 2-Wire
0dBm, 0.3kHz to 3.4kHz (Note 26,
Figure 9)
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
I = 2500/(R
DC1
0 C to 70 C (Note 27)
+ R
),
0.9I
0.8I
14
I
I
1.1I
1.2I
20
mA
mA
V
L
DC2
L
L
L
L
L
L
o
o
R
= 41.2kΩ
DCX
Loop Current Tolerance (Standby)
I = (V -3)/(R +1800),
L
BAT
L
o
o
0 C to 70 C (Note 28)
o
o
Open Circuit Voltage (V
TIP
- V
)
0 C to 70 C, (Active)
-
RING
LOOP CURRENT DETECTOR
On-Hook to Off-Hook
o
o
R
R
R
= 39kΩ, 0 C to 70 C
372/R
325/R
465/R
405/R
558/R
485/R
mA
mA
mA
D
D
D
D
D
D
D
o
o
Off-Hook to On-Hook
= 39kΩ, 0 C to 70 C
D
D
o
o
Loop Current Hysteresis
GROUND KEY DETECTOR
= 39kΩ, 0 C to 70 C
25/R
60/R
95/R
D
D
D
Tip/Ring Current Difference - Trigger
Tip/Ring Current Difference - Reset
(Note 29, Figure 11)
(Note 29, Figure 11)
8
3
12
7
17
12
mA
mA
61
HC5526
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V
= -28V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
A
R
CC
EE
BAT
= 10nF, C
DC1
DC2
= 39kΩ, R
= ∞, R = R = 0Ω, C
D
SG
F1 F2 HP
DC
L
pin number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
(Note 29, Figure 11)
MIN
TYP
MAX
UNITS
Hysteresis
0
5
9
mA
TIP
27
RSN
16
TIP
27
V
TX
19
R
DC1
41.2kΩ
R
R
L
T
V
600Ω
TR
V
TX
600kΩ
C
DC
R
DC2
R
RING
28
R
RX
DC
14
41.2kΩ
1.5µF
= C = 0, C = 1
DET
RING RSN
28
16
300kΩ
E
1
1
2
FIGURE 10. IDLE CHANNEL NOISE
FIGURE 11. GROUND KEY DETECT
RING TRIP DETECTOR (DT, DR)
Offset Voltage
Source Res = 0
-20
-
-
-
-
20
500
0
mV
nA
V
Input Bias Current
Source Res = 0
-500
Input Common-Mode Range
Input Resistance
Source Res = 0
V
+1
BAT
Source Res = 0, Balanced
3
-
MΩ
RING RELAY DRIVER
V
at 25mA
I
= 25mA
= 12V
-
-
1.0
-
1.5
10
V
SAT
OL
Off-State Leakage Current
V
µA
OH
DIGITAL INPUTS (E0, E1, C1, C2)
Input Low Voltage, V
IL
0
2
-
-
-
-
-
0.8
V
Input High Voltage, V
IH
V
V
CC
-
Input Low Current, I : C1, C2
IL
V
V
V
= 0.4V
= 0.4V
= 2.4V
-200
-100
-
µA
µA
µA
IL
IL
IH
Input Low Current, I : E0, E1
IL
-
Input High Current
40
DETECTOR OUTPUT (DET)
Output Low Voltage, V
OL
I
I
= 2mA
-
-
-
0.45
-
V
V
OL
Output High Voltage, V
OH
= 100µA
2.7
10
OH
Internal Pull-Up Resistor
POWER DISSIPATION
Open Circuit State
On-Hook, Standby
On-Hook, Active
15
20
kΩ
C1 = C2 = 0
C1 = C2 = 1
-
-
-
-
-
-
-
-
-
-
-
-
23
30
mW
mW
mW
W
C1 = 0, C2 = 1, R = High Impedance
150
1.1
0.75
0.5
L
Off-Hook, Active
R = 0Ω
L
R = 300Ω
W
L
R = 600Ω
W
L
TEMPERATURE GUARD
o
Thermal Shutdown
150
-
180
C
62
HC5526
o
o
Electrical Specifications T = 0 C to 70 C, V = 5V ±5%, V = -5V ±5%, V = -28V, AGND = BGND = 0V, R
BAT DC1
= R = 41.2kΩ,
DC2
A
R
CC
EE
= 39kΩ, R = ∞, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All
D
SG F1 F2 HP DC
L
pin number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
SUPPLY CURRENTS (V = -28V)
CONDITIONS
MIN
TYP
MAX
UNITS
BAT
I
I
I
, On-Hook
Open Circuit State (C1, 2 = 0, 0)
Standby State (C1, 2 = 1, 1)
Active State (C1, 2 = 0,1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
1.7
5.5
0.8
0.8
2.2
0.4
0.6
3.9
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
, On-Hook
EE
Open Circuit State (C1, 2 = 0, 0)
Standby State (C1, 2 = 1, 1)
Active State (C1, 2 = 0, 1)
, On-Hook
BAT
Open Circuit State (C1, 2 = 0, 0)
Standby State (C1, 2 = 1, 1)
Active State (C1, 2 = 0, 1)
PSRR
V
V
V
to 2 or 4-Wire Port
to 2 or 4-Wire Port
(Note 30, Figure 12)
(Note 30, Figure 12)
(Note 30, Figure 12)
-
-
-
40
40
40
-
-
-
dB
dB
dB
CC
EE
to 2 or 4-Wire Port
BAT
-48V SUPPLY
5V SUPPLY
-5V SUPPLY
100mV
, 50Hz TO 4kHz
RMS
TIP
27
V
TX
19
PSRR = 20 log (VTX/VIN
)
R
T
R
L
V
600kΩ
TX
600Ω
R
RX
RING RSN
28 16
300kΩ
FIGURE 12. POWER SUPPLY REJECTION RATIO
Circuit Operation and Design Information
The HC5526 is a current feed voltage sense Subscriber Line
Interface Circuit (SLIC). This means that for short loop
applications the SLIC provides a programmed constant
current to the tip and ring terminals while sensing the tip to
ring voltage.
the R pin (Figure 13). The R voltage is determined by
DC DC
the voltage across R in the saturation guard circuit. Under
1
constant current feed conditions, the voltage drop across R
1
sets the R voltage to -2.5V. This occurs when current
DC
flows through R into the current source I . The R voltage
1
2
DC
/(R
establishes a current (I
) that is equal to V
RSN
RDC DC1
The following discussion separates the SLIC’s operation into
its DC and AC paths, then follows up with additional circuit
and design information.
+R
). This current is then multiplied by 1000, in the loop
DC2
current circuit, to become the tip and ring loop currents.
For the purpose of the following discussion, the saturation
guard voltage is defined as the maximum tip to ring voltage
at which the SLIC can provide a constant current for a given
battery and overhead voltage.
Constant Loop Current (DC) Path
SLIC in the Active Mode
The DC path establishes a constant loop current that flows
out of tip and into the ring terminal. The loop current is
programmed by resistors R
, R
and the voltage on
DC1 DC2
63
HC5526
V
TX
I
+
-
RSN
R
R
R
RX
RSN
LOOP CURRENT
CIRCUIT
I
TIP
TIP
I
DC1
DC2
TIP
I
RING
RING
I
C
DC
RING
R
DC
SATURATION GUARD
CIRCUIT
-
-2.5V
+
-
+
A
2
A
1
R
1
-
I
2
+
R
I
SG
1
-5V
-5V
R
HC5526
SG
-5V
FIGURE 13. DC LOOP CURRENT
For loop resistances that result in a tip to ring voltage less than
the saturation guard voltage the loop current is defined as:
Figure 15 shows the relationship between the saturation guard
voltage, the loop current and the loop resistance. Notice from
Figure 15 that for a loop resistance <1.2kΩ (R
= 21.4kΩ) the
SG
2.5V
-------------------------------------
I
=
× 1000
(EQ. 1)
SLIC is operating in the constant current feed region and for
resistances >1.2kΩ the SLIC is operating in the resistive feed
region. Operation in the resistive feed region allows long loop
and off-hook transmission by keeping the tip and ring voltages
off the rails. Operation in this region is transparent to the
customer.
L
R
+ R
DC1
DC2
where: I = Constant loop current.
L
R
and R
= Loop current programming resistors.
and R removes the VF
DC1
DC2
Capacitor C
between R
DC1
DC
DC2
signals from the battery feed control loop. The value of C
DC
is determined by Equation 2:
50
CONSTANT CURRENT
V
= -48V, R = 21.4kΩ
SG
BAT
FEED REGION
1
1
(EQ. 2)
40
30
20
10
0
C
= T × --------------- + ---------------
SATURATION GUARD
DC
R
R
DC1
DC2
VOLTAGE, V = 38V
TR
where T = 30ms.
The minimum C
value is obtained if R
= R
.
DC2
V = -24V, R = ∞
BAT SG
DC
DC1
Figure 14 illustrates the relationship between the tip to ring
voltage and the loop resistance. For a 0Ω loop resistance both
SATURATION GUARD
RESISTIVE FEED
REGION
VOLTAGE, V = 13V
TR
tip and ring are at V
/2. As the loop resistance increases, so
BAT
0
10
20
LOOP CURRENT (mA)
30
does the voltage differential between tip and ring. When this
differential voltage becomes equal to the saturation guard
voltage, the operation of the SLIC’s loop feed changes from a
constant current feed to a resistive feed. The loop current in the
resistive feed region is no longer constant but varies as a
function of the loop resistance.
R
R
100kΩ
100kΩ
4kΩ
2kΩ
<1.2kΩ
<400Ω
R
R
= 21.4kΩ
= ∞Ω
L
RSG
1.5kΩ
700Ω
L
RSG
FIGURE 15. V vs I and R
TR
L
L
V
= -48V, I = 23mA, R
= 21.4kΩ
SG
BAT
L
0
-10
-20
-30
-40
-50
V
TIP
SATURATION
GUARD VOLTAGE
The Saturation Guard circuit (Figure 13) monitors the tip to
ring voltage via the transconductance amplifier A . A
1
1
CONSTANT CURRENT
FEED REGION
generates a current that is proportional to the tip to ring
RESISTIVE FEED
REGION
voltage difference. I is internally set to sink all of A ’s
1
1
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no R resistor) A
SG
1
supplies more current than I can sink. When this happens
1
A amplifies its input current by a factor of 12 and the current
2
through R becomes the difference between I and the
1
2
SATURATION
GUARD VOLTAGE
output current from A . As the current from A increases, the
2
2
V
RING
voltage across R decreases and the output voltage on R
1
DC
∞
0
1.2K
LOOP RESISTANCE (Ω)
decreases. This results in a corresponding decrease in the
loop current. The R pin provides the ability to increase the
SG
saturation guard reference voltage beyond 12.5V. Equation 3
FIGURE 14. V vs R
TR
L
64
HC5526
gives the relationship between the R
resistor value and
where:
SG
the programmable saturation guard reference voltage:
I = Loop current in the standby state,
L
5
5 • 10
(EQ. 3)
R = Loop resistance, and
L
V
= 12.5 + ------------------
SGREF
R
SG
V
= Battery voltage.
BAT
where:
(AC) Transmission Path
V
R
= Saturation Guard reference voltage, and
SGREF
SLIC in the Active Mode
= Saturation Guard programming resistor.
SG
Figure 16 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
(EQ. 9)
(EQ. 10)
(EQ. 11)
V
= V + I • 2R
5
TR
TX
M
F
16.66 + 5 • 10 ⁄ R
SG
(EQ. 4)
----------------------------------------------------------------------
= R ×
L
V
TR
R
+ (R
+ R
) ⁄ 600
DC2
L
DC1
V
V
I
TX
RX
M
---------- + ----------- = ------------
Z
Z
1000
= E – I • Z
L
T
RX
where:
= Voltage differential between tip and ring, and
V
V
TR
TR
G
M
R = Loop resistance.
L
where:
= Is the AC metallic voltage between tip and ring,
For on-hook transmission R = ∞, Equation 4 reduces to:
L
V
TR
including the voltage drop across the fuse resistors R ,
5
5 • 10
(EQ. 5)
F
V
= 16.66 + ------------------
TR
R
SG
V
= Is the AC metallic voltage. Either at the ground
TX
referenced 4-wire side or the SLIC tip and ring terminals,
The value of R
SG
should be calculated to allow maximum
I
= Is the AC metallic current,
M
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of R
calculated using Equation 6:
R = Is a fuse resisto,
F
Z = Is used to set the SLIC’s 2-wire impedance,
T
V
Z
= Is the analog ground referenced receive signal,
= Is used to set the 4-wire to 2-wire gain,
RX
is
SG
RX
5
E
= Is the AC open circuit voltage, and
G
5 • 10
R
= -------------------------------------------------------------------------------------------------------------------------------------------------
SG
Z = Is the line impedance.
L
(R
+ R
)
DC1
DC2
( V
– V
) × 1 + ------------------------------------------ – 16.66V
BAT
MARGIN
600R
L
(AC) 2-Wire Impedance
(EQ. 6)
The AC 2-wire impedance (Z ) is the impedance looking
TR
into the SLIC, including the fuse resistors, and is calculated
where:
as follows:
V
= Battery voltage, and
BAT
Let V
= 0. Then from Equation 10:
RX
V
= Recommended value of -8V to allow a maximum
MARGIN
overload level of 3.1V
.
PEAK
I
(EQ. 12)
(EQ. 13)
(EQ. 14)
M
------------
V
= Z
•
T
TX
1000
For on-hook transmission R = ∞, Equation 6 reduces to:
L
5
Z
is defined as:
TR
(EQ. 7)
5 • 10
R
= ----------------------------------------------------------------------------
SG
V
V
– V
– 16.66V
TR
BAT
MARGIN
Z
= -----------
TR
I
M
SLIC in the Standby Mode
Substituting in Equation 9 for V
TR
:
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
V
2R • I
F M
TX
Z
= ---------- + -----------------------
TR
I
I
M
M
connected between tip to ground and ring to V
. This
BAT
connection enables a loop current to flow when the phone
goes off-hook. The loop current detector then detects this
current and the SLIC is configured in the active mode for
voice transmission. The loop current in standby state is
calculated as follows:
Substituting in Equation 12 for V
:
TX
Z
T
(EQ. 15)
Z
= ------------ + 2R
TR
F
1000
V
– 3V
BAT
(EQ. 8)
-------------------------------
≈
I
L
R
+ 1800Ω
L
65
A
= –---------
- •
A
= ----------- = –---------
- •
HC5526
I
M
TIP
A = 250
R
F
Z
L
V
TX
+
-
Z
TR
+
TX
-
+
1
V
V
+
TX
TR
-
V
+
-
Z
T
E
G
-
I
M
A = 4
RSN
Z
A = 250
RX
R
I
F
M
RING
+
RX
1000
V
-
HC5526
FIGURE 16. SIMPLIFIED AC TRANSMISSION CIRCUIT
Therefore:
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to V /V
TX RX
.
(EQ. 16)
Z
= 1000 • (Z
– 2R )
TR F
T
From Equations 9, 10 and 11 with E = 0:
G
Equation 16 can now be used to match the SLIC’s
impedance to any known line impedance (Z ).
Z
+ 2R
F
V
Z
T
Z
RX
TR
L
TX
--------------------------------------------
A
= ----------- = –----------- •
4 – 4
(EQ. 20)
Z
V
T
RX
Example:
------------ + 2R + Z
F
L
1000
Calculate Z to make Z = 600Ω in series with 2.16µF.
TR
T
R = 20Ω.
F
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the receive
1
Z
= 1000 • 600 + ----------------------------------------- – 2 • 20
T
–6
jω • 2.16 • 10
signal (V ) from the transmit signal (V ), thereby preventing
RX TX
an echo on the transmit side. This is accomplished by using an
external op amp (usually part of the CODEC) and by the
inversion of the signal from the 4-wire receive port (RSN) to the
Z = 560kΩ in series with 2.16nF.
T
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to V / V
.
4-wire transmit port (V ). Figure 17 shows the transhybrid
TX TR
TX
circuit. The input signal will be subtracted from the output signal
From Equations 9 and 10 with V
= 0:
RX
if I equals I . Node analysis yields the following equation:
1
2
V
Z ⁄ 1000
T
Z ⁄ 1000 + 2R
T F
TX
(EQ. 17)
A
= ----------- = -----------------------------------------
2 – 4
V
V
RX
Z
B
V
TX
TR
(EQ. 21)
(EQ. 22)
----------- + ----------- = 0
R
TX
(AC) 4-Wire to 2-Wire Gain
The value of Z is then:
B
The 4-wire to 2-wire gain is equal to V /V
TR RX
.
From Equations 9, 10 and 11 with E = 0:
V
G
RX
-----------
Z
= –R
•
TX
B
V
For applications where the 2-wire impedance (Z
TR
,
TX
Z
V
Z
T
Z
RX
L
TR
Where V /V equals 1/ A
RX TX
.
4-4
--------------------------------------------
4 – 2
Z
V
(EQ. 18)
T
RX
------------ + 2R + Z
Therefore:
F
L
1000
Z
T
------------ + 2R + Z
Equation 15) is chosen to equal the line impedance (Z ), the
Z
(EQ. 23)
F
L
L
1000
RX
----------- --------------------------------------------
Z
= R •
TX
•
expression for A
simplifies to:
B
Z
Z + 2R
L F
4-2
T
Z
1
2
T
(EQ. 19)
--
Example:
4 – 2
Z
RX
Given: R = 20kΩ, Z = 280kΩ, Z = 562kΩ (standard
TX RX
T
value), R = 20Ω and Z = 600Ω.
F
L
The value of Z = 18.7kΩ.
B
66
HC5526
voltage drop across R exceeds 1.25V, and the logic is
R
D
FB
I
configured for loop current detection, the DET pin goes low.
2
R
V
TX
TX
The hysteresis resistor R adds an additional voltage
H
-
+
effectively across R , causing the on-hook to off-hook
D
threshold to be slightly higher than the off-hook to on-hook
threshold.
+
TX
-
I
1
V
Taking into account the hysteresis voltage, the typical value
Z
Z
B
HC5526
T
of R for the on-hook to off-hook condition is:
D
+
RX
-
465
(EQ. 25)
V
R
= --------------------------------------------------------------------------
D
I
ON – HOOK to OFF – HOOK
RSN
Z
Taking into account the hysteresis voltage, the typical value
RX
of R for the off-hook to on-hook condition is:
D
CODEC/
FILTER
375
(EQ. 26)
R
= --------------------------------------------------------------------------
D
I
OFF – HOOK to ON – HOOK
FIGURE 17. TRANSHYBRID CIRCUIT
A filter capacitor (C ) in parallel with R will improve the
accuracy of the trip point in a noisy environment. The value
D
D
Supervisory Functions
of this capacitor is calculated using the following Equation:
The loop current, ground key and the ring trip detector
outputs are multiplexed to a single logic output pin called
DET. See Table 1 to determine the active detector for a given
logic input. For further discussion of the logic circuitry see
section titled “Digital Logic Inputs”.
T
(EQ. 27)
C
= -------
D
R
D
where: T = 0.5ms.
Before proceeding with an explanation of the loop current
detector, ground key detector and later the longitudinal
impedance, it is important to understand the difference
between a “metallic” and “longitudinal” loop currents. Figure 18
illustrates 3 different types of loop current encountered.
Ground Key Detector
A simplified schematic of the ground key detector is shown in
Figure 18. Ground key, is the process in which the ring
terminal is shorted to ground for the purpose of signaling an
Operator or seizing a phone line (between the Central Office
and a Private Branch Exchange). The Ground Key detector is
Case 1 illustrates the metallic loop current. The definition of
a metallic loop current is when equal currents flow out of tip
and into ring. Loop current is a metallic current.
activated when unequal current flow through resistors R and
1
R . This results in a current (I ) out of the transconductance
2
GK
Cases 2 and 3 illustrate the longitudinal loop current. The
definition of a longitudinal loop current is a common mode
current, that flows either out of or into tip and ring
amplifier (gm ) that is equal to the product of gm and the
2
2
differential (I
-I
) loop current. If I
is less than the
TIP RING
GK
1
GK
2
internal current source (I ), then diode D is on and the output
1
simultaneously. Longitudinal currents in the on-hook state
result in equal currents flowing through the sense resistors
R and R (Figure 18). And longitudinal currents in the off-
of the ground key comparator is low. If I
is greater than the
internal current source (I ), then diode D is on and the output
1
of the ground key comparator is high. With the output of the
ground key comparator high, and the logic configured for
ground key detect, the DET pin goes low. The ground key
detector has a built in hysteresis of typically 5mA between its
trigger and reset values.
1
2
hook state result in unequal currents flowing through the
sense resistors R and R . Notice that for case 2,
1
2
longitudinal currents flowing away from the SLIC, the current
through R is the metallic loop current plus the longitudinal
1
current; whereas the current through R is the metallic loop
2
Ring Trip Detector
current minus the longitudinal current. Longitudinal currents
are generated when the phone line is influenced by
magnetic fields (e.g., power lines).
Ring trip detection is accomplished with the internal ring trip
comparator and the external circuitry shown in Figure 19. The
process of ring trip is initiated when the logic input pins are in the
following states: E0 = 0, E1 = 1/0, C1 = 1 and C2 = 0. This logic
condition connects the ring trip comparator to the DET output,
and causes the Ringrly pin to energize the ring relay. The ring
relay connects the tip and ring of the phone to the external
circuitry in Figure 19. When the phone is on-hook the DT pin is
more positive than the DR pin and the DET output is high. For
off-hook conditions DR is more positive than DT and DET goes
low. When DET goes low, indicating that the phone has gone
off-hook, the SLIC is commanded by the logic inputs to go into
the active state. In the active state, tip and ring are once again
connected to the phone and normal operation ensues.
Loop Current Detector
Figure 18 shows a simplified schematic of the loop current
and ground key detectors. The loop current detector works by
sensing the metallic current flowing through resistors R and
1
R . This results in a current (I ) out of the transconductance
2
RD
amplifier (gm ) that is equal to the product of gm and the
1
1
metallic loop current. I
then flows out the R pin and
RD
D
through resistor R to V . The value of I
is equal to:
D
EE RD
I
– I
I
L
300
(EQ. 24)
TIP
RING
I
= ----------------------------------- = ---------
RD
600
The I
current results in a voltage drop across R that is
D
RD
compared to an internal 1.25V reference voltage. When the
67
HC5526
gm (I
)
METALLIC
1
R
D
R
H
+
-
I
RD
C
D
R
CURRENT
LOOP
COMPARATOR
D
+
-
+
TIP
-
V
R
R
REF
1.25V
1
V
EE
gm
gm
1
gm (I
- I
)
2
TIP RING
-5V
2
2
I
GK
RING
R
H
+
-
-
D
2
CASE 1
CASE 2
CASE 3
+
D
1
I
GROUND
KEY
COMPARATOR
I
I
I
LONGITUDINAL
1
LONGITUDINAL
METALLIC
←
←
→
DIGITAL MULTIPLEXER
DET
HC5526
FIGURE 18. LOOP CURRENT AND GROUND KEY DETECTORS
Figure 19 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
amplifiers G and G accomplish this by sourcing or sinking
T R
the required current to maintain V at V
/2.
C
BAT
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at V moves from it’s equilibrium value
NOTE: The DET output will toggle at 20Hz because the DT input is
C
not completely filtered by C . Software can examine the duty cycle
RT
V
/2. When V changes by the amount ∆V , this change
BAT
appears between the input terminals of the differential
transconductance amplifiers G and G . The output of G
T
C C
and determine if the DET pin is low for more that half the time, if so
the off-hook condition is indicated.
T
R
and G are the differential currents ∆I and ∆I , which in
R
1
2
C
turn feed the differential inputs of current sources I and I
respectively. I and I have current gains of 250 single
RT
R
R
T
R
T
1
RT
R
3
DT
DR
T
R
-
DET
ended and 500 differentially, thus leading to a change in I
and I that is equal to 500(∆ ) and 500(∆I ).
+
R
I
2
R
4
RING TRIP
COMPARATOR
The circuit shown in Figure 20(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
TIP
R
2
E
RG
V
BAT
to current source 2I is now correlated, power savings due
O
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
RING
RINGRLY
HC5526
RING
RELAY
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5526 has two enable inputs pins (E0, E1)
and two control inputs pins (C1, C2).
FIGURE 19. RING TRIP CIRCUIT FOR BATTERY BACKED RINGING
Longitudinal Impedance
The enable pin E0 is used to enable or disable the DET
output pin. The DET pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
The feedback loop described in Figure 20(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22Ω.
The enable pin E1 gates the ground key detector to the DET
output with a logic level 0, and gates the loop or ring trip
detector to the DET output with a logic level 1.
In the presence of longitudinal currents this circuit
attenuates the voltages that would otherwise appear at the
tip and ring terminals, to levels well within the common mode
range of the SLIC. In fact, longitudinal currents may exceed
the programmed DC loop current without disturbing the
SLIC’s VF transmission capabilities.
A combination of the control pins C1 and C2 is used to
select 1 of the 4 possible operating states. A description of
each operating state and the control logic follow:
Open Circuit State (C1 = 0, C2 = 0)
The function of this circuit is to maintain the tip and ring
In this state the SLIC is effectively off. All detectors and both
the tip and ring line drive amplifiers are powered down,
presenting a high impedance to the line. Power dissipation is
at a minimum.
voltages symmetrically around V
/2, in the presence of
BAT
longitudinal currents. The differential transconductance
68
HC5526
I
LONG
TIP CURRENT SOURCE
WITH DIFFERENTIAL INPUTS
20Ω
I
I
LONG
T
TIP
R
TIP
+
T
∆I
∆I
1
1
∆V
5kΩ
5kΩ
-
G
T
-
+
LARGE
R
LARGE
∆I
∆I
1
1
V
/2
BAT
+
V
C
-
V
C
V
/2
BAT
G
R
R
LARGE
2I
0
I
LONG
R
∆I
∆I
LARGE
2
2
G
T
RING
TIP DIFFERENTIAL
TRANSCONDUCTANCE
AMPLIFIER
+
I
∆V
I
LONG
R
R
RING
HC5526
-
FIGURE 20A.
FIGURE 20. LONGITUDINAL IMPEDANCE NETWORK
FIGURE 20B.
Active State (C1 = 0, C2 = 1)
Thermal Shutdown Protection
The tip output is capable of sourcing loop current and for
open circuit conditions is about -4V from ground. The ring
output is capable of sinking loop current and for open circuit
The HC5526’s thermal shutdown protection is invoked if a
fault condition on the tip or ring causes the temperature of
the die to exceed 160 C. If this happens, the SLIC goes into
o
conditions is about V
+4V. VF signal transmission is
a high impedance state and will remain there until the
BAT
o
normal. The loop current and ground key detectors are both
active, E0 and E1 determine which detector is gated to the
DET output.
temperature of the die cools down by about 20 C. The SLIC
will return back to its normal operating mode, providing the
fault condition has been removed.
Ringing State (C1 = 1, C2 = 0)
Surge Voltage Protection
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
The HC5526 must be protected against surge voltages and
power crosses. Refer to “Maximum Ratings” TIPX and
RINGX terminals for maximum allowable transient tip and
ring voltages. The protection circuit shown in Figure 21
utilizes diodes together with a clamping device to protect tip
and ring against high voltage transients.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and ring
Positive transients on tip or ring are clamped to within a
couple of volts above ground via diodes D and D . Under
to V
to allow loop current detect in an off-hook condition.
BAT
1
2
The loop current and ground key detectors are both active, E0
and E1 determine which detector is gated to the DET output.
normal operating conditions D and D are reverse biased
1
2
and out of the circuit.
Negative transients on tip and ring are clamped to within a
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
couple of volts below ground via diodes D and D with the
3
4
help of a Surgector. The Surgector is required to block
compensation capacitors C and C
are required.
TC RC
conduction through diodes D and D under normal
3
4
Figure 21 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
operating conditions and allows negative surges to be
returned to system ground.
AC-DC Separation Capacitor, C
HP
The high pass filter capacitor connected between pins HPT
and HPR provides the separation between circuits sensing
tip to ring DC conditions and circuits processing AC signals.
The fuse resistors (R ) serve a dual purpose of being
F
nondestructive power dissipaters during surge and fuses
when the line in exposed to a power cross.
A 10nf C
will position the low end frequency response
HP
3dB break point at 48Hz. Where:
1
(EQ. 28)
f
= ----------------------------------------------------
3dB
(2 • π • R
• C
)
HP
HP
where R
= 330kΩ.
HP
69
HC5526
SLIC Operating States
TABLE 1. LOGIC TRUTH TABLE
E0
0
E1
0
C1
0
C2
0
SLIC OPERATING STATE
ACTIVE DETECTOR
DET OUTPUT
Logic Level High
Open Circuit
Active
No Active Detector
Ground Key Detector
No Active Detector
Ground Key Detector
0
0
0
1
Ground Key Status
Logic Level High
Ground Key Status
0
0
1
0
Ringing
0
0
1
1
Standby
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
Logic Level High
Loop Current Status
Ring Trip Status
Ringing
Standby
Loop Current Detector
Loop Current Status
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Open Circuit
Active
No Active Detector
Ground Key Detector
No Active Detector
Ground Key Detector
Logic Level High
Ringing
Standby
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
Ringing
Standby
Loop Current Detector
4. Longitudinal Current Limit (Off-Hook Active). Off-Hook (Ac-
tive, C = 1, C = 0) longitudinal current limit is determined by
Power-Up Sequence
1
2
The HC5526 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
increasing the amplitude of E (Figure 3A) until the 2-wire
L
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
5. Longitudinal Current Limit (On-Hook Standby). On-Hook
(Active, C = 1, C = 1) longitudinal current limit is determined
1
2
by increasing the amplitude of E (Figure 3B) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
L
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
6. Longitudinal to Metallic Balance. The longitudinal to metallic
balance is computed using the following equation:
BLME = 20 • log (E /V ), where: E and V
TR TR
are defined in
L
L
Figure 4.
The analog and digital grounds should be tied together at
the device.
7. Metallic to Longitudinal FCC Part 68, Para 68.310. The
metallic to longitudinal balance is defined in this spec.
Notes
8. Longitudinal to Four-Wire Balance. The longitudinal to 4-wire
balance is computed using the following equation:
2. Overload Level (Two-Wire port). The overload level is specified
at the 2-wire port (V
receive port (E ). I
RX DCMET
) with the signal source at the 4-wire
= 30mA, increase the amplitude of
TR0
BLFE = 20 • log (E /V ),: E and V are defined in Figure 4.
TX TX
L
L
9. Metallic to Longitudinal Balance. The metallic to longitudinal
E
until 1% THD is measured at V . Reference Figure 1.
RX
TRO
balance is computed using the following equation:
3. LongitudinalImpedance.The longitudinal impedance is com-
BMLE = 20 • log (E /V ), E
TR RX
= 0,
puted using the following equations, where TIP and RING volt-
L
ages are referenced to ground. L , L , V , V , A and A
ZT ZR T
T
R
R
where: E , V and E
are defined in Figure 5.
TR RX
L
are defined in Figure 2.
(TIP) L = V /A ,
10. Four-Wire to Longitudinal Balance. The 4-wire to longitudinal
ZT
T
T
balance is computed using the following equation:
(RING) L = V /A ,
ZR
R
R
BFLE = 20 • log (E /V ), E = source is removed,
RX TR
L
where: E = 1V
(0Hz to 100Hz).
RMS
L
where: E , V and E are defined in Figure 5.
RX TR
L
70
HC5526
11. Two-Wire Return Loss. The 2-wire return loss is computed
using the following equation:
20. Four-Wire to Two-Wire Insertion Loss. The 4-wire to 2-wire
insertion loss is measured based upon E = 0dBm, 1.0kHz
RX
= 23mA and is computed using
input signal, E = 0, I
G
DCMET
r = -20 • log (2V /V ),
M
S
the following equation:
where: Z = The desired impedance; e.g., the characteristic
D
impedance of the line, nominally 600Ω. (Reference Figure 6).
L
= 20 • log (V /E ).
TR RX
4-2
where: V and E
are defined in Figure 9.
TR RX
12. Overload Level (4-Wire port). The overload level is specified at
the 4-wire transmit port (V
) with the signal source (E ) at
21. Two-Wire to Four-Wire Gain Tracking. The 2-wire to 4-wire
TXO
G
the 2-wire port, I
= 23mA, Z = 20kΩ (Reference Figure
gain tracking is referenced to measurements taken for
DCMET
L
7). Increase the amplitude of E until 1% THD is measured at
E
= -10dBm, 1.0kHz signal, E
= 0, I
= 23mA and is
DCMET
G
G
RX
V
. Note that the gain from the 2-wire port to the 4-wire port
computed using the following equation.
TXO
is equal to 1.
G
= 20 • log (V /V ) vary amplitude -40dBm to +3dBm, or
TX TR
2-4
13. Output Offset Voltage. The output offset voltage is specified
-55dBm to -40dBm and compare to -10dBm reading.
with the following conditions: E = 0, I
= 23mA, Z = ∞
L
G
DCMET
V
and V are defined in Figure 9.
TX
TR
and is measured at V . E , I
, V and Z are defined
TX
G
DCMET TX
L
in Figure 7. Note: I
resistor between tip and ring.
is established with a series 600Ω
DCMET
22. Four-Wire to Two-Wire Gain Tracking. The 4-wire to 2-wire
gain tracking is referenced to measurements taken for
E
= -10dBm, 1.0kHz signal, E = 0, I
= 23mA and is
DCMET
RX
G
14. Two-Wire to Four-Wire (Metallic to VTX) Voltage Gain. The 2-
computed using the following equation:
wire to 4-wire (metallic to V ) voltage gain is computed using
TX
the following equation.
G
= 20 • log (V /E ) vary amplitude -40dBm to +3dBm,
TR RX
4-2
or -55dBm to -40dBm and compare to -10dBm reading.
G
= (V /V ), E = 0dBm0, V , V , and E are defined
TX TR TX TR
2-4
in Figure 7.
G
G
V
and E are defined in Figure 9. The level is specified at the
TR
RX
4-wire receive port and referenced to a 600Ω impedance level.
15. Current Gain RSN to Metallic. The current gain RSN to Metallic
is computed using the following equation:
23. Two-Wire Idle Channel Noise. The 2-wire idle channel noise at
V
is specified with the 2-wire port terminated in 600Ω (R )
TR
L
K = I [(R
DC1
+ R
)/(V
- V
)] K, I , R ,
, R
M
DC2
RDC
are defined in Figure 8.
RSN DC1 DC2
M
and with the 4-wire receive port grounded (Reference
Figure 10).
V
and V
RDC
16. Two-Wire to Four-Wire Frequency Response. The 2-wire to
4-wire frequency response is measured with respect to E = 0dBm
RSN
24. Four-Wire Idle Channel Noise. The 4-wire idle channel noise at
G
V
is specified with the 2-wire port terminated in 600Ω (R ).
L
TX
The noise specification is with respect to a 600Ω impedance
at 1.0kHz, E = 0V, I
= 23mA. The frequency response is
RX DCMET
computed using the following equation:
level at V . The 4-wire receive port is grounded (Reference
TX
F
= 20 • log (V /V ), vary frequency from 300Hz to
Figure 10).
2-4
TX TR
3.4kHz and compare to 1kHz reading.
25. Harmonic Distortion (2-Wire to 4-Wire). The harmonic distor-
V
, V , and E are defined in Figure 9.
TX TR
tion is measured with the following conditions. E = 0dBm at
G
G
1kHz, I
DCMET
Figure 7).
= 23mA. Measurement taken at V . (Reference
TX
17. Four-Wire to Two-Wire Frequency Response. The 4-wire to
2-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E = 0V, I
= 23mA. The fre-
DCMET
26. Harmonic Distortion (4-Wire to 2-Wire). The harmonic distor-
RX
G
quency response is computed using the following equation:
tion is measured with the following conditions. E
= 0dBm0.
RX
Vary frequency between 300Hz and 3.4kHz, I
= 23mA.
DCMET
F
= 20 • log (V /E ), vary frequency from 300Hz to
TR RX
4-2
Measurement taken at V . (Reference Figure 9).
TR
3.4kHz and compare to 1kHz reading.
27. Constant Loop Current. The constant loop current is calculated
V
and E are defined in Figure 9.
TR
RX
using the following equation:
18. Four-Wire to Four-Wire Frequency Response. The 4-wire to
I
= 2500 / (R
DC1
+ R
).
DC2
L
4-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E = 0V, I = 23mA. The fre-
DCMET
28. Standby State Loop Current. The standby state loop current is
RX
G
quency response is computed using the following equation:
calculated using the following equation:
o
F
= 20 • log (V /E ), vary frequency from 300Hz to
TX RX
I
= [|V
| - 3] / [R +1800], T = 25 C.
4-4
L
BAT
L
A
3.4kHz and compare to 1kHz reading.
29. Ground Key Detector. (TRIGGER) Increase the input current to
V
and E are defined in Figure 9.
8mA and verify that DET goes low.
TX
RX
19. Two-Wire to Four-Wire Insertion Loss. The 2-wire to 4-wire
insertion loss is measured with respect to E = 0dBm at 1.0kHz
(RESET) Decrease the input current from 17mA to 3mA and
verify that DET goes high.
G
input signal, E
= 0, I = 23mA and is computed using
RX
DCMET
(Hysteresis) Compare difference between trigger and reset.
the following equation:
= 20 • log (V /V ).
30. Power Supply Rejection Ratio. Inject signal
(50Hz to 4kHz) on V , V and V supplies. PSRR is
EE
a
100mV
RMS
L
2-4
TX TR
BAT
CC
where: V , V , and E are defined in Figure 9. (Note: The
computed using the following equation:
TX TR
G
fuse resistors, R , impact the insertion loss. The specified
F
PSRR = 20 • log (V /V ). V
Figure 12.
and V are defined in
TX IN
TX IN
insertion loss is for R = 0).
F
71
HC5526
Pin Descriptions
PLCC PDIP
SYMBOL
DESCRIPTION
1
RING
Internally connected to output of RING power amplifier.
SENSE
2
7
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
5
6
7
8
8
V
5V power supply.
CC
9
RINGRLY Ring relay driver output.
10
11
12
V
Battery supply voltage, -24V to -56V.
BAT
R
Saturation guard programming resistor pin.
SG
E1
TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector
is gated to the DET output.
9
13
14
E0
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set
to a logic level one.
11
DET
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered
(see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET
output is an open collector with an internal pull-up of approximately 15kΩ to V
CC.
12
13
14
15
16
17
C2
C1
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,
Ringing or Standby) of the SLIC.
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,
Ringing or Standby) of the SLIC.
R
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
DC1
and R
DC2
DC
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to
AGND to isolate the AC signal components.
15
16
18
19
AGND
RSN
Analog ground.
Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that
flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into
the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire
impedance all connect to this pin.
18
19
20
21
V
V
-5V power supply.
EE
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming
the 2-wire input impedance connects between this pin and RSN.
TX
20
21
22
23
25
22
1
HPR
HPT
RD
RING side of AC/DC separation capacitor C . C is required to properly separate the ring AC current from the
HP HP
DC loop current. The other end of C
is connected to HPT.
HP
TIP side of AC/DC separation capacitor C . C is required to properly separate the tip AC current from the DC
HP HP
is connected to HPR.
loop current. The other end of C
HP
2
Loop current programming resistor. Resistor R sets the trigger level for the loop current detect circuit. A filter
D
capacitor C is also connected between this pin and V
.
D
EE
3
DT
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a
comparator in the SLIC with inputs DT and DR.
4
DR
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a
comparator in the SLIC with inputs DT and DR.
26
27
28
TIP
Internally connected to output of tip power amplifier.
Output of tip power amplifier.
SENSE
5
6
TIPX
RINGX
N/C
Output of ring power amplifier.
3, 10,
No internal connection.
17, 24
72
HC5526
Pinouts
HC5526
(PLCC)
HC5526
(PDIP)
TOP VIEW
TOP VIEW
HPT
RD
1
2
22
21
HPR
V
TX
EE
DT
3
20 V
4
3
2
1
28 27 26
DR
4
19 RSN
TIPX
RINGX
BGND
5
18 AGND
6
17
R
RINGRLY
5
6
25 DR
24 N/C
23 DT
DC
7
16 C1
15 C2
V
BAT
V
8
CC
R
7
SG
14
13
12
RINGRLY
9
DET
E1
8
22
RD
V
10
11
E0
E1
BAT
9
E0
21 HPT
20 HPR
R
SG
10
11
N/C
DET
19 V
TX
12 13 14 15 16 17 18
73
HC5526
Application Circuit
C
(NOTE 32)
HP
R
C
R
RT
RT
1
2
R
U
FB
R
R
3
D
U
1
21 HPT
HPR 20
2
-5V
R
R
R
TX
4
22 RD
23 DT
V
V
19
18
-
TX
+
-5V
R
R
B
EE
T
V
BAT
R
RX
25 DR
RSN 16
AGND 15
PTC
PTC
R
F1
27 TIPX
R
DC1
D
D
TIP
D
1
3
CODEC/FILTER
C
TC
2 BGND
R
14
DC
NOTE 31
R
C
DC
DC2
C
4 V
CC
C1 13
C2 12
RC
D
RING
4
2
28 RINGX
R
Surgector
F2
V
BAT
K
A
DET 11
6 V
BAT
G
5 RINGRLY
E
9
8
O
D
5
R
SG
E
7 R
SG
1
RINGING
+ 90V
+5V
OR
12V
RELAY
-5V
(V
)
RMS
BAT
D
6
R
, R
Line Resistor, 20Ω, 1% Match, 2 W
Carbon column resistor or thick film on
ceramic
F1 F2
U1 SLIC (Subscriber Line Interface Circuit)
HC5526
U2 Combination CODEC/Filter e.g.
CD22354A or Programmable CODEC/
Filter, e.g. SLAC
R , R 200kΩ, 5%, 1/4W
1
3
2
4
R
R
R
910kΩ, 5%, 1/4W
1.2MΩ, 5%, 1/4W
18.7kΩ,1%, 1/4W
39kΩ, 5%, 1/4W
41.2kΩ, 5%, 1/4W
20.0kΩ, 1%, 1/4W
280kΩ, 1%, 1/4W
562kΩ, 1%, 1/4W
20kΩ, 1%, 1/4W
150Ω, 5%, 2W
C
1.5µF, 20%, 10V
DC
C
10nF, 20%, 100V (Note 2)
0.39µF, 20%, 100V
B
D
HP
R
C
RT
R
, R
C
, C
2200pF, 20%, 100V
DC1 DC2
TC RC
R
Relay Relay, 2C Contacts, 5V or 12V Coil
- D MOR120 Diode
FB
R
D
RX
1
5
R
T
Surgector SGT27S10
R
PTC Polyswitch TR600-150
TX
R
D
Diode, 1N4454
RT
6
R
V
V
= -28V, R
= -48V, R
= ∞
SG BAT
SG
SG
= 21.4kΩ, 1/4W 5%
BAT
NOTES:
31. It is recommended that the anodes of D and D be shorted to ground through a battery referenced surgector (SGT27S10).
3
4
32. To meet the specified 25dB 2-wire return loss at 200Hz, C
needs to be 20nF, 20%, 100V.
HP
FIGURE 21. APPLICATION CIRCUIT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
74
相关型号：
HC5544DCV-013.0M-T1K
HCSL Output Clock Oscillator, 13MHz Nom, ROHS COMPLIANT, CERAMIC, LCC, 6 PIN
PLETRONICS
HC5544DCV-013.0M-T500
HCSL Output Clock Oscillator, 13MHz Nom, ROHS COMPLIANT, CERAMIC, LCC, 6 PIN
PLETRONICS
HC5544DCV-FREQ-T1K
HCSL Output Clock Oscillator, 13MHz Min, 220MHz Max, ROHS COMPLIANT, CERAMIC, LCC, 6 PIN
PLETRONICS
HC5544DCV-FREQ-T250
HCSL Output Clock Oscillator, 13MHz Min, 220MHz Max, ROHS COMPLIANT, CERAMIC, LCC, 6 PIN
PLETRONICS
HC5544DCW-013.0M-T1K
HCSL Output Clock Oscillator, 13MHz Nom, ROHS COMPLIANT, CERAMIC, LCC, 6 PIN
PLETRONICS
©2020 ICPDF网 联系我们和版权申明