HC5517_00 [INTERSIL]
3 REN Ringing SLIC For ISDN Modem/TA and WLL; 3 REN振铃SLIC对于ISDN调制解调器/ TA和WLL
| 型号： | HC5517_00 |
| 厂家： | 
Intersil |
| 描述： | 3 REN Ringing SLIC For ISDN Modem/TA and WLL |
| 文件： | 总19页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC5517
®
October 2000
File Number 4147.3
3 REN Ringing SLIC For ISDN Modem/TA
and WLL
Features
• Thru-SLIC Open Circuit Ringing Voltage up to
77V /54V , 3 REN Capability at 44V
RMS
The HC5517 is a ringing SLIC designed to accommodate a
wide variety of local loop applications. The various applications
include, basic POTS lines with answering machines and fax
capabilities, ISDN networks, wireless local loop, and hybrid
fiber coax (HFC) terminals. The HC5517 provides a high
degree of flexibility with open circuit tip to ring DC voltages, user
defined ringing waveforms (sinusoidal to square wave), ring trip
detection thresholds and loop current limits that can be tailored
for many applications. Additional features of the HC5517 are
complex impedance matching, pulse metering and transhybrid
balance. The HC5517 is designed for use in systems where a
separate ring generator is not economically feasible.
PEAK
RMS
• Sinusoidal Ringing Capability
• DI Process Provides Substrate Latch Up Immunity when
Driving Inductive Ringers
• Adjustable On-Hook Voltage for Fax and Answering
Machine Compatibility
• Resistive and Complex Impedance Matching
• Programmable Loop Current Limit
• Switch Hook and Adjustable Ring Trip Detection
• Pulse Metering Capability
The device is manufactured in a high voltage Dielectric Isolation
(DI) process with an operating voltage range from -16V, for off-
hook operation and -80V for ring signal injection. The DI
process provides substrate latch up immunity, resulting in a
robust system design. Together with a secondary protection
diode bridge and “feed” resistors, the device will withstand
1000V lightning induced surges, in a plastic package.
• Single Low Voltage Positive Supply (+5V)
Applications
• Solid State Line Interface Circuit for Wireless Local Loop,
Hybrid Fiber Coax, Set Top Box, Voice/Data Modems
• Related Literature
- AN9606, Operation of the HC5517 Evaluation Board
- AN9607, Impedance Matching Design Equations
- AN9628, AC Voltage Gain
A thermal shutdown with an alarm output and line fault
protection are also included for operation in harsh
environments.
- AN9608, Implementing Pulse Metering
Part Number Information
- AN9636, Implementing an Analog Port for ISDN Using
the HC5517
TEMP.RANGE
o
PART NUMBER
HC5517IM
( C)
PACKAGE
28 Ld PLCC
28 Ld PLCC
28 SOIC
PKG. NO.
N28.45
N28.45
M28.3
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
-40 to 85
0 to 75
HC5517CM
HC5517IB
-40 to 85
0 to 75
HC5517CB
28 SOIC
M28.3
Block Diagram
V
V
RX
TX
TIP FEED
4-WIRE
INTERFACE
TIP SENSE
2-WIRE
INTERFACE
V
RING
LOOP CURRENT
DETECTOR
RING FEED
- IN 1
-
RING SENSE 1
RING SENSE 2
+
FAULT
DETECTOR
OUT 1
V
CURRENT
LIMIT
REF
SHD
ALM
RTI
I
RING TRIP
DETECTOR
LMT
V
BAT
V
CC
BIAS
RTD
RDO
AGND
BGND
RELAY
DRIVER
IIL LOGIC INTERFACE
F1
F0
RS TST
RDI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HC5517
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
Maximum Supply Voltages
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
(V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7V
CC
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
55
70
o
(V )-(V
CC BAT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +15V
o
o
o
Operating Conditions
(SOIC, PLCC - Lead Tips Only)
Operating Temperature Range
HC5517IM, HC5517IB . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
HC5517CM, HC5517CB . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V
o
o
o
o
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120
Positive Power Supply (V ). . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
CC
Negative Power Supply (V
) . . . . . . . . . . . . . . . . . . .-16V to -80V
BAT
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
BAT
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. All grounds (AGND, BGND) must be applied before V
or V
. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
CC
BAT
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V
= +5V, AGND = BGND = 0V. All AC Parameters are
BAT
CC
specified at 600Ω 2-Wire terminating impedance.
PARAMETER
RINGING TRANSMISSION PARAMETERS
Input Impedance
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 3)
to Vt-r (Note 3)
-
-
5.4
40
-
-
kΩ
RING
4-Wire to 2-Wire Gain
V
V/V
RING
AC TRANSMISSION PARAMETERS
RX Input Impedance
300Hz to 3.4kHz (Note 3)
300Hz to 3.4kHz (Note 3)
-
-
108
-
20
-
kΩ
TX Output Impedance
-
-
Ω
4-Wire Input Overload Level
300Hz to 3.4kHz R = 1200Ω, 600Ω Reference
+1.0
V
PEAK
L
(Note 3)
2-Wire Return Loss
SRL LO
Matched for 600Ω (Note 3)
26
30
30
58
35
40
40
63
-
-
-
-
dB
dB
dB
dB
ERL
SRL HI
2-Wire Longitudinal to Metallic Balance
Off Hook
Per ANSI/IEEE STD 455-1976 (Note 3)
300Hz to 3400Hz
4-Wire Longitudinal Balance Off Hook
Low Frequency Longitudinal Balance
Longitudinal Current Capability
Insertion Loss
300Hz to 3400Hz (Note 3)
o
50
-
55
10
-
-
dB
I
= 40mA T = 25 C (Note 3)
A
23
40
dBrnC
mA
LINE
o
I
= 40mA T = 25 C (Note 3)
-
LINE
A
RMS
0dBm at 1kHz, Referenced 600Ω
2-Wire/4-Wire (Includes external transhybrid
amplifier with a gain of 3)
-
±0.05
±0.2
dB
4-Wire/2-Wire
-
-
±0.05
±0.2
dB
dB
4-Wire/4-Wire (Includes external transhybrid
amplifier with a gain of 3)
-
±0.25
2
HC5517
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V
= +5V, AGND = BGND = 0V. All AC Parameters are
BAT
CC
specified at 600Ω 2-Wire terminating impedance. (Continued)
PARAMETER
Frequency Response
TEST CONDITIONS
MIN
TYP
MAX
UNITS
300Hz to 3400Hz (Note 3) Referenced to
-
±0.02
±0.06
dB
Absolute Level at 1kHz, 0dBm Referenced 600Ω
Level Linearity
Referenced to -10dBm (Note 3)
2-Wire to 4-Wire and 4-Wire to 2-Wire
+3 to -40dBm
-40 to -50dBm
-50 to -55dBm
-
-
-
-
-
-
±0.08
±0.12
±0.3
dB
dB
dB
Absolute Delay
2-Wire/4-Wire
(Note 3)
300Hz to 3400Hz
-
-
-
-
1.0
1.0
1.5
µs
µs
µs
dB
dB
4-Wire/2-Wire
4-Wire/4-Wire
300Hz to 3400Hz
300Hz to 3400Hz
-
0.95
40
-
Transhybrid Loss
V
= 1V
P-P
at 1kH (Notes 3, 4)
30
-
IN
Total Harmonic Distortion
Reference Level 0dBm at 600Ω
-50
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire
300Hz to 3400Hz (Note 3)
Idle Channel Noise
2-Wire and 4-Wire
(Note 3)
C-Message
-
-
3
-
-
dBrnC
dBmp
Psophometric (Note 3)
-87
Power Supply Rejection Ratio
(Note 3)
30Hz to 200Hz, R = 600Ω
L
V
V
V
V
V
V
V
V
to 2-Wire
to 4-Wire
20
20
20
20
30
20
20
20
40
40
40
50
40
28
50
50
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
CC
CC
to 2-Wire
to 4-Wire
BAT
BAT
to 2-Wire
to 4-Wire
(Note 3)
CC
200Hz to 16kHz, R = 600Ω
L
CC
to 2-Wire
to 4-Wire
BAT
BAT
DC PARAMETERS
Loop Current Programming
Limit Range
20
-
60
mA
(Note 5)
Accuracy
10
-
-
-
%
Loop Current During Power Denial
R
= 200Ω
±4
±7
mA
L
Fault Currents
TIP to Ground (Note 3)
-
30
120
150
12
-
-
mA
mA
mA
mA
V
RING to Ground
-
-
TIP and RING to Ground (Note 3)
Switch Hook Detection Threshold
Ring Trip Comparator Voltage Threshold
Thermal ALARM Output (Note 3)
-
-
15
-0.22
160
-0.28
140
-0.24
-
o
Safe Operating Die Temperature Exceeded
C
3
HC5517
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V
= +5V, AGND = BGND = 0V. All AC Parameters are
BAT
CC
specified at 600Ω 2-Wire terminating impedance. (Continued)
PARAMETER
Dial Pulse Distortion (Note 3)
Uncommitted Relay Driver
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
0.1
0.5
ms
On Voltage V
I
(RDO) = 30mA
-
-
0.2
0.5
V
OL
OL
Off Leakage Current
±10
±100
µA
TTL/CMOS Logic Inputs (F0, F1, RS, TST, RDI)
Logic ‘0’ V
0
2.0
-
-
-
-
-
0.8
5.5
-1
V
V
IL
Logic ‘1’ V
IH
Input Current (F0, F1, RS, TST, RDI)
Input Current (F0, F1, RS, TST, RDI)
Logic Outputs
IIH, 0V ≤ V ≤ 5V
IN
µA
µA
IIL, 0V ≤ V ≤ 5V
IN
-
-100
Logic ‘0’ V
I
I
= 800µA
= 40µA
-
0.1
-
0.5
V
OL
LOAD
Logic ‘1’ V
2.7
-
-
-
-
V
OH
LOAD
Power Dissipation On Hook
Power Dissipation Off Hook
V
V
V
= +5V, V
= +5V, V
= +5V, V
= -80V, R
= -48V, R
= -24V, R
= ∞
-
-
-
300
150
280
mW
mW
mW
CC
CC
CC
BAT
BAT
BAT
LOOP
LOOP
LOOP
= ∞
= 600Ω,
I
= 25mA
L
I
V
V
V
V
V
V
= +5V, V
= +5V, V
= +5V, V
= -80V, R
= -48V, R
= -24V, R
= ∞
= ∞
= ∞
-
-
-
-
-
-
3
6
5
4
7
6
4
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
CC
BAT
BAT
BAT
LOOP
LOOP
LOOP
2
1.9
3.6
2.6
1.8
I
= +5V, V - = -80V, R
= ∞
BAT
B
LOOP
LOOP
LOOP
= +5V, V - = -48V, R
= ∞
= ∞
B
= +5V, V - = -24V, R
B
UNCOMMITTED OP AMP PARAMETERS
Input Offset Voltage
-
-
-
-
-
±5
±10
1
-
-
-
-
-
mV
nA
Input Offset Current
Differential Input Resistance (Note 3)
Output Voltage Swing (Note 3)
Small Signal GBW (Note 3)
NOTES:
MΩ
R
= 10kΩ
±3
1
V
L
P-P
MHz
3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification com-
pliance.
4. For transhybrid circuit as shown in Figure 10.
5. Application limitation based on maximum switch hook detect limit and metallic currents. Not a part limitation.
4
HC5517
Functional Diagram
PLCC/SOIC
R
V
OUT 1
12
V
CC
-IN 1
13
VRX
17
V
AGND
RING
TX
19
24
2
1
R
R
TF
22
27
25
-
BGND
TF
+
-
BIAS
OP AMP
+
NETWORK
R/2
R/20
V
BAT
+2V
4
5
6
9
R
R
2R
F1
F0
TA
-
SH
R
SHD
RTD
+
14
TIP
SENSE
RS
TST
R
2R
THERM
LTD
TSD
4.5K
25K
100K
100K
15
GK
RA
RING
SENSE 1
-
100K
100K
4.5K
+
25K
16
FAULT
DET
RING
SENSE 2
7
SHD
RTD
ALM
8
90K
90K
RFC
10
RF
26
21
GM
-
RF
90K
RDO
RF2
+
VB/2
REF
-
+
R = 108kΩ
11
ILMT
20
3
18
NU
28
RTI
V
RDI
REF
HC5517 TRUTH TABLE
F1
F0
0
ACTION
Loop power Denial Active
Power Down Latch RESET
Power on RESET
RD Active
0
0
0
1
1
1
1
0
1
Normal Loop feed
.
Over Voltage Protection and Longitudinal Current
Protection
TABLE 1.
TEST
PERFORMANCE
(MAX)
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
PARAMETER
CONDITION
UNITS
Longitudinal
Surge
10µs Rise/
1000µs Fall
±1000 (Plastic)
±1000 (Plastic)
±1000 (Plastic)
V
V
V
PEAK
PEAK
PEAK
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
Metallic Surge
10µs Rise/
1000µs Fall
T/GND
R/GND
10µs Rise/
1000µs Fall
maximum or 30mA
, 15mA
per leg, without any
RMS
RMS
performance degradation
50/60Hz Current
T/GND
11 Cycles
Limited to
700 (Plastic)
V
RMS
R/GND
10A
RMS
5
HC5517
Circuit Operation and Design Information
The HC5517 is a voltage feed current sense Subscriber Line
Current Limit
Interface Circuit (SLIC). This means that for long loop
applications the SLIC provides a constant voltage to the tip
and ring terminals while sensing the tip to ring current. For
short loops, where the loop current limit is exceeded, the tip
to ring voltage decreases as a function of loop resistance.
The tip feed to ring feed voltage (Equation 1 minus
Equation 3) is equal to the battery voltage minus 8V. Thus,
with a 48 (24) volt battery and a 600Ω loop resistance,
including the feed resistors, the loop current is 66.6mA
(26.6mA). On short loops the line resistance often
approaches zero and the need exists to control the
maximum DC loop current.
The following discussion separates the SLIC’s operation into
its DC and AC path, then follows up with additional circuit
design and application information.
Current limiting is achieved by a feedback network (Figure 1)
that modifies the ring feed voltage (V ) as a function of the
loop current. The output of the Transversal Amplifier (TA)
has a DC voltage that is directly proportional to the loop
D
DC Operation of Tip and Ring Amplifiers
SLIC in the Active Mode
current. This voltage is scaled by R and R . The scaled
10 28
The tip and ring amplifiers are voltage feedback op amps that
are connected to generate a differential output (e.g. if tip
sources 20mA then ring sinks 20mA). Figure 1 shows the
connection of the tip and ring amplifiers. The tip DC voltage is
set by an internal +2V reference, resulting in -4V at the output.
The ring DC voltage is set by the tip DC output voltage and an
voltage is the input to a transconductance amplifier (GM)
that compares it to an internal reference level. When the
scaled voltage exceeds the internal reference level, the
transconductance amplifier sources current. This current
charges C in the positive direction causing the ring feed
16
voltage (V ) to approach the tip feed voltage (V ). This
D
C
internal V
/2 reference, resulting in V
+4V at the
BAT
BAT
effectively reduces the tip feed to ring feed voltage (V
and holds the maximum loop current constant.
),
T-R
output. (See Equation 1, Equation 2 and Equation 3.)
R
R ⁄ 2
(EQ. 1)
(EQ. 2)
V
= V = –2V ---------- = –4V
The maximum loop current is programed by resistors R and
10
TIPFEED
C
R
as shown in Equation 4 (Note: R is typically 100kΩ).
28
10
V
R
R
--
R
BAT
(0.6)(R + R
10
)
28
= ---------------------------------------------
V
V
= V = -------------- 1 + --- – V
(EQ. 4)
RINGFEED
RINGFEED
D
TIPFEED
I
2
R
LIMIT
(200xR
)
28
= V = V
+ 4
(EQ. 3)
0
D
BAT
V
= -4V
TIP FEED
-5
-10
-15
-20
-25
CONSTANT VOLTAGE
V
RX
REGION
R
R
R
OUT1
TIP FEED
R/20
R/2
R
R
TIP
11
13
V
V
= -20V
RING FEED
-
RING
+
CURRENT LIMIT
-
+
V
C
REGION I
= 25mA
LOOP
INTERNAL
+2V REF
+
-
TRANSVERSAL
AMP
250
500
LOOP RESISTANCE (Ω)
750
∞
0
TA
-
V
TX
+
R
R
FIGURE 2. V
vs R (V
BAT
= -24V, I
= 25mA)
10
28
LIMIT
T-R
L
GM
-
+
Figure 2 illustrates the relationship between V
and the
T-R
loop resistance. The conditions are shown for a battery
voltage of -24V and the loop current limit set to 25mA. For a
infinite loop resistance both tip feed and ring feed are at -4V
and -20V respectively. When the loop resistance decreases
from infinity to about 640Ω the loop current (obeying Ohm’s
Law) increases from 0mA to the set loop current limit. As the
loop resistance continues to decrease, the ring feed voltage
approaches the tip feed voltage as a function of the
programed loop current limit (Equation 4).
RF2
90kΩ
90kΩ
RING FEED
R
R
14
12
RING
V
90kΩ
-
+
+
-
V
BAT
2
-
, V
C
V
D
OUT1 RX
16
+
GROUNDED FOR
DC ANALYSIS
FIGURE 1. OPERATION OF THE TIP AND RING AMPLIFIERS
6
HC5517
AC Voltage Gain Design Equations
4R ∆I
R
V
S
L
8
RX
(EQ. 7)
I
= – -------------------- ------ + -----------
The HC5517 uses feedback to synthesize the impedance at
the 2-wire tip and ring terminals. This feedback network
defines the AC voltage gains for the SLIC.
R
R
R
R
9
The AC voltage at V is then equal to:
C
(EQ. 8)
(EQ. 9)
V
= (I )(R)
R
C
The 4-wire to 2-wire voltage gain (V
feedback loop shown in Figure 3. The feedback loop senses
to V ) is set by the
TR
RX
R
8
the loop current through resistors R and R , sums their
V
= –4R ∆I ------ + V
13
14
C
S
L
RX
R
9
voltage drop and multiplies it by 2 to produce an output voltage
at the V pin equal to +4R ∆I . The V voltage is then fed
TX TX
S L
and the AC voltage at V is:
D
into the -IN1 input of the SLIC’s internal op amp. This signal is
multiplied by the ratio R /R and fed into the tip current
R
8
8
9
(EQ. 10)
V
= 4R ∆I ------ – V
D
S
L
RX
summing node via the OUT1 pin. (Note: the internal V
/2
R
BAT
9
reference (ring feed amplifier) and the internal +2V reference
(tip feed amplifier) are grounded for the AC analysis.)
The values for R and R are selected to match the
8
9
impedance requirements on tip and ring, for more
The current into the OUT1 pin is equal to:
information reference AN9607 “Impedance Matching Design
Equations for the HC5509 Series of SLICs”. The following
loop current calculations will assume the proper R and R
4R ∆I
R
8
S
R
L
(EQ. 5)
I
= –-------------------- ------
OUT1
8
9
R
9
values for matching a 600Ω load.
Equation 6 is the node equation for the tip amplifier summing
The loop current (∆I ) with respect to the feedback network,
L
node. The current in the tip feedback resistor (I ) is given in
R
is calculated in Equations 11 through 14. Where R = 40kΩ,
8
Equation 7.
R = 40kΩ, R = 600Ω, R = R = R = R = 50Ω.
9
L
11
12
13
14
4R ∆I
R
V
RX
R
S
L
8
(EQ. 6)
V
– V
D
– I – -------------------- ------ + ----------- = 0
C
(EQ. 11)
R
∆I = --------------------------------------------------------------------------
R
R
L
9
R
+ R + R + R + R
11 12 13 14
L
R
1V
P
V
–4(R ∆I ) R
V
RX
S
L
8
RX
R
I
= ----------------------------- ------- + ------------
R
R
R
9
I
R
OUT1
R
R
∆I
∆I
4R ∆I
R
R
+
L
-
R/20
+
L
-
S
L
8
9
I
=
OUT1
V
RING
2R
R
R
13
11
-
TIP
R/2
+
†
-
+
V
+
C
2V
DC
-
R
A
8
-------
V
= –4R ∆I
+ V
C
S
L
RX
R
9
+R ∆I
S
L
R
8
-
-
∆I
+
+
V
TR
R
R
L
9
L
+
-
-IN
2
R
= R = R = R = R
12 13 14
-
1
V
TX
11
S
+
-
R
R
+
-
∆V
-
∆I
+
8
9
IN
+
4R ∆I
S
L
+
4R ∆I
L
-R ∆I
S
L
+
S
L
-
-
90kΩ
90kΩ
B
R
R
14
12
†
-
RING
+
+
-
∆I
V
BAT
2
∆I
-
L
-
R
† GROUNDED FOR AC ANALYSIS
L
+
-
+
V
8
+
D
V
D
= 4R ∆I ------- – V
S
L
RX
R
9
FIGURE 3. AC VOLTAGE GAIN AND IMPEDANCE MATCHING
7
HC5517
Substituting the expressions for V and V :
The net effect cancels out the voltage drop across the feed
C
D
R
resistors. By nullifying the effects of the feed resistors the
feedback circuitry becomes relatively easy to match the
impedance at points “A” and “B”.
8
2 × –4R ∆I ------ + V
S
L
RX
R
9
(EQ. 12)
∆I = --------------------------------------------------------------------------
L
R
+ R + R + R + R
11 12 13
L
14
IMPEDANCE MATCHING DESIGN EQUATIONS
Equation 12 simplifies to:
2V – 400∆I
Matching the impedance of the SLIC to the load is
accomplished by writing a loop equation starting at V and
RX
L
(EQ. 13)
(EQ. 14)
D
∆I = ----------------------------------------
L
800
going around the loop to V . The loop equation to match the
C
impedance of any load is as follows (Note: V
= 0 for this
RX
Solving for ∆I results in:
L
analysis):
V
RX
∆I = -----------
R
8
L
600
–4R ∆I ------ + 2R ∆I –∆V
+
S
L
S
L
IN
R
9
Equation 14 is the loop current with respect to the feedback
network. From this, the 4-wire to 2-wire and the 2-wire to
4-wire AC voltage gains are calculated. Equation 15 shows
the 4-wire to 2-wire AC voltage gain is equal to one.
R
8
(EQ. 17)
R ∆I + 2R ∆I –4R ∆I ------ = 0
L
L
S
L
S
L
R
9
R
8
(EQ. 18)
(EQ. 19)
∆V = –8R ∆I ------ + 4R ∆I + R ∆I
V
IN
S
L
S
L
L
L
RX
R
9
----------- (600)
V
∆I (R )
L L
600
TR
(EQ. 15)
A
= ----------- = -------------------- = -------------------------- = 1
4W – 2W
R
V
V
V
RX
8
RX
RX
∆V = ∆I –8R ------ + 4R + R
IN L
L
S
S
R
9
Equation 16 shows the 2-wire to 4-wire AC voltage gain is
equal to negative one-third.
Equation 19 can be separated into two terms, the feedback
(-8R (R /R )) and the loop impedance (+4R +R ).
S
8
9
S
L
R
8
V
∆V
R
(EQ. 20)
–4R ∆I ------
RX
–200----------- (1)
600
V
IN
------------ = –8R ------ + 4R + R
L
8
S
L
R
V
9
S
S
1
3
OUT1
∆I
R
9
A
= ------------------ = ------------------------------------- = --------------------------------- = –--
L
2W – 4W
V
∆I (R )
TR
L
L
RX
----------- (600)
600
The result is shown in Equation 20. Figure 4 is a schematic
representation of Equation 15.
(EQ. 16)
R
L
Impedance Matching
The feedback network, described above, is capable of
synthesizing both resistive and complex loads. Matching the
SLIC’s 2-wire impedance to the load is important to
LOAD
R
8
+
∆V
IN
SLIC
8RS ------- + 4R
-
S
R
9
maximize power transfer and minimize the 2-wire return
loss. The 2-wire return loss is a measure of the similarity of
the impedance of a transmission line (tip and ring) and the
impedance at it’s termination. It is a ratio, expressed in
decibels, of the power of the outgoing signal to the power of
the signal reflected back from an impedance discontinuity.
FIGURE 4. SCHEMATIC REPRESENTATION OF EQUATION 20
To match the impedance of the SLIC to the impedance of
the load, set:
R
8
(EQ. 21)
R
= 8R ------ + 4R
Requirements for Impedance Matching
L
S
S
R
9
Impedance matching of the HC5517 application circuit to the
transmission line requires that the impedance be matched to
points “A” and “B” in Figure 3. To do this, the sense resistors
If R is made to equal 8R then:
9
S
(EQ. 22)
R
= R + 4R
8 S
R
, R , R and R must be accounted for by the
L
11 12 13 14
feedback network to make it appear as if the output of the tip
and ring amplifiers are at points “A” and “B”. The feedback
network takes a voltage that is equal to the voltage drop
across the sense resistors and feeds it into the summing node
of the tip amplifier. The effect of this is to cause the tip feed
voltage to become more negative by a value that is
Therefore to match the HC5517, with R equal to 50Ω, to a
600Ω load:
S
(EQ. 23)
R
= 8R = 8(50Ω) = 400Ω
S
9
and:
= R –4R = 600Ω – 200Ω = 400Ω
proportional to the voltage drop across the sense resistors
(EQ. 24)
R
8
L
S
R
and R . At the same time the ring amplifier becomes
11
13
more positive by the same amount to account for resistors
and R
R
.
14
12
8
HC5517
To prevent loading of the V output, the value of R and R
9
+5V
TX
8
are typically scaled by a factor of 100:
(EQ. 25)
KR = 40kΩ
KR = 40kΩ
9
R
R
19
24
8
Since the impedance matching is a function of the voltage
gain, scaling of the resistors to achieve a standard value is
recommended.
T
2
RC
TO ZENER
DIODE D
11
D
13
R
R/20
R/2
For complex impedances the above analysis is the same.
Reactive
V
RING
D
6
KR = 40kΩ
KR = 100(Resistive – 200) + --------------------------
8
9
-
100
TF
+
(EQ. 26)
R
+
18
+2V
-
TIP FEED
V
C
AMPLIFIER
Reference application note AN9607 (“Impedance Matching
Design Equations for the HC5509 Series of SLICs”) for the
values of KR and KR for several worldwide Typical line
impedances.
9
8
90kΩ
90kΩ
90kΩ
-
V
Tip-to-Ring Open-Circuit Voltage
RF
BAT
2
+
----------------
The tip-to-ring open-circuit voltage, V , of the HC5517 is
programmable to meet a variety of applications. The design
RING FEED
AMPLIFIER
OC
of the HC5517 defaults the value of V
to:
OC
FIGURE 5. CENTERING VOLTAGE APPLICATION CIRCUIT
V
≅ V
– 8
BAT
OC
The circuitry within the dotted lines is internal to the HC5517.
The value of the resistor designated as R is 108kΩ and the
resistor R/20 is 5.4kΩ. The tip amplifier gain of 20V/V amplifies
The HC5517 application circuit overrides the default V
operation when operating from a -80V battery. While
operating from a -80V battery, the SLIC will be in either the
ringing mode or on-hook standby mode. In the ringing mode,
OC
the +1.8V
at V to +36V and adds it to the internal 4V
DC
offset, generating -40V
C DC DC
at the tip amplifier output. The -
DC
V
is designed to switch from 0V (centering voltage) to -
OC
40V
offset also sums into the ring amplifier, adding to the
DC
47V (Maintenance Termination Unit voltage). The centering
voltage is active during the ringing portion of the ringing
waveform and the Maintenance Termination Unit (MTU)
voltage is active during the silent portion of the ringing
signal. In the on-hook standby mode, the application circuit
battery voltage, achieving -40V at the ring amplifier output.
Centering Voltage Design Equations
The centering voltage (V ) is dependent on the battery
C
voltage. A battery voltage of -80V requires a +1.8V
DC
centering voltage. The equation used to calculate the
centering voltage is shown below.
is designed to maintain V
at the MTU voltage.
OC
Centering Voltage Application Circuit Overview
V
BAT
--------------
2
(EQ. 27)
V
=
– 4 ⁄ 20
The centering voltage is used during ringing to center the DC
outputs of the tip feed and ring feed amplifiers. Centering the
amplifier outputs allows for the maximum undistorted voltage
swing of the ringing signal. Without centering, the output of
C
The DC voltage at the outputs of the centered tip and ring
amplifiers can be calculated from Equation 28 and
Equation 29.
each amplifier would saturate at ground or V
, minimizing
BAT
the ringing capability of the HC5517. The required centering
voltage, V , is +1.8V when operating from a -80V battery.
(EQ. 28)
V
= –(20V + 4)
C
TC
C
DC
Centering Voltage Application Circuit Operation
(EQ. 29)
V
= V
+ (20V + 4)
C
RC
BAT
The circuit used to generate the centering voltage is shown
in Figure 5.
The shunt resistor of the divider network, R , is not
18
determined from a design equation. It is selected based on
the trade-off of power dissipation in the voltage divider (low
value of R ) and loading affects of the internal R/20 resistor
18
(high value of R ). The suggested range of R is between
18 18
1.0kΩ and 2.0kΩ. The application circuit design equation
used to calculate the value of R of the divider network is
19
as follows:
9
HC5517
Internal to the HC5517 are connections to the tip feed amplifier
output and V /2 reference. The DC voltage at the tip feed
output, V
TDC
(V
– V
– V – V )(R • R
D6 18
)
IN
CC
D13
C
(EQ. 30)
R
= ---------------------------------------------------------------------------------------------------
BAT
, is a constant -4V during on-hook standby.
19
(V + V )R + V R
C
D6 IN
C 18
where:V
forward drop of D , 0.63V.
D13
13
MTU Voltage Design Equations
V
forward drop of D , 0.54V.
D6
6
R
R
is the shunt resistor of the divider, 1.1kΩ.
The following equations are used to predict the DC output of
18
IN
is the input impedance of V
, 5.4kΩ.
the ring feed amplifier, V
.
RING
RDC
V
V
is the required centering voltage, 1.8V, V
is the +5V supply.
= -80V.
C
BAT
V
V
BAT
2
BAT
2
(EQ. 31)
CC
< V
V
= 2 ------------- + 4
--------------
Z
RDC
Centering Voltage Logic Control
The pnp transistor T is used to defeat the voltage divider
2
V
BAT
2
(EQ. 32)
≥ V
V
= 2(–V + (V – V )) + 4
CE BE
formed by R , R , D and D . When T is off (RC is logic
--------------
19 18
13
6
2
Z
RDC
Z
high), +5V
is divided to produce +1.8V
at the V
DC
DC RING
Where V is the zener diode voltage of D and V
11
and
Z
CE
input. When T is on (RC is logic low), its emitter base
2
V
are the saturation voltages of T . Using Equations 31
BE
2
voltage of +0.9V
is divided resulting in +0.2V at the anode
DC
and 32, the tip-to-ring open-circuit voltage can be calculated
for any value of zener diode and battery voltage.
of D , hence reverse biasing the diode (D ) and floating the
6
6
V
pin.
RING
V
V
--------------
BAT
2
BAT
2
(EQ. 33)
< V
V
= V
– 2 ------------- – 4
MTU Voltage Application Circuit Overview
Z
OC
TDC
According to Bellcore specification TR-NWT-000057, an MTU
voltage may be required by some operating companies. The
minimum allowable voltage to meet MTU requirements is -
42.75V, which is used by measurement equipment to verify an
active line. Also, some facsimile and answering machines use
the MTU voltage as an indication that the telephone is on-hook
or not answered. In addition to the Bellcore specification, FCC
Part 68.306 requires that the maximum tip to ground or ring to
ground voltage not exceed -56.5V for hazardous voltage
limitations. These two requirements have been combined and
the resulting range is defined as the MTU voltage. The HC5517
application circuit can be programmed to any voltage within this
range using the zener clamping circuit.
V
BAT
--------------
≥ V
V
= V
– 2(–V + (V
– V )) – 4
CE BE
Z
OC
TDC
Z
2
(EQ. 34)
as a function of battery voltage. The
Figure 7 plots V
graph illustrates the clamping function of the zener circuitry.
OC
+50
+40
+30
+20
+10
0
MTU Voltage Application Circuit Operation
The circuit used to generate the MTU voltage is shown in
Figure 6.
-16
-28
-40
-52
-58
-68
-80
FIGURE 7. V
AS A FUNCTION OF BATTERY VOLTAGE
90K
90K
OC
TIP FEED OUTPUT
MTU Voltage Logic Control
-
90K
RF
+
V
BAT
----------------
The same pnp transistor, T , that is used to control the
2
centering voltage is also used to control the MTU voltage.
RING FEED
AMPLIFIER
+5V
2
The application circuit uses T to ground or float the anode
2
V
3
REF
of the zener diode D . When RC is a logic low (T on) the
11
2
R
R
24
19
anode of D is referenced to ground through the collector
11
C
16
D
base junction of the transistor. Current then flows through
the zener, allowing the ring amplifier input to be clamped.
When RC is a logic high (T off) the anode of D floats,
11
RC
T
2
FIGURE 6. RING FEED AMPLIFIER CIRCUIT CONNECTIONS
2
11
inhibiting the clamping action of the zener.
The ring feed amplifier DC output voltage, V
, is a
RDC
/2 reference and external zener
HC5517 Modes of Operation
function of the internal V
BAT
diode D . When the magnitude of V
zener voltage, the zener is off and the input to the ring feed
/2 is less than the
The four modes of operation of the HC5517 Ringing SLIC are
ringing, on-hook standby, off-hook active and power denial.
Three control signals select the operating mode of the SLIC.
The signals are Battery Switch, F1 and Ring Cadence (RC).
The active application circuit and active supervisory function
are different for each mode, as shown in the Table 2.
11 BAT
amplifier is V /2. When the magnitude of V /2 is
BAT
BAT
greater than the zener voltage, the zener conducts and
clamps the noninverting terminal of the ring amplifier to the
zener voltage.
10
HC5517
the 4-wire side that is amplified by the SLIC to ring the
telephone. The centering voltage, as previously discussed,
is a positive DC offset that is applied to the V input
along with the ringing waveform. The HC5517 application
circuit provides the centering voltage, simplifying the system
interface to an AC coupled ringing waveform.
Mode Control Signals
The Battery Switch selects between the -80V and -24V
supplies. The Battery Switch circuitry is described in the
“Operation of the Battery Switch” section. A system alternative
to the battery switch signal is to use a buffered version of the
SHD output to select the battery voltage. Another alternative
is to control the output of a programmable battery supply,
removing the battery switch entirely from the application
circuit. F1 is used to put the SLIC in the power denial mode.
RING
Ringer Equivalence Number
Before any further discussion, the Ringer Equivalence
Number or REN must be discussed. Based on FCC Part
68.313 a single REN can be defined as 5kΩ, 7kΩ or 8kΩ of
AC impedance at the ringing frequency. The ringing
frequency is based on the ringing types listed in Table 1 of
the FCC specification. The impedance of multiple REN is the
paralleling of a single REN. Therefore 5 REN can either be
1kΩ, 1.4kΩ or 1.6kΩ. The 7kΩ model of a single REN will be
used throughout the remainder of the data sheet.
RC drives the base of T , which is the transistor used to
2
control the centering voltage and MTU voltage. The three
control signals can be driven from a TTL logic source or an
open collector output.
Ringing Mode
The ringing state, as the name indicates, is used to ring the
telephone with a -80V battery supply. The SLIC is designed
for balanced ringing with a differential gain of 40V/V across tip
and ring. Voltage feed amplifiers operating in the linear mode
are used to amplify the ringing signal. The linear amplifier
approach allows the system designer to define the shape and
amplitude of the ringing waveform. Both supervisory function
outputs, SHD and RTD, are active during ringing.
Ringing Waveform
An amplitude of 1.2V
RMS
to a 1 REN load, and 42V
will deliver approximately 46V
RMS
to a 3 REN load. The
RMS
amplitude is REN dependent and is slightly attenuated by
the feedback scheme used for impedance matching. The
ringing waveform is cadenced, alternating between a 20Hz
burst and a silent portion between bursts. Bellcore
specification TR-NWT-000057 defines seven distinct ringing
waveforms or alerting (ringing) patterns. The following table
lists each type.
Spectral Content of the Ringing Signal
The shape of the waveform can range from sinusoidal to
trapezoidal. Sinusoidal waveforms are spectrally cleaner
than trapezoidal waveforms, although the latter does result
in lower power dissipation across the SLIC for a given RMS
amplitude. Systems where the ringing signal will be in
proximity to digital data lines will benefit from the sinusoidal
ringing capability of the HC5517. The slow edge rates of a
sinusoid will minimize coupling of the large amplitude ringing
signal. The linear amplifier architecture of the HC5517
allows the system designer to optimize the design for power
dissipation and spectral purity.
TABLE 2. DISTINCTIVE ALERTING PATTERNS
INTERVAL DURATION IN SECONDS
PATTERN RINGING SILENT RINGING SILENT RINGING SILENT
A
B
C
D
E
F
0.4
0.2
0.8
0.4
1.2
0.2
0.1
0.4
0.2
4.0
0.4
0.2
0.8
0.6
0.2
0.1
0.4
4.0
0.8
0.6
4.0
4.0
1 ± 0.2 3 ± 0.3
0.3 0.2
Amplitude of the Ringing Signal
G
1.0
0.2
0.3
4.0
Amplitude control is another benefit of the linear amplifier
architecture. Systems that require less ringing amplitude are
able to do so by driving the HC5517 with a lower level
ringing waveform. Solutions that use saturated amplifiers
can only vary the amplitude of the ringing signal by changing
the negative battery voltage to the SLIC.
Figure 8 shows the relationship of the cadenced ringing
waveform and the Battery Switch and RC control signals.
Also shown are the states of the MTU voltage and the
centering voltage.
The state of Battery Switch is indicated by the desired
battery voltage to the SLIC. The RC signal is used to enable
and disable the centering voltage and MTU voltage. RC
follows the ring signal in that it is high during the 20Hz burst
and low during the static part of the waveform.
HC5517 Through SLIC Ringing
The HC5517 is designed with a high gain input, V
, that
RING
is one of
the system drives while ringing the phone. V
RING
many signals summed at the inverting input to the tip feed
amplifier. The gain of the V signal through the tip feed
RING
Open Circuit Voltage During the Ringing Mode
amplifier is set to 20V/V. The output of the tip feed amplifier
is summed at the inverting input of the ring feed amplifier,
configured for unity gain. The result is a differential gain of
40V/V across tip and ring of the ringing signal.
The mutually exclusive relationship of the centering voltage
and MTU implies that both functions will not exist at the
same time. During the silent portion of the ringing waveform
the HC5517 application circuit meets the hazardous voltage
requirements of FCC Part 68.306 by forcing the MTU
voltage. Without the zener clamping solution, a
The ringing function requires an input ringing waveform and
a centering voltage. The ringing waveform is the signal from
11
HC5517
programmable power supply would have to be designed.
The intervals listed in Table 1 would require the power
supply to switch voltages and settle to stable operation well
within 100ms. The design of such a power supply may prove
quite a challenge. The zener solution provides a cost
effective, low impact to meeting a wide variety of tip to ring
open circuit voltages.
47.00
46.00
45.00
44.00
43.00
42.00
41.00
40.00
39.00
CADENCED
WAVEFORM
-80V
BATTERY
SWITCH
-24V
1 REN
2 REN
3 REN
4 REN
5 REN
RC
FIGURE 9. MAXIMUM RINGING OUTPUT VOLTAGE
(V = 1.2V
CENTERING
VOLTAGE
)
RMS
RING
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
MTU
OFF
OFF
OFF
ON-Hook Standby Mode
FIGURE 8. RINGING WAVEFORM AND CONTROL SIGNALS
On-hook standby mode is with the phone on-hook (i.e., not
answered) and ready to accept an incoming voice signal or
electronic data. The HC5517 application circuit is designed
to maintain the MTU voltage during this mode of operation.
During this mode, the SHD output is valid and the RTD
output is invalid.
Ringing Design Equations
The differential tip to ring voltage during ringing, as a
function of REN, can be approximated from Equation 35.
V
(0.702)(200)V
TRO
RING
(R ) ≅ 2 × ----------------- – --------------------------------------------------- • 108e3
(EQ. 35)
V
TR
L
5.4e3
(108e3)R
L
Off-Hook Active Mode
Off-hook active accommodates voice and data
The voltage V
is defined as the RMS amplitude of the
RING
input ringing signal. V
communications, including pulse metering, with a battery
voltage of -24V. The MTU voltage during this mode is
defeated by the zener clamp design regardless of the state
of RC. It is important to have RC low to disable the ringing
voltage. Only the SHD output is valid during this mode.
is the open circuit tip to ring
TRO
differential output voltage, calculated as V
multiplied by
RING
the differential gain of 40V/V. The REN impedance is shown
as R . Figure 9 shows the relationship of REN load to
L
maximum differential tip to ring RMS voltage during ringing.
The maximum ringing signal amplitude herein assumes an
infinite source and sink capability of the tip feed and ring
feed amplifiers. Due to the amplifier output design, the
HC5517 is limited to 3 REN ringing capability for this reason.
Power Denial Mode
The HC5517 will enter the power denial mode whenever F1
is a logic low. During power denial, the tip and ring amplifiers
are active. The DC voltages of both amplifiers are near
ground, resulting in a maximum loop current of 7mA. Both
the SHD and the RTD detector output are invalid.
Table 2 summarizes the operating modes of the HC5517
application circuit. The table indicates the valid detectors in
each mode as well as valid application circuit operation.
12
HC5517
TABLE 3. HC5517 APPLICATION CIRCUIT OPERATING MODES SUMMARY
DETECTORS VALID
APPLICATION CIRCUIT VALID
BATTERY
SWITCH
F1
0
RC
0
MODE
Power Denial
Invalid
SHD
RTD
MTU
CENTERING
-24V
-24V
-24V
-24V
0
1
1
0
Off-Hook Active
Invalid
√
1
1
-80V
-80V
-80V
-80V
0
0
1
1
0
Power Denial
Invalid
√
√
1
0
On-Hook Standby
Ringing
√
1
(Note)
√
√
NOTE: During Ringing, the SHD output will be active for both on-hook and off-hook conditions. The AC current, for the on-hook condition, exceeds
the SHD threshold of 12mA. Valid off-hook detection during ringing is provided by the RTD output only.
Operation of the Battery Switch
EXTERNAL
The battery switch is used to select between the off-hook
battery of -24V and the ringing/standby battery of -80V.
TRANSHYBRID CIRCUIT
HC5517
V
V-REC
C
RX
7
When T is off (battery switch is logic low) the MOSFET T
is off and the -24V battery is supplied to the SLIC through
1
3
C
8
-
INCOMING
AC TRANSMISSION
C
+
5
D
. When T is on (battery switch is logic high) current
1
10
flows through the collector of T turning on the zener D .
R
R
I
9
8
1
R
2
1
9
180
-IN1
R
1
PHASE
SHIFT
OF AC
SIGNAL
When D turns on, the gate of the MOSFET is positive with
9
respect to the drain (-80V) and T turns on. Turning T on
3
3
R
V-XMIT
3
connects the -80V battery to the SLIC through D . This in
7
-
+
turn reverse biases D , isolating the two supplies.
10
OUT1
I
2
OUTGOING
AC TRANSMISSION
Transhybrid Balance (Voice Signal)
The purpose of the transhybrid circuit is to remove the
receive signal (V-REC) from the transmit signal (V-XMIT),
thereby preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
SUMMING NODE CANCELS OUT
INCOMING AC TRANSMISSION FROM
OUT GOING TRANSMISSION
FIGURE 10. TRANSHYBRID CIRCUIT (VOICE SIGNAL)
SLIC’s 4-wire receive port (V ) to the SLIC’s 4-wire
transmit port (OUT1).
RX
Transhybrid Balance (Pulse Metering)
Transhybrid balance of the pulse metering signal is
The external transhybrid circuit is shown in Figure 10. The
accomplished in 2 stages. The first stage uses the SLIC’s
internal op amp to invert the phase of the pulse metering
signal. The second stage sums the inverted pulse metering
signal with the incoming signal for cancellation in the
transhybrid amplifier. A third network can be added to offset
both tip and ring by the peak amplitude of the pulse metering
signal. This will allow both the maximum voice and pulse
metering signals to occur at the same time with no distortion.
effects of capacitors C , C and C are negligible and
therefore omitted from the analysis. The input signal (V-
REC) will be subtracted from the output signal (V-XMIT) if I
5
7
8
1
equals I are equal and opposite in phase. A node analysis
2
yields the following equation:
V–REC OUT1
(EQ. 36)
-------------------- + ---------------- = 0
R
R
2
3
The value of R is then:
2
Pulse Metering
V–REC
OUT1
(EQ. 37)
Pulse metering or Teletax is used outside the United States
for billing purposes at pay phones. A 12kHz or 16kHz burst
is injected into the 4-wire side of the SLIC and transmitted
across the tip and ring lines from the central office to the pay
phone. For more information about pulse metering than
covered here reference application note AN9608
“Implementing Pulse Metering for the HC5509 Series of
SLICs”.
R
= –R • --------------------
3
2
Given that OUT1 is equal to -1/3 of V-REC (Equation 16)
and V-REC is equal to VTR (A = 1, Equation
4-Wire-2-Wire
15), then R = 3R A transhybrid balance greater than 30dB
2
3.
can be achieved by using 1% resistors values.
13
HC5517
For a 600Ω termination and a pulse metering gain (G ) of
PM
Inverting Amplifier (A1)
1, the feedback voltage (V ) is equal to one third the
injected pulse metering signal of the 4-wire side. Note,
TX
The pulse metering signal is injected in the -IN1 pin of the
SLIC. This pin is the inverting input of the internal amplifier
depending upon the line impedance characteristics and the
degree of impedance matching, the pulse metering gain may
(A ) that is used to invert the pulse metering signal for later
cancellation. The components required for pulse metering
1
differ from the voice gain. The pulse metering gain (G
)
PM
must be accounted for in the transhybrid balance circuit.
are C and R , are shown in Figure 11. The pulse metering
6
5
signal is AC coupled to prevent a DC offset on the input of
the internal amplifier. The value of C should be 10µF. The
expression for the voltage at OUT1 is given in Equation 38
6
The polarity of the signal at OUT1 (Equation 38) is opposite
of V allowing the circuit of Figure 12 to perform the final
PM
C
R
stage of transhybrid cancellation.
6
5
TO EXTERNAL
V
PM
V
TRANSHYBRID AMP
RX
C
R
R
2
R
8
8
9
R
R
3
1
V
OUT
1
TX
OUT
1
-IN
1
-
V
+
A
PM
R
1
4
V
-
TXO
+
CA741C
FIGURE 12. CANCELLATION OF THE PULSE METERING SIGNAL
FIGURE 11. PULSE METERING PHASE SHIFT AMPLIFIER DESIGN
The following equations do not require much discussion. They
are based on inverting amplifier design theory. The voice path
.
R
R
8
R
5
V
signal has been omitted for clarity. All reference
8
(EQ. 38)
RX
designators refer to components of Figures 11 and 12.
V
= –V • ------ – V
• ------
OUT1
TX
R
PM
9
The first term is the gain of the feedback voltage from the
2-wire side and the second term is the gain of the injected
V
V
R
R
1
R
4
TX
PM
1
(EQ. 42)
V
= –R • – ---------- – ----------- • ------ – V
• ------
TXO
8
PM
R
R
R
3
9
5
pulse metering signal. The effects of C and C are
6
8
negligible and therefore omitted from the analysis.
The first term refers to the signal at OUT1 and the second
term refers to the 4-wire side pulse metering signal. Since
The injected pulse metering output term of Equation 38 is
shown below in Equation 39 and rearranged to solve for R
in Equation 40.
ideal transhybrid cancellation implies V
equals zero
TXO
when a signal is injected on the 4-wire side, V
5
is set to
TXO
zero and the resulting equation is shown below.
R
8
(EQ. 39)
V
(injected) = V
• ------ = 1
OUT1
PM
R
5
V
V
R
R
1
R
4
TX
PM
1
(EQ. 43)
0 = R
•
---------- + ----------- • ------ – V
• ------
8
PM
R
R
R
3
9
5
(EQ. 40)
R
= R
5
8
Rearranging terms of Equation 43 and solving for R results
4
The ratio of R to R is set equal to one and results in unity
8
5
in Equation 44. This is the only value to be calculated for the
transhybrid cancellation. All other values either exist in the
application circuit or have been calculated in previous
sections of this data sheet.
gain of the pulse metering signal from 4-wire side to 2-wire
side. The value of R is considered to be a constant since it
8
is selected based on impedance matching requirements.
Cancellation of the Pulse Metering Signal
–1
R
–200 • G
1
8
PM
------ • ------------------------------- + ------
• R
(EQ. 44)
R
=
The transhybrid cancellation technique that is used for the
voice signal is also implemented for pulse metering. The
technique is to drive the transhybrid amplifier with the signal
that is injected on the 4-wire side, then adjust its level to
match the amplitude of the feedback signal, and cancel the
signals at the summing node of an amplifier.
4
R
R
R
3
L
9
5
The value of R (Figure 12) is 12.37kΩ given the following
4
set of values:
R = 40kΩ
R = 40kΩ
8
9
R = 600Ω
L
NOTE: The CA741C operational amplifier is used in the application
as a “stand in” for the operational amplifier that is traditionally located
in the CODEC, where transhybrid cancellation is performed.
R = 8.25kΩ
3
R = 40kΩ
5
G
= 1
Referring to Figure 3, V is the 2-wire feedback used to
TX
PM
Substituting the same values into Equation 41 and Equation 42,
it can be shown that the signal at OUT is equal to -2/3V
drive the internal amplifier (A1) which in turn drives the
OUT1 pin of the SLIC. The voltage measured at V is
TX
.
PM
1
related to the loop impedance as follows:
This result, along with Equation 44 where R equals to 2/3R4,
3
indicates the signal levels into the transhybrid amplifier are
equalized by the amplifier gains and opposite in polarity,
–200
V
= ------------ • V
• G
PM PM
(EQ. 41)
TX
R
L
thereby achieving transhybrid balance at V
TXO
.
14
HC5517
standard value without significantly changing the offset
Additional Tip and Ring Offset Voltage
voltage.
A DC offset is required to level shift tip and ring from ground
and V
respectively. By design, the tip amplifier is offset
BAT
4V below ground and the ring amplifier is offset 4V above
. The 4V offset was designed so that the peak voice
Single Low Voltage Supply Operation
The application circuit shown Figure 15 requires 2 low
voltage supplies (+5V, -5V). The following application offers
away to make use of a 2.5V reference, provided with some
CODEC, to operate the transhybrid balance amplifier from
a single +5V supply. The implementation is shown in
Figure 14. Notice that the three inputs from the SLIC must all
be AC coupled to insure the proper DC gain through the
CODECs internal op amp. The resistor Ra is not used for
gain setting and is only intended to balance the DC offsets
generated by the input bias current of the CODEC amplifier.
If the DC offsets generated by the input bias currents are
negligible, then Ra may be omitted from the circuit. Ca may
be required for decoupling of the voltage reference pin and
does not contribute to the response of the amplifier.
V
BAT
signal could pass through the SLIC without distortion.
Therefore, to maintain distortion free transmission of pulse
metering and voice, an additional offset equal to the peak of
the pulse metering signal is required.
The tip and ring voltages are offset by a voltage divider network
on the V pin. The V pin is a unity gain input designed as
the 4-wire side voice input for the SLIC. Figure 13 details the
circuit used to generate the additional offset voltage.
RX RX
+5V
V
R
PMO
R
R
6
7
C
R
7
V
RX
-
4-WIRE SIDE
VOICE INPUT
+
C
5
2-WIRE SIDE
CODEC
R
0.1µ
0.1µ
0.1µ
F
F
F
2
V
RX
R
TO VOICE INPUT OF
TRANSHYBRID AMP
1
24.9kΩ
R
3
OUT
1
-
FIGURE 13. PULSE METERING OFFSET GENERATION
+
R
4
V
PM
Ra
24.9k
The amplifier shown is the tip amplifier. Other signals are
connected to the summing node of the amplifier but only those
components used for the offset generation are shown. The
offset generated at the output of the tip amplifier is summed at
the ring amplifier inverting input to provide a positive offset from
the battery voltage. The connection to the ring amplifier was
omitted from Figure 13 for clarity, refer to Figure 3 for details.
Ω
2.4V
REF
Ca
0.1
µ
F
FIGURE 14. SINGLE LOW VOLTAGE SUPPLY OPERATION
Layout Guidelines and Considerations
The term V
is defined to be the offset required for the
PMO
The printed circuit board trace length to all high impedance
nodes should be kept as short as possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:
pulse metering signal. The value of the offset voltage is
calculated as the peak value of the pulse metering signal.
Equation 45 assumes the amplitude of the pulse metering
signal is expressed as an RMS voltage.
V
=
2 • V
PM
(EQ. 45)
• V
pin 27, the 4-wire voice input.
• -IN1 pin 13, the inverting input of the internal amplifier.
PMO
RX
The value of R can be calculated from the following
6
equation:
• V
pin 3, the noninverting input to ring feed ampli-
REF
fier.
R R
5 – V
• V
pin 24, the 20V/V input for the ringing signal.
RING
7
PMO
----------------- -------------------------
+ R
(EQ. 46)
R
=
6
• U1 pin 2, inverting input of external amplifier.
R
V
PMO
7
For multi layer boards, the traces connected to tip should not
cross the traces connected to ring. Since they will be
carrying high voltages, and could be subject to lightning or
surge depending on the application, using a larger than
minimum trace width is advised.
The component labeled R is the internal summing resistor of
the tip amplifier and has a typical value of 108kΩ. The value
of R should be selected in the range of 4.99kΩ and 10kΩ.
7
Staying within these limits will minimize the parallel loading
effects of the internal resistor R on R as well as minimize
7
The 4-wire transmit and receive signal paths should not
the constant power dissipation introduced by the divider.
cross. The receive path is any trace associated with the V
input and the transmit path is any trace associated with V
output. The physical distance between the two signal paths
should be maximized to reduce crosstalk.
RX
Solving Equation 45 for 1V
results in a 1.414V
RMS
. Setting R of Equation 46 to 10kΩ
TX
requirement for V
PMO
and substituting the values for V
7
and R yields 23.2kΩ
PMO
for R . The value of R can be rounded to the nearest
6
6
The mode control signals and detector outputs should be
routed away from the analog circuitry. Though the digital
15
HC5517
signals are nearly static, care should be taken to minimize
coupling of the sharp digital edges to the analog signals.
A ground plane that provides a low impedance return path
for the supply currents should be used. A ground plane
provides isolation between analog and digital signals. If the
layout density does not accommodate a ground plane, a
single point grounding scheme should be used.
The part has two ground pins, one is labeled AGND and the
other BGND. Both pins should be connected together as
close as possible to the SLIC. If a ground plane is available,
then both AGND and BGND should be connected directly to
the ground plane.
Application Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
1
AGND
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and receive input
terminals.
2
3
V
Positive Voltage Source - Most Positive Supply.
CC
V
Ring amplifier reference override. An external voltage connected to this pin will override the internal V
reference.
/2
BAT
REF
4
F1
Power Denial -A low active TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp
close to the output voltage of the tip amplifier.
5
6
7
8
F0
TTL compatible logic control input that must be tied high for proper SLIC operation.
TTL compatible logic control input that must be tied high for proper SLIC operation.
Switch Hook Detection - An active low TTL compatible logic output. Indicates an offhook condition.
RS
SHD
RTD
Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is
ringing.
9
TST
A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the ALM pin
can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that
monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the TST pin (low) to
power down the SLIC. The timing of the thermal recovery is controlled by the system controller.
10
ALM
A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded.
11
12
13
I
Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider.
The analog output of the spare operational amplifier.
LMT
OUT1
-IN1
The inverting analog input of the spare operational amplifier. Note that the non-inverting input of the amplifier is
internally connected to AGND.
14
15
TIP
SENSE
An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor and ring relay
contact. Functions with the RING terminal to receive voice signals from the telephone and for loop monitoring
purpose.
RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions
with the TIP terminal to receive voice signals from the telephone and for loop monitoring purposes.
16
17
RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation.
V
Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed
and Ring Feed amplifiers deferentially.
RX
18
19
NU
Not used in this application.This pin should be left floating.
V
Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP
and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is
necessary.
TX
20
21
22
RDI
RDO
TTL compatible input to drive the uncommitted relay driver.
This is the output of the uncommitted relay driver.
BGND
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this
terminal.
23
24
25
26
27
NU
Not used in this application. This pin should be either grounded or left floating.
V
Ring signal input (0V to 3V
at 20Hz).
PEAK
RING
TF
This is the output of the tip amplifier.
This is the output of the ring amplifier.
The negative battery source.
RF
V
BAT
16
HC5517
Application Pin Descriptions (Continued)
PLCC
SYMBOL
DESCRIPTION
28
RTI
Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.
Pinouts
HC5517 (PLCC)
HC5517 (SOIC)
TOP VIEW
TOP VIEW
28 RTI
27 V
AGND
1
2
3
4
5
6
7
8
9
V
CC
BAT
4
3
27
2
1
28
26
26 RF
VREF
F1
TF
F0
25
24
5
6
25 TF
VRING
RS
24 VRING
23 NU
F0
RS
23 NU
22
SHD
RTD
TST
7
8
SHD
RTD
TST
22 BGND
21 RDO
BGND
RDO
RDI
21
20
19
9
20
RDI
ALM
ILMT
10
11
19 V
TX
ALM 10
ILMT 11
V
TX
18 NU
12
13
14
15
17
16
18
OUT 1 12
17 V
RX
16
-IN 1 13
RING SENSE 2
15 RING SENSE 1
TIP SENSE 14
Applications Circuit
17
HC5517
+5V
PULSE METERING OPTION
R
R
6
R
11
C
7
14 TIP SENSE
25 TF
TIP
V
17
V-REC
RX
R
13
D
R
C
1
+5V
1
-5V
3
5
7
C
C
17
ILIMT 11
C
C
4
R
2
28
D
2
R
R
C
10
1
2
9
C
C
U1
V
7
BAT
V
19
TX
2
6
D
D
-
4
3
C
8
V-XMIT
V-TELETAX
F1
+
R
R
††
3
5
26 RF
R
3
4
4
R
9
16 RING SENSE 2
-IN1 13
18
R
14
R
12
C
R
6
8
15 RING SENSE 1
RING
OUT1 12
F1 4
2 V
CC
V
CC
R
22
R
31
BAT
SWITCH
C
C
C
+5V
15
14
12
+5V
FO 5
R
D
19
12
VR
3
R
EF
24
T
1 AGND
2
T
1
RC
22 BGND
BGND
-24V
D
13
RDI 20
C
D
13
10
RDO 21
27 V
BAT
C
D
11
D
11
6
V
24
RING
D
7
R
C
T
18
16
3
HC5517
†D
8
R
D
21
5
D
9
RTI 28
SHD RTD ALM TST RS
10
-80V
R
17
R
16
7
8
9
6
V
RING
R
C
10
15
† Not required for MOSFETs with body diodes.
†† Diode bridge optional for in-house use.
R
R
30
+5V
29
FIGURE 15. APPLICATION CIRCUIT
18
HC5517
HC5517EVAL Evaluation Board Parts List
COMPONENT
SLIC
R , R
VALUE
HC5517
24.9kΩ
8.25kΩ
12.1kΩ
40kΩ
TOLERANCE
RATING
COMPONENT
VALUE
0.1µF
TOLERANCE
20%
RATING
50V
n/a
1%
1%
1%
1%
1%
1%
5%
1%
1%
1%
1%
1%
n/a
C , C , C
2
4
15
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
C , C
10µF
20%
20V
1
2
5
7
R
R
C , C
0.47µF
0.01µF
1.0µF
20%
20V
3
4
6
8
C , C
20%
100V
50V
9
12
R , R , R
C
C
C
C
C
D
20%
5
8
9
10
11
13
16
17
1-4
R (Not Provided)
23.2kΩ
10kΩ
100µF
0.1µF
20%
5V
6
R (Not Provided)
20%
100V
50V
7
R
R
R
R
R
R
100kΩ
50Ω
0.5µF
20%
10
, C
3300pF
1N4007
1N914
1N4744
1N5255
20%
100V
100V, 1A
100V, 1A
15V, 1W
11-14
15
18
, D , D , D
10
47kΩ
7
8
1.5MΩ
56.2kΩ
1.1kΩ
D , D , D , D
16
5
6
12
13
D
D
17
9
28V, 1/2-
Wire
18
11
R
R
R
825Ω
10kΩ
47kΩ
1%
5%
5%
1/4W
1/4W
1/4W
T
T
T
NTE 383
2N2907
100V, 1A
60V,150mA
100V, 2A
19
1
2
3
, R , R , R
31
22 29
30
RFP2N10 or
equivalent
24
R
R
R
560Ω
5%
1/4W
1/4W
1/4W
50V
F1, RC, Battery
U1
SPDT Toggle Switches, Center Off.
CA741C OpAmp
25-27
28
20kΩ Potentiometer
47kΩ
5%
Textool Socket
228-5523
21
C , C , C
14
0.01µF
20%
1
3
19
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