HC5503PRCRZ [INTERSIL]
Low Cost SLIC For Large Telecom Switches; 低成本SLIC为大型电信交换机
| 型号： | HC5503PRCRZ |
| 厂家： | 
Intersil |
| 描述： | Low Cost SLIC For Large Telecom Switches |
| 文件： | 总11页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC5503PRC
®
Data Sheet
J une 2004
FN4806.3
Low Cos t SLIC For Large Telecom
Switches
Features
• Wide Operating Battery Range (-40V to -58V)
• Single Additional +5V Supply
The HC5503PRC is a low cost SLIC optimized for large
Telecom switches. It combines a flexible voltage feed
architecture with the Intersil latch-free DI bonded wafer
process, to provide a low component count, carrier class
solution at very low cost. The re-configurable design permits
simple, economical solutions for campus-wide call center
and PBX applications. External components can be used in
conjunction with the high battery voltage capability to meet
the complex impedance and long loop drive requirements of
Central Office switches, worldwide.
• 30mA Short Loop Current Limit
• Ring Relay Driver
• Switch Hook and Ring Trip Detect
• Low On-Hook Power Consumption
• On-Hook Transmission
• ITU-T Longitudinal Balance Performance
• Loop Power Denial Function
Ordering Information
• Thermal Protection
TEMP.
PKG.
• Supports Tip, Ring or Balanced Ringing Schemes
• Low Profile SO and QFN Surface Mount Packaging
• Pb-free Available
PART NUMBER RANGE (°C)
PACKAGE
24 Ld SOIC
24 Ld SOIC (Pb-free)
DWG. #
HC5503PRCB
0 to 70
0 to 70
M24.3
M24.3
HC5503PRCBZ
(Note)
Applications
HC5503PRCBZ96
(Note)
0 to 70
24 Ld SOIC Tape & Reel M24.3
(Pb-free)
• Central Office, PBX, Call Centers
HC5503PRCR
0 to 70
0 to 70
32 Ld 7x7 QFN
L32.7x7
L32.7x7
• Related Literature
HC5503PRCRZ
(Note)
32 Ld 7x7 QFN
(Pb-free)
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
HC5503PRCRZ96
(Note)
0 to 70
32 Ld 7x7 QFN
Tape & Reel (Pb-free)
L32.7x7
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HC5503PRC
Block Diagram
RING RELAY
DRIVER
4-WIRE
RD
TX
RX
INTERFACE
VF SIGNAL
PATH
RFS
RING TRIP
DETECTOR
C
2
TIP
TF
2-WIRE
LOOP CURRENT
DETECTOR
SHD
INTERFACE
RING
RF
RS
RC
LOGIC
INTERFACE
THERMAL LIMIT
PD
V
BAT
V
CC
C1
BIAS
OUT
AGND
+IN
-IN
+
-
BGND
DGND
2
HC5503PRC
Absolute Maximum Ratings
Thermal Information
Maximum Continuous Supply Voltages
Thermal Resistance (Typical, Note 2, 3)
θJA (°C/W)
(V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V
B
24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 Lead 7x7 QFN . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
75
32
(V +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V
B
(V + - V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
B
B
Relay Drive Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
RD
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Die Characteristics
Relay Driver Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
RD
Positive Supply Voltage (V +). . . . . . . . . . . . . . . . . . 4.75V to 5.25V
B
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Negative Supply Voltage (V -) . . . . . . . . . . . . . . . . . . .-40V to -58V
B
High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V
Low Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
Subscriber Loop Resistance . . . . . . . . . . . . . . . . . . . 200Ω - 1800Ω
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
3. θ for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct
JA
attach features including conductive thermal vias. See Tech Brief TB379 and TB389 for additional information and board layout consideration
Electrical Specifications Unless Otherwise Specified, V - = -48V, V + = 5V, AG = BG = DG = 0V, R = 50Ω, R = 100Ω, Typical
B
B
P
S
Parameters. T = 25°C. Min-Max Parameters are Over Operating Temperature Range
A
PARAMETER
On Hook Power Dissipation
Off Hook Power Dissipation
CONDITIONS
MIN
TYP
MAX
UNITS
mW
mW
mA
I
= 0 (Note 4)
-
-
113
750
1.4
2.8
2.2
31
-
-
LONG
R
= 600Ω, I
= 0 (Notes 3, 4)
LONG
L
On Hook I +
R = ∞, I = 0
LONG
-
-
B
L
Off Hook I +
R = 600Ω, I
= 0
-
-
mA
B
L
LONG
On Hook I -
R = ∞, I = 0
LONG
-
-
mA
B
L
Off Hook I -
B
R = 600Ω, I
= 0
-
-
mA
L
LONG
Off Hook Loop Current
Off Hook Loop Current
R
R
= 1800Ω (I
= 0)
18
25
-
-
mA
L
L
LOOP
= 200Ω, I
= 0 (Note 3)
30
35
mA
LONG
Fault Currents
TIP to Ground
-
27
55
30
69
0.2
-
-
-
mA
mA
mA
mA
V
RING to Ground
TIP to RING
-
-
-
TIP and RING to Ground
-
-
Ring Relay Drive V
I
= 62mA
-
-
0.5
100
13.5
10
-
OL
OL
Ring Relay Driver Off Leakage
DC Ring Trip Threshold
V
= 12V, RC = 1 = HIGH, T = 25°C
A
µA
mA
mA
mA
ms
kΩ
Ω
RD
8.1
5.0
-
10.8
7.5
3.2
-
Switch Hook Detection Threshold
Loop Current During Power Denial
Dial Pulse Distortion
R
= 200Ω
L
(Note 4)
(Note 4)
(Note 4)
0
0.5
-
Receive Input Impedance
Transmit Output Impedance
-
110
10
-
20
3
HC5503PRC
Electrical Specifications Unless Otherwise Specified, V - = -48V, V + = 5V, AG = BG = DG = 0V, R = 50Ω, R = 100Ω, Typical
B
B
P
S
Parameters. T = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued)
A
PARAMETER
2-Wire Return Loss
SR LO
CONDITIONS
MIN
TYP
MAX
UNITS
(Referenced to 600Ω + 2.16µF), R = R = 150Ω
P
S
(Note 4)
-
-
-
15.5
24
-
-
-
dB
dB
dB
L
ER
L
SR HI
L
31
Longitudinal Balance
1V
200Hz - 3400Hz, (Note 4) IEEE Method
RMS
0°C ≤ T ≤ 75°C, R = R = 150Ω
A
P
S
2-Wire Off Hook (Note 4)
53
53
50
58
58
58
-
-
-
dB
dB
dB
2-Wire On Hook (Note 4)
4-Wire Off Hook
Insertion Loss
At 1kHz, 0dBm Input Level, Referenced 600Ω,
= R = 150Ω
R
P
S
2-Wire to 4-Wire, 4-Wire to 2-Wire
-
-
±0.05
±0.02
±0.2
dB
dB
Frequency Response
200 - 3400Hz Referenced to Absolute Loss at 1kHz and
0dBm Signal Level, R = R = 150Ω (Note 4)
±0.05
P
S
Idle Channel Noise
R
= R = 150Ω (Note 4)
S
P
P
2-Wire to 4-Wire, 4-Wire to 2-Wire
-
-
1
5
dBrnC
-89
-85
dBm0p
Absolute Delay
R
= R = 150Ω (Note 4)
S
2-Wire to 4-Wire, 4-Wire to 2-Wire
-
-
2
-
µs
Trans Hybrid Loss
Balance Network Set Up for 600Ω Termination at 1kHz,
= R = 150Ω (Note 4)
30
40
dB
R
P
S
Overload Level
V + = +5V, R = R = 150Ω (Note 4)
B P S
2-Wire to 4-Wire, 4-Wire to 2-Wire
1.5
-
-
V
PEAK
Level Linearity
At 1kHz, (Note 4) Referenced to 0dBm Level,
2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4)
R = R = 150Ω
P S
+3 to -40dBm
-40 to -50dBm
-50 to -55dBm
-
-
-
-
-
-
±0.05
±0.1
±0.3
dB
dB
dB
Power Supply Rejection Ratio
R
= R = 150Ω (Note 4)
S
P
30 - 60Hz, R = 600Ω
L
V + to 2-Wire
15
15
15
15
30
30
30
30
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
µA
B
V + to Transmit
-
B
V - to 2-Wire
-
B
V - to Transmit
-
B
V + to 2-Wire
200 - 16kHz, R = 600Ω, R = R = 150Ω
-
B
L
P
S
V + to Transmit
-
B
V - to 2-Wire
-
-
B
V - to Transmit
B
Logic Input Current (RS, RC, PD)
Logic Inputs
0V ≤ V ≤ 5V
IN
±100
Logic ‘0’ V
Logic ‘1’ V
-
-
-
0.8
5.5
V
V
IL
2.0
IH
Logic Outputs
Logic ‘0’ V
Logic ‘1’ V
I
I
800µA, V + = 5V
-
0.1
-
0.5
5.0
V
V
OL
LOAD
LOAD
B
40µA, V + = 5V
2.7
OH
B
4
HC5503PRC
Electrical Specifications Unless Otherwise Specified, V - = -48V, V + = 5V, AG = BG = DG = 0V, R = 50Ω, R = 100Ω, Typical
B
B
P
S
Parameters. T = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued)
A
PARAMETER
UNCOMMITTED OP AMP SPECIFICATIONS
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
-
-
-
-
-
-
-
±5
±10
20
1
-
-
-
-
-
-
-
mV
nA
Input Offset Current
Input Bias Current
nA
Differential Input Resistance
Output Voltage Swing
Output Resistance
(Note 4)
MΩ
R
= 10K, V + = 5V
±3
10
1
V
PEAK
L
B
A
= 1 (Note 4)
Ω
VCL
Small Signal GBW
(Note 4)
MHz
NOTES:
4. I
= Longitudinal Current.
LONG
5. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
Pin Des criptions
24 PIN
DIP/SOIC
7 x 7
QFN
SYMBOL
DESCRIPTION
1
2
3
28
31
32
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor
(R ) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone
S
and for loop monitoring purposes.
RING
RFS
An analog input connected to the RING (more negative) side of the subscriber loop through a sense
resistor (R ) and a ring relay contact. Functions with the Tip terminal to receive voice signals from the
S
telephone and for loop monitoring purposes.
Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted
into the line at this node and RF is isolated from RFS via a relay.
4
5
1
3
V +
Positive Voltage Source - Most positive supply. V + is typically.
B
B
C
Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required
1
for proper operation of the loop current limiting function, and for filtering V -. Typical value is 0.3µF, 30V.
B
6
7
4
5
DG
RS
Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and
outputs on the SLIC microcircuit.
Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a
positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS
terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing
and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay
activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not
required, the pin should be tied to 5V.
8
9
6
RD
TF
Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.
7, 8
Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (R ).
S
Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.
10
9, 10
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor
(R ). Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and
S
sink longitudinal current.
11
12
13
14
11
12
V -
B
Negative Voltage Source - Most negative supply. V - is typically -48V with an operational range of -42V
B
to -58V. Frequently referred to as “battery”.
BG
SHD
NC
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into
this ground terminal.
13
Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop
currents exceeding the switch hook threshold.
14,19
Used during production test. Leave disconnected.
5
HC5503PRC
Pin Des criptions (Continued)
24 PIN
DIP/SOIC
7 x 7
QFN
SYMBOL
DESCRIPTION
15
16
15
16
PD
Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses
to the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch
hook detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled.
RC
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output
goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial
state (PD = 0) or the subscriber is not already off- hook (SHD = 0).
17
18
19
20
21
NC
OUT
-IN
Leave disconnected.
20
21
22
23
The analog output of the spare operational amplifier.
The inverting analog input of the spare operational amplifier.
The non-inverting analog input of the spare operational amplifier.
+IN
RX
Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive
coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and
Ring feed terminals.
22
25
C
Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This
capacitor is required for the proper operation of ring trip detection. Recommended value 0.82µF ±10%
10V non-polarized.
2
23
24
26
27
AG
TX
Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX)
and receive input (RX) terminals.
Transmit Output, Four Wire Side - A low impedance analog output proportional to the loop current.
Transhybrid balancing must be performed beyond this output to completely implement two to four wire
conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output
varies with loop current, capacitive coupling to the next stage is essential.
2, 17,
18,24, 29,
30,
NC
No internal connection.
NOTE: All grounds (AG, BG, and DG) must be applied before V + or V -. Failure to do so may result in premature failure of the part. If a user wishes
B
B
to run separate grounds off a line card, the AG must be applied first.
6
HC5503PRC
Functional Diagram
RING
TRIP
RS
RC
RD
SHD
SWITCH HOOK
DETECTION
RING SYNC
RING
CONTROL
LOOP
MONITORING
RING COMMAND
R
P
TIP
1/2 RING
RELAY
TIP
DIFF
AMP
+
TX
TRANSMIT
OUTPUT
R
S
TF
2-WIRE
LOOP
V -
B
SECONDARY
PROTECTION
BATTERY
FEED
OUT
+IN
+1
BG
RF
V -
B
+
LOOP
CURRENT
LIMITER
OP
LINE
DRIVERS
RFS
AMP
1/2 RING
RELAY
-IN
RX
R
S
RING
RECEIVE
INPUT
RING
PD
R
-1
P
RING
VOLTAGE
V -
POWER DENIAL
SLIC MICROCIRCUIT
B
R : 100Ω; 1/2W to 2W depending on surge requirements
S
R : 50Ω; 1/2W to 2W depending on surge requirements
P
7
HC5503PRC
SLIC FUNCTIONAL SCHEMATIC
SOIC PIN NUMBERS SHOWN
21
22
11
12
23
6
4
20
+
19
-
18
BAT
GND
ANA
GND
DIG
GND
RX
C2
V
V +
B
OUT
BAT
V +
V +
B
B
V
V
V
V
V
B1
B2
B3
B4
B5
A-500
OP AMP
VOLTAGE AND CURRENT
BIAS NETWORK
V
BAT
5V
R
I
17
B3
V +
+
B
A-400
TIP FEED
AMP
I
I
I
I
I
I
I
I
I
I
I
V
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
BAT
V
B2
TF
9
V
BAT
R
RING TRIP DETECTOR
5V
-
I
B4
I
V +
B
B10
5V
R
12
V +
B
7
-
GK
TIP
1
R
Q
Q
A-200
LONG’L
I/V AMP
20
D3 D36
R
8
V +
B
V
I
V
+
BAT
B4
NC
14
GND SHORTS
CURRENT
LIMITING
R
10
V
BAT
+
I
R
B7
RING
FEED
SENSE
9
R
B8
11
I
B1
V
BAT
R
5
V +
V
BAT
B
R
R
23
22
3
-
+
NC
17
STTL
AND LOGIC
INTERFACE
V
V +
B3
B
+
-
SWITCH HOOK
DETECTOR
R
3
A-100
V
BAT
TRANSV’L
I/V AMP
R
4
1
2
V +
B
RING
2
SHD
13
V
R
R
SH
BAT
+
I
-
B6
V
B1
R
6
I
B6
R
16
15
Q
Q
D28
D27
V
REFERENCE
RC
16
BAT/2
R
THERMAL
LIMITING
V
B2
R
14
LOAD CURRENT
LIMITING
R
R
18
I
RFC
B2
R
-
21
PD
15
A-300
RING FEED
AMP
V
V
B5
RF
10
B5
-
+
+
19
V
BAT
V
BAT
I
B5
R
13
V
BAT
V
BAT
C1
TX
24
RS
RD
8
5
7
8
HC5503PRC
LOGIC GATE SCHEMATIC
LOGIC BIAS
GK
2
1
DELAY
3
6
8
9
4
5
7
12
SH
16
10
13
RELAY
DRIVER
11
14
15
STTL
TO
TTL
TTL
TO
STTL
TTL
TO
STTL
TTL
TO
STTL
C
B
A
TO
21
R
A
B
C
RS
RC
PD
RD
SHD
SCHOTTKY LOGIC
This device is intended for use with an appropriate
secondary protection circuit scheme.
Surge Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
The SLIC will withstand longitudinal currents up to a
maximum or 30mA
, 15mA per leg, without any
RMS
RMS
performance degradation.
The voltage withstand capability of pins ‘Tip’, ‘Ring’ and
‘RFs’ is ±450V with respect to ground, as shown in Table 1.
TABLE 1.
TEST
CONDITION
PERFORMANCE
(MAX)
PARAMETER
UNITS
Longitudinal Surge 10µs Rise/
1000µs Fall
±450 (Plastic)
±450 (Plastic)
±450 (Plastic)
315 (Plastic)
V
V
V
PEAK
PEAK
PEAK
Metallic Surge
10µs Rise/
1000µs Fall
T/GND
R/GND
10µs Rise/
1000µs Fall
50/60Hz Current
T/GND
11 Cycles
Limited to
V
RMS
R/GND
10A
RMS
9
HC5503PRC
Small Outline Plas tic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
15.60
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
-
-A-
o
0.6141 15.20
3
h x 45
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
24
24
7
o
o
o
o
0
8
0
8
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
HC5503PRC
Quad Flat No-Lead Plas tic Package (QFN)
L32.7x7
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKC ISSUE C)
Micro Lead Frame Plas tic Package (MLFP)
2X
0.15
C A
MILLIMETERS
D
A
SYMBOL
MIN
TYP
MAX
1.00
NOTES
9
D/2
A
A1
A2
A3
b
0.80
0.90
-
D1
-
-
-
0.05
1.00
-
D1/2
-
9
2X
N
0.15 C
B
6
0.20 REF
9
INDEX
AREA
0.23
0.28
0.38
4.85
4.85
5, 8
1
2
3
E1/2
E/2
9
D
7.00 BSC
-
E1
E
B
D1
D2
E
6.75 BSC
9
4.55
4.55
4.70
7, 8
2X
7.00 BSC
-
0.15 C
B
E1
E2
e
6.75 BSC
9
2X
TOP VIEW
0.15 C
A
4.70
7, 8
0.65 BSC
-
0
A2
4X
C
A
/ /
0.10 C
0.08 C
k
0.25
0.50
-
-
-
0.75
0.15
-
L
0.60
8
L1
N
-
32
8
8
-
10
SEATING PLANE
A1
A3
SIDE VIEW
2
9
Nd
Ne
P
3
5
NX b
0.10 M C A B
3
4X P
D2
D2
8
7
-
-
0.60
9
NX k
θ
-
12
9
(DATUM B)
2
N
Rev. 4 8/03
4X P
NOTES:
1
2
(DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
(Ne-1)Xe
REF.
3
E2
6
INDEX
AREA
7
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
8
NX L
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
N
e
9
(Nd-1)Xe
REF.
CORNER
OPTION 4X
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
9. Features and dimensions A2, A3, D1, E1, P & θ are present
when Anvil singulation method is used and not present for saw
singulation.
C
L
C
L
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
L
L
10
L1
10
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
11
相关型号：
HC5503PRIBZ96
Low Cost 24V SLIC For PABX / Key Systems; SOIC24; Temp Range: 0° to 70°
RENESAS
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