HA2-5137/883 [INTERSIL]
60MHz, Ultra Low Noise, Precision Operational Amplifier; 为60MHz ，超低噪声，精密运算放大器
| 型号： | HA2-5137/883 |
| 厂家： | 
Intersil |
| 描述： | 60MHz, Ultra Low Noise, Precision Operational Amplifier |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5137/883
60MHz, Ultra Low Noise, Precision
Operational Amplifier
June 1998
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HA-5137/883 monolithic operational amplifier features
an excellent combination of precision DC and wideband high
speed characteristics. Utilizing the Intersil DI technology and
advanced processing techniques, this unique design unites
low noise precision instrumentation performance with high
speed, wideband capability.
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 14V/µs (Min)
• Wide Gain Bandwidth (A ≥ 5) . . . . . . . . . 60MHz (Min)
V
This amplifier’s impressive list of features include low V
OS
,
• Low Noise (at 1kHz). . . . . . . . . . . . . . . 4.5nV/√Hz (Max)
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . .100µV (Max)
wide gain-bandwidth, high open loop gain, and high CMRR.
Additionally, this flexible device operates over a wide supply
range while consuming only 120mW of power.
o
• Low Offset Drift With Temperature. . . . 1.8µV/ C (Max)
Using the HA-5137/883 allows designers to minimize errors
while maximizing speed and bandwidth in applications
requiring gains greater than five.
• High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . .100dB (Min)
• High Voltage Gain . . . . . . . . . . . . . . . . . . 700kV/V (Min)
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5137/883’s qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal
conditioning circuits.
Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers
• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• Pulse/RF Amplifiers
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
HA2-5137/883
HA4-5137/883
HA7-5137/883
-55 to 125 8 Pin Metal Can
-55 to 125 20 Ld CLCC
-55 to 125 8 Ld CERDIP
T8.C
J20.A
F8.3A
Pinouts
HA-5137/883
(CERDIP)
TOP VIEW
HA-5137/883
(CLCC)
TOP VIEW
HA-5137/883
(METAL CAN)
TOP VIEW
BAL
8
BAL
-IN
+IN
V-
1
2
3
4
8
7
6
5
BAL
V+
3
2
1 20 19
1
3
7
5
-
+
V+
BAL
2
18
17
16
15
NC
V+
4
5
6
7
8
NC
-IN
OUT
NC
-
-
6
OUT
-IN
NC
OUT
NC
+IN
NC
+
+
14 NC
NC
+IN
4
9
10 11 12 13
V- (CASE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number 511034-883
File Number 3714.1
1
HA-5137/883
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 44V Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
Differential Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . .0.7V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
115
85
155
28
26
67
Metal Can Package . . . . . . . . . . . . . . .
o
o
Package Power Dissipation Limit at 75 C for T ≤ 175 C
J
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870mW
CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.18W
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645mW
Package Power Dissipation Derating Factor Above 75 C
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.7mW/ C
Operating Conditions
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15V
o
CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.8mW/ C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5mW/ C
V
R
≤ 1/2 (V+ - V-)
INCM
≥ 600Ω
o
L
o
Maximum Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . 175 C
J
o
o
Maximum Storage Temperature Range . . . . . . . . . . -65 C to150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: V
= ±15V, R
= 50Ω, R = 100kΩ, V
LOAD OUT
= 0V, Unless Otherwise Specified.
SUPPLY
SOURCE
GROUP A
SUBGROUPS
o
PARAMETER
SYMBOL
CONDITIONS
TEMP. ( C)
MIN
-100
-300
-
MAX
100
300
80
UNITS
µV
Input Offset Voltage
V
V
= 0V
1
25
IO
CM
CM
2, 3
1
125, -55
25
µV
Input Bias Current
I
V
R
= 0V,
= 10kΩ, 50Ω
nA
B
S
2, 3
125, -55
-
150
nA
+I + -I
B
B
---------------------------
2
Input Offset Current
I
V
= 0V,
1
25
-75
75
nA
nA
IO
CM
+R = 10kΩ,
-R = 10kΩ
S
2, 3
125, -55
-135
135
S
Common Mode
Range
+CMR
-CMR
V+ = +4.7V,
V- = -25.3V
1
2, 3
1
25
125, -55
25
10.3
10.3
-
-
V
V
-
V+ = 25.3V,
V- = -4.7V
-10.3
V
2, 3
4
125, -55
25
-
-10.3
V
Large Signal Voltage
Gain
+A
VOL
V
R
= 0V and +10V,
700
300
700
300
100
100
100
100
-
-
-
-
-
-
-
-
kV/V
kV/V
kV/V
kV/V
dB
OUT
= 2kΩ
L
5, 6
4
125, -55
25
-A
VOL
V
= 0V and -10V,
OUT
R
= 2kΩ
L
5, 6
1
125, -55
25
Common Mode
Rejection Ratio
+CMRR
-CMRR
∆V
∆V
∆V
∆V
= +11V
= +10V
= -11V
= -10V
CM
CM
CM
CM
2, 3
1
125, -55
25
dB
dB
2, 3
125, -55
dB
Spec Number 511034-883
2
HA-5137/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: V
= ±15V, R
= 50Ω, R = 100kΩ, V
LOAD OUT
= 0V, Unless Otherwise Specified.
SUPPLY
SOURCE
GROUP A
SUBGROUPS
o
PARAMETER
SYMBOL
CONDITIONS
TEMP. ( C)
MIN
MAX
UNITS
V
Output Voltage Swing
+V
R
R
= 2kΩ
4
5, 6
4
25
11.5
-
OUT1
L
L
125, -55
25
11.5
-
V
-V
= 2kΩ
-
-
-11.5
V
OUT1
5, 6
4
125, -55
25
-11.5
V
+V
R
R
= 600Ω
= 600Ω
10
-
-
V
OUT2
L
L
-V
+I
4
25
-10
V
OUT2
Output Current
V
= -10V
= +10V
4
25
16.5
-
-
mA
mA
mA
mA
mA
mA
dB
dB
OUT
OUT
OUT
-I
V
4
25
-16.5
OUT
Quiescent Power
Supply Current
+I
V
= 0V, I
= 0mA
= 0mA
1
25
-
4
4
-
CC
OUT
OUT
2, 3
1
125, -55
25
-
-I
V
= 0V, I
-4
-4
86
86
CC
OUT
OUT
2, 3
1
125, -55
25
-
Power Supply
Rejection Ratio
+PSRR
-PSRR
∆V
SUP
= 14V,
-
V+ = +4V, V- = -15V,
V+ = +18V, V- = -15V
2, 3
125, -55
-
∆V
SUP
= 14V,
1
25
86
86
-
-
dB
dB
V+ = +15V, V- = -4V,
V+ = +15V, V- = -18V
2, 3
125, -55
Offset Voltage
Adjustment
+V Adj
IO
Note 3
Note 3
1
25
V
-1
-
-
-
-
mV
mV
mV
mV
IO
2, 3
1
125, -55
25
V
-1
IO
-V Adj
IO
V
V
+1
+1
IO
2, 3
125, -55
IO
NOTE:
3. Offset adjustment range is [V (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment
IO
through 0V.
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: V
= ±15V, R
SOURCE
= 50Ω, R
LOAD
= 2kΩ, C
= 50pF, A
LOAD VCL
= +10V/V, Unless Otherwise Specified.
SUPPLY
GROUP A
SUBGROUPS
o
PARAMETER
SYMBOL
+SR
CONDITIONS
TEMP. ( C)
MIN
14
14
-
MAX
UNITS
V/µs
V/µs
ns
Slew Rate
V
= -3V to +3V
= +3V to -3V
= 0 to +200mV
OUT
7
7
7
25
25
25
-
-
OUT
-SR
V
OUT
Rise and Fall Time
Overshoot
t
V
100
r
10% ≤ t ≤ 90%
r
t
V
= 0 to -200mV
7
25
-
100
ns
f
OUT
10% ≤ t ≤ 90%
f
+OS
-OS
V
= 0 to +200mV
= 0 to -200mV
7
7
25
25
-
-
40
40
%
%
OUT
V
OUT
Spec Number 511034-883
3
HA-5137/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Characterized at: V
= ±15V, R
= 2kΩ, C = 50pF, A = +5V/V, Unless Otherwise Specified.
LOAD V
SUPPLY
LOAD
o
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMP. ( C)
MIN
MAX
UNITS
o
Average Offset Voltage
Drift
V
TC
V
V
= 0V
4
-55 to 125
-
1.8
µV/ C
IO
CM
CM
Differential Input
Resistance
R
= 0V
4
4
25
25
0.8
-
-
MΩ
IN
Low Frequency
E
0.1Hz to 10Hz
0.25
µV
P-P
NP-P
Peak-to-Peak Noise
Input Noise Voltage
Density
E
R
R
R
R
R
R
= 20Ω, f = 10Hz
4
4
25
-
-
10
5.6
4.5
4.0
2.3
0.6
-
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
MHz
N
S
S
S
S
S
S
O
= 20Ω, f = 100Hz
25
O
= 20Ω, f = 1kHz
4
25
-
O
Input Noise Current
Density
I
= 2MΩ, f = 10Hz
4
25
-
N
O
= 2MΩ, f = 100Hz
4
25
-
O
= 2MΩ, f = 1kHz
4
25
25
-
O
Gain Bandwidth Product
Full Power Bandwidth
GBWP
V
= 100mV, f = 10kHz
4
60
43
220
±5
O
O
V
= 100mV, f = 1MHz
4
25
-
MHz
O
O
FPBW
CLSG
V
= 10V
4, 5
4
25
-
kHz
PEAK
Minimum Closed Loop
Stable Gain
R
= 2kΩ, C = 50pF
-55 to 125
-
V/V
L
L
Settling Time
t
To 0.1% for a 10V Step
Open Loop
4
4
25
25
-
-
-
1.5
100
120
µs
Ω
S
Output Resistance
R
OUT
Quiescent Power
Consumption
PC
V
= 0V, I
OUT
= 0mA
4, 6
-55 to 125
mW
OUT
NOTES:
4. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-
eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot to lot and within lot variation.
5. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
).
PEAK
6. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on output.)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
SUBGROUPS (SEE TABLES 1 AND 2)
1
1 (Note 7), 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7
1
Groups C and D Endpoints
NOTE:
7. PDA applies to Subgroup 1 only.
Spec Number 511034-883
4
HA-5137/883
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
5
2
104.3 x 65 x 19 mils
3.6 x 10 A/cm at 15mA
2650 x 1650 x 483µm
This device meets Glassivation Integrity Test Requirement
per MIL-STD-883 Method 2021 and MIL-I-38535 Paragraph
30.5.5.4.
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ± 2kÅ
SUBSTRATE POTENTIAL (Powered Up):
V-
GLASSIVATION:
TRANSISTOR COUNT:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
3
4
2
Silox Thickness: 12kÅ ± 2kÅ
63
Nitride Thickness: 3.5kÅ ± 1.5kÅ
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5137/883
BAL
BAL
-IN
V+
+IN
OUT
V-
NC
Spec Number 511034-883
5
HA-5137/883
Metal Can Packages (Can)
REFERENCE PLANE
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
A
e1
L
INCHES
MILLIMETERS
L2
L1
SYMBOL
A
MIN
MAX
0.185
0.019
0.021
0.024
0.375
0.335
0.160
MIN
4.19
0.41
0.41
0.41
8.51
7.75
2.79
MAX
4.70
0.48
0.53
0.61
9.40
8.51
4.06
NOTES
ØD2
0.165
0.016
0.016
0.016
0.335
0.305
0.110
-
A
A
Øb
Øb1
Øb2
ØD
ØD1
ØD2
e
1
k1
1
Øe
ØD ØD1
2
-
N
1
-
-
Øb1
β
α
C
L
-
Øb
k
F
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
BASE AND
Q
e1
-
SEATING PLANE
F
-
0.040
0.034
0.045
0.750
0.050
-
-
1.02
0.86
1.14
19.05
1.27
-
-
BASE METAL
LEAD FINISH
Øb2
k
0.027
0.027
0.500
-
0.69
0.69
12.70
-
-
k1
2
Øb1
L
1
L1
1
SECTION A-A
L2
0.250
0.010
6.35
0.25
1
Q
0.045
1.14
-
NOTES:
o
o
45 BSC
45 BSC
3
α
β
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
o
o
45 BSC
45 BSC
3
4
N
8
8
2. Measured from maximum diameter of the product.
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
Spec Number 511034-883
6
HA-5137/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
D
S
M
S
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
Spec Number 511034-883
7
HA-5137/883
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES MILLIMETERS
MIN
D3
SYMBOL
A
MAX
0.100
0.088
-
MIN
1.52
1.27
-
MAX
2.54
2.23
-
NOTES
o
j x 45
0.060
0.050
-
6, 7
A1
B
-
-
B1
B2
B3
D
0.022
0.028
0.56
0.71
2, 4
-
0.072 REF
1.83 REF
E3
E
B
0.006
0.342
0.022
0.358
0.15
8.69
0.56
9.09
-
-
D1
D2
D3
E
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
-
-
0.358
0.358
-
9.09
9.09
2
-
o
h x 45
0.342
8.69
0.010 S E F S
A1
E1
E2
E3
e
0.200 BSC
0.100 BSC
0.358
0.050 BSC
0.015
5.08 BSC
2.54 BSC
9.09
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
-
-
2
-
PLANE 2
PLANE 1
e1
h
-
-
2
5
5
-
-E-
0.040 REF
0.020 REF
j
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.91
0.08
1.40
1.40
2.41
0.38
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
0.007 M E F S H S
-
B1
-
e
L3
5
5
5
5
3
3
3
L
-H-
20
20
Rev. 0 5/18/94
NOTES:
-F-
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
B3
E1
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
L2
E2
B2
L1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
D2
e1
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
D1
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 511034-883
8
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